diff options
Diffstat (limited to 'test/CodeGen/PowerPC')
137 files changed, 6214 insertions, 593 deletions
diff --git a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll index ecf45efee2e6..3d3728dcde12 100644 --- a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll +++ b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll @@ -1,9 +1,23 @@ -; RUN: llc < %s +; RUN: llc < %s | FileCheck %s ;; Formerly crashed, see PR 1508 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin8" %struct.Range = type { i64, i64 } +; CHECK: .cfi_startproc +; CHECK: .cfi_personality 155, L___gxx_personality_v0$non_lazy_ptr +; CHECK: .cfi_lsda 16, Lexception0 +; CHECK: .cfi_def_cfa_offset 176 +; CHECK: .cfi_offset r31, -8 +; CHECK: .cfi_offset lr, 16 +; CHECK: .cfi_def_cfa_register r31 +; CHECK: .cfi_offset r27, -16 +; CHECK: .cfi_offset r28, -24 +; CHECK: .cfi_offset r29, -32 +; CHECK: .cfi_offset r30, -40 +; CHECK: .cfi_endproc + + define void @Bork(i64 %range.0.0, i64 %range.0.1, i64 %size) { entry: %effectiveRange = alloca %struct.Range, align 8 ; <%struct.Range*> [#uses=2] diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll index 6c23a6162c9d..8d5ea8af0f28 100644 --- a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll +++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll @@ -5,7 +5,7 @@ target triple = "powerpc-apple-darwin9.6" define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind { entry: -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: subfc ; CHECK: subfe ; CHECK: subfc diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 097611a7619c..b0c37b80ed2f 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 -break-anti-dependencies=none | FileCheck %s ; ModuleID = 'hh.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target triple = "powerpc-apple-darwin9.6" diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll index d1a3c9f46b57..a25ce07e83bf 100644 --- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll +++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll @@ -6,7 +6,7 @@ target triple = "powerpc-apple-darwin9.8" define i32 @main() nounwind { entry: ; Make sure we're generating references using the red zone -; CHECK: main: +; CHECK-LABEL: main: ; CHECK: stw r2, -12(r1) %retval = alloca i32 %0 = alloca i32 diff --git a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll index a18829e1bce8..b1cbb36fe041 100644 --- a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll +++ b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll @@ -9,7 +9,7 @@ entry: store i64 %z2, i64* %xx, align 4 ret void -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: sldi {{.*}}, {{.*}}, 32 ; Note: it's okay if someday CodeGen gets smart enough to optimize out ; the shift. diff --git a/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll b/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll new file mode 100644 index 000000000000..542a766300ef --- /dev/null +++ b/test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i8* @test(i8* %base, i8 %val) { +entry: + %arrayidx = getelementptr inbounds i8* %base, i32 -1 + store i8 %val, i8* %arrayidx, align 1 + %arrayidx2 = getelementptr inbounds i8* %base, i32 1 + store i8 %val, i8* %arrayidx2, align 1 + ret i8* %arrayidx +} +; CHECK: @test +; CHECK: %entry +; CHECK-NEXT: stbu 4, -1(3) +; CHECK-NEXT: stb 4, 2(3) +; CHECK-NEXT: blr + +define i64* @test64(i64* %base, i64 %val) { +entry: + %arrayidx = getelementptr inbounds i64* %base, i32 -1 + store i64 %val, i64* %arrayidx, align 8 + %arrayidx2 = getelementptr inbounds i64* %base, i32 1 + store i64 %val, i64* %arrayidx2, align 8 + ret i64* %arrayidx +} +; CHECK: @test64 +; CHECK: %entry +; CHECK-NEXT: stdu 4, -8(3) +; CHECK-NEXT: std 4, 16(3) +; CHECK-NEXT: blr + diff --git a/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll new file mode 100644 index 000000000000..9bf25c8ffe49 --- /dev/null +++ b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -verify-machineinstrs | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@g_51 = external global [8 x i32], align 4 + +; CHECK: func_7 + +; Function Attrs: nounwind +define fastcc void @func_7() #0 { +entry: + %arrayidx638 = getelementptr inbounds [3 x [1 x i32]]* undef, i64 0, i64 1, i64 0 + br i1 undef, label %for.cond940, label %if.end1018 + +for.cond940: ; preds = %for.cond940, %if.else876 + %l_655.1 = phi i32* [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ], [ %l_654.0, %for.cond940 ] + %l_654.0 = phi i32* [ null, %entry ], [ %arrayidx638, %for.cond940 ] + %exitcond = icmp eq i32 undef, 20 + br i1 %exitcond, label %if.end1018, label %for.cond940 + +if.end1018: ; preds = %for.end957, %for.end834 + %l_655.3.ph33 = phi i32* [ %l_655.1, %for.cond940 ], [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ] + store i32 0, i32* %l_655.3.ph33, align 4 + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll index 28dd08c7fed1..4588bc05352b 100644 --- a/test/CodeGen/PowerPC/Frames-alloca.ll +++ b/test/CodeGen/PowerPC/Frames-alloca.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32 -; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64 -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP -; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32 -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32-RS -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-RS-NOFP +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32 +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC64 +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC32-NOFP +; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC64-NOFP +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32 +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32-RS +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC32-RS-NOFP ; CHECK-PPC32: stw r31, -4(r1) ; CHECK-PPC32: lwz r1, 0(r1) diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll index 8c928ce8bcad..500d126ebed7 100644 --- a/test/CodeGen/PowerPC/addc.ll +++ b/test/CodeGen/PowerPC/addc.ll @@ -5,7 +5,7 @@ define i64 @add_ll(i64 %a, i64 %b) nounwind { entry: %tmp.2 = add i64 %b, %a ; <i64> [#uses=1] ret i64 %tmp.2 -; CHECK: add_ll: +; CHECK-LABEL: add_ll: ; CHECK: addc r4, r6, r4 ; CHECK: adde r3, r5, r3 ; CHECK: blr @@ -15,7 +15,7 @@ define i64 @add_l_5(i64 %a) nounwind { entry: %tmp.1 = add i64 %a, 5 ; <i64> [#uses=1] ret i64 %tmp.1 -; CHECK: add_l_5: +; CHECK-LABEL: add_l_5: ; CHECK: addic r4, r4, 5 ; CHECK: addze r3, r3 ; CHECK: blr @@ -25,7 +25,7 @@ define i64 @add_l_m5(i64 %a) nounwind { entry: %tmp.1 = add i64 %a, -5 ; <i64> [#uses=1] ret i64 %tmp.1 -; CHECK: add_l_m5: +; CHECK-LABEL: add_l_m5: ; CHECK: addic r4, r4, -5 ; CHECK: addme r3, r3 ; CHECK: blr diff --git a/test/CodeGen/PowerPC/addrfuncstr.ll b/test/CodeGen/PowerPC/addrfuncstr.ll new file mode 100644 index 000000000000..6750b5cfebf6 --- /dev/null +++ b/test/CodeGen/PowerPC/addrfuncstr.ll @@ -0,0 +1,27 @@ +; RUN: llc -O0 < %s | FileCheck %s + +; Verify that a constant with an initializer that may turn into a dynamic +; relocation is not placed in .rodata, but rather in .data.rel.ro. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.x = type { i64 (i8*, i64, i64, %struct._IO_FILE*)* } +%struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] } +%struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 } + +@_ZL1y = internal constant %struct.x { i64 (i8*, i64, i64, %struct._IO_FILE*)* @fread }, align 8 + +; Function Attrs: nounwind +define %struct.x* @_Z3foov() #0 { +entry: + ret %struct.x* @_ZL1y +} + +declare i64 @fread(i8*, i64, i64, %struct._IO_FILE*) #1 + +; CHECK: .section .data.rel.ro +; CHECK: .quad fread + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/altivec-ord.ll b/test/CodeGen/PowerPC/altivec-ord.ll new file mode 100644 index 000000000000..6aea8433a1eb --- /dev/null +++ b/test/CodeGen/PowerPC/altivec-ord.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define <4 x i16> @test(<4 x float> %f, <4 x float> %g) { +entry: + %r = fcmp ord <4 x float> %f, %g + %s = sext <4 x i1> %r to <4 x i16> + ret <4 x i16> %s +} + +define <4 x i16> @test2(<4 x float> %f, <4 x float> %g) { +entry: + %r = fcmp one <4 x float> %f, %g + %s = sext <4 x i1> %r to <4 x i16> + ret <4 x i16> %s +} + diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll index 52587e2c0b87..1525e05501ee 100644 --- a/test/CodeGen/PowerPC/anon_aggr.ll +++ b/test/CodeGen/PowerPC/anon_aggr.ll @@ -1,6 +1,9 @@ -; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s +; RUN: llc -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s +; RUN: llc -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s ; Test case for PR 14779: anonymous aggregates are not handled correctly. +; Darwin bug report PR 15821 is similar. ; The bug is triggered by passing a byval structure after an anonymous ; aggregate. @@ -17,13 +20,33 @@ unequal: ret i8* %ptr } -; CHECK: func1: +; CHECK-LABEL: func1: ; CHECK: cmpld {{[0-9]+}}, 4, 5 -; CHECK: std 4, -[[OFFSET1:[0-9]+]] -; CHECK: std 5, -[[OFFSET2:[0-9]+]] +; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]] +; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) +; DARWIN32: _func1: +; DARWIN32: mr +; DARWIN32: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] +; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] +; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REGB]] +; DARWIN32: stw r[[REG1]], -[[OFFSET1:[0-9]+]] +; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]] +; DARWIN32: lwz r3, -[[OFFSET1]] +; DARWIN32: lwz r3, -[[OFFSET2]] + +; DARWIN64: _func1: +; DARWIN64: mr +; DARWIN64: mr r[[REG1:[0-9]+]], r[[REGA:[0-9]+]] +; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]] +; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REGB]] +; DARWIN64: std r[[REG1]], -[[OFFSET1:[0-9]+]] +; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] +; DARWIN64: ld r3, -[[OFFSET1]] +; DARWIN64: ld r3, -[[OFFSET2]] + define i8* @func2({ i64, i8* } %array1, %tarray* byval %array2) { entry: @@ -38,15 +61,38 @@ unequal: ret i8* %array2_ptr } -; CHECK: func2: +; CHECK-LABEL: func2: ; CHECK: addi [[REG1:[0-9]+]], 1, 64 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]]) ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]] -; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]] -; CHECK: std 4, -[[OFFSET2:[0-9]+]] +; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]] +; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) +; DARWIN32: _func2: +; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36 +; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]]) +; DARWIN32: mr +; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] +; DARWIN32: cmplw cr{{[0-9]+}}, r[[REGA]], r[[REG2]] +; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]] +; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]] +; DARWIN32: lwz r3, -[[OFFSET1]] +; DARWIN32: lwz r3, -[[OFFSET2]] + +; DARWIN64: _func2: +; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64 +; DARWIN64: ld r[[REG2:[0-9]+]], 8(r[[REG1]]) +; DARWIN64: mr +; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] +; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]] +; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] +; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]] +; DARWIN64: ld r3, -[[OFFSET1]] +; DARWIN64: ld r3, -[[OFFSET2]] + + define i8* @func3({ i64, i8* }* byval %array1, %tarray* byval %array2) { entry: %tmp1 = getelementptr inbounds { i64, i8* }* %array1, i32 0, i32 1 @@ -61,7 +107,7 @@ unequal: ret i8* %array2_ptr } -; CHECK: func3: +; CHECK-LABEL: func3: ; CHECK: addi [[REG1:[0-9]+]], 1, 64 ; CHECK: addi [[REG2:[0-9]+]], 1, 48 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) @@ -72,6 +118,29 @@ unequal: ; CHECK: ld 3, -[[OFFSET2]](1) ; CHECK: ld 3, -[[OFFSET1]](1) +; DARWIN32: _func3: +; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 40 +; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24 +; DARWIN32: lwz r[[REG3:[0-9]+]], 48(r[[REGSP]]) +; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]]) +; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]] +; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]] +; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]] +; DARWIN32: lwz r3, -[[OFFSET2]] +; DARWIN32: lwz r3, -[[OFFSET1]] + +; DARWIN64: _func3: +; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64 +; DARWIN64: addi r[[REG2:[0-9]+]], r1, 48 +; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]]) +; DARWIN64: ld r[[REG4:[0-9]+]], 8(r[[REG2]]) +; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]] +; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] +; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]] +; DARWIN64: ld r3, -[[OFFSET2]] +; DARWIN64: ld r3, -[[OFFSET1]] + + define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6, i64 %p7, i64 %p8, { i64, i8* } %array1, %tarray* byval %array2) { @@ -87,7 +156,7 @@ unequal: ret i8* %array2_ptr } -; CHECK: func4: +; CHECK-LABEL: func4: ; CHECK: addi [[REG1:[0-9]+]], 1, 128 ; CHECK: ld [[REG2:[0-9]+]], 120(1) ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) @@ -97,3 +166,24 @@ unequal: ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) +; DARWIN32: _func4: +; DARWIN32: lwz r[[REG4:[0-9]+]], 96(r1) +; DARWIN32: addi r[[REG1:[0-9]+]], r1, 100 +; DARWIN32: lwz r[[REG3:[0-9]+]], 108(r1) +; DARWIN32: mr r[[REG2:[0-9]+]], r[[REG4]] +; DARWIN32: cmplw cr{{[0-9]+}}, r[[REG4]], r[[REG3]] +; DARWIN32: stw r[[REG4]], -[[OFFSET1:[0-9]+]] +; DARWIN32: stw r[[REG3]], -[[OFFSET2:[0-9]+]] +; DARWIN32: lwz r[[REG1]], -[[OFFSET1]] +; DARWIN32: lwz r[[REG1]], -[[OFFSET2]] + +; DARWIN64: _func4: +; DARWIN64: addi r[[REG1:[0-9]+]], r1, 128 +; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1) +; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]]) +; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]] +; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]] +; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] +; DARWIN64: std r[[REG3]], -[[OFFSET2:[0-9]+]] +; DARWIN64: ld r3, -[[OFFSET1]] +; DARWIN64: ld r3, -[[OFFSET2]] diff --git a/test/CodeGen/PowerPC/ashr-neg1.ll b/test/CodeGen/PowerPC/ashr-neg1.ll new file mode 100644 index 000000000000..28e74f4d2988 --- /dev/null +++ b/test/CodeGen/PowerPC/ashr-neg1.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD30723(i32) { +BB: + br label %CF80 + +CF80: ; preds = %CF80, %BB + %B = ashr i32 %0, -1 + br i1 undef, label %CF80, label %CF84 + +CF84: ; preds = %CF84, %CF80 + %Cmp62 = icmp sge i32 undef, %B + br i1 %Cmp62, label %CF84, label %CF85 + +CF85: ; preds = %CF85, %CF84 + br label %CF85 +} diff --git a/test/CodeGen/PowerPC/asm-dialect.ll b/test/CodeGen/PowerPC/asm-dialect.ll new file mode 100644 index 000000000000..e8fd2516b5a5 --- /dev/null +++ b/test/CodeGen/PowerPC/asm-dialect.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s + +; This test verifies that we choose "assembler variant 1" (which GCC +; uses for "new-style mnemonics" as opposed to POWER mnemonics) when +; processing multi-variant inline asm statements, on all subtargets. + +; CHECK: subfe +; CHECK-NOT: sfe + +define i32 @test(i32 %in1, i32 %in2) { +entry: + %0 = tail call i32 asm "$(sfe$|subfe$) $0,$1,$2", "=r,r,r"(i32 %in1, i32 %in2) + ret i32 %0 +} + diff --git a/test/CodeGen/PowerPC/asym-regclass-copy.ll b/test/CodeGen/PowerPC/asym-regclass-copy.ll index d04a6c98ee19..b19125b064e7 100644 --- a/test/CodeGen/PowerPC/asym-regclass-copy.ll +++ b/test/CodeGen/PowerPC/asym-regclass-copy.ll @@ -52,5 +52,5 @@ declare void @free(i8* nocapture) #0 declare i64 @strtol(i8*, i8** nocapture, i32 signext) #0 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll index 838db20ddd1b..1737916375ca 100644 --- a/test/CodeGen/PowerPC/atomic-1.ll +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 | FileCheck %s define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { -; CHECK: exchange_and_add: +; CHECK-LABEL: exchange_and_add: ; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}} %tmp = atomicrmw add i32* %mem, i32 %val monotonic ; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}} @@ -9,7 +9,7 @@ define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { } define i32 @exchange_and_cmp(i32* %mem) nounwind { -; CHECK: exchange_and_cmp: +; CHECK-LABEL: exchange_and_cmp: ; CHECK: lwarx %tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic ; CHECK: stwcx. @@ -18,7 +18,7 @@ define i32 @exchange_and_cmp(i32* %mem) nounwind { } define i32 @exchange(i32* %mem, i32 %val) nounwind { -; CHECK: exchange: +; CHECK-LABEL: exchange: ; CHECK: lwarx %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic ; CHECK: stwcx. diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index 40b4a2eea976..e56a77966714 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=ppc64 | FileCheck %s define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { -; CHECK: exchange_and_add: +; CHECK-LABEL: exchange_and_add: ; CHECK: ldarx %tmp = atomicrmw add i64* %mem, i64 %val monotonic ; CHECK: stdcx. @@ -9,7 +9,7 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { } define i64 @exchange_and_cmp(i64* %mem) nounwind { -; CHECK: exchange_and_cmp: +; CHECK-LABEL: exchange_and_cmp: ; CHECK: ldarx %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic ; CHECK: stdcx. @@ -18,7 +18,7 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind { } define i64 @exchange(i64* %mem, i64 %val) nounwind { -; CHECK: exchange: +; CHECK-LABEL: exchange: ; CHECK: ldarx %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic ; CHECK: stdcx. diff --git a/test/CodeGen/PowerPC/bdzlr.ll b/test/CodeGen/PowerPC/bdzlr.ll index 656a85860df0..e487558e942a 100644 --- a/test/CodeGen/PowerPC/bdzlr.ll +++ b/test/CodeGen/PowerPC/bdzlr.ll @@ -35,15 +35,15 @@ for.body: ; preds = %for.body.for.body_c %0 = phi %struct.lua_TValue.17.692* [ undef, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ] %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ] %tt = getelementptr inbounds %struct.lua_TValue.17.692* %0, i64 %indvars.iv, i32 1 - %1 = load i32* %tt, align 4, !tbaa !0 - store i32 %1, i32* undef, align 4, !tbaa !0 + %1 = load i32* %tt, align 4 + store i32 %1, i32* undef, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge for.body.for.body_crit_edge: ; preds = %for.body - %.pre = load %struct.lua_TValue.17.692** undef, align 8, !tbaa !3 + %.pre = load %struct.lua_TValue.17.692** undef, align 8 br label %for.body for.end: ; preds = %for.body, %if.end, %entry @@ -57,8 +57,3 @@ for.end: ; preds = %for.body, %if.end, } attributes #0 = { nounwind } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"any pointer", metadata !1} diff --git a/test/CodeGen/PowerPC/bv-pres-v8i1.ll b/test/CodeGen/PowerPC/bv-pres-v8i1.ll new file mode 100644 index 000000000000..5bf84ed1c5c8 --- /dev/null +++ b/test/CodeGen/PowerPC/bv-pres-v8i1.ll @@ -0,0 +1,39 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD70() { +BB: + br label %CF78 + +CF78: ; preds = %CF87, %CF78, %BB + br i1 undef, label %CF78, label %CF87 + +CF87: ; preds = %CF78 + %Cmp19 = icmp sge <8 x i1> zeroinitializer, zeroinitializer + %Cmp26 = icmp slt i32 -1, undef + br i1 %Cmp26, label %CF78, label %CF79 + +CF79: ; preds = %CF79, %CF87 + br i1 undef, label %CF79, label %CF82 + +CF82: ; preds = %CF82, %CF79 + br i1 undef, label %CF82, label %CF84 + +CF84: ; preds = %CF82 + br label %CF + +CF: ; preds = %CF88, %CF, %CF84 + br i1 undef, label %CF, label %CF85 + +CF85: ; preds = %CF85, %CF + %I52 = insertelement <8 x i1> %Cmp19, i1 %Cmp26, i32 6 + %Cmp61 = icmp ult i32 477567, undef + br i1 %Cmp61, label %CF85, label %CF88 + +CF88: ; preds = %CF85 + %E63 = extractelement <8 x i1> %I52, i32 5 + br i1 %E63, label %CF, label %CF80 + +CF80: ; preds = %CF80, %CF88 + br label %CF80 +} diff --git a/test/CodeGen/PowerPC/bv-widen-undef.ll b/test/CodeGen/PowerPC/bv-widen-undef.ll new file mode 100644 index 000000000000..9e58f0d95023 --- /dev/null +++ b/test/CodeGen/PowerPC/bv-widen-undef.ll @@ -0,0 +1,23 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD4357(i8) { +BB: + br label %CF + +CF: ; preds = %CF, %BB + br i1 undef, label %CF, label %CF77 + +CF77: ; preds = %CF81, %CF77, %CF + %Shuff12 = shufflevector <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 -1, i8 -1>, <2 x i32> <i32 0, i32 undef> + br i1 undef, label %CF77, label %CF80 + +CF80: ; preds = %CF80, %CF77 + %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1> + %Cmp24 = fcmp une ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000 + br i1 %Cmp24, label %CF80, label %CF81 + +CF81: ; preds = %CF80 + %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0 + br label %CF77 +} diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll index f12152ff0fca..3eb30e93fd31 100644 --- a/test/CodeGen/PowerPC/complex-return.ll +++ b/test/CodeGen/PowerPC/complex-return.ll @@ -23,7 +23,7 @@ entry: ret { ppc_fp128, ppc_fp128 } %0 } -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: lfd 3 ; CHECK: lfd 4 ; CHECK: lfd 2 @@ -49,7 +49,7 @@ entry: ret { float, float } %0 } -; CHECK: oof: +; CHECK-LABEL: oof: ; CHECK: lfs 2 ; CHECK: lfs 1 diff --git a/test/CodeGen/PowerPC/copysignl.ll b/test/CodeGen/PowerPC/copysignl.ll new file mode 100644 index 000000000000..4b801b791d62 --- /dev/null +++ b/test/CodeGen/PowerPC/copysignl.ll @@ -0,0 +1,67 @@ +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define double @foo_d_ll(ppc_fp128 %a, ppc_fp128 %b) #0 { +entry: + %call = tail call ppc_fp128 @copysignl(ppc_fp128 %a, ppc_fp128 %b) #0 + %conv = fptrunc ppc_fp128 %call to double + ret double %conv + +; CHECK-LABEL: @foo_d_ll +; CHECK: fcpsgn 1, 3, 1 +; CHECK: blr +} + +declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) #0 + +define double @foo_dl(double %a, ppc_fp128 %b) #0 { +entry: + %conv = fptrunc ppc_fp128 %b to double + %call = tail call double @copysign(double %a, double %conv) #0 + ret double %call + +; CHECK-LABEL: @foo_dl +; CHECK: fcpsgn 1, 2, 1 +; CHECK: blr +} + +declare double @copysign(double, double) #0 + +define ppc_fp128 @foo_ll(double %a, ppc_fp128 %b) #0 { +entry: + %conv = fpext double %a to ppc_fp128 + %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %b) #0 + ret ppc_fp128 %call + +; CHECK-LABEL: @foo_ll +; CHECK: bl copysignl +; CHECK: blr +} + +define ppc_fp128 @foo_ld(double %a, double %b) #0 { +entry: + %conv = fpext double %a to ppc_fp128 + %conv1 = fpext double %b to ppc_fp128 + %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0 + ret ppc_fp128 %call + +; CHECK-LABEL: @foo_ld +; CHECK: bl copysignl +; CHECK: blr +} + +define ppc_fp128 @foo_lf(double %a, float %b) #0 { +entry: + %conv = fpext double %a to ppc_fp128 + %conv1 = fpext float %b to ppc_fp128 + %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0 + ret ppc_fp128 %call + +; CHECK-LABEL: @foo_lf +; CHECK: bl copysignl +; CHECK: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/cr-spills.ll b/test/CodeGen/PowerPC/cr-spills.ll index d6df7a237668..be0dbad6289e 100644 --- a/test/CodeGen/PowerPC/cr-spills.ll +++ b/test/CodeGen/PowerPC/cr-spills.ll @@ -53,11 +53,11 @@ for.cond286.preheader: ; preds = %for.body252 for.cond290.preheader: ; preds = %for.end520, %for.cond286.preheader %srcptr.31595 = phi i16* [ getelementptr inbounds ([768 x i16]* @SetupFastFullPelSearch.orig_pels, i64 0, i64 0), %for.cond286.preheader ], [ null, %for.end520 ] - %1 = load i32* undef, align 4, !tbaa !0 - %2 = load i32* @weight_luma, align 4, !tbaa !0 - %3 = load i32* @wp_luma_round, align 4, !tbaa !0 - %4 = load i32* @luma_log_weight_denom, align 4, !tbaa !0 - %5 = load i32* @offset_luma, align 4, !tbaa !0 + %1 = load i32* undef, align 4 + %2 = load i32* @weight_luma, align 4 + %3 = load i32* @wp_luma_round, align 4 + %4 = load i32* @luma_log_weight_denom, align 4 + %5 = load i32* @offset_luma, align 4 %incdec.ptr502.sum = add i64 undef, 16 br label %for.body293 @@ -68,7 +68,7 @@ for.body293: ; preds = %for.body293, %for.c %LineSadBlk1.01587 = phi i32 [ 0, %for.cond290.preheader ], [ %add402, %for.body293 ] %LineSadBlk3.01586 = phi i32 [ 0, %for.cond290.preheader ], [ %add514, %for.body293 ] %LineSadBlk2.01585 = phi i32 [ 0, %for.cond290.preheader ], [ %add458, %for.body293 ] - %6 = load i16* %refptr.11590, align 2, !tbaa !3 + %6 = load i16* %refptr.11590, align 2 %conv294 = zext i16 %6 to i32 %mul295 = mul nsw i32 %conv294, %2 %add296 = add nsw i32 %mul295, %3 @@ -78,16 +78,16 @@ for.body293: ; preds = %for.body293, %for.c %cond.i.i1514 = select i1 %cmp.i.i1513, i32 %add297, i32 0 %cmp.i4.i1515 = icmp slt i32 %cond.i.i1514, %1 %cond.i5.i1516 = select i1 %cmp.i4.i1515, i32 %cond.i.i1514, i32 %1 - %7 = load i16* %srcptr.41591, align 2, !tbaa !3 + %7 = load i16* %srcptr.41591, align 2 %conv300 = zext i16 %7 to i32 %sub301 = sub nsw i32 %cond.i5.i1516, %conv300 %idxprom302 = sext i32 %sub301 to i64 %arrayidx303 = getelementptr inbounds i32* %cond, i64 %idxprom302 - %8 = load i32* %arrayidx303, align 4, !tbaa !0 + %8 = load i32* %arrayidx303, align 4 %add304 = add nsw i32 %8, %LineSadBlk0.01588 - %9 = load i32* undef, align 4, !tbaa !0 + %9 = load i32* undef, align 4 %add318 = add nsw i32 %add304, %9 - %10 = load i16* undef, align 2, !tbaa !3 + %10 = load i16* undef, align 2 %conv321 = zext i16 %10 to i32 %mul322 = mul nsw i32 %conv321, %2 %add323 = add nsw i32 %mul322, %3 @@ -100,22 +100,22 @@ for.body293: ; preds = %for.body293, %for.c %sub329 = sub nsw i32 %cond.i5.i1508, 0 %idxprom330 = sext i32 %sub329 to i64 %arrayidx331 = getelementptr inbounds i32* %cond, i64 %idxprom330 - %11 = load i32* %arrayidx331, align 4, !tbaa !0 + %11 = load i32* %arrayidx331, align 4 %add332 = add nsw i32 %add318, %11 %cmp.i.i1501 = icmp sgt i32 undef, 0 %cond.i.i1502 = select i1 %cmp.i.i1501, i32 undef, i32 0 %cmp.i4.i1503 = icmp slt i32 %cond.i.i1502, %1 %cond.i5.i1504 = select i1 %cmp.i4.i1503, i32 %cond.i.i1502, i32 %1 %incdec.ptr341 = getelementptr inbounds i16* %srcptr.41591, i64 4 - %12 = load i16* null, align 2, !tbaa !3 + %12 = load i16* null, align 2 %conv342 = zext i16 %12 to i32 %sub343 = sub nsw i32 %cond.i5.i1504, %conv342 %idxprom344 = sext i32 %sub343 to i64 %arrayidx345 = getelementptr inbounds i32* %cond, i64 %idxprom344 - %13 = load i32* %arrayidx345, align 4, !tbaa !0 + %13 = load i32* %arrayidx345, align 4 %add346 = add nsw i32 %add332, %13 %incdec.ptr348 = getelementptr inbounds i16* %refptr.11590, i64 5 - %14 = load i16* null, align 2, !tbaa !3 + %14 = load i16* null, align 2 %conv349 = zext i16 %14 to i32 %mul350 = mul nsw i32 %conv349, %2 %add351 = add nsw i32 %mul350, %3 @@ -126,15 +126,15 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1499 = icmp slt i32 %cond.i.i1498, %1 %cond.i5.i1500 = select i1 %cmp.i4.i1499, i32 %cond.i.i1498, i32 %1 %incdec.ptr355 = getelementptr inbounds i16* %srcptr.41591, i64 5 - %15 = load i16* %incdec.ptr341, align 2, !tbaa !3 + %15 = load i16* %incdec.ptr341, align 2 %conv356 = zext i16 %15 to i32 %sub357 = sub nsw i32 %cond.i5.i1500, %conv356 %idxprom358 = sext i32 %sub357 to i64 %arrayidx359 = getelementptr inbounds i32* %cond, i64 %idxprom358 - %16 = load i32* %arrayidx359, align 4, !tbaa !0 + %16 = load i32* %arrayidx359, align 4 %add360 = add nsw i32 %16, %LineSadBlk1.01587 %incdec.ptr362 = getelementptr inbounds i16* %refptr.11590, i64 6 - %17 = load i16* %incdec.ptr348, align 2, !tbaa !3 + %17 = load i16* %incdec.ptr348, align 2 %conv363 = zext i16 %17 to i32 %mul364 = mul nsw i32 %conv363, %2 %add365 = add nsw i32 %mul364, %3 @@ -145,15 +145,15 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1495 = icmp slt i32 %cond.i.i1494, %1 %cond.i5.i1496 = select i1 %cmp.i4.i1495, i32 %cond.i.i1494, i32 %1 %incdec.ptr369 = getelementptr inbounds i16* %srcptr.41591, i64 6 - %18 = load i16* %incdec.ptr355, align 2, !tbaa !3 + %18 = load i16* %incdec.ptr355, align 2 %conv370 = zext i16 %18 to i32 %sub371 = sub nsw i32 %cond.i5.i1496, %conv370 %idxprom372 = sext i32 %sub371 to i64 %arrayidx373 = getelementptr inbounds i32* %cond, i64 %idxprom372 - %19 = load i32* %arrayidx373, align 4, !tbaa !0 + %19 = load i32* %arrayidx373, align 4 %add374 = add nsw i32 %add360, %19 %incdec.ptr376 = getelementptr inbounds i16* %refptr.11590, i64 7 - %20 = load i16* %incdec.ptr362, align 2, !tbaa !3 + %20 = load i16* %incdec.ptr362, align 2 %conv377 = zext i16 %20 to i32 %mul378 = mul nsw i32 %conv377, %2 %add379 = add nsw i32 %mul378, %3 @@ -164,14 +164,14 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1491 = icmp slt i32 %cond.i.i1490, %1 %cond.i5.i1492 = select i1 %cmp.i4.i1491, i32 %cond.i.i1490, i32 %1 %incdec.ptr383 = getelementptr inbounds i16* %srcptr.41591, i64 7 - %21 = load i16* %incdec.ptr369, align 2, !tbaa !3 + %21 = load i16* %incdec.ptr369, align 2 %conv384 = zext i16 %21 to i32 %sub385 = sub nsw i32 %cond.i5.i1492, %conv384 %idxprom386 = sext i32 %sub385 to i64 %arrayidx387 = getelementptr inbounds i32* %cond, i64 %idxprom386 - %22 = load i32* %arrayidx387, align 4, !tbaa !0 + %22 = load i32* %arrayidx387, align 4 %add388 = add nsw i32 %add374, %22 - %23 = load i16* %incdec.ptr376, align 2, !tbaa !3 + %23 = load i16* %incdec.ptr376, align 2 %conv391 = zext i16 %23 to i32 %mul392 = mul nsw i32 %conv391, %2 %add395 = add nsw i32 0, %5 @@ -180,25 +180,25 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1487 = icmp slt i32 %cond.i.i1486, %1 %cond.i5.i1488 = select i1 %cmp.i4.i1487, i32 %cond.i.i1486, i32 %1 %incdec.ptr397 = getelementptr inbounds i16* %srcptr.41591, i64 8 - %24 = load i16* %incdec.ptr383, align 2, !tbaa !3 + %24 = load i16* %incdec.ptr383, align 2 %conv398 = zext i16 %24 to i32 %sub399 = sub nsw i32 %cond.i5.i1488, %conv398 %idxprom400 = sext i32 %sub399 to i64 %arrayidx401 = getelementptr inbounds i32* %cond, i64 %idxprom400 - %25 = load i32* %arrayidx401, align 4, !tbaa !0 + %25 = load i32* %arrayidx401, align 4 %add402 = add nsw i32 %add388, %25 %incdec.ptr404 = getelementptr inbounds i16* %refptr.11590, i64 9 %cmp.i4.i1483 = icmp slt i32 undef, %1 %cond.i5.i1484 = select i1 %cmp.i4.i1483, i32 undef, i32 %1 - %26 = load i16* %incdec.ptr397, align 2, !tbaa !3 + %26 = load i16* %incdec.ptr397, align 2 %conv412 = zext i16 %26 to i32 %sub413 = sub nsw i32 %cond.i5.i1484, %conv412 %idxprom414 = sext i32 %sub413 to i64 %arrayidx415 = getelementptr inbounds i32* %cond, i64 %idxprom414 - %27 = load i32* %arrayidx415, align 4, !tbaa !0 + %27 = load i32* %arrayidx415, align 4 %add416 = add nsw i32 %27, %LineSadBlk2.01585 %incdec.ptr418 = getelementptr inbounds i16* %refptr.11590, i64 10 - %28 = load i16* %incdec.ptr404, align 2, !tbaa !3 + %28 = load i16* %incdec.ptr404, align 2 %conv419 = zext i16 %28 to i32 %mul420 = mul nsw i32 %conv419, %2 %add421 = add nsw i32 %mul420, %3 @@ -212,10 +212,10 @@ for.body293: ; preds = %for.body293, %for.c %sub427 = sub nsw i32 %cond.i5.i1480, 0 %idxprom428 = sext i32 %sub427 to i64 %arrayidx429 = getelementptr inbounds i32* %cond, i64 %idxprom428 - %29 = load i32* %arrayidx429, align 4, !tbaa !0 + %29 = load i32* %arrayidx429, align 4 %add430 = add nsw i32 %add416, %29 %incdec.ptr432 = getelementptr inbounds i16* %refptr.11590, i64 11 - %30 = load i16* %incdec.ptr418, align 2, !tbaa !3 + %30 = load i16* %incdec.ptr418, align 2 %conv433 = zext i16 %30 to i32 %mul434 = mul nsw i32 %conv433, %2 %add435 = add nsw i32 %mul434, %3 @@ -225,15 +225,15 @@ for.body293: ; preds = %for.body293, %for.c %cond.i.i1474 = select i1 %cmp.i.i1473, i32 %add437, i32 0 %cmp.i4.i1475 = icmp slt i32 %cond.i.i1474, %1 %cond.i5.i1476 = select i1 %cmp.i4.i1475, i32 %cond.i.i1474, i32 %1 - %31 = load i16* %incdec.ptr425, align 2, !tbaa !3 + %31 = load i16* %incdec.ptr425, align 2 %conv440 = zext i16 %31 to i32 %sub441 = sub nsw i32 %cond.i5.i1476, %conv440 %idxprom442 = sext i32 %sub441 to i64 %arrayidx443 = getelementptr inbounds i32* %cond, i64 %idxprom442 - %32 = load i32* %arrayidx443, align 4, !tbaa !0 + %32 = load i32* %arrayidx443, align 4 %add444 = add nsw i32 %add430, %32 %incdec.ptr446 = getelementptr inbounds i16* %refptr.11590, i64 12 - %33 = load i16* %incdec.ptr432, align 2, !tbaa !3 + %33 = load i16* %incdec.ptr432, align 2 %conv447 = zext i16 %33 to i32 %mul448 = mul nsw i32 %conv447, %2 %add449 = add nsw i32 %mul448, %3 @@ -244,15 +244,15 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1471 = icmp slt i32 %cond.i.i1470, %1 %cond.i5.i1472 = select i1 %cmp.i4.i1471, i32 %cond.i.i1470, i32 %1 %incdec.ptr453 = getelementptr inbounds i16* %srcptr.41591, i64 12 - %34 = load i16* undef, align 2, !tbaa !3 + %34 = load i16* undef, align 2 %conv454 = zext i16 %34 to i32 %sub455 = sub nsw i32 %cond.i5.i1472, %conv454 %idxprom456 = sext i32 %sub455 to i64 %arrayidx457 = getelementptr inbounds i32* %cond, i64 %idxprom456 - %35 = load i32* %arrayidx457, align 4, !tbaa !0 + %35 = load i32* %arrayidx457, align 4 %add458 = add nsw i32 %add444, %35 %incdec.ptr460 = getelementptr inbounds i16* %refptr.11590, i64 13 - %36 = load i16* %incdec.ptr446, align 2, !tbaa !3 + %36 = load i16* %incdec.ptr446, align 2 %conv461 = zext i16 %36 to i32 %mul462 = mul nsw i32 %conv461, %2 %add463 = add nsw i32 %mul462, %3 @@ -263,12 +263,12 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1467 = icmp slt i32 %cond.i.i1466, %1 %cond.i5.i1468 = select i1 %cmp.i4.i1467, i32 %cond.i.i1466, i32 %1 %incdec.ptr467 = getelementptr inbounds i16* %srcptr.41591, i64 13 - %37 = load i16* %incdec.ptr453, align 2, !tbaa !3 + %37 = load i16* %incdec.ptr453, align 2 %conv468 = zext i16 %37 to i32 %sub469 = sub nsw i32 %cond.i5.i1468, %conv468 %idxprom470 = sext i32 %sub469 to i64 %arrayidx471 = getelementptr inbounds i32* %cond, i64 %idxprom470 - %38 = load i32* %arrayidx471, align 4, !tbaa !0 + %38 = load i32* %arrayidx471, align 4 %add472 = add nsw i32 %38, %LineSadBlk3.01586 %incdec.ptr474 = getelementptr inbounds i16* %refptr.11590, i64 14 %add477 = add nsw i32 0, %3 @@ -279,15 +279,15 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1463 = icmp slt i32 %cond.i.i1462, %1 %cond.i5.i1464 = select i1 %cmp.i4.i1463, i32 %cond.i.i1462, i32 %1 %incdec.ptr481 = getelementptr inbounds i16* %srcptr.41591, i64 14 - %39 = load i16* %incdec.ptr467, align 2, !tbaa !3 + %39 = load i16* %incdec.ptr467, align 2 %conv482 = zext i16 %39 to i32 %sub483 = sub nsw i32 %cond.i5.i1464, %conv482 %idxprom484 = sext i32 %sub483 to i64 %arrayidx485 = getelementptr inbounds i32* %cond, i64 %idxprom484 - %40 = load i32* %arrayidx485, align 4, !tbaa !0 + %40 = load i32* %arrayidx485, align 4 %add486 = add nsw i32 %add472, %40 %incdec.ptr488 = getelementptr inbounds i16* %refptr.11590, i64 15 - %41 = load i16* %incdec.ptr474, align 2, !tbaa !3 + %41 = load i16* %incdec.ptr474, align 2 %conv489 = zext i16 %41 to i32 %mul490 = mul nsw i32 %conv489, %2 %add491 = add nsw i32 %mul490, %3 @@ -298,14 +298,14 @@ for.body293: ; preds = %for.body293, %for.c %cmp.i4.i1459 = icmp slt i32 %cond.i.i1458, %1 %cond.i5.i1460 = select i1 %cmp.i4.i1459, i32 %cond.i.i1458, i32 %1 %incdec.ptr495 = getelementptr inbounds i16* %srcptr.41591, i64 15 - %42 = load i16* %incdec.ptr481, align 2, !tbaa !3 + %42 = load i16* %incdec.ptr481, align 2 %conv496 = zext i16 %42 to i32 %sub497 = sub nsw i32 %cond.i5.i1460, %conv496 %idxprom498 = sext i32 %sub497 to i64 %arrayidx499 = getelementptr inbounds i32* %cond, i64 %idxprom498 - %43 = load i32* %arrayidx499, align 4, !tbaa !0 + %43 = load i32* %arrayidx499, align 4 %add500 = add nsw i32 %add486, %43 - %44 = load i16* %incdec.ptr488, align 2, !tbaa !3 + %44 = load i16* %incdec.ptr488, align 2 %conv503 = zext i16 %44 to i32 %mul504 = mul nsw i32 %conv503, %2 %add505 = add nsw i32 %mul504, %3 @@ -315,22 +315,22 @@ for.body293: ; preds = %for.body293, %for.c %cond.i.i1454 = select i1 %cmp.i.i1453, i32 %add507, i32 0 %cmp.i4.i1455 = icmp slt i32 %cond.i.i1454, %1 %cond.i5.i1456 = select i1 %cmp.i4.i1455, i32 %cond.i.i1454, i32 %1 - %45 = load i16* %incdec.ptr495, align 2, !tbaa !3 + %45 = load i16* %incdec.ptr495, align 2 %conv510 = zext i16 %45 to i32 %sub511 = sub nsw i32 %cond.i5.i1456, %conv510 %idxprom512 = sext i32 %sub511 to i64 %arrayidx513 = getelementptr inbounds i32* %cond, i64 %idxprom512 - %46 = load i32* %arrayidx513, align 4, !tbaa !0 + %46 = load i32* %arrayidx513, align 4 %add514 = add nsw i32 %add500, %46 %add.ptr517 = getelementptr inbounds i16* %refptr.11590, i64 %incdec.ptr502.sum %exitcond1692 = icmp eq i32 undef, 4 br i1 %exitcond1692, label %for.end520, label %for.body293 for.end520: ; preds = %for.body293 - store i32 %add346, i32* undef, align 4, !tbaa !0 - store i32 %add402, i32* undef, align 4, !tbaa !0 - store i32 %add458, i32* undef, align 4, !tbaa !0 - store i32 %add514, i32* null, align 4, !tbaa !0 + store i32 %add346, i32* undef, align 4 + store i32 %add402, i32* undef, align 4 + store i32 %add458, i32* undef, align 4 + store i32 %add514, i32* null, align 4 br i1 undef, label %for.end543, label %for.cond290.preheader for.end543: ; preds = %for.end520 @@ -400,10 +400,5 @@ for.end999: ; preds = %for.inc997 ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"short", metadata !1} diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index f1cbc5afa8ac..a9b4b3607830 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -1,9 +1,9 @@ -; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64 +; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32 +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64 declare void @foo() -define i32 @test_cr2() nounwind { +define i32 @test_cr2() nounwind uwtable { entry: %ret = alloca i32, align 4 %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind @@ -18,14 +18,19 @@ entry: ; PPC32: mfcr 12 ; PPC32-NEXT: stw 12, 24(31) ; PPC32: lwz 12, 24(31) -; PPC32-NEXT: mtcrf 32, 12 +; PPC32-NEXT: mtocrf 32, 12 +; PPC64: .cfi_startproc ; PPC64: mfcr 12 ; PPC64: stw 12, 8(1) ; PPC64: stdu 1, -[[AMT:[0-9]+]](1) +; PPC64: .cfi_def_cfa_offset 128 +; PPC64: .cfi_offset lr, 16 +; PPC64: .cfi_offset cr2, 8 ; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64: mtcrf 32, 12 +; PPC64: mtocrf 32, 12 +; PPC64: .cfi_endproc define i32 @test_cr234() nounwind { entry: @@ -42,16 +47,16 @@ entry: ; PPC32: mfcr 12 ; PPC32-NEXT: stw 12, 24(31) ; PPC32: lwz 12, 24(31) -; PPC32-NEXT: mtcrf 32, 12 -; PPC32-NEXT: mtcrf 16, 12 -; PPC32-NEXT: mtcrf 8, 12 +; PPC32-NEXT: mtocrf 32, 12 +; PPC32-NEXT: mtocrf 16, 12 +; PPC32-NEXT: mtocrf 8, 12 ; PPC64: mfcr 12 ; PPC64: stw 12, 8(1) ; PPC64: stdu 1, -[[AMT:[0-9]+]](1) ; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64: mtcrf 32, 12 -; PPC64: mtcrf 16, 12 -; PPC64: mtcrf 8, 12 +; PPC64: mtocrf 32, 12 +; PPC64: mtocrf 16, 12 +; PPC64: mtocrf 8, 12 diff --git a/test/CodeGen/PowerPC/ctr-cleanup.ll b/test/CodeGen/PowerPC/ctr-cleanup.ll index 04e4ffb0d48d..1a669eb051d8 100644 --- a/test/CodeGen/PowerPC/ctr-cleanup.ll +++ b/test/CodeGen/PowerPC/ctr-cleanup.ll @@ -22,4 +22,4 @@ for.end: ; preds = %for.body, %entry ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/ctrloop-asm.ll b/test/CodeGen/PowerPC/ctrloop-asm.ll new file mode 100644 index 000000000000..28afbf2babcf --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-asm.ll @@ -0,0 +1,38 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-freebsd10.0" +; RUN: llc < %s -march=ppc64 | FileCheck %s + +define void @test1(i32 %c) nounwind { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + call void asm sideeffect "", "~{r5}"() nounwind + %inc = add nsw i32 %i.01, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +; CHECK: @test1 +; CHECK: mtctr +} + +define void @test2(i32 %c) nounwind { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + call void asm sideeffect "", "~{ctr}"() nounwind + %inc = add nsw i32 %i.01, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +; CHECK: @test2 +; CHECK-NOT: mtctr +} + diff --git a/test/CodeGen/PowerPC/ctrloop-cpsgn.ll b/test/CodeGen/PowerPC/ctrloop-cpsgn.ll new file mode 100644 index 000000000000..2f0440912cc9 --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-cpsgn.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -mcpu=ppc | FileCheck %s + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-linux-gnu" + +define ppc_fp128 @foo(ppc_fp128* nocapture %n, ppc_fp128 %d) nounwind readonly { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %x.05 = phi ppc_fp128 [ %d, %entry ], [ %conv, %for.body ] + %arrayidx = getelementptr inbounds ppc_fp128* %n, i32 %i.06 + %0 = load ppc_fp128* %arrayidx, align 8 + %conv = tail call ppc_fp128 @copysignl(ppc_fp128 %x.05, ppc_fp128 %d) nounwind readonly + %inc = add nsw i32 %i.06, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret ppc_fp128 %conv +} + +declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) #0 + +; CHECK: @foo +; CHECK-NOT: mtctr + diff --git a/test/CodeGen/PowerPC/ctrloop-fp64.ll b/test/CodeGen/PowerPC/ctrloop-fp64.ll new file mode 100644 index 000000000000..77555ac58de2 --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-fp64.ll @@ -0,0 +1,60 @@ +; RUN: llc < %s -mcpu=ppc | FileCheck %s + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-linux-gnu" + +define i64 @foo(double* nocapture %n) nounwind readonly { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ] + %arrayidx = getelementptr inbounds double* %n, i32 %i.06 + %0 = load double* %arrayidx, align 8 + %conv = sitofp i64 %x.05 to double + %add = fadd double %conv, %0 + %conv1 = fptosi double %add to i64 + %inc = add nsw i32 %i.06, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i64 %conv1 +} + +; CHECK: @foo +; CHECK-NOT: mtctr + +@init_value = global double 1.000000e+00, align 8 +@data64 = global [8000 x i64] zeroinitializer, align 8 + +define i32 @main(i32 %argc, i8** nocapture %argv) { +entry: + %0 = load double* @init_value, align 8 + %conv = fptosi double %0 to i64 + %broadcast.splatinsert.i = insertelement <2 x i64> undef, i64 %conv, i32 0 + %broadcast.splat.i = shufflevector <2 x i64> %broadcast.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer + br label %vector.body.i + +vector.body.i: ; preds = %vector.body.i, %entry + %index.i = phi i32 [ 0, %entry ], [ %index.next.i, %vector.body.i ] + %next.gep.i = getelementptr [8000 x i64]* @data64, i32 0, i32 %index.i + %1 = bitcast i64* %next.gep.i to <2 x i64>* + store <2 x i64> %broadcast.splat.i, <2 x i64>* %1, align 8 + %next.gep.sum24.i = or i32 %index.i, 2 + %2 = getelementptr [8000 x i64]* @data64, i32 0, i32 %next.gep.sum24.i + %3 = bitcast i64* %2 to <2 x i64>* + store <2 x i64> %broadcast.splat.i, <2 x i64>* %3, align 8 + %index.next.i = add i32 %index.i, 4 + %4 = icmp eq i32 %index.next.i, 8000 + br i1 %4, label %_Z4fillIPxxEvT_S1_T0_.exit, label %vector.body.i + +_Z4fillIPxxEvT_S1_T0_.exit: ; preds = %vector.body.i + ret i32 0 +} + +; CHECK: @main +; CHECK: __fixdfdi +; CHECK: mtctr + diff --git a/test/CodeGen/PowerPC/ctrloop-i64.ll b/test/CodeGen/PowerPC/ctrloop-i64.ll new file mode 100644 index 000000000000..9e01392a458f --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-i64.ll @@ -0,0 +1,93 @@ +; RUN: llc < %s -mcpu=ppc | FileCheck %s + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-linux-gnu" + +define i64 @foo(i64* nocapture %n, i64 %d) nounwind readonly { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ] + %arrayidx = getelementptr inbounds i64* %n, i32 %i.06 + %0 = load i64* %arrayidx, align 8 + %conv = udiv i64 %x.05, %d + %conv1 = add i64 %conv, %0 + %inc = add nsw i32 %i.06, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i64 %conv1 +} + +; CHECK: @foo +; CHECK-NOT: mtctr + +define i64 @foo2(i64* nocapture %n, i64 %d) nounwind readonly { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ] + %arrayidx = getelementptr inbounds i64* %n, i32 %i.06 + %0 = load i64* %arrayidx, align 8 + %conv = sdiv i64 %x.05, %d + %conv1 = add i64 %conv, %0 + %inc = add nsw i32 %i.06, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i64 %conv1 +} + +; CHECK: @foo2 +; CHECK-NOT: mtctr + +define i64 @foo3(i64* nocapture %n, i64 %d) nounwind readonly { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ] + %arrayidx = getelementptr inbounds i64* %n, i32 %i.06 + %0 = load i64* %arrayidx, align 8 + %conv = urem i64 %x.05, %d + %conv1 = add i64 %conv, %0 + %inc = add nsw i32 %i.06, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i64 %conv1 +} + +; CHECK: @foo3 +; CHECK-NOT: mtctr + +define i64 @foo4(i64* nocapture %n, i64 %d) nounwind readonly { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %x.05 = phi i64 [ 0, %entry ], [ %conv1, %for.body ] + %arrayidx = getelementptr inbounds i64* %n, i32 %i.06 + %0 = load i64* %arrayidx, align 8 + %conv = srem i64 %x.05, %d + %conv1 = add i64 %conv, %0 + %inc = add nsw i32 %i.06, 1 + %exitcond = icmp eq i32 %inc, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i64 %conv1 +} + +; CHECK: @foo4 +; CHECK-NOT: mtctr + diff --git a/test/CodeGen/PowerPC/ctrloop-large-ec.ll b/test/CodeGen/PowerPC/ctrloop-large-ec.ll new file mode 100644 index 000000000000..c18bdabdb03a --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-large-ec.ll @@ -0,0 +1,23 @@ +; RUN: llc -mcpu=ppc32 < %s +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-linux-gnu" + +define void @fn1() { +entry: + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %inc3 = phi i64 [ %inc, %for.body ], [ undef, %entry ] + %inc = add nsw i64 %inc3, 1 + %tobool = icmp eq i64 %inc, 0 + br i1 %tobool, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count. +; CHECK: @fn1 +; CHECK-NOT: mtctr +; CHECK: blr + diff --git a/test/CodeGen/PowerPC/ctrloop-le.ll b/test/CodeGen/PowerPC/ctrloop-le.ll new file mode 100644 index 000000000000..7b8185ed5261 --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-le.ll @@ -0,0 +1,441 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc < %s -march=ppc64 | FileCheck %s + +; CHECK: test_pos1_ir_sle +; CHECK: bdnz +; a < b +define void @test_pos1_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 28395, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 28395, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_ir_sle +; CHECK: bdnz +; a < b +define void @test_pos2_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 9073, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 9073, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_ir_sle +; CHECK: bdnz +; a < b +define void @test_pos4_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 21956, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 21956, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_ir_sle +; CHECK: bdnz +; a < b +define void @test_pos8_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 16782, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 16782, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_ir_sle +; CHECK: bdnz +; a < b +define void @test_pos16_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 19097, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 19097, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos1_ri_sle +; CHECK: bdnz +; a < b +define void @test_pos1_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, 14040 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp sle i32 %inc, 14040 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_ri_sle +; CHECK: bdnz +; a < b +define void @test_pos2_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, 13710 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp sle i32 %inc, 13710 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_ri_sle +; CHECK: bdnz +; a < b +define void @test_pos4_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, 9920 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp sle i32 %inc, 9920 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_ri_sle +; CHECK: bdnz +; a < b +define void @test_pos8_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, 18924 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp sle i32 %inc, 18924 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_ri_sle +; CHECK: bdnz +; a < b +define void @test_pos16_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, 11812 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp sle i32 %inc, 11812 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos1_rr_sle +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos1_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_rr_sle +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos2_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_rr_sle +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos4_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_rr_sle +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos8_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_rr_sle +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos16_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp sle i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp sle i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/CodeGen/PowerPC/ctrloop-lt.ll b/test/CodeGen/PowerPC/ctrloop-lt.ll new file mode 100644 index 000000000000..eaab61a826d9 --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-lt.ll @@ -0,0 +1,438 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc < %s -march=ppc64 | FileCheck %s + +; CHECK: test_pos1_ir_slt +; CHECK: bdnz +; a < b +define void @test_pos1_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 8531, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 8531, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_ir_slt +; FIXME: Support this loop! +; CHECK: bdnz +; a < b +define void @test_pos2_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 9152, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 9152, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_ir_slt +; FIXME: Support this loop! +; CHECK: bdnz +; a < b +define void @test_pos4_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 18851, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 18851, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_ir_slt +; CHECK: bdnz +; a < b +define void @test_pos8_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 25466, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 25466, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_ir_slt +; CHECK: bdnz +; a < b +define void @test_pos16_ir_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 9295, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 9295, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos1_ri_slt +; CHECK: bdnz +; a < b +define void @test_pos1_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 31236 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp slt i32 %inc, 31236 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_ri_slt +; CHECK: bdnz +; a < b +define void @test_pos2_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 22653 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp slt i32 %inc, 22653 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_ri_slt +; CHECK: bdnz +; a < b +define void @test_pos4_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 1431 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp slt i32 %inc, 1431 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_ri_slt +; CHECK: bdnz +; a < b +define void @test_pos8_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 22403 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp slt i32 %inc, 22403 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_ri_slt +; CHECK: bdnz +; a < b +define void @test_pos16_ri_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 21715 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp slt i32 %inc, 21715 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos1_rr_slt +; CHECK: bdnz +; a < b +define void @test_pos1_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_rr_slt +; CHECK: bdnz +; a < b +define void @test_pos2_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_rr_slt +; CHECK: bdnz +; a < b +define void @test_pos4_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_rr_slt +; CHECK: bdnz +; a < b +define void @test_pos8_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_rr_slt +; CHECK: bdnz +; a < b +define void @test_pos16_rr_slt(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp slt i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/CodeGen/PowerPC/ctrloop-ne.ll b/test/CodeGen/PowerPC/ctrloop-ne.ll new file mode 100644 index 000000000000..636030a15dd2 --- /dev/null +++ b/test/CodeGen/PowerPC/ctrloop-ne.ll @@ -0,0 +1,449 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc < %s -march=ppc64 | FileCheck %s + +; CHECK: test_pos1_ir_ne +; CHECK: bdnz +; a < b +define void @test_pos1_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 32623, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 32623, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_ir_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos2_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 29554, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 29554, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_ir_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos4_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 15692, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 15692, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_ir_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos8_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 10449, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 10449, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_ir_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos16_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 32087, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ 32087, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos1_ri_ne +; CHECK: bdnz +; a < b +define void @test_pos1_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 3472 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp ne i32 %inc, 3472 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_ri_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos2_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 8730 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp ne i32 %inc, 8730 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_ri_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos4_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 1493 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp ne i32 %inc, 1493 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_ri_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos8_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 1706 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp ne i32 %inc, 1706 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_ri_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos16_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, 1886 + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp ne i32 %inc, 1886 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos1_rr_ne +; CHECK: bdnz +; a < b +define void @test_pos1_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 1 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos2_rr_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos2_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 2 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos4_rr_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos4_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 4 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos8_rr_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos8_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 8 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + + + +; CHECK: test_pos16_rr_ne +; FIXME: Support this loop! +; CHECK-NOT: bdnz +; a < b +define void @test_pos16_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind { +entry: + %cmp3 = icmp slt i32 %a, %b + br i1 %cmp3, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 + %0 = load i8* %arrayidx, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 1 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %arrayidx, align 1 + %inc = add nsw i32 %i.04, 16 + %cmp = icmp ne i32 %inc, %b + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret void +} + diff --git a/test/CodeGen/PowerPC/ctrloops.ll b/test/CodeGen/PowerPC/ctrloops.ll index f11e332d5fbc..ca00f687aa4e 100644 --- a/test/CodeGen/PowerPC/ctrloops.ll +++ b/test/CodeGen/PowerPC/ctrloops.ll @@ -22,7 +22,7 @@ for.end: ; preds = %for.body ; CHECK: @test1 ; CHECK-NOT: or 3, 3, 3 ; CHECK: mtctr -; CHECK-NOT: addi +; CHECK-NOT: addi {[0-9]+} ; CHECK-NOT: cmplwi ; CHECK: bdnz } @@ -45,7 +45,7 @@ for.end: ; preds = %for.body, %entry ret void ; CHECK: @test2 ; CHECK: mtctr -; CHECK-NOT: addi +; CHECK-NOT: addi {[0-9]+} ; CHECK-NOT: cmplwi ; CHECK: bdnz } @@ -69,7 +69,7 @@ for.end: ; preds = %for.body, %entry ret void ; CHECK: @test3 ; CHECK: mtctr -; CHECK-NOT: addi +; CHECK-NOT: addi {[0-9]+} ; CHECK-NOT: cmplwi ; CHECK: bdnz } diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll index 21e36618c5c1..cb93decac8e9 100644 --- a/test/CodeGen/PowerPC/dbg.ll +++ b/test/CodeGen/PowerPC/dbg.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s -; CHECK: main: +; CHECK-LABEL: main: target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -15,18 +15,19 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!22} -!0 = metadata !{i32 720913, i32 12, metadata !6, metadata !"clang version 3.1", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 720913, metadata !21, i32 12, metadata !"clang version 3.1", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !"", metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} -!5 = metadata !{i32 720942, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13} ; [ DW_TAG_subprogram ] -!6 = metadata !{i32 720937, metadata !"dbg.c", metadata !"/src", null} ; [ DW_TAG_file_type ] -!7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 720942, metadata !21, null, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13, i32 0} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 720937, metadata !21} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 720917, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !8 = metadata !{metadata !9, metadata !9, metadata !10} -!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!10 = metadata !{i32 720911, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] -!11 = metadata !{i32 720911, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ] -!12 = metadata !{i32 720932, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!10 = metadata !{i32 720911, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] +!11 = metadata !{i32 720911, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ] +!12 = metadata !{i32 720932, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] !13 = metadata !{metadata !14} !14 = metadata !{metadata !15, metadata !16} !15 = metadata !{i32 721153, metadata !5, metadata !"argc", metadata !6, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] @@ -34,5 +35,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !17 = metadata !{i32 1, i32 14, metadata !5, null} !18 = metadata !{i32 1, i32 26, metadata !5, null} !19 = metadata !{i32 2, i32 3, metadata !20, null} -!20 = metadata !{i32 720907, metadata !5, i32 1, i32 34, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] - +!20 = metadata !{i32 720907, metadata !21, metadata !5, i32 1, i32 34, i32 0} ; [ DW_TAG_lexical_block ] +!21 = metadata !{metadata !"dbg.c", metadata !"/src"} +!22 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll new file mode 100644 index 000000000000..a5d45b8e94a0 --- /dev/null +++ b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.s = type { i32, i32 } + +declare void @bar(i32*, i32*) #0 + +define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 { +entry: + %0 = zext i32 %n to i64 + %vla = alloca i32, i64 %0, align 128 + %vla1 = alloca i32, i64 %0, align 128 + %a2 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %1 = load i32* %a2, align 4 + store i32 %1, i32* %vla1, align 128 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %2 = load i32* %b, align 4 + %arrayidx3 = getelementptr inbounds i32* %vla1, i64 1 + store i32 %2, i32* %arrayidx3, align 4 + call void @bar(i32* %vla1, i32* %vla) #0 + ret void + +; CHECK-LABEL: @goo + +; CHECK-DAG: li [[REG1:[0-9]+]], -128 +; CHECK-DAG: neg [[REG2:[0-9]+]], +; CHECK: and [[REG1]], [[REG2]], [[REG1]] +; CHECK: stdux {{[0-9]+}}, 1, [[REG1]] + +; CHECK: blr + +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/emptystruct.ll b/test/CodeGen/PowerPC/emptystruct.ll index 36b4abd2bfad..47cfadd0a7bb 100644 --- a/test/CodeGen/PowerPC/emptystruct.ll +++ b/test/CodeGen/PowerPC/emptystruct.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s ; This tests correct handling of empty aggregate parameters and return values. ; An empty parameter passed by value does not consume a protocol register or @@ -25,9 +25,8 @@ entry: ret void } -; CHECK: callee: +; CHECK-LABEL: callee: ; CHECK: std 4, -; CHECK: std 3, ; CHECK-NOT: std 5, ; CHECK-NOT: std 6, ; CHECK: blr @@ -43,9 +42,8 @@ entry: ret void } -; CHECK: caller: +; CHECK-LABEL: caller: ; CHECK: addi 4, -; CHECK: std 3, ; CHECK-NOT: std 5, ; CHECK-NOT: std 6, ; CHECK: bl callee diff --git a/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll b/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll new file mode 100644 index 000000000000..7bdda0494b8f --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] } +%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] } + +@arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4 +@A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4 +@B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4 + +define i32* @t1() nounwind { +entry: +; ELF64: t1 + %addr = alloca i32*, align 4 + store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4 +; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 124 + %0 = load i32** %addr, align 4 + ret i32* %0 +} + +define i32* @t2() nounwind { +entry: +; ELF64: t2 + %addr = alloca i32*, align 4 + store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4 +; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1148 + %0 = load i32** %addr, align 4 + ret i32* %0 +} + +define i32* @t3() nounwind { +entry: +; ELF64: t3 + %addr = alloca i32*, align 4 + store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4 +; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 140 + %0 = load i32** %addr, align 4 + ret i32* %0 +} + +define i32* @t4() nounwind { +entry: +; ELF64: t4 + %addr = alloca i32*, align 4 + store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4 +; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1284 + %0 = load i32** %addr, align 4 + ret i32* %0 +} diff --git a/test/CodeGen/PowerPC/fast-isel-binary.ll b/test/CodeGen/PowerPC/fast-isel-binary.ll new file mode 100644 index 000000000000..43a6cd085055 --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-binary.ll @@ -0,0 +1,137 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +; Test add with non-legal types + +define void @add_i8(i8 %a, i8 %b) nounwind ssp { +entry: +; ELF64: add_i8 + %a.addr = alloca i8, align 4 + %0 = add i8 %a, %b +; ELF64: add + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @add_i8_imm(i8 %a) nounwind ssp { +entry: +; ELF64: add_i8_imm + %a.addr = alloca i8, align 4 + %0 = add i8 %a, 22; +; ELF64: addi + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @add_i16(i16 %a, i16 %b) nounwind ssp { +entry: +; ELF64: add_i16 + %a.addr = alloca i16, align 4 + %0 = add i16 %a, %b +; ELF64: add + store i16 %0, i16* %a.addr, align 4 + ret void +} + +define void @add_i16_imm(i16 %a, i16 %b) nounwind ssp { +entry: +; ELF64: add_i16_imm + %a.addr = alloca i16, align 4 + %0 = add i16 %a, 243; +; ELF64: addi + store i16 %0, i16* %a.addr, align 4 + ret void +} + +; Test or with non-legal types + +define void @or_i8(i8 %a, i8 %b) nounwind ssp { +entry: +; ELF64: or_i8 + %a.addr = alloca i8, align 4 + %0 = or i8 %a, %b +; ELF64: or + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @or_i8_imm(i8 %a) nounwind ssp { +entry: +; ELF64: or_i8_imm + %a.addr = alloca i8, align 4 + %0 = or i8 %a, -13; +; ELF64: ori + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @or_i16(i16 %a, i16 %b) nounwind ssp { +entry: +; ELF64: or_i16 + %a.addr = alloca i16, align 4 + %0 = or i16 %a, %b +; ELF64: or + store i16 %0, i16* %a.addr, align 4 + ret void +} + +define void @or_i16_imm(i16 %a) nounwind ssp { +entry: +; ELF64: or_i16_imm + %a.addr = alloca i16, align 4 + %0 = or i16 %a, 273; +; ELF64: ori + store i16 %0, i16* %a.addr, align 4 + ret void +} + +; Test sub with non-legal types + +define void @sub_i8(i8 %a, i8 %b) nounwind ssp { +entry: +; ELF64: sub_i8 + %a.addr = alloca i8, align 4 + %0 = sub i8 %a, %b +; ELF64: subf + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @sub_i8_imm(i8 %a) nounwind ssp { +entry: +; ELF64: sub_i8_imm + %a.addr = alloca i8, align 4 + %0 = sub i8 %a, 22; +; ELF64: addi + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @sub_i16(i16 %a, i16 %b) nounwind ssp { +entry: +; ELF64: sub_i16 + %a.addr = alloca i16, align 4 + %0 = sub i16 %a, %b +; ELF64: subf + store i16 %0, i16* %a.addr, align 4 + ret void +} + +define void @sub_i16_imm(i16 %a) nounwind ssp { +entry: +; ELF64: sub_i16_imm + %a.addr = alloca i16, align 4 + %0 = sub i16 %a, 247; +; ELF64: addi + store i16 %0, i16* %a.addr, align 4 + ret void +} + +define void @sub_i16_badimm(i16 %a) nounwind ssp { +entry: +; ELF64: sub_i16_imm + %a.addr = alloca i16, align 4 + %0 = sub i16 %a, -32768; +; ELF64: subf + store i16 %0, i16* %a.addr, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/fast-isel-br-const.ll b/test/CodeGen/PowerPC/fast-isel-br-const.ll new file mode 100644 index 000000000000..2cfb8a225745 --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-br-const.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { +entry: +; ELF64: t1 + %x = add i32 %a, %b + br i1 1, label %if.then, label %if.else +; ELF64-NOT: b {{\.?}}LBB0_1 + +if.then: ; preds = %entry + call void @foo1() + br label %if.end7 + +if.else: ; preds = %entry + br i1 0, label %if.then2, label %if.else3 +; ELF64: b {{\.?}}LBB0_4 + +if.then2: ; preds = %if.else + call void @foo2() + br label %if.end6 + +if.else3: ; preds = %if.else + %y = sub i32 %a, %b + br i1 1, label %if.then5, label %if.end +; ELF64-NOT: b {{\.?}}LBB0_5 + +if.then5: ; preds = %if.else3 + call void @foo1() + br label %if.end + +if.end: ; preds = %if.then5, %if.else3 + br label %if.end6 + +if.end6: ; preds = %if.end, %if.then2 + br label %if.end7 + +if.end7: ; preds = %if.end6, %if.then + ret i32 0 +} + +declare void @foo1() + +declare void @foo2() diff --git a/test/CodeGen/PowerPC/fast-isel-call.ll b/test/CodeGen/PowerPC/fast-isel-call.ll new file mode 100644 index 000000000000..33a8ba903e3d --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-call.ll @@ -0,0 +1,132 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +define i32 @t1(i8 signext %a) nounwind { + %1 = sext i8 %a to i32 + ret i32 %1 +} + +define i32 @t2(i8 zeroext %a) nounwind { + %1 = zext i8 %a to i32 + ret i32 %1 +} + +define i32 @t3(i16 signext %a) nounwind { + %1 = sext i16 %a to i32 + ret i32 %1 +} + +define i32 @t4(i16 zeroext %a) nounwind { + %1 = zext i16 %a to i32 + ret i32 %1 +} + +define void @foo(i8 %a, i16 %b) nounwind { +; ELF64: foo + %1 = call i32 @t1(i8 signext %a) +; ELF64: extsb + %2 = call i32 @t2(i8 zeroext %a) +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 + %3 = call i32 @t3(i16 signext %b) +; ELF64: extsh + %4 = call i32 @t4(i16 zeroext %b) +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 + +;; A few test to check materialization + %5 = call i32 @t2(i8 zeroext 255) +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 + %6 = call i32 @t4(i16 zeroext 65535) +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 + ret void +} + +define void @foo2() nounwind { + %1 = call signext i16 @t5() + %2 = call zeroext i16 @t6() + %3 = call signext i8 @t7() + %4 = call zeroext i8 @t8() + ret void +} + +declare signext i16 @t5(); +declare zeroext i16 @t6(); +declare signext i8 @t7(); +declare zeroext i8 @t8(); + +define i32 @t10(i32 %argc, i8** nocapture %argv) { +entry: +; ELF64: t10 + %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70) +; ELF64: li 3, 0 +; ELF64: li 4, 248 +; ELF64: li 5, 187 +; ELF64: li 6, 28 +; ELF64: li 7, 40 +; ELF64: li 8, 186 +; ELF64: rldicl 3, 3, 0, 56 +; ELF64: rldicl 4, 4, 0, 56 +; ELF64: rldicl 5, 5, 0, 56 +; ELF64: rldicl 6, 6, 0, 56 +; ELF64: rldicl 7, 7, 0, 56 +; ELF64: rldicl 8, 8, 0, 56 + ret i32 0 +} + +declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext) + +define i32 @bar0(i32 %i) nounwind { + ret i32 0 +} + +; Function pointers are not yet implemented. +;define void @foo3() uwtable { +; %fptr = alloca i32 (i32)*, align 8 +; store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8 +; %1 = load i32 (i32)** %fptr, align 8 +; %call = call i32 %1(i32 0) +; ret void +;} + +; Intrinsic calls not yet implemented, and udiv isn't one for PPC anyway. +;define i32 @LibCall(i32 %a, i32 %b) { +;entry: +; %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] +; ret i32 %tmp1 +;} + +declare void @float_foo(float %f) ssp + +define void @float_const() ssp { +entry: +; ELF64: float_const + call void @float_foo(float 0x401C666660000000) +; ELF64: addis [[REG:[0-9]+]], 2, .LCPI[[SUF:[0-9_]+]]@toc@ha +; ELF64: lfs 1, .LCPI[[SUF]]@toc@l([[REG]]) + ret void +} + +define void @float_reg(float %dummy, float %f) ssp { +entry: +; ELF64: float_reg + call void @float_foo(float %f) +; ELF64: fmr 1, 2 + ret void +} + +declare void @double_foo(double %d) ssp + +define void @double_const() ssp { +entry: +; ELF64: double_const + call void @double_foo(double 0x1397723CCABD0000401C666660000000) +; ELF64: addis [[REG2:[0-9]+]], 2, .LCPI[[SUF2:[0-9_]+]]@toc@ha +; ELF64: lfd 1, .LCPI[[SUF2]]@toc@l([[REG2]]) + ret void +} + +define void @double_reg(double %dummy, double %d) ssp { +entry: +; ELF64: double_reg + call void @double_foo(double %d) +; ELF64: fmr 1, 2 + ret void +} diff --git a/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll new file mode 100644 index 000000000000..33f7a79783cc --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll @@ -0,0 +1,289 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +define void @t1a(float %a) uwtable ssp { +entry: +; ELF64: t1a + %cmp = fcmp oeq float %a, 0.000000e+00 +; ELF64: addis +; ELF64: lfs +; ELF64: fcmpu + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +declare void @foo() + +define void @t1b(float %a) uwtable ssp { +entry: +; ELF64: t1b + %cmp = fcmp oeq float %a, -0.000000e+00 +; ELF64: addis +; ELF64: lfs +; ELF64: fcmpu + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t2a(double %a) uwtable ssp { +entry: +; ELF64: t2a + %cmp = fcmp oeq double %a, 0.000000e+00 +; ELF64: addis +; ELF64: lfd +; ELF64: fcmpu + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t2b(double %a) uwtable ssp { +entry: +; ELF64: t2b + %cmp = fcmp oeq double %a, -0.000000e+00 +; ELF64: addis +; ELF64: lfd +; ELF64: fcmpu + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t4(i8 signext %a) uwtable ssp { +entry: +; ELF64: t4 + %cmp = icmp eq i8 %a, -1 +; ELF64: extsb +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t5(i8 zeroext %a) uwtable ssp { +entry: +; ELF64: t5 + %cmp = icmp eq i8 %a, 1 +; ELF64: extsb +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t6(i16 signext %a) uwtable ssp { +entry: +; ELF64: t6 + %cmp = icmp eq i16 %a, -1 +; ELF64: extsh +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t7(i16 zeroext %a) uwtable ssp { +entry: +; ELF64: t7 + %cmp = icmp eq i16 %a, 1 +; ELF64: extsh +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t8(i32 %a) uwtable ssp { +entry: +; ELF64: t8 + %cmp = icmp eq i32 %a, -1 +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t9(i32 %a) uwtable ssp { +entry: +; ELF64: t9 + %cmp = icmp eq i32 %a, 1 +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t10(i32 %a) uwtable ssp { +entry: +; ELF64: t10 + %cmp = icmp eq i32 %a, 384 +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t11(i32 %a) uwtable ssp { +entry: +; ELF64: t11 + %cmp = icmp eq i32 %a, 4096 +; ELF64: cmpwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t12(i8 %a) uwtable ssp { +entry: +; ELF64: t12 + %cmp = icmp ugt i8 %a, -113 +; ELF64: rlwinm +; ELF64: cmplwi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t13() nounwind ssp { +entry: +; ELF64: t13 + %cmp = icmp slt i32 -123, -2147483648 +; ELF64: li +; ELF64: lis +; ELF64: cmpw + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + ret void + +if.end: ; preds = %entry + ret void +} + +define void @t14(i64 %a) uwtable ssp { +entry: +; ELF64: t14 + %cmp = icmp eq i64 %a, -1 +; ELF64: cmpdi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t15(i64 %a) uwtable ssp { +entry: +; ELF64: t15 + %cmp = icmp eq i64 %a, 1 +; ELF64: cmpdi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t16(i64 %a) uwtable ssp { +entry: +; ELF64: t16 + %cmp = icmp eq i64 %a, 384 +; ELF64: cmpdi + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +define void @t17(i64 %a) uwtable ssp { +entry: +; ELF64: t17 + %cmp = icmp eq i64 %a, 32768 +; Extra operand so we don't match on cmpdi. +; ELF64: cmpd {{[0-9]+}} + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + diff --git a/test/CodeGen/PowerPC/fast-isel-conversion.ll b/test/CodeGen/PowerPC/fast-isel-conversion.ll new file mode 100644 index 000000000000..a31c31210c39 --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -0,0 +1,305 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +; Test sitofp + +define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp { +entry: +; ELF64: sitofp_single_i64 + %b.addr = alloca float, align 4 + %conv = sitofp i64 %a to float +; ELF64: std +; ELF64: lfd +; ELF64: fcfids + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { +entry: +; ELF64: sitofp_single_i32 + %b.addr = alloca float, align 4 + %conv = sitofp i32 %a to float +; ELF64: std +; ELF64: lfiwax +; ELF64: fcfids + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp { +entry: +; ELF64: sitofp_single_i16 + %b.addr = alloca float, align 4 + %conv = sitofp i16 %a to float +; ELF64: extsh +; ELF64: std +; ELF64: lfd +; ELF64: fcfids + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @sitofp_single_i8(i8 %a) nounwind ssp { +entry: +; ELF64: sitofp_single_i8 + %b.addr = alloca float, align 4 + %conv = sitofp i8 %a to float +; ELF64: extsb +; ELF64: std +; ELF64: lfd +; ELF64: fcfids + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { +entry: +; ELF64: sitofp_double_i32 + %b.addr = alloca double, align 8 + %conv = sitofp i32 %a to double +; ELF64: std +; ELF64: lfiwax +; ELF64: fcfid + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp { +entry: +; ELF64: sitofp_double_i64 + %b.addr = alloca double, align 8 + %conv = sitofp i64 %a to double +; ELF64: std +; ELF64: lfd +; ELF64: fcfid + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp { +entry: +; ELF64: sitofp_double_i16 + %b.addr = alloca double, align 8 + %conv = sitofp i16 %a to double +; ELF64: extsh +; ELF64: std +; ELF64: lfd +; ELF64: fcfid + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp { +entry: +; ELF64: sitofp_double_i8 + %b.addr = alloca double, align 8 + %conv = sitofp i8 %a to double +; ELF64: extsb +; ELF64: std +; ELF64: lfd +; ELF64: fcfid + store double %conv, double* %b.addr, align 8 + ret void +} + +; Test uitofp + +define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp { +entry: +; ELF64: uitofp_single_i64 + %b.addr = alloca float, align 4 + %conv = uitofp i64 %a to float +; ELF64: std +; ELF64: lfd +; ELF64: fcfidus + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp { +entry: +; ELF64: uitofp_single_i32 + %b.addr = alloca float, align 4 + %conv = uitofp i32 %a to float +; ELF64: std +; ELF64: lfiwzx +; ELF64: fcfidus + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp { +entry: +; ELF64: uitofp_single_i16 + %b.addr = alloca float, align 4 + %conv = uitofp i16 %a to float +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: std +; ELF64: lfd +; ELF64: fcfidus + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @uitofp_single_i8(i8 %a) nounwind ssp { +entry: +; ELF64: uitofp_single_i8 + %b.addr = alloca float, align 4 + %conv = uitofp i8 %a to float +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: std +; ELF64: lfd +; ELF64: fcfidus + store float %conv, float* %b.addr, align 4 + ret void +} + +define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp { +entry: +; ELF64: uitofp_double_i64 + %b.addr = alloca double, align 8 + %conv = uitofp i64 %a to double +; ELF64: std +; ELF64: lfd +; ELF64: fcfidu + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp { +entry: +; ELF64: uitofp_double_i32 + %b.addr = alloca double, align 8 + %conv = uitofp i32 %a to double +; ELF64: std +; ELF64: lfiwzx +; ELF64: fcfidu + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp { +entry: +; ELF64: uitofp_double_i16 + %b.addr = alloca double, align 8 + %conv = uitofp i16 %a to double +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: std +; ELF64: lfd +; ELF64: fcfidu + store double %conv, double* %b.addr, align 8 + ret void +} + +define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp { +entry: +; ELF64: uitofp_double_i8 + %b.addr = alloca double, align 8 + %conv = uitofp i8 %a to double +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: std +; ELF64: lfd +; ELF64: fcfidu + store double %conv, double* %b.addr, align 8 + ret void +} + +; Test fptosi + +define void @fptosi_float_i32(float %a) nounwind ssp { +entry: +; ELF64: fptosi_float_i32 + %b.addr = alloca i32, align 4 + %conv = fptosi float %a to i32 +; ELF64: fctiwz +; ELF64: stfd +; ELF64: lwa + store i32 %conv, i32* %b.addr, align 4 + ret void +} + +define void @fptosi_float_i64(float %a) nounwind ssp { +entry: +; ELF64: fptosi_float_i64 + %b.addr = alloca i64, align 4 + %conv = fptosi float %a to i64 +; ELF64: fctidz +; ELF64: stfd +; ELF64: ld + store i64 %conv, i64* %b.addr, align 4 + ret void +} + +define void @fptosi_double_i32(double %a) nounwind ssp { +entry: +; ELF64: fptosi_double_i32 + %b.addr = alloca i32, align 8 + %conv = fptosi double %a to i32 +; ELF64: fctiwz +; ELF64: stfd +; ELF64: lwa + store i32 %conv, i32* %b.addr, align 8 + ret void +} + +define void @fptosi_double_i64(double %a) nounwind ssp { +entry: +; ELF64: fptosi_double_i64 + %b.addr = alloca i64, align 8 + %conv = fptosi double %a to i64 +; ELF64: fctidz +; ELF64: stfd +; ELF64: ld + store i64 %conv, i64* %b.addr, align 8 + ret void +} + +; Test fptoui + +define void @fptoui_float_i32(float %a) nounwind ssp { +entry: +; ELF64: fptoui_float_i32 + %b.addr = alloca i32, align 4 + %conv = fptoui float %a to i32 +; ELF64: fctiwuz +; ELF64: stfd +; ELF64: lwz + store i32 %conv, i32* %b.addr, align 4 + ret void +} + +define void @fptoui_float_i64(float %a) nounwind ssp { +entry: +; ELF64: fptoui_float_i64 + %b.addr = alloca i64, align 4 + %conv = fptoui float %a to i64 +; ELF64: fctiduz +; ELF64: stfd +; ELF64: ld + store i64 %conv, i64* %b.addr, align 4 + ret void +} + +define void @fptoui_double_i32(double %a) nounwind ssp { +entry: +; ELF64: fptoui_double_i32 + %b.addr = alloca i32, align 8 + %conv = fptoui double %a to i32 +; ELF64: fctiwuz +; ELF64: stfd +; ELF64: lwz + store i32 %conv, i32* %b.addr, align 8 + ret void +} + +define void @fptoui_double_i64(double %a) nounwind ssp { +entry: +; ELF64: fptoui_double_i64 + %b.addr = alloca i64, align 8 + %conv = fptoui double %a to i64 +; ELF64: fctiduz +; ELF64: stfd +; ELF64: ld + store i64 %conv, i64* %b.addr, align 8 + ret void +} diff --git a/test/CodeGen/PowerPC/fast-isel-crash.ll b/test/CodeGen/PowerPC/fast-isel-crash.ll new file mode 100644 index 000000000000..1813fc96acee --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-crash.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 + +; Ensure this doesn't crash. + +%union.anon = type { <16 x i32> } + +@__md0 = external global [137 x i8] + +define internal void @stretch(<4 x i8> addrspace(1)* %src, <4 x i8> addrspace(1)* %dst, i32 %width, i32 %height, i32 %iLS, i32 %oLS, <2 x float> %c, <4 x float> %param) nounwind { +entry: + ret void +} + +define internal i32 @_Z13get_global_idj(i32 %dim) nounwind ssp { +entry: + ret i32 undef +} + +define void @wrap(i8 addrspace(1)* addrspace(1)* %arglist, i32 addrspace(1)* %gtid) nounwind ssp { +entry: + call void @stretch(<4 x i8> addrspace(1)* undef, <4 x i8> addrspace(1)* undef, i32 undef, i32 undef, i32 undef, i32 undef, <2 x float> undef, <4 x float> undef) + ret void +} diff --git a/test/CodeGen/PowerPC/fast-isel-ext.ll b/test/CodeGen/PowerPC/fast-isel-ext.ll new file mode 100644 index 000000000000..753305a68dda --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-ext.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +; zext + +define i32 @zext_8_32(i8 %a) nounwind ssp { +; ELF64: zext_8_32 + %r = zext i8 %a to i32 +; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 + ret i32 %r +} + +define i32 @zext_16_32(i16 %a) nounwind ssp { +; ELF64: zext_16_32 + %r = zext i16 %a to i32 +; ELF64: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 + ret i32 %r +} + +define i64 @zext_8_64(i8 %a) nounwind ssp { +; ELF64: zext_8_64 + %r = zext i8 %a to i64 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 + ret i64 %r +} + +define i64 @zext_16_64(i16 %a) nounwind ssp { +; ELF64: zext_16_64 + %r = zext i16 %a to i64 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 + ret i64 %r +} + +define i64 @zext_32_64(i32 %a) nounwind ssp { +; ELF64: zext_32_64 + %r = zext i32 %a to i64 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 + ret i64 %r +} + +; sext + +define i32 @sext_8_32(i8 %a) nounwind ssp { +; ELF64: sext_8_32 + %r = sext i8 %a to i32 +; ELF64: extsb + ret i32 %r +} + +define i32 @sext_16_32(i16 %a) nounwind ssp { +; ELF64: sext_16_32 + %r = sext i16 %a to i32 +; ELF64: extsh + ret i32 %r +} + +define i64 @sext_8_64(i8 %a) nounwind ssp { +; ELF64: sext_8_64 + %r = sext i8 %a to i64 +; ELF64: extsb + ret i64 %r +} + +define i64 @sext_16_64(i16 %a) nounwind ssp { +; ELF64: sext_16_64 + %r = sext i16 %a to i64 +; ELF64: extsh + ret i64 %r +} + +define i64 @sext_32_64(i32 %a) nounwind ssp { +; ELF64: sext_32_64 + %r = sext i32 %a to i64 +; ELF64: extsw + ret i64 %r +} diff --git a/test/CodeGen/PowerPC/fast-isel-fold.ll b/test/CodeGen/PowerPC/fast-isel-fold.ll new file mode 100644 index 000000000000..4de345f309af --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-fold.ll @@ -0,0 +1,129 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +@a = global i8 1, align 1 +@b = global i16 2, align 2 +@c = global i32 4, align 4 + +define void @t1() nounwind uwtable ssp { +; ELF64: t1 + %1 = load i8* @a, align 1 + call void @foo1(i8 zeroext %1) +; ELF64: lbz +; ELF64-NOT: rldicl +; ELF64-NOT: rlwinm + ret void +} + +define void @t2() nounwind uwtable ssp { +; ELF64: t2 + %1 = load i16* @b, align 2 + call void @foo2(i16 zeroext %1) +; ELF64: lhz +; ELF64-NOT: rldicl +; ELF64-NOT: rlwinm + ret void +} + +define void @t2a() nounwind uwtable ssp { +; ELF64: t2a + %1 = load i32* @c, align 4 + call void @foo3(i32 zeroext %1) +; ELF64: lwz +; ELF64-NOT: rldicl +; ELF64-NOT: rlwinm + ret void +} + +declare void @foo1(i8 zeroext) +declare void @foo2(i16 zeroext) +declare void @foo3(i32 zeroext) + +define i32 @t3() nounwind uwtable ssp { +; ELF64: t3 + %1 = load i8* @a, align 1 + %2 = zext i8 %1 to i32 +; ELF64: lbz +; ELF64-NOT: rlwinm + ret i32 %2 +} + +define i32 @t4() nounwind uwtable ssp { +; ELF64: t4 + %1 = load i16* @b, align 2 + %2 = zext i16 %1 to i32 +; ELF64: lhz +; ELF64-NOT: rlwinm + ret i32 %2 +} + +define i32 @t5() nounwind uwtable ssp { +; ELF64: t5 + %1 = load i16* @b, align 2 + %2 = sext i16 %1 to i32 +; ELF64: lha +; ELF64-NOT: rlwinm + ret i32 %2 +} + +define i32 @t6() nounwind uwtable ssp { +; ELF64: t6 + %1 = load i8* @a, align 2 + %2 = sext i8 %1 to i32 +; ELF64: lbz +; ELF64-NOT: rlwinm + ret i32 %2 +} + +define i64 @t7() nounwind uwtable ssp { +; ELF64: t7 + %1 = load i8* @a, align 1 + %2 = zext i8 %1 to i64 +; ELF64: lbz +; ELF64-NOT: rldicl + ret i64 %2 +} + +define i64 @t8() nounwind uwtable ssp { +; ELF64: t8 + %1 = load i16* @b, align 2 + %2 = zext i16 %1 to i64 +; ELF64: lhz +; ELF64-NOT: rldicl + ret i64 %2 +} + +define i64 @t9() nounwind uwtable ssp { +; ELF64: t9 + %1 = load i16* @b, align 2 + %2 = sext i16 %1 to i64 +; ELF64: lha +; ELF64-NOT: extsh + ret i64 %2 +} + +define i64 @t10() nounwind uwtable ssp { +; ELF64: t10 + %1 = load i8* @a, align 2 + %2 = sext i8 %1 to i64 +; ELF64: lbz +; ELF64: extsb + ret i64 %2 +} + +define i64 @t11() nounwind uwtable ssp { +; ELF64: t11 + %1 = load i32* @c, align 4 + %2 = zext i32 %1 to i64 +; ELF64: lwz +; ELF64-NOT: rldicl + ret i64 %2 +} + +define i64 @t12() nounwind uwtable ssp { +; ELF64: t12 + %1 = load i32* @c, align 4 + %2 = sext i32 %1 to i64 +; ELF64: lwa +; ELF64-NOT: extsw + ret i64 %2 +} diff --git a/test/CodeGen/PowerPC/fast-isel-indirectbr.ll b/test/CodeGen/PowerPC/fast-isel-indirectbr.ll new file mode 100644 index 000000000000..88ccf918ae96 --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-indirectbr.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +define void @t1(i8* %x) { +entry: +; ELF64: t1 + br label %L0 + +L0: + br label %L1 + +L1: + indirectbr i8* %x, [ label %L0, label %L1 ] +; ELF64: mtctr 3 +; ELF64: bctr +} diff --git a/test/CodeGen/PowerPC/fast-isel-load-store.ll b/test/CodeGen/PowerPC/fast-isel-load-store.ll new file mode 100644 index 000000000000..026b15fe5e4e --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-load-store.ll @@ -0,0 +1,202 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +; This test verifies that load/store instructions are properly generated, +; and that they pass MI verification. + +@a = global i8 1, align 1 +@b = global i16 2, align 2 +@c = global i32 4, align 4 +@d = global i64 8, align 8 +@e = global float 1.25, align 4 +@f = global double 3.5, align 8 + +%struct.s = type<{ i8, i32 }> +%struct.t = type<{ i8, i64 }> + +@g = global %struct.s <{ i8 1, i32 2 }>, align 1 +@h = global %struct.t <{ i8 1, i64 2 }>, align 1 + +@i = common global [8192 x i64] zeroinitializer, align 8 + +; load + +define i8 @t1() nounwind uwtable ssp { +; ELF64: t1 + %1 = load i8* @a, align 1 +; ELF64: lbz + %2 = add nsw i8 %1, 1 +; ELF64: addi + ret i8 %2 +} + +define i16 @t2() nounwind uwtable ssp { +; ELF64: t2 + %1 = load i16* @b, align 2 +; ELF64: lhz + %2 = add nsw i16 %1, 1 +; ELF64: addi + ret i16 %2 +} + +define i32 @t3() nounwind uwtable ssp { +; ELF64: t3 + %1 = load i32* @c, align 4 +; ELF64: lwz + %2 = add nsw i32 %1, 1 +; ELF64: addi + ret i32 %2 +} + +define i64 @t4() nounwind uwtable ssp { +; ELF64: t4 + %1 = load i64* @d, align 4 +; ELF64: ld + %2 = add nsw i64 %1, 1 +; ELF64: addi + ret i64 %2 +} + +define float @t5() nounwind uwtable ssp { +; ELF64: t5 + %1 = load float* @e, align 4 +; ELF64: lfs + %2 = fadd float %1, 1.0 +; ELF64: fadds + ret float %2 +} + +define double @t6() nounwind uwtable ssp { +; ELF64: t6 + %1 = load double* @f, align 8 +; ELF64: lfd + %2 = fadd double %1, 1.0 +; ELF64: fadd + ret double %2 +} + +; store + +define void @t7(i8 %v) nounwind uwtable ssp { +; ELF64: t7 + %1 = add nsw i8 %v, 1 + store i8 %1, i8* @a, align 1 +; ELF64: addis +; ELF64: addi +; ELF64: addi +; ELF64: stb + ret void +} + +define void @t8(i16 %v) nounwind uwtable ssp { +; ELF64: t8 + %1 = add nsw i16 %v, 1 + store i16 %1, i16* @b, align 2 +; ELF64: addis +; ELF64: addi +; ELF64: addi +; ELF64: sth + ret void +} + +define void @t9(i32 %v) nounwind uwtable ssp { +; ELF64: t9 + %1 = add nsw i32 %v, 1 + store i32 %1, i32* @c, align 4 +; ELF64: addis +; ELF64: addi +; ELF64: addi +; ELF64: stw + ret void +} + +define void @t10(i64 %v) nounwind uwtable ssp { +; ELF64: t10 + %1 = add nsw i64 %v, 1 + store i64 %1, i64* @d, align 4 +; ELF64: addis +; ELF64: addi +; ELF64: addi +; ELF64: std + ret void +} + +define void @t11(float %v) nounwind uwtable ssp { +; ELF64: t11 + %1 = fadd float %v, 1.0 + store float %1, float* @e, align 4 +; ELF64: fadds +; ELF64: stfs + ret void +} + +define void @t12(double %v) nounwind uwtable ssp { +; ELF64: t12 + %1 = fadd double %v, 1.0 + store double %1, double* @f, align 8 +; ELF64: fadd +; ELF64: stfd + ret void +} + +;; lwa requires an offset divisible by 4, so we need lwax here. +define i64 @t13() nounwind uwtable ssp { +; ELF64: t13 + %1 = load i32* getelementptr inbounds (%struct.s* @g, i32 0, i32 1), align 1 + %2 = sext i32 %1 to i64 +; ELF64: li +; ELF64: lwax + %3 = add nsw i64 %2, 1 +; ELF64: addi + ret i64 %3 +} + +;; ld requires an offset divisible by 4, so we need ldx here. +define i64 @t14() nounwind uwtable ssp { +; ELF64: t14 + %1 = load i64* getelementptr inbounds (%struct.t* @h, i32 0, i32 1), align 1 +; ELF64: li +; ELF64: ldx + %2 = add nsw i64 %1, 1 +; ELF64: addi + ret i64 %2 +} + +;; std requires an offset divisible by 4, so we need stdx here. +define void @t15(i64 %v) nounwind uwtable ssp { +; ELF64: t15 + %1 = add nsw i64 %v, 1 + store i64 %1, i64* getelementptr inbounds (%struct.t* @h, i32 0, i32 1), align 1 +; ELF64: addis +; ELF64: addi +; ELF64: addi +; ELF64: li +; ELF64: stdx + ret void +} + +;; ld requires an offset that fits in 16 bits, so we need ldx here. +define i64 @t16() nounwind uwtable ssp { +; ELF64: t16 + %1 = load i64* getelementptr inbounds ([8192 x i64]* @i, i32 0, i64 5000), align 8 +; ELF64: lis +; ELF64: ori +; ELF64: ldx + %2 = add nsw i64 %1, 1 +; ELF64: addi + ret i64 %2 +} + +;; std requires an offset that fits in 16 bits, so we need stdx here. +define void @t17(i64 %v) nounwind uwtable ssp { +; ELF64: t17 + %1 = add nsw i64 %v, 1 + store i64 %1, i64* getelementptr inbounds ([8192 x i64]* @i, i32 0, i64 5000), align 8 +; ELF64: addis +; ELF64: ld +; ELF64: addi +; ELF64: lis +; ELF64: ori +; ELF64: stdx + ret void +} + diff --git a/test/CodeGen/PowerPC/fast-isel-redefinition.ll b/test/CodeGen/PowerPC/fast-isel-redefinition.ll new file mode 100644 index 000000000000..72422bda4433 --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-redefinition.ll @@ -0,0 +1,10 @@ +; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +; This isn't exactly a useful set of command-line options, but check that it +; doesn't crash. (It crashed formerly on ARM, and proved useful in +; discovering a bug on PowerPC as well.) + +define i32 @f(i32* %x) nounwind ssp { + %y = getelementptr inbounds i32* %x, i32 5000 + %tmp103 = load i32* %y, align 4 + ret i32 %tmp103 +} diff --git a/test/CodeGen/PowerPC/fast-isel-ret.ll b/test/CodeGen/PowerPC/fast-isel-ret.ll new file mode 100644 index 000000000000..fa19f8b11fd6 --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-ret.ll @@ -0,0 +1,142 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp { +entry: +; ELF64: ret2 +; ELF64: extsb +; ELF64: blr + ret i8 %a +} + +define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp { +entry: +; ELF64: ret3 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: blr + ret i8 %a +} + +define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp { +entry: +; ELF64: ret4 +; ELF64: extsh +; ELF64: blr + ret i16 %a +} + +define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp { +entry: +; ELF64: ret5 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: blr + ret i16 %a +} + +define i16 @ret6(i16 %a) nounwind uwtable ssp { +entry: +; ELF64: ret6 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: blr + ret i16 %a +} + +define signext i32 @ret7(i32 signext %a) nounwind uwtable ssp { +entry: +; ELF64: ret7 +; ELF64: extsw +; ELF64: blr + ret i32 %a +} + +define zeroext i32 @ret8(i32 signext %a) nounwind uwtable ssp { +entry: +; ELF64: ret8 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: blr + ret i32 %a +} + +define i32 @ret9(i32 %a) nounwind uwtable ssp { +entry: +; ELF64: ret9 +; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: blr + ret i32 %a +} + +define i64 @ret10(i64 %a) nounwind uwtable ssp { +entry: +; ELF64: ret10 +; ELF64-NOT: exts +; ELF64-NOT: rldicl +; ELF64: blr + ret i64 %a +} + +define float @ret11(float %a) nounwind uwtable ssp { +entry: +; ELF64: ret11 +; ELF64: blr + ret float %a +} + +define double @ret12(double %a) nounwind uwtable ssp { +entry: +; ELF64: ret12 +; ELF64: blr + ret double %a +} + +define i8 @ret13() nounwind uwtable ssp { +entry: +; ELF64: ret13 +; ELF64: li +; ELF64: blr + ret i8 15; +} + +define i16 @ret14() nounwind uwtable ssp { +entry: +; ELF64: ret14 +; ELF64: li +; ELF64: blr + ret i16 -225; +} + +define i32 @ret15() nounwind uwtable ssp { +entry: +; ELF64: ret15 +; ELF64: lis +; ELF64: ori +; ELF64: blr + ret i32 278135; +} + +define i64 @ret16() nounwind uwtable ssp { +entry: +; ELF64: ret16 +; ELF64: li +; ELF64: sldi +; ELF64: oris +; ELF64: ori +; ELF64: blr + ret i64 27813515225; +} + +define float @ret17() nounwind uwtable ssp { +entry: +; ELF64: ret17 +; ELF64: addis +; ELF64: lfs +; ELF64: blr + ret float 2.5; +} + +define double @ret18() nounwind uwtable ssp { +entry: +; ELF64: ret18 +; ELF64: addis +; ELF64: lfd +; ELF64: blr + ret double 2.5e-33; +} diff --git a/test/CodeGen/PowerPC/fast-isel-shifter.ll b/test/CodeGen/PowerPC/fast-isel-shifter.ll new file mode 100644 index 000000000000..198bfbecda63 --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-shifter.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +define i32 @shl() nounwind ssp { +entry: +; ELF64: shl +; ELF64: slw + %shl = shl i32 -1, 2 + ret i32 %shl +} + +define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp { +entry: +; ELF64: shl_reg +; ELF64: slw + %shl = shl i32 %src1, %src2 + ret i32 %shl +} + +define i32 @lshr() nounwind ssp { +entry: +; ELF64: lshr +; ELF64: srw + %lshr = lshr i32 -1, 2 + ret i32 %lshr +} + +define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp { +entry: +; ELF64: lshr_reg +; ELF64: srw + %lshr = lshr i32 %src1, %src2 + ret i32 %lshr +} + +define i32 @ashr() nounwind ssp { +entry: +; ELF64: ashr +; ELF64: srawi + %ashr = ashr i32 -1, 2 + ret i32 %ashr +} + +define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp { +entry: +; ELF64: ashr_reg +; ELF64: sraw + %ashr = ashr i32 %src1, %src2 + ret i32 %ashr +} + diff --git a/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll b/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll new file mode 100644 index 000000000000..4bcacf009746 --- /dev/null +++ b/test/CodeGen/PowerPC/fastisel-gep-promote-before-add.ll @@ -0,0 +1,17 @@ +; fastisel should not fold add with non-pointer bitwidth +; sext(a) + sext(b) != sext(a + b) +; RUN: llc -mtriple=powerpc64-unknown-freebsd10.0 %s -O0 -o - | FileCheck %s + +define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp { +entry: + %ptr.addr = alloca i8*, align 8 + %add = add i8 64, 64 ; 0x40 + 0x40 + %0 = load i8** %ptr.addr, align 8 + + ; CHECK-LABEL: gep_promotion: + ; CHECK: lbz {{[0-9]+}}, 0({{.*}}) + %arrayidx = getelementptr inbounds i8* %0, i8 %add + + %1 = load i8* %arrayidx, align 1 + ret i8 %1 +} diff --git a/test/CodeGen/PowerPC/fcpsgn.ll b/test/CodeGen/PowerPC/fcpsgn.ll new file mode 100644 index 000000000000..f4699816340a --- /dev/null +++ b/test/CodeGen/PowerPC/fcpsgn.ll @@ -0,0 +1,52 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define double @foo_dd(double %a, double %b) #0 { +entry: + %call = tail call double @copysign(double %a, double %b) #0 + ret double %call + +; CHECK-LABEL: @foo_dd +; CHECK: fcpsgn 1, 2, 1 +; CHECK: blr +} + +declare double @copysign(double, double) #0 + +define float @foo_ss(float %a, float %b) #0 { +entry: + %call = tail call float @copysignf(float %a, float %b) #0 + ret float %call + +; CHECK-LABEL: @foo_ss +; CHECK: fcpsgn 1, 2, 1 +; CHECK: blr +} + +declare float @copysignf(float, float) #0 + +define float @foo_sd(float %a, double %b) #0 { +entry: + %conv = fptrunc double %b to float + %call = tail call float @copysignf(float %a, float %conv) #0 + ret float %call + +; CHECK-LABEL: @foo_sd +; CHECK: fcpsgn 1, 2, 1 +; CHECK: blr +} + +define double @foo_ds(double %a, float %b) #0 { +entry: + %conv = fpext float %b to double + %call = tail call double @copysign(double %a, double %conv) #0 + ret double %call + +; CHECK-LABEL: @foo_ds +; CHECK: fcpsgn 1, 2, 1 +; CHECK: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/floatPSA.ll b/test/CodeGen/PowerPC/floatPSA.ll index b5631a160561..f14c73630a6f 100644 --- a/test/CodeGen/PowerPC/floatPSA.ll +++ b/test/CodeGen/PowerPC/floatPSA.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s ; This verifies that single-precision floating point values that can't ; be passed in registers are stored in the rightmost word of the parameter diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll index a173c9154041..db19761b431c 100644 --- a/test/CodeGen/PowerPC/fma.ll +++ b/test/CodeGen/PowerPC/fma.ll @@ -4,7 +4,7 @@ define double @test_FMADD1(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fadd double %D, %C ; <double> [#uses=1] ret double %E -; CHECK: test_FMADD1: +; CHECK-LABEL: test_FMADD1: ; CHECK: fmadd ; CHECK-NEXT: blr } @@ -13,7 +13,7 @@ define double @test_FMADD2(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fadd double %D, %C ; <double> [#uses=1] ret double %E -; CHECK: test_FMADD2: +; CHECK-LABEL: test_FMADD2: ; CHECK: fmadd ; CHECK-NEXT: blr } @@ -22,7 +22,7 @@ define double @test_FMSUB(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fsub double %D, %C ; <double> [#uses=1] ret double %E -; CHECK: test_FMSUB: +; CHECK-LABEL: test_FMSUB: ; CHECK: fmsub ; CHECK-NEXT: blr } @@ -32,7 +32,7 @@ define double @test_FNMADD1(double %A, double %B, double %C) { %E = fadd double %D, %C ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F -; CHECK: test_FNMADD1: +; CHECK-LABEL: test_FNMADD1: ; CHECK: fnmadd ; CHECK-NEXT: blr } @@ -42,7 +42,7 @@ define double @test_FNMADD2(double %A, double %B, double %C) { %E = fadd double %C, %D ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F -; CHECK: test_FNMADD2: +; CHECK-LABEL: test_FNMADD2: ; CHECK: fnmadd ; CHECK-NEXT: blr } @@ -51,7 +51,7 @@ define double @test_FNMSUB1(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fsub double %C, %D ; <double> [#uses=1] ret double %E -; CHECK: test_FNMSUB1: +; CHECK-LABEL: test_FNMSUB1: ; CHECK: fnmsub ; CHECK-NEXT: blr } @@ -61,7 +61,7 @@ define double @test_FNMSUB2(double %A, double %B, double %C) { %E = fsub double %D, %C ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F -; CHECK: test_FNMSUB2: +; CHECK-LABEL: test_FNMSUB2: ; CHECK: fnmsub ; CHECK-NEXT: blr } @@ -71,7 +71,7 @@ define float @test_FNMSUBS(float %A, float %B, float %C) { %E = fsub float %D, %C ; <float> [#uses=1] %F = fsub float -0.000000e+00, %E ; <float> [#uses=1] ret float %F -; CHECK: test_FNMSUBS: +; CHECK-LABEL: test_FNMSUBS: ; CHECK: fnmsubs ; CHECK-NEXT: blr } diff --git a/test/CodeGen/PowerPC/frameaddr.ll b/test/CodeGen/PowerPC/frameaddr.ll index eabd4a68aa83..4480273673f6 100644 --- a/test/CodeGen/PowerPC/frameaddr.ll +++ b/test/CodeGen/PowerPC/frameaddr.ll @@ -40,8 +40,8 @@ declare void @use(i8*) declare i8* @llvm.frameaddress(i32) #2 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { noreturn nounwind } attributes #2 = { nounwind readnone } -attributes #3 = { nounwind naked "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind naked "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/glob-comp-aa-crash.ll b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll new file mode 100644 index 000000000000..f97d0ff6268c --- /dev/null +++ b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll @@ -0,0 +1,139 @@ +; RUN: llc -mtriple=powerpc64-bgq-linux -mcpu=a2 < %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +%"class.std::__1::__assoc_sub_state" = type { %"class.std::__1::__shared_count", %"class.std::__exception_ptr::exception_ptr", %"class.std::__1::mutex", %"class.std::__1::condition_variable", i32 } +%"class.std::__1::__shared_count" = type { i32 (...)**, i64 } +%"class.std::__exception_ptr::exception_ptr" = type { i8* } +%"class.std::__1::mutex" = type { %union.pthread_mutex_t } +%union.pthread_mutex_t = type { %"struct.<anonymous union>::__pthread_mutex_s" } +%"struct.<anonymous union>::__pthread_mutex_s" = type { i32, i32, i32, i32, i32, i32, %struct.__pthread_internal_list } +%struct.__pthread_internal_list = type { %struct.__pthread_internal_list*, %struct.__pthread_internal_list* } +%"class.std::__1::condition_variable" = type { %union.pthread_cond_t } +%union.pthread_cond_t = type { %struct.anon } +%struct.anon = type { i32, i32, i64, i64, i64, i8*, i32, i32 } +%"class.std::__1::unique_lock" = type { %"class.std::__1::mutex"*, i8 } + +declare i32 @__gxx_personality_v0(...) + +; Function Attrs: optsize +define void @_ZNSt3__117__assoc_sub_state4copyEv(%"class.std::__1::__assoc_sub_state"* %this) #0 align 2 { +entry: + %__lk = alloca %"class.std::__1::unique_lock", align 8 + %ref.tmp = alloca %"class.std::__exception_ptr::exception_ptr", align 8 + %tmp = alloca { i64, i64 }, align 8 + %agg.tmp = alloca %"class.std::__exception_ptr::exception_ptr", align 8 + %__mut_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 2 + %__m_.i.i = getelementptr inbounds %"class.std::__1::unique_lock"* %__lk, i64 0, i32 0 + store %"class.std::__1::mutex"* %__mut_, %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5 + %__owns_.i.i = getelementptr inbounds %"class.std::__1::unique_lock"* %__lk, i64 0, i32 1 + store i8 1, i8* %__owns_.i.i, align 8, !tbaa !6 + call void @_ZNSt3__15mutex4lockEv(%"class.std::__1::mutex"* %__mut_) #4 + invoke void @_ZNSt3__117__assoc_sub_state10__sub_waitERNS_11unique_lockINS_5mutexEEE(%"class.std::__1::__assoc_sub_state"* %this, %"class.std::__1::unique_lock"* %__lk) #4 + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %entry + %__exception_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 1 + %0 = bitcast { i64, i64 }* %tmp to i8* + call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 16, i32 8, i1 false) + call void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp, { i64, i64 }* byval %tmp) #5 + %call = call zeroext i1 @_ZNSt15__exception_ptrneERKNS_13exception_ptrES2_(%"class.std::__exception_ptr::exception_ptr"* %__exception_, %"class.std::__exception_ptr::exception_ptr"* %ref.tmp) #5 + call void @_ZNSt15__exception_ptr13exception_ptrD1Ev(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp) #5 + br i1 %call, label %if.then, label %if.end + +if.then: ; preds = %invoke.cont + call void @_ZNSt15__exception_ptr13exception_ptrC1ERKS0_(%"class.std::__exception_ptr::exception_ptr"* %agg.tmp, %"class.std::__exception_ptr::exception_ptr"* %__exception_) #5 + invoke void @_ZSt17rethrow_exceptionNSt15__exception_ptr13exception_ptrE(%"class.std::__exception_ptr::exception_ptr"* %agg.tmp) #6 + to label %invoke.cont4 unwind label %lpad3 + +invoke.cont4: ; preds = %if.then + unreachable + +lpad: ; preds = %entry + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + %2 = extractvalue { i8*, i32 } %1, 0 + %3 = extractvalue { i8*, i32 } %1, 1 + br label %ehcleanup + +lpad3: ; preds = %if.then + %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + %5 = extractvalue { i8*, i32 } %4, 0 + %6 = extractvalue { i8*, i32 } %4, 1 + call void @_ZNSt15__exception_ptr13exception_ptrD1Ev(%"class.std::__exception_ptr::exception_ptr"* %agg.tmp) #5 + br label %ehcleanup + +if.end: ; preds = %invoke.cont + %7 = load i8* %__owns_.i.i, align 8, !tbaa !6, !range !4 + %tobool.i.i = icmp eq i8 %7, 0 + br i1 %tobool.i.i, label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit, label %if.then.i.i + +if.then.i.i: ; preds = %if.end + %8 = load %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5 + call void @_ZNSt3__15mutex6unlockEv(%"class.std::__1::mutex"* %8) #5 + br label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit + +_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit: ; preds = %if.then.i.i, %if.end + ret void + +ehcleanup: ; preds = %lpad3, %lpad + %exn.slot.0 = phi i8* [ %5, %lpad3 ], [ %2, %lpad ] + %ehselector.slot.0 = phi i32 [ %6, %lpad3 ], [ %3, %lpad ] + %9 = load i8* %__owns_.i.i, align 8, !tbaa !6, !range !4 + %tobool.i.i9 = icmp eq i8 %9, 0 + br i1 %tobool.i.i9, label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit12, label %if.then.i.i11 + +if.then.i.i11: ; preds = %ehcleanup + %10 = load %"class.std::__1::mutex"** %__m_.i.i, align 8, !tbaa !5 + call void @_ZNSt3__15mutex6unlockEv(%"class.std::__1::mutex"* %10) #5 + br label %_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit12 + +_ZNSt3__111unique_lockINS_5mutexEED1Ev.exit12: ; preds = %if.then.i.i11, %ehcleanup + %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.0, 0 + %lpad.val5 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.0, 1 + resume { i8*, i32 } %lpad.val5 +} + +; Function Attrs: optsize +declare void @_ZNSt3__117__assoc_sub_state10__sub_waitERNS_11unique_lockINS_5mutexEEE(%"class.std::__1::__assoc_sub_state"*, %"class.std::__1::unique_lock"*) #0 align 2 + +; Function Attrs: nounwind optsize +declare zeroext i1 @_ZNSt15__exception_ptrneERKNS_13exception_ptrES2_(%"class.std::__exception_ptr::exception_ptr"*, %"class.std::__exception_ptr::exception_ptr"*) #1 + +; Function Attrs: nounwind optsize +declare void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"*, { i64, i64 }* byval) #1 + +; Function Attrs: nounwind optsize +declare void @_ZNSt15__exception_ptr13exception_ptrD1Ev(%"class.std::__exception_ptr::exception_ptr"*) #1 + +; Function Attrs: noreturn optsize +declare void @_ZSt17rethrow_exceptionNSt15__exception_ptr13exception_ptrE(%"class.std::__exception_ptr::exception_ptr"*) #2 + +; Function Attrs: nounwind optsize +declare void @_ZNSt15__exception_ptr13exception_ptrC1ERKS0_(%"class.std::__exception_ptr::exception_ptr"*, %"class.std::__exception_ptr::exception_ptr"*) #1 + +; Function Attrs: nounwind optsize +declare void @_ZNSt3__15mutex6unlockEv(%"class.std::__1::mutex"*) #1 + +; Function Attrs: optsize +declare void @_ZNSt3__15mutex4lockEv(%"class.std::__1::mutex"*) #0 + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #3 + +attributes #0 = { optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { noreturn optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind } +attributes #4 = { optsize } +attributes #5 = { nounwind optsize } +attributes #6 = { noreturn optsize } + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"bool", metadata !1} +!4 = metadata !{i8 0, i8 2} +!5 = metadata !{metadata !0, metadata !0, i64 0} +!6 = metadata !{metadata !3, metadata !3, i64 0} diff --git a/test/CodeGen/PowerPC/hello-reloc.s b/test/CodeGen/PowerPC/hello-reloc.s new file mode 100644 index 000000000000..9bbfb3817890 --- /dev/null +++ b/test/CodeGen/PowerPC/hello-reloc.s @@ -0,0 +1,84 @@ +; This tests for the basic implementation of PPCMachObjectWriter.cpp, +; which is responsible for writing mach-o relocation entries for (PIC) +; PowerPC objects. +; NOTE: Darwin PPC asm syntax is not yet supported by PPCAsmParser, +; so this test case uses ELF PPC asm syntax to produce a mach-o object. +; Once PPCAsmParser supports darwin asm syntax, this test case should +; be updated accordingly. + +; RUN: llvm-mc -filetype=obj -relocation-model=pic -mcpu=g4 -triple=powerpc-apple-darwin8 %s -o - | llvm-readobj -relocations | FileCheck -check-prefix=DARWIN-G4-DUMP %s + +; .machine ppc7400 + .section __TEXT,__textcoal_nt,coalesced,pure_instructions + .section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32 + .section __TEXT,__text,regular,pure_instructions + .globl _main + .align 4 +_main: ; @main +; BB#0: ; %entry + mflr 0 + stw 31, -4(1) + stw 0, 8(1) + stwu 1, -80(1) + bl L0$pb +L0$pb: + mr 31, 1 + li 5, 0 + mflr 2 + stw 3, 68(31) + stw 5, 72(31) + stw 4, 64(31) + addis 2, 2, (L_.str-L0$pb)@ha + la 3, (L_.str-L0$pb)@l(2) + bl L_puts$stub + li 3, 0 + addi 1, 1, 80 + lwz 0, 8(1) + lwz 31, -4(1) + mtlr 0 + blr + + .section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32 + .align 4 +L_puts$stub: + .indirect_symbol _puts + mflr 0 + bcl 20, 31, L_puts$stub$tmp +L_puts$stub$tmp: + mflr 11 + addis 11, 11, (L_puts$lazy_ptr-L_puts$stub$tmp)@ha + mtlr 0 + lwzu 12, (L_puts$lazy_ptr-L_puts$stub$tmp)@l(11) + mtctr 12 + bctr + .section __DATA,__la_symbol_ptr,lazy_symbol_pointers +L_puts$lazy_ptr: + .indirect_symbol _puts + .long dyld_stub_binding_helper + +.subsections_via_symbols + .section __TEXT,__cstring,cstring_literals +L_.str: ; @.str + .asciz "Hello, world!" + +; DARWIN-G4-DUMP:Format: Mach-O 32-bit ppc +; DARWIN-G4-DUMP:Arch: powerpc +; DARWIN-G4-DUMP:AddressSize: 32bit +; DARWIN-G4-DUMP:Relocations [ +; DARWIN-G4-DUMP: Section __text { +; DARWIN-G4-DUMP: 0x34 1 2 0 PPC_RELOC_BR24 0 - +; DARWIN-G4-DUMP: 0x30 0 2 n/a PPC_RELOC_LO16_SECTDIFF 1 _main +; DARWIN-G4-DUMP: 0x0 0 2 n/a PPC_RELOC_PAIR 1 _main +; DARWIN-G4-DUMP: 0x2C 0 2 n/a PPC_RELOC_HA16_SECTDIFF 1 _main +; DARWIN-G4-DUMP: 0x60 0 2 n/a PPC_RELOC_PAIR 1 _main +; DARWIN-G4-DUMP: } +; DARWIN-G4-DUMP: Section __picsymbolstub1 { +; DARWIN-G4-DUMP: 0x14 0 2 n/a PPC_RELOC_LO16_SECTDIFF 1 _main +; DARWIN-G4-DUMP: 0x0 0 2 n/a PPC_RELOC_PAIR 1 _main +; DARWIN-G4-DUMP: 0xC 0 2 n/a PPC_RELOC_HA16_SECTDIFF 1 _main +; DARWIN-G4-DUMP: 0x18 0 2 n/a PPC_RELOC_PAIR 1 _main +; DARWIN-G4-DUMP: } +; DARWIN-G4-DUMP: Section __la_symbol_ptr { +; DARWIN-G4-DUMP: 0x0 0 2 1 PPC_RELOC_VANILLA 0 dyld_stub_binding_helper +; DARWIN-G4-DUMP: } +; DARWIN-G4-DUMP:] diff --git a/test/CodeGen/PowerPC/i64_fp_round.ll b/test/CodeGen/PowerPC/i64_fp_round.ll index d2a3239ab865..5770d788caf7 100644 --- a/test/CodeGen/PowerPC/i64_fp_round.ll +++ b/test/CodeGen/PowerPC/i64_fp_round.ll @@ -22,6 +22,6 @@ entry: ; Also check that with -enable-unsafe-fp-math we do not get that extra ; code sequence. Simply verify that there is no "isel" present. -; RUN: llc -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE +; RUN: llc -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE ; CHECK-UNSAFE-NOT: isel diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index 4b6f88bb4a00..fd06fd9b7f46 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -6,9 +6,9 @@ @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] define internal i32 @foo(i32 %i) nounwind { -; PIC: foo: -; STATIC: foo: -; PPC64: foo: +; PIC-LABEL: foo: +; STATIC-LABEL: foo: +; PPC64-LABEL: foo: entry: %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2] %1 = icmp eq i8* %0, null ; <i1> [#uses=1] diff --git a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll new file mode 100644 index 000000000000..5e31cd58301c --- /dev/null +++ b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll @@ -0,0 +1,108 @@ +; RUN: llc -mtriple=powerpc64-bgq-linux -mcpu=a2 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +%struct.BG_CoordinateMapping_t = type { [4 x i8] } + +; Function Attrs: alwaysinline inlinehint nounwind +define zeroext i32 @Kernel_RanksToCoords(i64 %mapsize, %struct.BG_CoordinateMapping_t* %map, i64* %numentries) #0 { +entry: + %mapsize.addr = alloca i64, align 8 + %map.addr = alloca %struct.BG_CoordinateMapping_t*, align 8 + %numentries.addr = alloca i64*, align 8 + %r0 = alloca i64, align 8 + %r3 = alloca i64, align 8 + %r4 = alloca i64, align 8 + %r5 = alloca i64, align 8 + %tmp = alloca i64, align 8 + store i64 %mapsize, i64* %mapsize.addr, align 8 + store %struct.BG_CoordinateMapping_t* %map, %struct.BG_CoordinateMapping_t** %map.addr, align 8 + store i64* %numentries, i64** %numentries.addr, align 8 + store i64 1055, i64* %r0, align 8 + %0 = load i64* %mapsize.addr, align 8 + store i64 %0, i64* %r3, align 8 + %1 = load %struct.BG_CoordinateMapping_t** %map.addr, align 8 + %2 = ptrtoint %struct.BG_CoordinateMapping_t* %1 to i64 + store i64 %2, i64* %r4, align 8 + %3 = load i64** %numentries.addr, align 8 + %4 = ptrtoint i64* %3 to i64 + store i64 %4, i64* %r5, align 8 + %5 = load i64* %r0, align 8 + %6 = load i64* %r3, align 8 + %7 = load i64* %r4, align 8 + %8 = load i64* %r5, align 8 + %9 = call { i64, i64, i64, i64 } asm sideeffect "sc", "={r0},={r3},={r4},={r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 %5, i64 %6, i64 %7, i64 %8) #1, !srcloc !0 + +; CHECK-LABEL: @Kernel_RanksToCoords + +; These need to be 64-bit loads, not 32-bit loads (not lwz). +; CHECK-NOT: lwz + +; CHECK: #APP +; CHECK: sc +; CHECK: #NO_APP + +; CHECK: blr + + %asmresult = extractvalue { i64, i64, i64, i64 } %9, 0 + %asmresult1 = extractvalue { i64, i64, i64, i64 } %9, 1 + %asmresult2 = extractvalue { i64, i64, i64, i64 } %9, 2 + %asmresult3 = extractvalue { i64, i64, i64, i64 } %9, 3 + store i64 %asmresult, i64* %r0, align 8 + store i64 %asmresult1, i64* %r3, align 8 + store i64 %asmresult2, i64* %r4, align 8 + store i64 %asmresult3, i64* %r5, align 8 + %10 = load i64* %r3, align 8 + store i64 %10, i64* %tmp + %11 = load i64* %tmp + %conv = trunc i64 %11 to i32 + ret i32 %conv +} + +declare void @mtrace() + +define signext i32 @main(i32 signext %argc, i8** %argv) { +entry: + %argc.addr = alloca i32, align 4 + store i32 %argc, i32* %argc.addr, align 4 + %0 = call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1076) + %asmresult1.i = extractvalue { i64, i64 } %0, 1 + %conv.i = trunc i64 %asmresult1.i to i32 + %cmp = icmp eq i32 %conv.i, 0 + br i1 %cmp, label %if.then, label %if.end + +; CHECK-LABEL: @main + +; CHECK-DAG: mr [[REG:[0-9]+]], 3 +; CHECK-DAG: li 0, 1076 +; CHECK: stw [[REG]], + +; CHECK: #APP +; CHECK: sc +; CHECK: #NO_APP + +; CHECK: cmpwi {{[0-9]+}}, [[REG]], 1 + +; CHECK: blr + +if.then: ; preds = %entry + call void @mtrace() + %.pre = load i32* %argc.addr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + %1 = phi i32 [ %.pre, %if.then ], [ %argc, %entry ] + %cmp1 = icmp slt i32 %1, 2 + br i1 %cmp1, label %usage, label %if.end40 + +usage: + ret i32 8 + +if.end40: + ret i32 0 +} + +attributes #0 = { alwaysinline inlinehint nounwind } +attributes #1 = { nounwind } + +!0 = metadata !{i32 -2146895770} diff --git a/test/CodeGen/PowerPC/isel-rc-nox0.ll b/test/CodeGen/PowerPC/isel-rc-nox0.ll new file mode 100644 index 000000000000..ac99aa408bdd --- /dev/null +++ b/test/CodeGen/PowerPC/isel-rc-nox0.ll @@ -0,0 +1,46 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@g_62 = external global [1 x [9 x i32]], align 4 + +; Function Attrs: nounwind +define void @main() #0 { +entry: + br i1 undef, label %cond.true, label %for.cond1.preheader.i + +cond.true: ; preds = %entry + br label %for.cond1.preheader.i + +for.cond1.preheader.i: ; preds = %for.cond1.preheader.i, %cond.true, %entry + br i1 undef, label %crc32_gentab.exit, label %for.cond1.preheader.i + +crc32_gentab.exit: ; preds = %for.cond1.preheader.i + %tobool.i19.i.i = icmp eq i32 undef, 0 + %retval.0.i.i.i = select i1 %tobool.i19.i.i, i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 6), i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 8) + br label %for.cond1.preheader.i2961.i + +for.cond1.preheader.i2961.i: ; preds = %for.inc44.i2977.i, %crc32_gentab.exit + call void @llvm.memset.p0i8.i64(i8* bitcast ([1 x [9 x i32]]* @g_62 to i8*), i8 -1, i64 36, i32 4, i1 false) #1 + %0 = load i32* %retval.0.i.i.i, align 4 + %tobool.i2967.i = icmp eq i32 %0, 0 + br label %for.body21.i2968.i + +for.body21.i2968.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.cond1.preheader.i2961.i + br i1 %tobool.i2967.i, label %safe_mod_func_int32_t_s_s.exit.i2974.i, label %for.inc44.i2977.i + +safe_mod_func_int32_t_s_s.exit.i2974.i: ; preds = %for.body21.i2968.i + br i1 undef, label %for.body21.i2968.i, label %for.inc44.i2977.i + +for.inc44.i2977.i: ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.body21.i2968.i + br i1 undef, label %func_80.exit2978.i, label %for.cond1.preheader.i2961.i + +func_80.exit2978.i: ; preds = %for.inc44.i2977.i + unreachable +} + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } diff --git a/test/CodeGen/PowerPC/jaggedstructs.ll b/test/CodeGen/PowerPC/jaggedstructs.ll index a10c5ddb36fb..82d4fef10cb3 100644 --- a/test/CodeGen/PowerPC/jaggedstructs.ll +++ b/test/CodeGen/PowerPC/jaggedstructs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s ; This tests receiving and re-passing parameters consisting of structures ; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in @@ -18,25 +18,25 @@ entry: ret void } -; CHECK: std 6, 216(1) -; CHECK: std 5, 208(1) -; CHECK: std 4, 200(1) -; CHECK: std 3, 192(1) -; CHECK: lbz {{[0-9]+}}, 199(1) -; CHECK: lhz {{[0-9]+}}, 197(1) +; CHECK: std 6, 184(1) +; CHECK: std 5, 176(1) +; CHECK: std 4, 168(1) +; CHECK: std 3, 160(1) +; CHECK: lbz {{[0-9]+}}, 167(1) +; CHECK: lhz {{[0-9]+}}, 165(1) ; CHECK: stb {{[0-9]+}}, 55(1) ; CHECK: sth {{[0-9]+}}, 53(1) -; CHECK: lbz {{[0-9]+}}, 207(1) -; CHECK: lwz {{[0-9]+}}, 203(1) +; CHECK: lbz {{[0-9]+}}, 175(1) +; CHECK: lwz {{[0-9]+}}, 171(1) ; CHECK: stb {{[0-9]+}}, 63(1) ; CHECK: stw {{[0-9]+}}, 59(1) -; CHECK: lhz {{[0-9]+}}, 214(1) -; CHECK: lwz {{[0-9]+}}, 210(1) +; CHECK: lhz {{[0-9]+}}, 182(1) +; CHECK: lwz {{[0-9]+}}, 178(1) ; CHECK: sth {{[0-9]+}}, 70(1) ; CHECK: stw {{[0-9]+}}, 66(1) -; CHECK: lbz {{[0-9]+}}, 223(1) -; CHECK: lhz {{[0-9]+}}, 221(1) -; CHECK: lwz {{[0-9]+}}, 217(1) +; CHECK: lbz {{[0-9]+}}, 191(1) +; CHECK: lhz {{[0-9]+}}, 189(1) +; CHECK: lwz {{[0-9]+}}, 185(1) ; CHECK: stb {{[0-9]+}}, 79(1) ; CHECK: sth {{[0-9]+}}, 77(1) ; CHECK: stw {{[0-9]+}}, 73(1) diff --git a/test/CodeGen/PowerPC/lit.local.cfg b/test/CodeGen/PowerPC/lit.local.cfg index aaa31d93d5f2..2e463005586f 100644 --- a/test/CodeGen/PowerPC/lit.local.cfg +++ b/test/CodeGen/PowerPC/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.ll', '.c', '.cpp', '.test'] - targets = set(config.root.targets_to_build.split()) if not 'PowerPC' in targets: config.unsupported = True diff --git a/test/CodeGen/PowerPC/mcm-1.ll b/test/CodeGen/PowerPC/mcm-1.ll index a57fb9dd98d0..4e31550c40d4 100644 --- a/test/CodeGen/PowerPC/mcm-1.ll +++ b/test/CodeGen/PowerPC/mcm-1.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; CHECK: test_external: +; CHECK-LABEL: test_external: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-10.ll b/test/CodeGen/PowerPC/mcm-10.ll index 4bec3e16fa04..b479559b97f5 100644 --- a/test/CodeGen/PowerPC/mcm-10.ll +++ b/test/CodeGen/PowerPC/mcm-10.ll @@ -16,7 +16,7 @@ entry: ret i32 %0 } -; CHECK: test_fn_static: +; CHECK-LABEL: test_fn_static: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/mcm-11.ll b/test/CodeGen/PowerPC/mcm-11.ll index f2bc4c9cb72c..c49e8655cf5b 100644 --- a/test/CodeGen/PowerPC/mcm-11.ll +++ b/test/CodeGen/PowerPC/mcm-11.ll @@ -16,7 +16,7 @@ entry: ret i32 %0 } -; CHECK: test_file_static: +; CHECK-LABEL: test_file_static: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/mcm-12.ll b/test/CodeGen/PowerPC/mcm-12.ll index 911305d4355f..b31b6053fca0 100644 --- a/test/CodeGen/PowerPC/mcm-12.ll +++ b/test/CodeGen/PowerPC/mcm-12.ll @@ -13,6 +13,6 @@ entry: ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]: ; CHECK: .quad 4562098671269285104 -; CHECK: test_double_const: +; CHECK-LABEL: test_double_const: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/mcm-2.ll b/test/CodeGen/PowerPC/mcm-2.ll index f0dff4c5a39c..fee98d838ff1 100644 --- a/test/CodeGen/PowerPC/mcm-2.ll +++ b/test/CodeGen/PowerPC/mcm-2.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; MEDIUM: test_fn_static: +; MEDIUM-LABEL: test_fn_static: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]]) @@ -26,12 +26,14 @@ entry: ; MEDIUM: .local [[VAR]] ; MEDIUM: .comm [[VAR]],4,4 -; LARGE: test_fn_static: +; LARGE-LABEL: test_fn_static: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; LARGE: lwz {{[0-9]+}}, 0([[REG2]]) ; LARGE: stw {{[0-9]+}}, 0([[REG2]]) -; LARGE: .type [[VAR]],@object -; LARGE: .local [[VAR]] -; LARGE: .comm [[VAR]],4,4 +; LARGE: [[VAR]]: +; LARGE: .tc [[VAR2:[a-z0-9A-Z_.]+]][TC],[[VAR2]] +; LARGE: .type [[VAR2]],@object +; LARGE: .local [[VAR2]] +; LARGE: .comm [[VAR2]],4,4 diff --git a/test/CodeGen/PowerPC/mcm-3.ll b/test/CodeGen/PowerPC/mcm-3.ll index b7905503f458..b6d681d580ad 100644 --- a/test/CodeGen/PowerPC/mcm-3.ll +++ b/test/CodeGen/PowerPC/mcm-3.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; MEDIUM: test_file_static: +; MEDIUM-LABEL: test_file_static: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]]) @@ -28,14 +28,16 @@ entry: ; MEDIUM: [[VAR]]: ; MEDIUM: .long 5 -; LARGE: test_file_static: +; LARGE-LABEL: test_file_static: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; LARGE: lwz {{[0-9]+}}, 0([[REG2]]) ; LARGE: stw {{[0-9]+}}, 0([[REG2]]) -; LARGE: .type [[VAR]],@object -; LARGE: .data -; LARGE: .globl [[VAR]] ; LARGE: [[VAR]]: +; LARGE: .tc [[VAR2:[a-z0-9A-Z_.]+]][TC],[[VAR2]] +; LARGE: .type [[VAR2]],@object +; LARGE: .data +; LARGE: .globl [[VAR2]] +; LARGE: [[VAR2]]: ; LARGE: .long 5 diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll index 47c60c936038..73dd902cd028 100644 --- a/test/CodeGen/PowerPC/mcm-4.ll +++ b/test/CodeGen/PowerPC/mcm-4.ll @@ -1,5 +1,5 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s -; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s ; Test correct code generation for medium and large code model ; for loading a value from the constant pool (TOC-relative). @@ -14,14 +14,14 @@ entry: ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]: ; MEDIUM: .quad 4562098671269285104 -; MEDIUM: test_double_const: +; MEDIUM-LABEL: test_double_const: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE: .quad 4562098671269285104 -; LARGE: test_double_const: -; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) +; LARGE-LABEL: test_double_const: +; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha +; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll index 1be27b7e8cc0..92ddecaeb8c8 100644 --- a/test/CodeGen/PowerPC/mcm-5.ll +++ b/test/CodeGen/PowerPC/mcm-5.ll @@ -51,7 +51,7 @@ sw.epilog: ; preds = %sw.bb3, %sw.default ret i32 %5 } -; CHECK: test_jump_table: +; CHECK-LABEL: test_jump_table: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]] diff --git a/test/CodeGen/PowerPC/mcm-6.ll b/test/CodeGen/PowerPC/mcm-6.ll index 35efaaa5628f..f7838b4b2527 100644 --- a/test/CodeGen/PowerPC/mcm-6.ll +++ b/test/CodeGen/PowerPC/mcm-6.ll @@ -17,7 +17,7 @@ entry: ret i32 %0 } -; CHECK: test_tentative: +; CHECK-LABEL: test_tentative: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-7.ll b/test/CodeGen/PowerPC/mcm-7.ll index 0dd39ee4109d..7caa13bcdcf8 100644 --- a/test/CodeGen/PowerPC/mcm-7.ll +++ b/test/CodeGen/PowerPC/mcm-7.ll @@ -18,7 +18,7 @@ entry: declare signext i32 @foo(i32 signext) -; CHECK: test_fnaddr: +; CHECK-LABEL: test_fnaddr: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: .section .toc diff --git a/test/CodeGen/PowerPC/mcm-8.ll b/test/CodeGen/PowerPC/mcm-8.ll index 3ece786d6447..643548f6b125 100644 --- a/test/CodeGen/PowerPC/mcm-8.ll +++ b/test/CodeGen/PowerPC/mcm-8.ll @@ -16,7 +16,7 @@ entry: ret i8 %1 } -; CHECK: test_avext: +; CHECK-LABEL: test_avext: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lbz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-9.ll b/test/CodeGen/PowerPC/mcm-9.ll index f366f45cc863..7906b6abea6a 100644 --- a/test/CodeGen/PowerPC/mcm-9.ll +++ b/test/CodeGen/PowerPC/mcm-9.ll @@ -7,8 +7,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -@ei = external global i32 -@a = alias i32* @ei +@a = external global i32 define signext i32 @test_external() nounwind { entry: @@ -18,7 +17,7 @@ entry: ret i32 %0 } -; CHECK: test_external: +; CHECK-LABEL: test_external: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-default.ll b/test/CodeGen/PowerPC/mcm-default.ll index 19de2536aec3..8d4ff14118f3 100644 --- a/test/CodeGen/PowerPC/mcm-default.ll +++ b/test/CodeGen/PowerPC/mcm-default.ll @@ -16,7 +16,7 @@ entry: ret i32 %0 } -; CHECK: test_external: +; CHECK-LABEL: test_external: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) diff --git a/test/CodeGen/PowerPC/mcm-obj-2.ll b/test/CodeGen/PowerPC/mcm-obj-2.ll index bc60b3baf2bb..a6e985545164 100644 --- a/test/CodeGen/PowerPC/mcm-obj-2.ll +++ b/test/CodeGen/PowerPC/mcm-obj-2.ll @@ -20,7 +20,7 @@ entry: ; accessing function-scoped variable si. ; ; CHECK: Relocations [ -; CHECK: Section (1) .text { +; CHECK: Section (2) .rela.text { ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] ; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll index 720c5fb6dd65..d3d05eb48d32 100644 --- a/test/CodeGen/PowerPC/mcm-obj.ll +++ b/test/CodeGen/PowerPC/mcm-obj.ll @@ -1,6 +1,6 @@ -; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \ +; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s -; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \ +; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \ ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s ; FIXME: When asm-parse is available, could make this an assembly test. @@ -22,12 +22,12 @@ entry: ; accessing external variable ei. ; ; MEDIUM: Relocations [ -; MEDIUM: Section (1) .text { +; MEDIUM: Section (2) .rela.text { ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] ; ; LARGE: Relocations [ -; LARGE: Section (1) .text { +; LARGE: Section (2) .rela.text { ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] diff --git a/test/CodeGen/PowerPC/misched-inorder-latency.ll b/test/CodeGen/PowerPC/misched-inorder-latency.ll index 8fae7ad4d1df..b259ff182c0c 100644 --- a/test/CodeGen/PowerPC/misched-inorder-latency.ll +++ b/test/CodeGen/PowerPC/misched-inorder-latency.ll @@ -6,7 +6,7 @@ target triple = "powerpc64-bgq-linux" ; %val1 is a load live out of %entry. It should be hoisted ; above the add. -; CHECK: testload: +; CHECK-LABEL: testload: ; CHECK: %entry ; CHECK: lwz ; CHECK: addi @@ -34,7 +34,7 @@ end: ; The prefetch gets a default latency of 3 cycles and should be hoisted ; above the add. ; -; CHECK: testprefetch: +; CHECK-LABEL: testprefetch: ; CHECK: %entry ; CHECK: dcbt ; CHECK: addi diff --git a/test/CodeGen/PowerPC/mulli64.ll b/test/CodeGen/PowerPC/mulli64.ll new file mode 100644 index 000000000000..21bc9cc37700 --- /dev/null +++ b/test/CodeGen/PowerPC/mulli64.ll @@ -0,0 +1,16 @@ +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(i64 %a) #0 { +entry: + %mul = mul nsw i64 %a, 3 + ret i64 %mul +} + +; CHECK-LABEL: @foo +; CHECK: mulli 3, 3, 3 +; CHECK: blr + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/negctr.ll b/test/CodeGen/PowerPC/negctr.ll index 2f6995c65dd8..2e649930da61 100644 --- a/test/CodeGen/PowerPC/negctr.ll +++ b/test/CodeGen/PowerPC/negctr.ll @@ -14,9 +14,12 @@ for.body: ; preds = %for.body, %entry %exitcond = icmp eq i32 %lftr.wideiv, 0 br i1 %exitcond, label %for.end, label %for.body -; FIXME: We currently can't form the 32-bit unsigned trip count necessary here! ; CHECK: @main -; CHECK-NOT: bdnz +; CHECK: li [[REG:[0-9]+]], 0 +; CHECK: oris [[REG2:[0-9]+]], [[REG]], 65535 +; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535 +; CHECK: mtctr [[REG3]] +; CHECK: bdnz for.end: ; preds = %for.body, %entry ret void @@ -80,4 +83,4 @@ for.end: ; preds = %for.body, %entry ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll index 523f329303bf..35aabfa52c1d 100644 --- a/test/CodeGen/PowerPC/optcmp.ll +++ b/test/CodeGen/PowerPC/optcmp.ll @@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu" define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 { entry: %sub = sub nsw i32 %a, %b - store i32 %sub, i32* %c, align 4, !tbaa !0 + store i32 %sub, i32* %c, align 4 %cmp = icmp sgt i32 %a, %b %cond = select i1 %cmp, i32 %a, i32 %b ret i32 %cond @@ -17,7 +17,7 @@ entry: define signext i32 @foo2(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 { entry: %shl = shl i32 %a, %b - store i32 %shl, i32* %c, align 4, !tbaa !0 + store i32 %shl, i32* %c, align 4 %cmp = icmp sgt i32 %shl, 0 %conv = zext i1 %cmp to i32 ret i32 %conv @@ -29,7 +29,7 @@ entry: define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 { entry: %sub = sub nsw i64 %a, %b - store i64 %sub, i64* %c, align 8, !tbaa !3 + store i64 %sub, i64* %c, align 8 %cmp = icmp sgt i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b ret i64 %cond @@ -43,7 +43,7 @@ entry: define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 { entry: %sub = sub nsw i64 %a, %b - store i64 %sub, i64* %c, align 8, !tbaa !3 + store i64 %sub, i64* %c, align 8 %cmp = icmp sle i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b ret i64 %cond @@ -57,7 +57,7 @@ entry: define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 { entry: %sub = sub nsw i64 %b, %a - store i64 %sub, i64* %c, align 8, !tbaa !3 + store i64 %sub, i64* %c, align 8 %cmp = icmp sgt i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b ret i64 %cond @@ -71,7 +71,7 @@ entry: define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 { entry: %sub = sub nsw i64 %b, %a - store i64 %sub, i64* %c, align 8, !tbaa !3 + store i64 %sub, i64* %c, align 8 %cmp = icmp eq i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b ret i64 %cond @@ -85,7 +85,7 @@ entry: define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 { entry: %sub = sub nsw i64 %a, %b - store i64 %sub, i64* %c, align 8, !tbaa !3 + store i64 %sub, i64* %c, align 8 %cmp = icmp eq i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b ret i64 %cond @@ -99,7 +99,7 @@ entry: define i64 @foo2l(i64 %a, i64 %b, i64* nocapture %c) #0 { entry: %shl = shl i64 %a, %b - store i64 %shl, i64* %c, align 8, !tbaa !3 + store i64 %shl, i64* %c, align 8 %cmp = icmp sgt i64 %shl, 0 %conv1 = zext i1 %cmp to i64 ret i64 %conv1 @@ -112,7 +112,7 @@ entry: define double @food(double %a, double %b, double* nocapture %c) #0 { entry: %sub = fsub double %a, %b - store double %sub, double* %c, align 8, !tbaa !3 + store double %sub, double* %c, align 8 %cmp = fcmp ogt double %a, %b %cond = select i1 %cmp, double %a, double %b ret double %cond @@ -125,7 +125,7 @@ entry: define float @foof(float %a, float %b, float* nocapture %c) #0 { entry: %sub = fsub float %a, %b - store float %sub, float* %c, align 4, !tbaa !3 + store float %sub, float* %c, align 4 %cmp = fcmp ogt float %a, %b %cond = select i1 %cmp, float %a, float %b ret float %cond @@ -135,9 +135,18 @@ entry: ; CHECK: stfs 0, 0(5) } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"long", metadata !1} -!4 = metadata !{metadata !"any pointer", metadata !1} +declare i64 @llvm.ctpop.i64(i64); + +define signext i64 @fooct(i64 signext %a, i64 signext %b, i64* nocapture %c) #0 { +entry: + %sub = sub nsw i64 %a, %b + %subc = call i64 @llvm.ctpop.i64(i64 %sub) + store i64 %subc, i64* %c, align 4 + %cmp = icmp sgt i64 %subc, 0 + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond + +; CHECK: @fooct +; CHECK-NOT: popcntd. +} diff --git a/test/CodeGen/PowerPC/ppc32-vacopy.ll b/test/CodeGen/PowerPC/ppc32-vacopy.ll new file mode 100644 index 000000000000..bc394125f135 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc32-vacopy.ll @@ -0,0 +1,24 @@ +; RUN: llc -mtriple="powerpc-unknown-linux-gnu" < %s | FileCheck %s +; PR15286 + +%va_list = type {i8, i8, i16, i8*, i8*} +declare void @llvm.va_copy(i8*, i8*) + +define void @test_vacopy() nounwind { +entry: + %0 = alloca %va_list + %1 = alloca %va_list + %2 = bitcast %va_list* %0 to i8* + %3 = bitcast %va_list* %1 to i8* + + call void @llvm.va_copy(i8* %3, i8* %2) + + ret void +} +; CHECK: test_vacopy: +; CHECK: lwz [[REG1:[0-9]+]], {{.*}} +; CHECK: lwz [[REG2:[0-9]+]], {{.*}} +; CHECK: lwz [[REG3:[0-9]+]], {{.*}} +; CHECK: stw [[REG1]], {{.*}} +; CHECK: stw [[REG2]], {{.*}} +; CHECK: stw [[REG3]], {{.*}} diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll index 10b70d02e5cc..764d3ce5fd45 100644 --- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll +++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s ; Verify internal alignment of long double in a struct. The double ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll index c382edbbce4e..1f3bb7111efd 100644 --- a/test/CodeGen/PowerPC/ppc64-calls.ll +++ b/test/CodeGen/PowerPC/ppc64-calls.ll @@ -12,7 +12,7 @@ define weak void @foo_weak() nounwind { ; Calls to local function does not require the TOC restore 'nop' define void @test_direct() nounwind readnone { -; CHECK: test_direct: +; CHECK-LABEL: test_direct: tail call void @foo() nounwind ; CHECK: bl foo ; CHECK-NOT: nop @@ -22,7 +22,7 @@ define void @test_direct() nounwind readnone { ; Calls to weak function requires a TOC restore 'nop' because they ; may be overridden in a different module. define void @test_weak() nounwind readnone { -; CHECK: test_weak: +; CHECK-LABEL: test_weak: tail call void @foo_weak() nounwind ; CHECK: bl foo ; CHECK-NEXT: nop @@ -31,7 +31,7 @@ define void @test_weak() nounwind readnone { ; Indirect calls requires a full stub creation define void @test_indirect(void ()* nocapture %fp) nounwind { -; CHECK: test_indirect: +; CHECK-LABEL: test_indirect: tail call void %fp() nounwind ; CHECK: ld [[FP:[0-9]+]], 0(3) ; CHECK: ld 11, 16(3) @@ -44,7 +44,7 @@ define void @test_indirect(void ()* nocapture %fp) nounwind { ; Absolute vales should be have the TOC restore 'nop' define void @test_abs() nounwind { -; CHECK: test_abs: +; CHECK-LABEL: test_abs: tail call void inttoptr (i64 1024 to void ()*)() nounwind ; CHECK: bla 1024 ; CHECK-NEXT: nop @@ -55,7 +55,7 @@ declare double @sin(double) nounwind ; External functions call should also have a 'nop' define double @test_external(double %x) nounwind { -; CHECK: test_external: +; CHECK-LABEL: test_external: %call = tail call double @sin(double %x) nounwind ; CHECK: bl sin ; CHECK-NEXT: nop diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll index 7f30ef883e9a..f349919b7e99 100644 --- a/test/CodeGen/PowerPC/ppc64-toc.ll +++ b/test/CodeGen/PowerPC/ppc64-toc.ll @@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu" define i64 @access_int64(i64 %a) nounwind readonly { entry: -; CHECK: access_int64: +; CHECK-LABEL: access_int64: ; CHECK-NEXT: .align 3 ; CHECK-NEXT: .quad .L.access_int64 ; CHECK-NEXT: .quad .TOC.@tocbase @@ -23,7 +23,7 @@ entry: define i64 @internal_static_var(i64 %a) nounwind { entry: -; CHECK: internal_static_var: +; CHECK-LABEL: internal_static_var: ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) %0 = load i64* @internal_static_var.x, align 8 %cmp = icmp eq i64 %0, %a @@ -33,7 +33,7 @@ entry: define i32 @access_double(double %a) nounwind readnone { entry: -; CHECK: access_double: +; CHECK-LABEL: access_double: ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) %cmp = fcmp oeq double %a, 2.000000e+00 %conv = zext i1 %cmp to i32 @@ -43,7 +43,7 @@ entry: define i32 @access_double_array(double %a, i32 %i) nounwind readonly { entry: -; CHECK: access_double_array: +; CHECK-LABEL: access_double_array: %idxprom = sext i32 %i to i64 %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom %0 = load double* %arrayidx, align 8 diff --git a/test/CodeGen/PowerPC/pr13891.ll b/test/CodeGen/PowerPC/pr13891.ll index 3ae73850a342..4be65dd43d6a 100644 --- a/test/CodeGen/PowerPC/pr13891.ll +++ b/test/CodeGen/PowerPC/pr13891.ll @@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.foo = type { i8, i8 } define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline { -; CHECK: _Z5check3foos: +; CHECK-LABEL: _Z5check3foos: ; CHECK: sth 3, {{[0-9]+}}(1) ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1) entry: diff --git a/test/CodeGen/PowerPC/pr15031.ll b/test/CodeGen/PowerPC/pr15031.ll index 5ccf941a1f16..e58ad80e139b 100644 --- a/test/CodeGen/PowerPC/pr15031.ll +++ b/test/CodeGen/PowerPC/pr15031.ll @@ -317,54 +317,42 @@ if.then: ; preds = %entry if.end: ; preds = %entry, %if.then %Reg.addr.0 = phi i32 [ %call3, %if.then ], [ %Reg, %entry ] %RegNo.i.i = getelementptr inbounds %"class.llvm::MachineOperand"* %this, i64 0, i32 2, i32 0 - %1 = load i32* %RegNo.i.i, align 4, !tbaa !0 + %1 = load i32* %RegNo.i.i, align 4 %cmp.i = icmp eq i32 %1, %Reg.addr.0 br i1 %cmp.i, label %_ZN4llvm14MachineOperand6setRegEj.exit, label %if.end.i if.end.i: ; preds = %if.end %ParentMI.i.i = getelementptr inbounds %"class.llvm::MachineOperand"* %this, i64 0, i32 3 - %2 = load %"class.llvm::MachineInstr"** %ParentMI.i.i, align 8, !tbaa !3 + %2 = load %"class.llvm::MachineInstr"** %ParentMI.i.i, align 8 %tobool.i = icmp eq %"class.llvm::MachineInstr"* %2, null br i1 %tobool.i, label %if.end13.i, label %if.then3.i if.then3.i: ; preds = %if.end.i %Parent.i.i = getelementptr inbounds %"class.llvm::MachineInstr"* %2, i64 0, i32 2 - %3 = load %"class.llvm::MachineBasicBlock"** %Parent.i.i, align 8, !tbaa !3 + %3 = load %"class.llvm::MachineBasicBlock"** %Parent.i.i, align 8 %tobool5.i = icmp eq %"class.llvm::MachineBasicBlock"* %3, null br i1 %tobool5.i, label %if.end13.i, label %if.then6.i if.then6.i: ; preds = %if.then3.i %xParent.i.i = getelementptr inbounds %"class.llvm::MachineBasicBlock"* %3, i64 0, i32 4 - %4 = load %"class.llvm::MachineFunction"** %xParent.i.i, align 8, !tbaa !3 + %4 = load %"class.llvm::MachineFunction"** %xParent.i.i, align 8 %tobool8.i = icmp eq %"class.llvm::MachineFunction"* %4, null br i1 %tobool8.i, label %if.end13.i, label %if.then9.i if.then9.i: ; preds = %if.then6.i %RegInfo.i.i = getelementptr inbounds %"class.llvm::MachineFunction"* %4, i64 0, i32 5 - %5 = load %"class.llvm::MachineRegisterInfo"** %RegInfo.i.i, align 8, !tbaa !3 + %5 = load %"class.llvm::MachineRegisterInfo"** %RegInfo.i.i, align 8 tail call void @_ZN4llvm19MachineRegisterInfo27removeRegOperandFromUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"* %5, %"class.llvm::MachineOperand"* %this) - store i32 %Reg.addr.0, i32* %RegNo.i.i, align 4, !tbaa !0 + store i32 %Reg.addr.0, i32* %RegNo.i.i, align 4 tail call void @_ZN4llvm19MachineRegisterInfo22addRegOperandToUseListEPNS_14MachineOperandE(%"class.llvm::MachineRegisterInfo"* %5, %"class.llvm::MachineOperand"* %this) br label %_ZN4llvm14MachineOperand6setRegEj.exit if.end13.i: ; preds = %if.then6.i, %if.then3.i, %if.end.i - store i32 %Reg.addr.0, i32* %RegNo.i.i, align 4, !tbaa !0 + store i32 %Reg.addr.0, i32* %RegNo.i.i, align 4 br label %_ZN4llvm14MachineOperand6setRegEj.exit _ZN4llvm14MachineOperand6setRegEj.exit: ; preds = %if.end, %if.then9.i, %if.end13.i ret void } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"any pointer", metadata !1} -!4 = metadata !{metadata !"vtable pointer", metadata !2} -!5 = metadata !{metadata !"long", metadata !1} -!6 = metadata !{i64 0, i64 8, metadata !3, i64 8, i64 8, metadata !5} -!7 = metadata !{metadata !"short", metadata !1} -!8 = metadata !{i64 0, i64 1, metadata !1, i64 1, i64 4, metadata !0, i64 2, i64 1, metadata !1, i64 3, i64 1, metadata !9, i64 3, i64 1, metadata !9, i64 3, i64 1, metadata !9, i64 3, i64 1, metadata !9, i64 3, i64 1, metadata !9, i64 3, i64 1, metadata !9, i64 3, i64 1, metadata !9, i64 3, i64 1, metadata !9, i64 4, i64 4, metadata !0, i64 4, i64 4, metadata !0, i64 8, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !5, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 24, i64 8, metadata !3, i64 16, i64 4, metadata !0, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 16, i64 8, metadata !3, i64 24, i64 4, metadata !0} -!9 = metadata !{metadata !"bool", metadata !1} -!10 = metadata !{i8 0, i8 2} - ; CHECK-NOT: lbzu 3, 1(3) diff --git a/test/CodeGen/PowerPC/pr16556-2.ll b/test/CodeGen/PowerPC/pr16556-2.ll new file mode 100644 index 000000000000..e2dae4573c72 --- /dev/null +++ b/test/CodeGen/PowerPC/pr16556-2.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s + +; This test formerly failed because of wrong custom lowering for +; fptosi of ppc_fp128. + +target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "powerpc-unknown-linux-gnu" + +%core.time.TickDuration = type { i64 } + +@_D4core4time12TickDuration11ticksPerSecyl = global i64 0 +@.str5 = internal unnamed_addr constant [40 x i8] c"..\5Cldc\5Cruntime\5Cdruntime\5Csrc\5Ccore\5Ctime.d\00" +@.str83 = internal constant [10 x i8] c"null this\00" +@.modulefilename = internal constant { i32, i8* } { i32 39, i8* getelementptr inbounds ([40 x i8]* @.str5, i32 0, i32 0) } + +declare i8* @_d_assert_msg({ i32, i8* }, { i32, i8* }, i32) + + +define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(%core.time.TickDuration* %.this_arg) { +entry: + %unitsPerSec = alloca i64, align 8 + %tmp = icmp ne %core.time.TickDuration* %.this_arg, null + br i1 %tmp, label %noassert, label %assert + +assert: ; preds = %entry + %tmp1 = load { i32, i8* }* @.modulefilename + %0 = call i8* @_d_assert_msg({ i32, i8* } { i32 9, i8* getelementptr inbounds ([10 x i8]* @.str83, i32 0, i32 0) }, { i32, i8* } %tmp1, i32 1586) + unreachable + +noassert: ; preds = %entry + %tmp2 = getelementptr %core.time.TickDuration* %.this_arg, i32 0, i32 0 + %tmp3 = load i64* %tmp2 + %tmp4 = sitofp i64 %tmp3 to ppc_fp128 + %tmp5 = load i64* @_D4core4time12TickDuration11ticksPerSecyl + %tmp6 = sitofp i64 %tmp5 to ppc_fp128 + %tmp7 = fdiv ppc_fp128 %tmp6, 0xM80000000000000000000000000000000 + %tmp8 = fdiv ppc_fp128 %tmp4, %tmp7 + %tmp9 = fptosi ppc_fp128 %tmp8 to i64 + ret i64 %tmp9 +} + diff --git a/test/CodeGen/PowerPC/pr16556.ll b/test/CodeGen/PowerPC/pr16556.ll new file mode 100644 index 000000000000..dc36f0b6eafc --- /dev/null +++ b/test/CodeGen/PowerPC/pr16556.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s + +; This test formerly failed due to no handling for a ppc_fp128 undef. + +target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "powerpc-unknown-linux-gnu" + +%core.time.TickDuration.37.125 = type { i64 } + +define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(%core.time.TickDuration.37.125* %.this_arg) { +entry: + br i1 undef, label %noassert, label %assert + +assert: ; preds = %entry + unreachable + +noassert: ; preds = %entry + %tmp9 = fptosi ppc_fp128 undef to i64 + ret i64 %tmp9 +} diff --git a/test/CodeGen/PowerPC/pr16573.ll b/test/CodeGen/PowerPC/pr16573.ll new file mode 100644 index 000000000000..7a7a8decc81f --- /dev/null +++ b/test/CodeGen/PowerPC/pr16573.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s | FileCheck %s + +target triple = "powerpc64-unknown-linux-gnu" + +define double @test() { + %1 = fptrunc ppc_fp128 0xM818F2887B9295809800000000032D000 to double + ret double %1 +} + +; CHECK: .quad -9111018957755033591 + diff --git a/test/CodeGen/PowerPC/pr17168.ll b/test/CodeGen/PowerPC/pr17168.ll new file mode 100644 index 000000000000..2848221e0764 --- /dev/null +++ b/test/CodeGen/PowerPC/pr17168.ll @@ -0,0 +1,521 @@ +; RUN: llc -mcpu=pwr7 -O0 < %s + +; This test formerly failed due to a DBG_VALUE being placed prior to a PHI +; when fast-isel is partially successful before punting to DAG-isel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@grid_points = external global [3 x i32], align 4 + +; Function Attrs: nounwind +define fastcc void @compute_rhs() #0 { +entry: + br i1 undef, label %for.cond871.preheader.for.inc960_crit_edge, label %for.end1042, !dbg !439 + +for.cond871.preheader.for.inc960_crit_edge: ; preds = %for.cond871.preheader.for.inc960_crit_edge, %entry + br i1 false, label %for.cond871.preheader.for.inc960_crit_edge, label %for.cond964.preheader, !dbg !439 + +for.cond964.preheader: ; preds = %for.cond871.preheader.for.inc960_crit_edge + br i1 undef, label %for.cond968.preheader, label %for.end1042, !dbg !441 + +for.cond968.preheader: ; preds = %for.cond968.preheader, %for.cond964.preheader + br i1 false, label %for.cond968.preheader, label %for.end1042, !dbg !441 + +for.end1042: ; preds = %for.cond968.preheader, %for.cond964.preheader, %entry + %0 = phi i32 [ undef, %for.cond964.preheader ], [ undef, %for.cond968.preheader ], [ undef, %entry ] + %1 = load i32* getelementptr inbounds ([3 x i32]* @grid_points, i64 0, i64 0), align 4, !dbg !443, !tbaa !444 + tail call void @llvm.dbg.value(metadata !447, i64 0, metadata !119), !dbg !448 + %sub10454270 = add nsw i32 %0, -1, !dbg !448 + %cmp10464271 = icmp sgt i32 %sub10454270, 1, !dbg !448 + %sub11134263 = add nsw i32 %1, -1, !dbg !450 + %cmp11144264 = icmp sgt i32 %sub11134263, 1, !dbg !450 + br i1 %cmp11144264, label %for.cond1116.preheader, label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !450 + +for.cond1116.preheader: ; preds = %for.inc1658, %for.end1042 + br i1 %cmp10464271, label %for.body1123, label %for.inc1658, !dbg !452 + +for.body1123: ; preds = %for.body1123, %for.cond1116.preheader + br label %for.body1123, !dbg !455 + +for.inc1658: ; preds = %for.cond1116.preheader + br i1 undef, label %for.cond1116.preheader, label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !450 + +for.cond1816.preheader.for.inc1898_crit_edge: ; preds = %for.cond1816.preheader.for.inc1898_crit_edge, %for.inc1658, %for.end1042 + br label %for.cond1816.preheader.for.inc1898_crit_edge, !dbg !458 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!438, !464} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4 (trunk 190311)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !298, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] [DW_LANG_C99] +!1 = metadata !{metadata !"bt.c", metadata !"/home/hfinkel/src/NPB2.3-omp-C/BT"} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4, metadata !82, metadata !102, metadata !114, metadata !132, metadata !145, metadata !154, metadata !155, metadata !162, metadata !183, metadata !200, metadata !201, metadata !207, metadata !208, metadata !215, metadata !221, metadata !230, metadata !238, metadata !246, metadata !255, metadata !260, metadata !261, metadata !268, metadata !274, metadata !279, metadata !280, metadata !287, metadata !293} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 74, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !12, i32 74} ; [ DW_TAG_subprogram ] [line 74] [def] [main] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{metadata !8, metadata !8, metadata !9} +!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] +!10 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char] +!11 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_unsigned_char] +!12 = metadata !{metadata !13, metadata !14, metadata !15, metadata !16, metadata !17, metadata !18, metadata !19, metadata !21, metadata !22, metadata !23, metadata !25, metadata !26} +!13 = metadata !{i32 786689, metadata !4, metadata !"argc", metadata !5, i32 16777290, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argc] [line 74] +!14 = metadata !{i32 786689, metadata !4, metadata !"argv", metadata !5, i32 33554506, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argv] [line 74] +!15 = metadata !{i32 786688, metadata !4, metadata !"niter", metadata !5, i32 76, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [niter] [line 76] +!16 = metadata !{i32 786688, metadata !4, metadata !"step", metadata !5, i32 76, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [step] [line 76] +!17 = metadata !{i32 786688, metadata !4, metadata !"n3", metadata !5, i32 76, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [n3] [line 76] +!18 = metadata !{i32 786688, metadata !4, metadata !"nthreads", metadata !5, i32 77, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [nthreads] [line 77] +!19 = metadata !{i32 786688, metadata !4, metadata !"navg", metadata !5, i32 78, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [navg] [line 78] +!20 = metadata !{i32 786468, null, null, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float] +!21 = metadata !{i32 786688, metadata !4, metadata !"mflops", metadata !5, i32 78, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [mflops] [line 78] +!22 = metadata !{i32 786688, metadata !4, metadata !"tmax", metadata !5, i32 80, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [tmax] [line 80] +!23 = metadata !{i32 786688, metadata !4, metadata !"verified", metadata !5, i32 81, metadata !24, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [verified] [line 81] +!24 = metadata !{i32 786454, metadata !1, null, metadata !"boolean", i32 12, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] [boolean] [line 12, size 0, align 0, offset 0] [from int] +!25 = metadata !{i32 786688, metadata !4, metadata !"class", metadata !5, i32 82, metadata !11, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [class] [line 82] +!26 = metadata !{i32 786688, metadata !4, metadata !"fp", metadata !5, i32 83, metadata !27, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [fp] [line 83] +!27 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !28} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from FILE] +!28 = metadata !{i32 786454, metadata !1, null, metadata !"FILE", i32 49, i64 0, i64 0, i64 0, i32 0, metadata !29} ; [ DW_TAG_typedef ] [FILE] [line 49, size 0, align 0, offset 0] [from _IO_FILE] +!29 = metadata !{i32 786451, metadata !30, null, metadata !"_IO_FILE", i32 271, i64 1728, i64 64, i32 0, i32 0, null, metadata !31, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [_IO_FILE] [line 271, size 1728, align 64, offset 0] [def] [from ] +!30 = metadata !{metadata !"/usr/include/libio.h", metadata !"/home/hfinkel/src/NPB2.3-omp-C/BT"} +!31 = metadata !{metadata !32, metadata !33, metadata !34, metadata !35, metadata !36, metadata !37, metadata !38, metadata !39, metadata !40, metadata !41, metadata !42, metadata !43, metadata !44, metadata !52, metadata !53, metadata !54, metadata !55, metadata !58, metadata !60, metadata !62, metadata !66, metadata !68, metadata !70, metadata !71, metadata !72, metadata !73, metadata !74, metadata !77, metadata !78} +!32 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_flags", i32 272, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_member ] [_flags] [line 272, size 32, align 32, offset 0] [from int] +!33 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_read_ptr", i32 277, i64 64, i64 64, i64 64, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_read_ptr] [line 277, size 64, align 64, offset 64] [from ] +!34 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_read_end", i32 278, i64 64, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_read_end] [line 278, size 64, align 64, offset 128] [from ] +!35 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_read_base", i32 279, i64 64, i64 64, i64 192, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_read_base] [line 279, size 64, align 64, offset 192] [from ] +!36 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_write_base", i32 280, i64 64, i64 64, i64 256, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_write_base] [line 280, size 64, align 64, offset 256] [from ] +!37 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_write_ptr", i32 281, i64 64, i64 64, i64 320, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_write_ptr] [line 281, size 64, align 64, offset 320] [from ] +!38 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_write_end", i32 282, i64 64, i64 64, i64 384, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_write_end] [line 282, size 64, align 64, offset 384] [from ] +!39 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_buf_base", i32 283, i64 64, i64 64, i64 448, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_buf_base] [line 283, size 64, align 64, offset 448] [from ] +!40 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_buf_end", i32 284, i64 64, i64 64, i64 512, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_buf_end] [line 284, size 64, align 64, offset 512] [from ] +!41 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_save_base", i32 286, i64 64, i64 64, i64 576, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_save_base] [line 286, size 64, align 64, offset 576] [from ] +!42 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_backup_base", i32 287, i64 64, i64 64, i64 640, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_backup_base] [line 287, size 64, align 64, offset 640] [from ] +!43 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_IO_save_end", i32 288, i64 64, i64 64, i64 704, i32 0, metadata !10} ; [ DW_TAG_member ] [_IO_save_end] [line 288, size 64, align 64, offset 704] [from ] +!44 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_markers", i32 290, i64 64, i64 64, i64 768, i32 0, metadata !45} ; [ DW_TAG_member ] [_markers] [line 290, size 64, align 64, offset 768] [from ] +!45 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !46} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_marker] +!46 = metadata !{i32 786451, metadata !30, null, metadata !"_IO_marker", i32 186, i64 192, i64 64, i32 0, i32 0, null, metadata !47, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [_IO_marker] [line 186, size 192, align 64, offset 0] [def] [from ] +!47 = metadata !{metadata !48, metadata !49, metadata !51} +!48 = metadata !{i32 786445, metadata !30, metadata !46, metadata !"_next", i32 187, i64 64, i64 64, i64 0, i32 0, metadata !45} ; [ DW_TAG_member ] [_next] [line 187, size 64, align 64, offset 0] [from ] +!49 = metadata !{i32 786445, metadata !30, metadata !46, metadata !"_sbuf", i32 188, i64 64, i64 64, i64 64, i32 0, metadata !50} ; [ DW_TAG_member ] [_sbuf] [line 188, size 64, align 64, offset 64] [from ] +!50 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !29} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_FILE] +!51 = metadata !{i32 786445, metadata !30, metadata !46, metadata !"_pos", i32 192, i64 32, i64 32, i64 128, i32 0, metadata !8} ; [ DW_TAG_member ] [_pos] [line 192, size 32, align 32, offset 128] [from int] +!52 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_chain", i32 292, i64 64, i64 64, i64 832, i32 0, metadata !50} ; [ DW_TAG_member ] [_chain] [line 292, size 64, align 64, offset 832] [from ] +!53 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_fileno", i32 294, i64 32, i64 32, i64 896, i32 0, metadata !8} ; [ DW_TAG_member ] [_fileno] [line 294, size 32, align 32, offset 896] [from int] +!54 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_flags2", i32 298, i64 32, i64 32, i64 928, i32 0, metadata !8} ; [ DW_TAG_member ] [_flags2] [line 298, size 32, align 32, offset 928] [from int] +!55 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_old_offset", i32 300, i64 64, i64 64, i64 960, i32 0, metadata !56} ; [ DW_TAG_member ] [_old_offset] [line 300, size 64, align 64, offset 960] [from __off_t] +!56 = metadata !{i32 786454, metadata !30, null, metadata !"__off_t", i32 141, i64 0, i64 0, i64 0, i32 0, metadata !57} ; [ DW_TAG_typedef ] [__off_t] [line 141, size 0, align 0, offset 0] [from long int] +!57 = metadata !{i32 786468, null, null, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed] +!58 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_cur_column", i32 304, i64 16, i64 16, i64 1024, i32 0, metadata !59} ; [ DW_TAG_member ] [_cur_column] [line 304, size 16, align 16, offset 1024] [from unsigned short] +!59 = metadata !{i32 786468, null, null, metadata !"unsigned short", i32 0, i64 16, i64 16, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned] +!60 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_vtable_offset", i32 305, i64 8, i64 8, i64 1040, i32 0, metadata !61} ; [ DW_TAG_member ] [_vtable_offset] [line 305, size 8, align 8, offset 1040] [from signed char] +!61 = metadata !{i32 786468, null, null, metadata !"signed char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [signed char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char] +!62 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_shortbuf", i32 306, i64 8, i64 8, i64 1048, i32 0, metadata !63} ; [ DW_TAG_member ] [_shortbuf] [line 306, size 8, align 8, offset 1048] [from ] +!63 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 8, i64 8, i32 0, i32 0, metadata !11, metadata !64, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 8, align 8, offset 0] [from char] +!64 = metadata !{metadata !65} +!65 = metadata !{i32 786465, i64 0, i64 1} ; [ DW_TAG_subrange_type ] [0, 0] +!66 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_lock", i32 310, i64 64, i64 64, i64 1088, i32 0, metadata !67} ; [ DW_TAG_member ] [_lock] [line 310, size 64, align 64, offset 1088] [from ] +!67 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] +!68 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_offset", i32 319, i64 64, i64 64, i64 1152, i32 0, metadata !69} ; [ DW_TAG_member ] [_offset] [line 319, size 64, align 64, offset 1152] [from __off64_t] +!69 = metadata !{i32 786454, metadata !30, null, metadata !"__off64_t", i32 142, i64 0, i64 0, i64 0, i32 0, metadata !57} ; [ DW_TAG_typedef ] [__off64_t] [line 142, size 0, align 0, offset 0] [from long int] +!70 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"__pad1", i32 328, i64 64, i64 64, i64 1216, i32 0, metadata !67} ; [ DW_TAG_member ] [__pad1] [line 328, size 64, align 64, offset 1216] [from ] +!71 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"__pad2", i32 329, i64 64, i64 64, i64 1280, i32 0, metadata !67} ; [ DW_TAG_member ] [__pad2] [line 329, size 64, align 64, offset 1280] [from ] +!72 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"__pad3", i32 330, i64 64, i64 64, i64 1344, i32 0, metadata !67} ; [ DW_TAG_member ] [__pad3] [line 330, size 64, align 64, offset 1344] [from ] +!73 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"__pad4", i32 331, i64 64, i64 64, i64 1408, i32 0, metadata !67} ; [ DW_TAG_member ] [__pad4] [line 331, size 64, align 64, offset 1408] [from ] +!74 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"__pad5", i32 332, i64 64, i64 64, i64 1472, i32 0, metadata !75} ; [ DW_TAG_member ] [__pad5] [line 332, size 64, align 64, offset 1472] [from size_t] +!75 = metadata !{i32 786454, metadata !30, null, metadata !"size_t", i32 42, i64 0, i64 0, i64 0, i32 0, metadata !76} ; [ DW_TAG_typedef ] [size_t] [line 42, size 0, align 0, offset 0] [from long unsigned int] +!76 = metadata !{i32 786468, null, null, metadata !"long unsigned int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned] +!77 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_mode", i32 334, i64 32, i64 32, i64 1536, i32 0, metadata !8} ; [ DW_TAG_member ] [_mode] [line 334, size 32, align 32, offset 1536] [from int] +!78 = metadata !{i32 786445, metadata !30, metadata !29, metadata !"_unused2", i32 336, i64 160, i64 8, i64 1568, i32 0, metadata !79} ; [ DW_TAG_member ] [_unused2] [line 336, size 160, align 8, offset 1568] [from ] +!79 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 160, i64 8, i32 0, i32 0, metadata !11, metadata !80, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char] +!80 = metadata !{metadata !81} +!81 = metadata !{i32 786465, i64 0, i64 20} ; [ DW_TAG_subrange_type ] [0, 19] +!82 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"verify", metadata !"verify", metadata !"", i32 2388, metadata !83, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !86, i32 2388} ; [ DW_TAG_subprogram ] [line 2388] [local] [def] [verify] +!83 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !84, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!84 = metadata !{null, metadata !8, metadata !10, metadata !85} +!85 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !24} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from boolean] +!86 = metadata !{metadata !87, metadata !88, metadata !89, metadata !90, metadata !94, metadata !95, metadata !96, metadata !97, metadata !98, metadata !99, metadata !100, metadata !101} +!87 = metadata !{i32 786689, metadata !82, metadata !"no_time_steps", metadata !5, i32 16779604, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [no_time_steps] [line 2388] +!88 = metadata !{i32 786689, metadata !82, metadata !"class", metadata !5, i32 33556820, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [class] [line 2388] +!89 = metadata !{i32 786689, metadata !82, metadata !"verified", metadata !5, i32 50334036, metadata !85, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [verified] [line 2388] +!90 = metadata !{i32 786688, metadata !82, metadata !"xcrref", metadata !5, i32 2397, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xcrref] [line 2397] +!91 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 320, i64 64, i32 0, i32 0, metadata !20, metadata !92, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 320, align 64, offset 0] [from double] +!92 = metadata !{metadata !93} +!93 = metadata !{i32 786465, i64 0, i64 5} ; [ DW_TAG_subrange_type ] [0, 4] +!94 = metadata !{i32 786688, metadata !82, metadata !"xceref", metadata !5, i32 2397, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xceref] [line 2397] +!95 = metadata !{i32 786688, metadata !82, metadata !"xcrdif", metadata !5, i32 2397, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xcrdif] [line 2397] +!96 = metadata !{i32 786688, metadata !82, metadata !"xcedif", metadata !5, i32 2397, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xcedif] [line 2397] +!97 = metadata !{i32 786688, metadata !82, metadata !"epsilon", metadata !5, i32 2398, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [epsilon] [line 2398] +!98 = metadata !{i32 786688, metadata !82, metadata !"xce", metadata !5, i32 2398, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xce] [line 2398] +!99 = metadata !{i32 786688, metadata !82, metadata !"xcr", metadata !5, i32 2398, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xcr] [line 2398] +!100 = metadata !{i32 786688, metadata !82, metadata !"dtref", metadata !5, i32 2398, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [dtref] [line 2398] +!101 = metadata !{i32 786688, metadata !82, metadata !"m", metadata !5, i32 2399, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 2399] +!102 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"rhs_norm", metadata !"rhs_norm", metadata !"", i32 266, metadata !103, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !106, i32 266} ; [ DW_TAG_subprogram ] [line 266] [local] [def] [rhs_norm] +!103 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !104, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!104 = metadata !{null, metadata !105} +!105 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from double] +!106 = metadata !{metadata !107, metadata !108, metadata !109, metadata !110, metadata !111, metadata !112, metadata !113} +!107 = metadata !{i32 786689, metadata !102, metadata !"rms", metadata !5, i32 16777482, metadata !105, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [rms] [line 266] +!108 = metadata !{i32 786688, metadata !102, metadata !"i", metadata !5, i32 271, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 271] +!109 = metadata !{i32 786688, metadata !102, metadata !"j", metadata !5, i32 271, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 271] +!110 = metadata !{i32 786688, metadata !102, metadata !"k", metadata !5, i32 271, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 271] +!111 = metadata !{i32 786688, metadata !102, metadata !"d", metadata !5, i32 271, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [d] [line 271] +!112 = metadata !{i32 786688, metadata !102, metadata !"m", metadata !5, i32 271, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 271] +!113 = metadata !{i32 786688, metadata !102, metadata !"add", metadata !5, i32 272, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [add] [line 272] +!114 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"compute_rhs", metadata !"compute_rhs", metadata !"", i32 1767, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @compute_rhs, null, null, metadata !117, i32 1767} ; [ DW_TAG_subprogram ] [line 1767] [local] [def] [compute_rhs] +!115 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !116, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!116 = metadata !{null} +!117 = metadata !{metadata !118, metadata !119, metadata !120, metadata !121, metadata !122, metadata !123, metadata !124, metadata !125, metadata !126, metadata !127, metadata !128, metadata !129, metadata !130, metadata !131} +!118 = metadata !{i32 786688, metadata !114, metadata !"i", metadata !5, i32 1769, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 1769] +!119 = metadata !{i32 786688, metadata !114, metadata !"j", metadata !5, i32 1769, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 1769] +!120 = metadata !{i32 786688, metadata !114, metadata !"k", metadata !5, i32 1769, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 1769] +!121 = metadata !{i32 786688, metadata !114, metadata !"m", metadata !5, i32 1769, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 1769] +!122 = metadata !{i32 786688, metadata !114, metadata !"rho_inv", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [rho_inv] [line 1770] +!123 = metadata !{i32 786688, metadata !114, metadata !"uijk", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [uijk] [line 1770] +!124 = metadata !{i32 786688, metadata !114, metadata !"up1", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [up1] [line 1770] +!125 = metadata !{i32 786688, metadata !114, metadata !"um1", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [um1] [line 1770] +!126 = metadata !{i32 786688, metadata !114, metadata !"vijk", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [vijk] [line 1770] +!127 = metadata !{i32 786688, metadata !114, metadata !"vp1", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [vp1] [line 1770] +!128 = metadata !{i32 786688, metadata !114, metadata !"vm1", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [vm1] [line 1770] +!129 = metadata !{i32 786688, metadata !114, metadata !"wijk", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [wijk] [line 1770] +!130 = metadata !{i32 786688, metadata !114, metadata !"wp1", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [wp1] [line 1770] +!131 = metadata !{i32 786688, metadata !114, metadata !"wm1", metadata !5, i32 1770, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [wm1] [line 1770] +!132 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"error_norm", metadata !"error_norm", metadata !"", i32 225, metadata !103, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !133, i32 225} ; [ DW_TAG_subprogram ] [line 225] [local] [def] [error_norm] +!133 = metadata !{metadata !134, metadata !135, metadata !136, metadata !137, metadata !138, metadata !139, metadata !140, metadata !141, metadata !142, metadata !143, metadata !144} +!134 = metadata !{i32 786689, metadata !132, metadata !"rms", metadata !5, i32 16777441, metadata !105, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [rms] [line 225] +!135 = metadata !{i32 786688, metadata !132, metadata !"i", metadata !5, i32 232, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 232] +!136 = metadata !{i32 786688, metadata !132, metadata !"j", metadata !5, i32 232, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 232] +!137 = metadata !{i32 786688, metadata !132, metadata !"k", metadata !5, i32 232, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 232] +!138 = metadata !{i32 786688, metadata !132, metadata !"m", metadata !5, i32 232, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 232] +!139 = metadata !{i32 786688, metadata !132, metadata !"d", metadata !5, i32 232, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [d] [line 232] +!140 = metadata !{i32 786688, metadata !132, metadata !"xi", metadata !5, i32 233, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xi] [line 233] +!141 = metadata !{i32 786688, metadata !132, metadata !"eta", metadata !5, i32 233, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [eta] [line 233] +!142 = metadata !{i32 786688, metadata !132, metadata !"zeta", metadata !5, i32 233, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [zeta] [line 233] +!143 = metadata !{i32 786688, metadata !132, metadata !"u_exact", metadata !5, i32 233, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [u_exact] [line 233] +!144 = metadata !{i32 786688, metadata !132, metadata !"add", metadata !5, i32 233, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [add] [line 233] +!145 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"exact_solution", metadata !"exact_solution", metadata !"", i32 643, metadata !146, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !148, i32 644} ; [ DW_TAG_subprogram ] [line 643] [local] [def] [scope 644] [exact_solution] +!146 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !147, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!147 = metadata !{null, metadata !20, metadata !20, metadata !20, metadata !105} +!148 = metadata !{metadata !149, metadata !150, metadata !151, metadata !152, metadata !153} +!149 = metadata !{i32 786689, metadata !145, metadata !"xi", metadata !5, i32 16777859, metadata !20, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [xi] [line 643] +!150 = metadata !{i32 786689, metadata !145, metadata !"eta", metadata !5, i32 33555075, metadata !20, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [eta] [line 643] +!151 = metadata !{i32 786689, metadata !145, metadata !"zeta", metadata !5, i32 50332291, metadata !20, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [zeta] [line 643] +!152 = metadata !{i32 786689, metadata !145, metadata !"dtemp", metadata !5, i32 67109508, metadata !105, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [dtemp] [line 644] +!153 = metadata !{i32 786688, metadata !145, metadata !"m", metadata !5, i32 653, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 653] +!154 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"set_constants", metadata !"set_constants", metadata !"", i32 2191, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !2, i32 2191} ; [ DW_TAG_subprogram ] [line 2191] [local] [def] [set_constants] +!155 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"lhsinit", metadata !"lhsinit", metadata !"", i32 855, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !156, i32 855} ; [ DW_TAG_subprogram ] [line 855] [local] [def] [lhsinit] +!156 = metadata !{metadata !157, metadata !158, metadata !159, metadata !160, metadata !161} +!157 = metadata !{i32 786688, metadata !155, metadata !"i", metadata !5, i32 857, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 857] +!158 = metadata !{i32 786688, metadata !155, metadata !"j", metadata !5, i32 857, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 857] +!159 = metadata !{i32 786688, metadata !155, metadata !"k", metadata !5, i32 857, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 857] +!160 = metadata !{i32 786688, metadata !155, metadata !"m", metadata !5, i32 857, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 857] +!161 = metadata !{i32 786688, metadata !155, metadata !"n", metadata !5, i32 857, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [n] [line 857] +!162 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"initialize", metadata !"initialize", metadata !"", i32 669, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !163, i32 669} ; [ DW_TAG_subprogram ] [line 669] [local] [def] [initialize] +!163 = metadata !{metadata !164, metadata !165, metadata !166, metadata !167, metadata !168, metadata !169, metadata !170, metadata !171, metadata !172, metadata !173, metadata !174, metadata !179, metadata !180, metadata !181, metadata !182} +!164 = metadata !{i32 786688, metadata !162, metadata !"i", metadata !5, i32 679, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 679] +!165 = metadata !{i32 786688, metadata !162, metadata !"j", metadata !5, i32 679, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 679] +!166 = metadata !{i32 786688, metadata !162, metadata !"k", metadata !5, i32 679, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 679] +!167 = metadata !{i32 786688, metadata !162, metadata !"m", metadata !5, i32 679, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 679] +!168 = metadata !{i32 786688, metadata !162, metadata !"ix", metadata !5, i32 679, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [ix] [line 679] +!169 = metadata !{i32 786688, metadata !162, metadata !"iy", metadata !5, i32 679, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [iy] [line 679] +!170 = metadata !{i32 786688, metadata !162, metadata !"iz", metadata !5, i32 679, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [iz] [line 679] +!171 = metadata !{i32 786688, metadata !162, metadata !"xi", metadata !5, i32 680, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xi] [line 680] +!172 = metadata !{i32 786688, metadata !162, metadata !"eta", metadata !5, i32 680, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [eta] [line 680] +!173 = metadata !{i32 786688, metadata !162, metadata !"zeta", metadata !5, i32 680, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [zeta] [line 680] +!174 = metadata !{i32 786688, metadata !162, metadata !"Pface", metadata !5, i32 680, metadata !175, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [Pface] [line 680] +!175 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 1920, i64 64, i32 0, i32 0, metadata !20, metadata !176, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1920, align 64, offset 0] [from double] +!176 = metadata !{metadata !177, metadata !178, metadata !93} +!177 = metadata !{i32 786465, i64 0, i64 2} ; [ DW_TAG_subrange_type ] [0, 1] +!178 = metadata !{i32 786465, i64 0, i64 3} ; [ DW_TAG_subrange_type ] [0, 2] +!179 = metadata !{i32 786688, metadata !162, metadata !"Pxi", metadata !5, i32 680, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [Pxi] [line 680] +!180 = metadata !{i32 786688, metadata !162, metadata !"Peta", metadata !5, i32 680, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [Peta] [line 680] +!181 = metadata !{i32 786688, metadata !162, metadata !"Pzeta", metadata !5, i32 680, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [Pzeta] [line 680] +!182 = metadata !{i32 786688, metadata !162, metadata !"temp", metadata !5, i32 680, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [temp] [line 680] +!183 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"exact_rhs", metadata !"exact_rhs", metadata !"", i32 301, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !184, i32 301} ; [ DW_TAG_subprogram ] [line 301] [local] [def] [exact_rhs] +!184 = metadata !{metadata !185, metadata !186, metadata !187, metadata !188, metadata !189, metadata !190, metadata !191, metadata !192, metadata !193, metadata !194, metadata !195, metadata !196, metadata !197, metadata !198, metadata !199} +!185 = metadata !{i32 786688, metadata !183, metadata !"dtemp", metadata !5, i32 310, metadata !91, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [dtemp] [line 310] +!186 = metadata !{i32 786688, metadata !183, metadata !"xi", metadata !5, i32 310, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [xi] [line 310] +!187 = metadata !{i32 786688, metadata !183, metadata !"eta", metadata !5, i32 310, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [eta] [line 310] +!188 = metadata !{i32 786688, metadata !183, metadata !"zeta", metadata !5, i32 310, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [zeta] [line 310] +!189 = metadata !{i32 786688, metadata !183, metadata !"dtpp", metadata !5, i32 310, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [dtpp] [line 310] +!190 = metadata !{i32 786688, metadata !183, metadata !"m", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 311] +!191 = metadata !{i32 786688, metadata !183, metadata !"i", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 311] +!192 = metadata !{i32 786688, metadata !183, metadata !"j", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 311] +!193 = metadata !{i32 786688, metadata !183, metadata !"k", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 311] +!194 = metadata !{i32 786688, metadata !183, metadata !"ip1", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [ip1] [line 311] +!195 = metadata !{i32 786688, metadata !183, metadata !"im1", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [im1] [line 311] +!196 = metadata !{i32 786688, metadata !183, metadata !"jp1", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [jp1] [line 311] +!197 = metadata !{i32 786688, metadata !183, metadata !"jm1", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [jm1] [line 311] +!198 = metadata !{i32 786688, metadata !183, metadata !"km1", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [km1] [line 311] +!199 = metadata !{i32 786688, metadata !183, metadata !"kp1", metadata !5, i32 311, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [kp1] [line 311] +!200 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"adi", metadata !"adi", metadata !"", i32 210, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !2, i32 210} ; [ DW_TAG_subprogram ] [line 210] [local] [def] [adi] +!201 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"add", metadata !"add", metadata !"", i32 187, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !202, i32 187} ; [ DW_TAG_subprogram ] [line 187] [local] [def] [add] +!202 = metadata !{metadata !203, metadata !204, metadata !205, metadata !206} +!203 = metadata !{i32 786688, metadata !201, metadata !"i", metadata !5, i32 193, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 193] +!204 = metadata !{i32 786688, metadata !201, metadata !"j", metadata !5, i32 193, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 193] +!205 = metadata !{i32 786688, metadata !201, metadata !"k", metadata !5, i32 193, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 193] +!206 = metadata !{i32 786688, metadata !201, metadata !"m", metadata !5, i32 193, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 193] +!207 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"z_solve", metadata !"z_solve", metadata !"", i32 3457, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !2, i32 3457} ; [ DW_TAG_subprogram ] [line 3457] [local] [def] [z_solve] +!208 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"z_backsubstitute", metadata !"z_backsubstitute", metadata !"", i32 3480, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !209, i32 3480} ; [ DW_TAG_subprogram ] [line 3480] [local] [def] [z_backsubstitute] +!209 = metadata !{metadata !210, metadata !211, metadata !212, metadata !213, metadata !214} +!210 = metadata !{i32 786688, metadata !208, metadata !"i", metadata !5, i32 3492, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 3492] +!211 = metadata !{i32 786688, metadata !208, metadata !"j", metadata !5, i32 3492, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 3492] +!212 = metadata !{i32 786688, metadata !208, metadata !"k", metadata !5, i32 3492, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 3492] +!213 = metadata !{i32 786688, metadata !208, metadata !"m", metadata !5, i32 3492, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 3492] +!214 = metadata !{i32 786688, metadata !208, metadata !"n", metadata !5, i32 3492, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [n] [line 3492] +!215 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"z_solve_cell", metadata !"z_solve_cell", metadata !"", i32 3512, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !216, i32 3512} ; [ DW_TAG_subprogram ] [line 3512] [local] [def] [z_solve_cell] +!216 = metadata !{metadata !217, metadata !218, metadata !219, metadata !220} +!217 = metadata !{i32 786688, metadata !215, metadata !"i", metadata !5, i32 3527, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 3527] +!218 = metadata !{i32 786688, metadata !215, metadata !"j", metadata !5, i32 3527, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 3527] +!219 = metadata !{i32 786688, metadata !215, metadata !"k", metadata !5, i32 3527, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 3527] +!220 = metadata !{i32 786688, metadata !215, metadata !"ksize", metadata !5, i32 3527, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [ksize] [line 3527] +!221 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"binvrhs", metadata !"binvrhs", metadata !"", i32 3154, metadata !222, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !225, i32 3154} ; [ DW_TAG_subprogram ] [line 3154] [local] [def] [binvrhs] +!222 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !223, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!223 = metadata !{null, metadata !224, metadata !105} +!224 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !91} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] +!225 = metadata !{metadata !226, metadata !227, metadata !228, metadata !229} +!226 = metadata !{i32 786689, metadata !221, metadata !"lhs", metadata !5, i32 16780370, metadata !224, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [lhs] [line 3154] +!227 = metadata !{i32 786689, metadata !221, metadata !"r", metadata !5, i32 33557586, metadata !105, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [r] [line 3154] +!228 = metadata !{i32 786688, metadata !221, metadata !"pivot", metadata !5, i32 3159, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [pivot] [line 3159] +!229 = metadata !{i32 786688, metadata !221, metadata !"coeff", metadata !5, i32 3159, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [coeff] [line 3159] +!230 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"matmul_sub", metadata !"matmul_sub", metadata !"", i32 2841, metadata !231, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !233, i32 2842} ; [ DW_TAG_subprogram ] [line 2841] [local] [def] [scope 2842] [matmul_sub] +!231 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !232, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!232 = metadata !{null, metadata !224, metadata !224, metadata !224} +!233 = metadata !{metadata !234, metadata !235, metadata !236, metadata !237} +!234 = metadata !{i32 786689, metadata !230, metadata !"ablock", metadata !5, i32 16780057, metadata !224, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [ablock] [line 2841] +!235 = metadata !{i32 786689, metadata !230, metadata !"bblock", metadata !5, i32 33557273, metadata !224, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [bblock] [line 2841] +!236 = metadata !{i32 786689, metadata !230, metadata !"cblock", metadata !5, i32 50334490, metadata !224, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [cblock] [line 2842] +!237 = metadata !{i32 786688, metadata !230, metadata !"j", metadata !5, i32 2851, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 2851] +!238 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"matvec_sub", metadata !"matvec_sub", metadata !"", i32 2814, metadata !239, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !241, i32 2814} ; [ DW_TAG_subprogram ] [line 2814] [local] [def] [matvec_sub] +!239 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !240, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!240 = metadata !{null, metadata !224, metadata !105, metadata !105} +!241 = metadata !{metadata !242, metadata !243, metadata !244, metadata !245} +!242 = metadata !{i32 786689, metadata !238, metadata !"ablock", metadata !5, i32 16780030, metadata !224, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [ablock] [line 2814] +!243 = metadata !{i32 786689, metadata !238, metadata !"avec", metadata !5, i32 33557246, metadata !105, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [avec] [line 2814] +!244 = metadata !{i32 786689, metadata !238, metadata !"bvec", metadata !5, i32 50334462, metadata !105, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [bvec] [line 2814] +!245 = metadata !{i32 786688, metadata !238, metadata !"i", metadata !5, i32 2823, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 2823] +!246 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"binvcrhs", metadata !"binvcrhs", metadata !"", i32 2885, metadata !247, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !249, i32 2885} ; [ DW_TAG_subprogram ] [line 2885] [local] [def] [binvcrhs] +!247 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !248, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!248 = metadata !{null, metadata !224, metadata !224, metadata !105} +!249 = metadata !{metadata !250, metadata !251, metadata !252, metadata !253, metadata !254} +!250 = metadata !{i32 786689, metadata !246, metadata !"lhs", metadata !5, i32 16780101, metadata !224, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [lhs] [line 2885] +!251 = metadata !{i32 786689, metadata !246, metadata !"c", metadata !5, i32 33557317, metadata !224, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [c] [line 2885] +!252 = metadata !{i32 786689, metadata !246, metadata !"r", metadata !5, i32 50334533, metadata !105, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [r] [line 2885] +!253 = metadata !{i32 786688, metadata !246, metadata !"pivot", metadata !5, i32 2890, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [pivot] [line 2890] +!254 = metadata !{i32 786688, metadata !246, metadata !"coeff", metadata !5, i32 2890, metadata !20, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [coeff] [line 2890] +!255 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"lhsz", metadata !"lhsz", metadata !"", i32 1475, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !256, i32 1475} ; [ DW_TAG_subprogram ] [line 1475] [local] [def] [lhsz] +!256 = metadata !{metadata !257, metadata !258, metadata !259} +!257 = metadata !{i32 786688, metadata !255, metadata !"i", metadata !5, i32 1484, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 1484] +!258 = metadata !{i32 786688, metadata !255, metadata !"j", metadata !5, i32 1484, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 1484] +!259 = metadata !{i32 786688, metadata !255, metadata !"k", metadata !5, i32 1484, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 1484] +!260 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"y_solve", metadata !"y_solve", metadata !"", i32 3299, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !2, i32 3299} ; [ DW_TAG_subprogram ] [line 3299] [local] [def] [y_solve] +!261 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"y_backsubstitute", metadata !"y_backsubstitute", metadata !"", i32 3323, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !262, i32 3323} ; [ DW_TAG_subprogram ] [line 3323] [local] [def] [y_backsubstitute] +!262 = metadata !{metadata !263, metadata !264, metadata !265, metadata !266, metadata !267} +!263 = metadata !{i32 786688, metadata !261, metadata !"i", metadata !5, i32 3335, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 3335] +!264 = metadata !{i32 786688, metadata !261, metadata !"j", metadata !5, i32 3335, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 3335] +!265 = metadata !{i32 786688, metadata !261, metadata !"k", metadata !5, i32 3335, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 3335] +!266 = metadata !{i32 786688, metadata !261, metadata !"m", metadata !5, i32 3335, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 3335] +!267 = metadata !{i32 786688, metadata !261, metadata !"n", metadata !5, i32 3335, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [n] [line 3335] +!268 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"y_solve_cell", metadata !"y_solve_cell", metadata !"", i32 3355, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !269, i32 3355} ; [ DW_TAG_subprogram ] [line 3355] [local] [def] [y_solve_cell] +!269 = metadata !{metadata !270, metadata !271, metadata !272, metadata !273} +!270 = metadata !{i32 786688, metadata !268, metadata !"i", metadata !5, i32 3370, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 3370] +!271 = metadata !{i32 786688, metadata !268, metadata !"j", metadata !5, i32 3370, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 3370] +!272 = metadata !{i32 786688, metadata !268, metadata !"k", metadata !5, i32 3370, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 3370] +!273 = metadata !{i32 786688, metadata !268, metadata !"jsize", metadata !5, i32 3370, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [jsize] [line 3370] +!274 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"lhsy", metadata !"lhsy", metadata !"", i32 1181, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !275, i32 1181} ; [ DW_TAG_subprogram ] [line 1181] [local] [def] [lhsy] +!275 = metadata !{metadata !276, metadata !277, metadata !278} +!276 = metadata !{i32 786688, metadata !274, metadata !"i", metadata !5, i32 1190, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 1190] +!277 = metadata !{i32 786688, metadata !274, metadata !"j", metadata !5, i32 1190, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 1190] +!278 = metadata !{i32 786688, metadata !274, metadata !"k", metadata !5, i32 1190, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 1190] +!279 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"x_solve", metadata !"x_solve", metadata !"", i32 2658, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !2, i32 2658} ; [ DW_TAG_subprogram ] [line 2658] [local] [def] [x_solve] +!280 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"x_backsubstitute", metadata !"x_backsubstitute", metadata !"", i32 2684, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !281, i32 2684} ; [ DW_TAG_subprogram ] [line 2684] [local] [def] [x_backsubstitute] +!281 = metadata !{metadata !282, metadata !283, metadata !284, metadata !285, metadata !286} +!282 = metadata !{i32 786688, metadata !280, metadata !"i", metadata !5, i32 2696, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 2696] +!283 = metadata !{i32 786688, metadata !280, metadata !"j", metadata !5, i32 2696, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 2696] +!284 = metadata !{i32 786688, metadata !280, metadata !"k", metadata !5, i32 2696, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 2696] +!285 = metadata !{i32 786688, metadata !280, metadata !"m", metadata !5, i32 2696, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [m] [line 2696] +!286 = metadata !{i32 786688, metadata !280, metadata !"n", metadata !5, i32 2696, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [n] [line 2696] +!287 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"x_solve_cell", metadata !"x_solve_cell", metadata !"", i32 2716, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !288, i32 2716} ; [ DW_TAG_subprogram ] [line 2716] [local] [def] [x_solve_cell] +!288 = metadata !{metadata !289, metadata !290, metadata !291, metadata !292} +!289 = metadata !{i32 786688, metadata !287, metadata !"i", metadata !5, i32 2728, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 2728] +!290 = metadata !{i32 786688, metadata !287, metadata !"j", metadata !5, i32 2728, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 2728] +!291 = metadata !{i32 786688, metadata !287, metadata !"k", metadata !5, i32 2728, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 2728] +!292 = metadata !{i32 786688, metadata !287, metadata !"isize", metadata !5, i32 2728, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [isize] [line 2728] +!293 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"lhsx", metadata !"lhsx", metadata !"", i32 898, metadata !115, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !294, i32 898} ; [ DW_TAG_subprogram ] [line 898] [local] [def] [lhsx] +!294 = metadata !{metadata !295, metadata !296, metadata !297} +!295 = metadata !{i32 786688, metadata !293, metadata !"i", metadata !5, i32 907, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 907] +!296 = metadata !{i32 786688, metadata !293, metadata !"j", metadata !5, i32 907, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [j] [line 907] +!297 = metadata !{i32 786688, metadata !293, metadata !"k", metadata !5, i32 907, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k] [line 907] +!298 = metadata !{metadata !299, metadata !304, metadata !305, metadata !309, metadata !310, metadata !311, metadata !312, metadata !313, metadata !314, metadata !315, metadata !316, metadata !317, metadata !318, metadata !319, metadata !320, metadata !321, metadata !322, metadata !323, metadata !324, metadata !325, metadata !326, metadata !327, metadata !328, metadata !329, metadata !330, metadata !331, metadata !332, metadata !333, metadata !334, metadata !335, metadata !336, metadata !337, metadata !338, metadata !339, metadata !340, metadata !341, metadata !342, metadata !343, metadata !347, metadata !350, metadata !351, metadata !352, metadata !353, metadata !354, metadata !355, metadata !356, metadata !360, metadata !361, metadata !362, metadata !363, metadata !364, metadata !365, metadata !366, metadata !367, metadata !368, metadata !369, metadata !370, metadata !371, metadata !372, metadata !373, metadata !374, metadata !375, metadata !376, metadata !377, metadata !378, metadata !379, metadata !380, metadata !381, metadata !382, metadata !383, metadata !384, metadata !385, metadata !386, metadata !387, metadata !388, metadata !389, metadata !390, metadata !391, metadata !392, metadata !393, metadata !394, metadata !395, metadata !396, metadata !397, metadata !398, metadata !399, metadata !400, metadata !401, metadata !402, metadata !403, metadata !404, metadata !405, metadata !406, metadata !407, metadata !408, metadata !409, metadata !410, metadata !411, metadata !412, metadata !413, metadata !414, metadata !415, metadata !416, metadata !417, metadata !418, metadata !419, metadata !422, metadata !426, metadata !427, metadata !430, metadata !431, metadata !434, metadata !435, metadata !436, metadata !437} +!299 = metadata !{i32 786484, i32 0, null, metadata !"grid_points", metadata !"grid_points", metadata !"", metadata !300, i32 28, metadata !302, i32 1, i32 1, [3 x i32]* @grid_points, null} ; [ DW_TAG_variable ] [grid_points] [line 28] [local] [def] +!300 = metadata !{i32 786473, metadata !301} ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/./header.h] +!301 = metadata !{metadata !"./header.h", metadata !"/home/hfinkel/src/NPB2.3-omp-C/BT"} +!302 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 96, i64 32, i32 0, i32 0, metadata !8, metadata !303, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 96, align 32, offset 0] [from int] +!303 = metadata !{metadata !178} +!304 = metadata !{i32 786484, i32 0, null, metadata !"dt", metadata !"dt", metadata !"", metadata !300, i32 35, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dt] [line 35] [local] [def] +!305 = metadata !{i32 786484, i32 0, null, metadata !"rhs", metadata !"rhs", metadata !"", metadata !300, i32 68, metadata !306, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [rhs] [line 68] [local] [def] +!306 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 1385839040, i64 64, i32 0, i32 0, metadata !20, metadata !307, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1385839040, align 64, offset 0] [from double] +!307 = metadata !{metadata !308, metadata !308, metadata !308, metadata !93} +!308 = metadata !{i32 786465, i64 0, i64 163} ; [ DW_TAG_subrange_type ] [0, 162] +!309 = metadata !{i32 786484, i32 0, null, metadata !"zzcon5", metadata !"zzcon5", metadata !"", metadata !300, i32 42, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [zzcon5] [line 42] [local] [def] +!310 = metadata !{i32 786484, i32 0, null, metadata !"zzcon4", metadata !"zzcon4", metadata !"", metadata !300, i32 42, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [zzcon4] [line 42] [local] [def] +!311 = metadata !{i32 786484, i32 0, null, metadata !"zzcon3", metadata !"zzcon3", metadata !"", metadata !300, i32 42, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [zzcon3] [line 42] [local] [def] +!312 = metadata !{i32 786484, i32 0, null, metadata !"dz5tz1", metadata !"dz5tz1", metadata !"", metadata !300, i32 43, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz5tz1] [line 43] [local] [def] +!313 = metadata !{i32 786484, i32 0, null, metadata !"dz4tz1", metadata !"dz4tz1", metadata !"", metadata !300, i32 43, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz4tz1] [line 43] [local] [def] +!314 = metadata !{i32 786484, i32 0, null, metadata !"dz3tz1", metadata !"dz3tz1", metadata !"", metadata !300, i32 43, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz3tz1] [line 43] [local] [def] +!315 = metadata !{i32 786484, i32 0, null, metadata !"zzcon2", metadata !"zzcon2", metadata !"", metadata !300, i32 42, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [zzcon2] [line 42] [local] [def] +!316 = metadata !{i32 786484, i32 0, null, metadata !"dz2tz1", metadata !"dz2tz1", metadata !"", metadata !300, i32 43, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz2tz1] [line 43] [local] [def] +!317 = metadata !{i32 786484, i32 0, null, metadata !"tz2", metadata !"tz2", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tz2] [line 31] [local] [def] +!318 = metadata !{i32 786484, i32 0, null, metadata !"dz1tz1", metadata !"dz1tz1", metadata !"", metadata !300, i32 43, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz1tz1] [line 43] [local] [def] +!319 = metadata !{i32 786484, i32 0, null, metadata !"yycon5", metadata !"yycon5", metadata !"", metadata !300, i32 40, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [yycon5] [line 40] [local] [def] +!320 = metadata !{i32 786484, i32 0, null, metadata !"yycon4", metadata !"yycon4", metadata !"", metadata !300, i32 40, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [yycon4] [line 40] [local] [def] +!321 = metadata !{i32 786484, i32 0, null, metadata !"yycon3", metadata !"yycon3", metadata !"", metadata !300, i32 40, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [yycon3] [line 40] [local] [def] +!322 = metadata !{i32 786484, i32 0, null, metadata !"dy5ty1", metadata !"dy5ty1", metadata !"", metadata !300, i32 41, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy5ty1] [line 41] [local] [def] +!323 = metadata !{i32 786484, i32 0, null, metadata !"dy4ty1", metadata !"dy4ty1", metadata !"", metadata !300, i32 41, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy4ty1] [line 41] [local] [def] +!324 = metadata !{i32 786484, i32 0, null, metadata !"dy3ty1", metadata !"dy3ty1", metadata !"", metadata !300, i32 41, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy3ty1] [line 41] [local] [def] +!325 = metadata !{i32 786484, i32 0, null, metadata !"yycon2", metadata !"yycon2", metadata !"", metadata !300, i32 40, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [yycon2] [line 40] [local] [def] +!326 = metadata !{i32 786484, i32 0, null, metadata !"dy2ty1", metadata !"dy2ty1", metadata !"", metadata !300, i32 41, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy2ty1] [line 41] [local] [def] +!327 = metadata !{i32 786484, i32 0, null, metadata !"ty2", metadata !"ty2", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [ty2] [line 31] [local] [def] +!328 = metadata !{i32 786484, i32 0, null, metadata !"dy1ty1", metadata !"dy1ty1", metadata !"", metadata !300, i32 41, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy1ty1] [line 41] [local] [def] +!329 = metadata !{i32 786484, i32 0, null, metadata !"dssp", metadata !"dssp", metadata !"", metadata !300, i32 35, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dssp] [line 35] [local] [def] +!330 = metadata !{i32 786484, i32 0, null, metadata !"c1", metadata !"c1", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c1] [line 45] [local] [def] +!331 = metadata !{i32 786484, i32 0, null, metadata !"xxcon5", metadata !"xxcon5", metadata !"", metadata !300, i32 38, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [xxcon5] [line 38] [local] [def] +!332 = metadata !{i32 786484, i32 0, null, metadata !"xxcon4", metadata !"xxcon4", metadata !"", metadata !300, i32 38, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [xxcon4] [line 38] [local] [def] +!333 = metadata !{i32 786484, i32 0, null, metadata !"xxcon3", metadata !"xxcon3", metadata !"", metadata !300, i32 38, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [xxcon3] [line 38] [local] [def] +!334 = metadata !{i32 786484, i32 0, null, metadata !"dx5tx1", metadata !"dx5tx1", metadata !"", metadata !300, i32 39, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx5tx1] [line 39] [local] [def] +!335 = metadata !{i32 786484, i32 0, null, metadata !"dx4tx1", metadata !"dx4tx1", metadata !"", metadata !300, i32 39, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx4tx1] [line 39] [local] [def] +!336 = metadata !{i32 786484, i32 0, null, metadata !"dx3tx1", metadata !"dx3tx1", metadata !"", metadata !300, i32 39, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx3tx1] [line 39] [local] [def] +!337 = metadata !{i32 786484, i32 0, null, metadata !"c2", metadata !"c2", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c2] [line 45] [local] [def] +!338 = metadata !{i32 786484, i32 0, null, metadata !"con43", metadata !"con43", metadata !"", metadata !300, i32 48, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [con43] [line 48] [local] [def] +!339 = metadata !{i32 786484, i32 0, null, metadata !"xxcon2", metadata !"xxcon2", metadata !"", metadata !300, i32 38, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [xxcon2] [line 38] [local] [def] +!340 = metadata !{i32 786484, i32 0, null, metadata !"dx2tx1", metadata !"dx2tx1", metadata !"", metadata !300, i32 39, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx2tx1] [line 39] [local] [def] +!341 = metadata !{i32 786484, i32 0, null, metadata !"tx2", metadata !"tx2", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tx2] [line 31] [local] [def] +!342 = metadata !{i32 786484, i32 0, null, metadata !"dx1tx1", metadata !"dx1tx1", metadata !"", metadata !300, i32 39, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx1tx1] [line 39] [local] [def] +!343 = metadata !{i32 786484, i32 0, null, metadata !"forcing", metadata !"forcing", metadata !"", metadata !300, i32 66, metadata !344, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [forcing] [line 66] [local] [def] +!344 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 1663006848, i64 64, i32 0, i32 0, metadata !20, metadata !345, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1663006848, align 64, offset 0] [from double] +!345 = metadata !{metadata !308, metadata !308, metadata !308, metadata !346} +!346 = metadata !{i32 786465, i64 0, i64 6} ; [ DW_TAG_subrange_type ] [0, 5] +!347 = metadata !{i32 786484, i32 0, null, metadata !"qs", metadata !"qs", metadata !"", metadata !300, i32 63, metadata !348, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [qs] [line 63] [local] [def] +!348 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 277167808, i64 64, i32 0, i32 0, metadata !20, metadata !349, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 277167808, align 64, offset 0] [from double] +!349 = metadata !{metadata !308, metadata !308, metadata !308} +!350 = metadata !{i32 786484, i32 0, null, metadata !"square", metadata !"square", metadata !"", metadata !300, i32 65, metadata !348, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [square] [line 65] [local] [def] +!351 = metadata !{i32 786484, i32 0, null, metadata !"ws", metadata !"ws", metadata !"", metadata !300, i32 62, metadata !348, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [ws] [line 62] [local] [def] +!352 = metadata !{i32 786484, i32 0, null, metadata !"vs", metadata !"vs", metadata !"", metadata !300, i32 61, metadata !348, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [vs] [line 61] [local] [def] +!353 = metadata !{i32 786484, i32 0, null, metadata !"us", metadata !"us", metadata !"", metadata !300, i32 60, metadata !348, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [us] [line 60] [local] [def] +!354 = metadata !{i32 786484, i32 0, null, metadata !"rho_i", metadata !"rho_i", metadata !"", metadata !300, i32 64, metadata !348, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [rho_i] [line 64] [local] [def] +!355 = metadata !{i32 786484, i32 0, null, metadata !"u", metadata !"u", metadata !"", metadata !300, i32 67, metadata !306, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [u] [line 67] [local] [def] +!356 = metadata !{i32 786484, i32 0, null, metadata !"ce", metadata !"ce", metadata !"", metadata !300, i32 36, metadata !357, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [ce] [line 36] [local] [def] +!357 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 4160, i64 64, i32 0, i32 0, metadata !20, metadata !358, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 4160, align 64, offset 0] [from double] +!358 = metadata !{metadata !93, metadata !359} +!359 = metadata !{i32 786465, i64 0, i64 13} ; [ DW_TAG_subrange_type ] [0, 12] +!360 = metadata !{i32 786484, i32 0, null, metadata !"dnzm1", metadata !"dnzm1", metadata !"", metadata !300, i32 44, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dnzm1] [line 44] [local] [def] +!361 = metadata !{i32 786484, i32 0, null, metadata !"dnym1", metadata !"dnym1", metadata !"", metadata !300, i32 44, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dnym1] [line 44] [local] [def] +!362 = metadata !{i32 786484, i32 0, null, metadata !"dnxm1", metadata !"dnxm1", metadata !"", metadata !300, i32 44, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dnxm1] [line 44] [local] [def] +!363 = metadata !{i32 786484, i32 0, null, metadata !"zzcon1", metadata !"zzcon1", metadata !"", metadata !300, i32 42, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [zzcon1] [line 42] [local] [def] +!364 = metadata !{i32 786484, i32 0, null, metadata !"yycon1", metadata !"yycon1", metadata !"", metadata !300, i32 40, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [yycon1] [line 40] [local] [def] +!365 = metadata !{i32 786484, i32 0, null, metadata !"xxcon1", metadata !"xxcon1", metadata !"", metadata !300, i32 38, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [xxcon1] [line 38] [local] [def] +!366 = metadata !{i32 786484, i32 0, null, metadata !"con16", metadata !"con16", metadata !"", metadata !300, i32 48, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [con16] [line 48] [local] [def] +!367 = metadata !{i32 786484, i32 0, null, metadata !"c2iv", metadata !"c2iv", metadata !"", metadata !300, i32 48, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c2iv] [line 48] [local] [def] +!368 = metadata !{i32 786484, i32 0, null, metadata !"c3c4tz3", metadata !"c3c4tz3", metadata !"", metadata !300, i32 48, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c3c4tz3] [line 48] [local] [def] +!369 = metadata !{i32 786484, i32 0, null, metadata !"c3c4ty3", metadata !"c3c4ty3", metadata !"", metadata !300, i32 48, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c3c4ty3] [line 48] [local] [def] +!370 = metadata !{i32 786484, i32 0, null, metadata !"c3c4tx3", metadata !"c3c4tx3", metadata !"", metadata !300, i32 48, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c3c4tx3] [line 48] [local] [def] +!371 = metadata !{i32 786484, i32 0, null, metadata !"comz6", metadata !"comz6", metadata !"", metadata !300, i32 47, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [comz6] [line 47] [local] [def] +!372 = metadata !{i32 786484, i32 0, null, metadata !"comz5", metadata !"comz5", metadata !"", metadata !300, i32 47, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [comz5] [line 47] [local] [def] +!373 = metadata !{i32 786484, i32 0, null, metadata !"comz4", metadata !"comz4", metadata !"", metadata !300, i32 47, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [comz4] [line 47] [local] [def] +!374 = metadata !{i32 786484, i32 0, null, metadata !"comz1", metadata !"comz1", metadata !"", metadata !300, i32 47, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [comz1] [line 47] [local] [def] +!375 = metadata !{i32 786484, i32 0, null, metadata !"dtdssp", metadata !"dtdssp", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dtdssp] [line 45] [local] [def] +!376 = metadata !{i32 786484, i32 0, null, metadata !"c2dttz1", metadata !"c2dttz1", metadata !"", metadata !300, i32 47, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c2dttz1] [line 47] [local] [def] +!377 = metadata !{i32 786484, i32 0, null, metadata !"c2dtty1", metadata !"c2dtty1", metadata !"", metadata !300, i32 47, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c2dtty1] [line 47] [local] [def] +!378 = metadata !{i32 786484, i32 0, null, metadata !"c2dttx1", metadata !"c2dttx1", metadata !"", metadata !300, i32 47, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c2dttx1] [line 47] [local] [def] +!379 = metadata !{i32 786484, i32 0, null, metadata !"dttz2", metadata !"dttz2", metadata !"", metadata !300, i32 46, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dttz2] [line 46] [local] [def] +!380 = metadata !{i32 786484, i32 0, null, metadata !"dttz1", metadata !"dttz1", metadata !"", metadata !300, i32 46, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dttz1] [line 46] [local] [def] +!381 = metadata !{i32 786484, i32 0, null, metadata !"dtty2", metadata !"dtty2", metadata !"", metadata !300, i32 46, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dtty2] [line 46] [local] [def] +!382 = metadata !{i32 786484, i32 0, null, metadata !"dtty1", metadata !"dtty1", metadata !"", metadata !300, i32 46, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dtty1] [line 46] [local] [def] +!383 = metadata !{i32 786484, i32 0, null, metadata !"dttx2", metadata !"dttx2", metadata !"", metadata !300, i32 46, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dttx2] [line 46] [local] [def] +!384 = metadata !{i32 786484, i32 0, null, metadata !"dttx1", metadata !"dttx1", metadata !"", metadata !300, i32 46, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dttx1] [line 46] [local] [def] +!385 = metadata !{i32 786484, i32 0, null, metadata !"c5dssp", metadata !"c5dssp", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c5dssp] [line 45] [local] [def] +!386 = metadata !{i32 786484, i32 0, null, metadata !"c4dssp", metadata !"c4dssp", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c4dssp] [line 45] [local] [def] +!387 = metadata !{i32 786484, i32 0, null, metadata !"dzmax", metadata !"dzmax", metadata !"", metadata !300, i32 37, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dzmax] [line 37] [local] [def] +!388 = metadata !{i32 786484, i32 0, null, metadata !"dymax", metadata !"dymax", metadata !"", metadata !300, i32 37, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dymax] [line 37] [local] [def] +!389 = metadata !{i32 786484, i32 0, null, metadata !"dxmax", metadata !"dxmax", metadata !"", metadata !300, i32 37, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dxmax] [line 37] [local] [def] +!390 = metadata !{i32 786484, i32 0, null, metadata !"dz5", metadata !"dz5", metadata !"", metadata !300, i32 34, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz5] [line 34] [local] [def] +!391 = metadata !{i32 786484, i32 0, null, metadata !"dz4", metadata !"dz4", metadata !"", metadata !300, i32 34, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz4] [line 34] [local] [def] +!392 = metadata !{i32 786484, i32 0, null, metadata !"dz3", metadata !"dz3", metadata !"", metadata !300, i32 34, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz3] [line 34] [local] [def] +!393 = metadata !{i32 786484, i32 0, null, metadata !"dz2", metadata !"dz2", metadata !"", metadata !300, i32 34, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz2] [line 34] [local] [def] +!394 = metadata !{i32 786484, i32 0, null, metadata !"dz1", metadata !"dz1", metadata !"", metadata !300, i32 34, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dz1] [line 34] [local] [def] +!395 = metadata !{i32 786484, i32 0, null, metadata !"dy5", metadata !"dy5", metadata !"", metadata !300, i32 33, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy5] [line 33] [local] [def] +!396 = metadata !{i32 786484, i32 0, null, metadata !"dy4", metadata !"dy4", metadata !"", metadata !300, i32 33, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy4] [line 33] [local] [def] +!397 = metadata !{i32 786484, i32 0, null, metadata !"dy3", metadata !"dy3", metadata !"", metadata !300, i32 33, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy3] [line 33] [local] [def] +!398 = metadata !{i32 786484, i32 0, null, metadata !"dy2", metadata !"dy2", metadata !"", metadata !300, i32 33, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy2] [line 33] [local] [def] +!399 = metadata !{i32 786484, i32 0, null, metadata !"dy1", metadata !"dy1", metadata !"", metadata !300, i32 33, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dy1] [line 33] [local] [def] +!400 = metadata !{i32 786484, i32 0, null, metadata !"dx5", metadata !"dx5", metadata !"", metadata !300, i32 32, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx5] [line 32] [local] [def] +!401 = metadata !{i32 786484, i32 0, null, metadata !"dx4", metadata !"dx4", metadata !"", metadata !300, i32 32, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx4] [line 32] [local] [def] +!402 = metadata !{i32 786484, i32 0, null, metadata !"dx3", metadata !"dx3", metadata !"", metadata !300, i32 32, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx3] [line 32] [local] [def] +!403 = metadata !{i32 786484, i32 0, null, metadata !"dx2", metadata !"dx2", metadata !"", metadata !300, i32 32, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx2] [line 32] [local] [def] +!404 = metadata !{i32 786484, i32 0, null, metadata !"dx1", metadata !"dx1", metadata !"", metadata !300, i32 32, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [dx1] [line 32] [local] [def] +!405 = metadata !{i32 786484, i32 0, null, metadata !"tz3", metadata !"tz3", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tz3] [line 31] [local] [def] +!406 = metadata !{i32 786484, i32 0, null, metadata !"tz1", metadata !"tz1", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tz1] [line 31] [local] [def] +!407 = metadata !{i32 786484, i32 0, null, metadata !"ty3", metadata !"ty3", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [ty3] [line 31] [local] [def] +!408 = metadata !{i32 786484, i32 0, null, metadata !"ty1", metadata !"ty1", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [ty1] [line 31] [local] [def] +!409 = metadata !{i32 786484, i32 0, null, metadata !"tx3", metadata !"tx3", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tx3] [line 31] [local] [def] +!410 = metadata !{i32 786484, i32 0, null, metadata !"tx1", metadata !"tx1", metadata !"", metadata !300, i32 31, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tx1] [line 31] [local] [def] +!411 = metadata !{i32 786484, i32 0, null, metadata !"conz1", metadata !"conz1", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [conz1] [line 45] [local] [def] +!412 = metadata !{i32 786484, i32 0, null, metadata !"c1345", metadata !"c1345", metadata !"", metadata !300, i32 44, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c1345] [line 44] [local] [def] +!413 = metadata !{i32 786484, i32 0, null, metadata !"c3c4", metadata !"c3c4", metadata !"", metadata !300, i32 44, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c3c4] [line 44] [local] [def] +!414 = metadata !{i32 786484, i32 0, null, metadata !"c1c5", metadata !"c1c5", metadata !"", metadata !300, i32 44, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c1c5] [line 44] [local] [def] +!415 = metadata !{i32 786484, i32 0, null, metadata !"c1c2", metadata !"c1c2", metadata !"", metadata !300, i32 44, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c1c2] [line 44] [local] [def] +!416 = metadata !{i32 786484, i32 0, null, metadata !"c5", metadata !"c5", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c5] [line 45] [local] [def] +!417 = metadata !{i32 786484, i32 0, null, metadata !"c4", metadata !"c4", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c4] [line 45] [local] [def] +!418 = metadata !{i32 786484, i32 0, null, metadata !"c3", metadata !"c3", metadata !"", metadata !300, i32 45, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [c3] [line 45] [local] [def] +!419 = metadata !{i32 786484, i32 0, null, metadata !"lhs", metadata !"lhs", metadata !"", metadata !300, i32 69, metadata !420, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [lhs] [line 69] [local] [def] +!420 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 20787585600, i64 64, i32 0, i32 0, metadata !20, metadata !421, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 20787585600, align 64, offset 0] [from double] +!421 = metadata !{metadata !308, metadata !308, metadata !308, metadata !178, metadata !93, metadata !93} +!422 = metadata !{i32 786484, i32 0, null, metadata !"q", metadata !"q", metadata !"", metadata !300, i32 73, metadata !423, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [q] [line 73] [local] [def] +!423 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 10368, i64 64, i32 0, i32 0, metadata !20, metadata !424, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 10368, align 64, offset 0] [from double] +!424 = metadata !{metadata !425} +!425 = metadata !{i32 786465, i64 0, i64 162} ; [ DW_TAG_subrange_type ] [0, 161] +!426 = metadata !{i32 786484, i32 0, null, metadata !"cuf", metadata !"cuf", metadata !"", metadata !300, i32 72, metadata !423, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [cuf] [line 72] [local] [def] +!427 = metadata !{i32 786484, i32 0, null, metadata !"buf", metadata !"buf", metadata !"", metadata !300, i32 75, metadata !428, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [buf] [line 75] [local] [def] +!428 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 51840, i64 64, i32 0, i32 0, metadata !20, metadata !429, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 51840, align 64, offset 0] [from double] +!429 = metadata !{metadata !425, metadata !93} +!430 = metadata !{i32 786484, i32 0, null, metadata !"ue", metadata !"ue", metadata !"", metadata !300, i32 74, metadata !428, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [ue] [line 74] [local] [def] +!431 = metadata !{i32 786484, i32 0, null, metadata !"njac", metadata !"njac", metadata !"", metadata !300, i32 86, metadata !432, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [njac] [line 86] [local] [def] +!432 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 6886684800, i64 64, i32 0, i32 0, metadata !20, metadata !433, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 6886684800, align 64, offset 0] [from double] +!433 = metadata !{metadata !308, metadata !308, metadata !425, metadata !93, metadata !93} +!434 = metadata !{i32 786484, i32 0, null, metadata !"fjac", metadata !"fjac", metadata !"", metadata !300, i32 84, metadata !432, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [fjac] [line 84] [local] [def] +!435 = metadata !{i32 786484, i32 0, null, metadata !"tmp3", metadata !"tmp3", metadata !"", metadata !300, i32 88, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tmp3] [line 88] [local] [def] +!436 = metadata !{i32 786484, i32 0, null, metadata !"tmp2", metadata !"tmp2", metadata !"", metadata !300, i32 88, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tmp2] [line 88] [local] [def] +!437 = metadata !{i32 786484, i32 0, null, metadata !"tmp1", metadata !"tmp1", metadata !"", metadata !300, i32 88, metadata !20, i32 1, i32 1, null, null} ; [ DW_TAG_variable ] [tmp1] [line 88] [local] [def] +!438 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!439 = metadata !{i32 1898, i32 0, metadata !440, null} +!440 = metadata !{i32 786443, metadata !1, metadata !114, i32 1898, i32 0, i32 107} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!441 = metadata !{i32 1913, i32 0, metadata !442, null} +!442 = metadata !{i32 786443, metadata !1, metadata !114, i32 1913, i32 0, i32 115} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!443 = metadata !{i32 1923, i32 0, metadata !114, null} +!444 = metadata !{metadata !"int", metadata !445} +!445 = metadata !{metadata !"omnipotent char", metadata !446} +!446 = metadata !{metadata !"Simple C/C++ TBAA"} +!447 = metadata !{i32 1} +!448 = metadata !{i32 1925, i32 0, metadata !449, null} +!449 = metadata !{i32 786443, metadata !1, metadata !114, i32 1925, i32 0, i32 121} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!450 = metadata !{i32 1939, i32 0, metadata !451, null} +!451 = metadata !{i32 786443, metadata !1, metadata !114, i32 1939, i32 0, i32 127} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!452 = metadata !{i32 1940, i32 0, metadata !453, null} +!453 = metadata !{i32 786443, metadata !1, metadata !454, i32 1940, i32 0, i32 129} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!454 = metadata !{i32 786443, metadata !1, metadata !451, i32 1939, i32 0, i32 128} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!455 = metadata !{i32 1941, i32 0, metadata !456, null} +!456 = metadata !{i32 786443, metadata !1, metadata !457, i32 1941, i32 0, i32 131} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!457 = metadata !{i32 786443, metadata !1, metadata !453, i32 1940, i32 0, i32 130} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!458 = metadata !{i32 2020, i32 0, metadata !459, null} +!459 = metadata !{i32 786443, metadata !1, metadata !460, i32 2020, i32 0, i32 149} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!460 = metadata !{i32 786443, metadata !1, metadata !461, i32 2019, i32 0, i32 148} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!461 = metadata !{i32 786443, metadata !1, metadata !462, i32 2019, i32 0, i32 147} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!462 = metadata !{i32 786443, metadata !1, metadata !463, i32 2018, i32 0, i32 146} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!463 = metadata !{i32 786443, metadata !1, metadata !114, i32 2018, i32 0, i32 145} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!464 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/PowerPC/pr17354.ll b/test/CodeGen/PowerPC/pr17354.ll new file mode 100644 index 000000000000..dca81b1c2ca6 --- /dev/null +++ b/test/CodeGen/PowerPC/pr17354.ll @@ -0,0 +1,39 @@ +; RUN: llc -mcpu=pwr7 -relocation-model=pic <%s | FileCheck %s + +; Test that PR17354 is fixed. We must generate a nop following even +; local calls when generating code for shared libraries, to permit +; TOC fixup. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.CS = type { i32 } + +@_ZL3glb = internal global [1 x %struct.CS] zeroinitializer, align 4 +@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }] + +define internal void @__cxx_global_var_init() section ".text.startup" { +entry: + call void @_Z4funcv(%struct.CS* sret getelementptr inbounds ([1 x %struct.CS]* @_ZL3glb, i64 0, i64 0)) + ret void +} + +; CHECK-LABEL: __cxx_global_var_init: +; CHECK: bl _Z4funcv +; CHECK-NEXT: nop + +; Function Attrs: nounwind +define void @_Z4funcv(%struct.CS* noalias sret %agg.result) #0 { +entry: + %a_ = getelementptr inbounds %struct.CS* %agg.result, i32 0, i32 0 + store i32 0, i32* %a_, align 4 + ret void +} + +define internal void @_GLOBAL__I_a() section ".text.startup" { +entry: + call void @__cxx_global_var_init() + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/recipest.ll b/test/CodeGen/PowerPC/recipest.ll index 89705faa46e9..891e801dd3b5 100644 --- a/test/CodeGen/PowerPC/recipest.ll +++ b/test/CodeGen/PowerPC/recipest.ll @@ -14,8 +14,8 @@ entry: ret double %r ; CHECK: @foo -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -39,8 +39,8 @@ entry: ret double %r ; CHECK: @foof -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls @@ -61,8 +61,8 @@ entry: ret float %r ; CHECK: @foo -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -86,8 +86,8 @@ entry: ret float %r ; CHECK: @goo -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls @@ -120,8 +120,8 @@ entry: ret double %r ; CHECK: @foo2 -; CHECK: fre -; CHECK: fnmsub +; CHECK-DAG: fre +; CHECK-DAG: fnmsub ; CHECK: fmadd ; CHECK: fnmsub ; CHECK: fmadd @@ -139,8 +139,8 @@ entry: ret float %r ; CHECK: @goo2 -; CHECK: fres -; CHECK: fnmsubs +; CHECK-DAG: fres +; CHECK-DAG: fnmsubs ; CHECK: fmadds ; CHECK: fmuls ; CHECK: blr @@ -169,8 +169,9 @@ entry: ret double %r ; CHECK: @foo3 -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK: fcmpu +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -195,8 +196,9 @@ entry: ret float %r ; CHECK: @goo3 -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK: fcmpu +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls @@ -217,7 +219,8 @@ entry: ; CHECK: @hoo3 ; CHECK: vrsqrtefp -; CHECK: vrefp +; CHECK-DAG: vrefp +; CHECK-DAG: vcmpeqfp ; CHECK-SAFE: @hoo3 ; CHECK-SAFE-NOT: vrsqrtefp diff --git a/test/CodeGen/PowerPC/reg-names.ll b/test/CodeGen/PowerPC/reg-names.ll new file mode 100644 index 000000000000..f8fa7e4020e9 --- /dev/null +++ b/test/CodeGen/PowerPC/reg-names.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-FN %s + +define i64 @test1(i64 %a, i64 %b) { +; CHECK-LABEL: @test1 +; CHECK-FN-LABEL: @test1 + +entry: + ret i64 %b + +; CHECK: mr 3, 4 +; CHECK-FN: mr r3, r4 + +; CHECK: blr +; CHECK-FN: blr +} + diff --git a/test/CodeGen/PowerPC/reloc-align.ll b/test/CodeGen/PowerPC/reloc-align.ll new file mode 100644 index 000000000000..13d6adadfcae --- /dev/null +++ b/test/CodeGen/PowerPC/reloc-align.ll @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/remap-crash.ll b/test/CodeGen/PowerPC/remap-crash.ll new file mode 100644 index 000000000000..515f720ba448 --- /dev/null +++ b/test/CodeGen/PowerPC/remap-crash.ll @@ -0,0 +1,57 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD13() { +BB: + br label %CF78 + +CF78: ; preds = %CF87, %CF86, %CF78, %BB + %Cmp = icmp ule <16 x i64> zeroinitializer, zeroinitializer + br i1 undef, label %CF78, label %CF86 + +CF86: ; preds = %CF78 + br i1 undef, label %CF78, label %CF84 + +CF84: ; preds = %CF84, %CF86 + br i1 undef, label %CF84, label %CF87 + +CF87: ; preds = %CF84 + br i1 undef, label %CF78, label %CF82 + +CF82: ; preds = %CF82, %CF87 + br i1 undef, label %CF82, label %CF83 + +CF83: ; preds = %CF82 + br label %CF + +CF: ; preds = %CF80, %CF81, %CF, %CF83 + br i1 undef, label %CF, label %CF81 + +CF81: ; preds = %CF + %Se = sext <16 x i1> %Cmp to <16 x i16> + br i1 undef, label %CF, label %CF80 + +CF80: ; preds = %CF81 + br i1 undef, label %CF, label %CF76 + +CF76: ; preds = %CF76, %CF80 + %Sl58 = select i1 undef, <16 x i16> %Se, <16 x i16> %Se + br label %CF76 +} + +define void @autogen_SD1067() { +BB: + %FC = sitofp <4 x i32> zeroinitializer to <4 x ppc_fp128> + br label %CF77 + +CF77: ; preds = %CF77, %BB + %brmerge = or i1 false, undef + br i1 %brmerge, label %CF77, label %CF85 + +CF85: ; preds = %CF77 + %Shuff19 = shufflevector <4 x ppc_fp128> %FC, <4 x ppc_fp128> %FC, <4 x i32> <i32 7, i32 1, i32 3, i32 5> + br label %CF75 + +CF75: ; preds = %CF75, %CF85 + br label %CF75 +} diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll new file mode 100644 index 000000000000..7963249ddf83 --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi-and.ll @@ -0,0 +1,43 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +define void @test() align 2 { +entry: + br i1 undef, label %codeRepl1, label %codeRepl31 + +codeRepl1: ; preds = %entry + br i1 undef, label %codeRepl4, label %codeRepl29 + +codeRepl4: ; preds = %codeRepl1 + br i1 undef, label %codeRepl12, label %codeRepl17 + +codeRepl12: ; preds = %codeRepl4 + unreachable + +codeRepl17: ; preds = %codeRepl4 + %0 = load i8* undef, align 2 + %1 = and i8 %0, 1 + %not.tobool.i.i.i = icmp eq i8 %1, 0 + %2 = select i1 %not.tobool.i.i.i, i16 0, i16 256 + %3 = load i8* undef, align 1 + %4 = and i8 %3, 1 + %not.tobool.i.1.i.i = icmp eq i8 %4, 0 + %rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1 + %rvml38.sroa.0.0.insert.insert = or i16 %rvml38.sroa.1.1.insert.ext, %2 + store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2 + unreachable + +; FIXME: the SLWI could be folded into the RLWIMI to give a rotate of 8. +; CHECK: @test +; CHECK-DAG: slwi [[R1:[0-9]+]], {{[0-9]+}}, 31 +; CHECK-DAG: rlwinm [[R2:[0-9]+]], {{[0-9]+}}, 0, 31, 31 +; CHECK: rlwimi [[R2]], [[R1]], 9, 23, 23 + +codeRepl29: ; preds = %codeRepl1 + unreachable + +codeRepl31: ; preds = %entry + ret void +} + diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll index 2b5e1c9a289b..bf0a6415df67 100644 --- a/test/CodeGen/PowerPC/rounding-ops.ll +++ b/test/CodeGen/PowerPC/rounding-ops.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-FM %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -7,11 +6,8 @@ define float @test1(float %x) nounwind { %call = tail call float @floorf(float %x) nounwind readnone ret float %call -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: frim 1, 1 - -; CHECK-FM: test1: -; CHECK-FM: frim 1, 1 } declare float @floorf(float) nounwind readnone @@ -20,50 +16,38 @@ define double @test2(double %x) nounwind { %call = tail call double @floor(double %x) nounwind readnone ret double %call -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: frim 1, 1 - -; CHECK-FM: test2: -; CHECK-FM: frim 1, 1 } declare double @floor(double) nounwind readnone define float @test3(float %x) nounwind { - %call = tail call float @nearbyintf(float %x) nounwind readnone + %call = tail call float @roundf(float %x) nounwind readnone ret float %call -; CHECK: test3: -; CHECK-NOT: frin - -; CHECK-FM: test3: -; CHECK-FM: frin 1, 1 +; CHECK-LABEL: test3: +; CHECK: frin 1, 1 } -declare float @nearbyintf(float) nounwind readnone +declare float @roundf(float) nounwind readnone define double @test4(double %x) nounwind { - %call = tail call double @nearbyint(double %x) nounwind readnone + %call = tail call double @round(double %x) nounwind readnone ret double %call -; CHECK: test4: -; CHECK-NOT: frin - -; CHECK-FM: test4: -; CHECK-FM: frin 1, 1 +; CHECK-LABEL: test4: +; CHECK: frin 1, 1 } -declare double @nearbyint(double) nounwind readnone +declare double @round(double) nounwind readnone define float @test5(float %x) nounwind { %call = tail call float @ceilf(float %x) nounwind readnone ret float %call -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: frip 1, 1 - -; CHECK-FM: test5: -; CHECK-FM: frip 1, 1 } declare float @ceilf(float) nounwind readnone @@ -72,11 +56,8 @@ define double @test6(double %x) nounwind { %call = tail call double @ceil(double %x) nounwind readnone ret double %call -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: frip 1, 1 - -; CHECK-FM: test6: -; CHECK-FM: frip 1, 1 } declare double @ceil(double) nounwind readnone @@ -85,11 +66,8 @@ define float @test9(float %x) nounwind { %call = tail call float @truncf(float %x) nounwind readnone ret float %call -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: friz 1, 1 - -; CHECK-FM: test9: -; CHECK-FM: friz 1, 1 } declare float @truncf(float) nounwind readnone @@ -98,50 +76,9 @@ define double @test10(double %x) nounwind { %call = tail call double @trunc(double %x) nounwind readnone ret double %call -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: friz 1, 1 - -; CHECK-FM: test10: -; CHECK-FM: friz 1, 1 } declare double @trunc(double) nounwind readnone -define void @test11(float %x, float* %y) nounwind { - %call = tail call float @rintf(float %x) nounwind readnone - store float %call, float* %y - ret void - -; CHECK: test11: -; CHECK-NOT: frin - -; CHECK-FM: test11: -; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]] -; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]] -; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2 -; CHECK-FM: mtfsb1 6 -; CHECK-FM: .LBB[[BB]]_2: -; CHECK-FM: blr -} - -declare float @rintf(float) nounwind readnone - -define void @test12(double %x, double* %y) nounwind { - %call = tail call double @rint(double %x) nounwind readnone - store double %call, double* %y - ret void - -; CHECK: test12: -; CHECK-NOT: frin - -; CHECK-FM: test12: -; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]] -; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]] -; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2 -; CHECK-FM: mtfsb1 6 -; CHECK-FM: .LBB[[BB]]_2: -; CHECK-FM: blr -} - -declare double @rint(double) nounwind readnone - diff --git a/test/CodeGen/PowerPC/rs-undef-use.ll b/test/CodeGen/PowerPC/rs-undef-use.ll new file mode 100644 index 000000000000..24dd5fd9da99 --- /dev/null +++ b/test/CodeGen/PowerPC/rs-undef-use.ll @@ -0,0 +1,48 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD156869(i8*, i64*) { +BB: + %A3 = alloca <2 x i1> + %A2 = alloca <8 x i32> + br label %CF + +CF: ; preds = %CF85, %CF, %BB + br i1 undef, label %CF, label %CF82.critedge + +CF82.critedge: ; preds = %CF + store i8 -59, i8* %0 + br label %CF82 + +CF82: ; preds = %CF82, %CF82.critedge + %L17 = load i8* %0 + %E18 = extractelement <2 x i64> undef, i32 0 + %PC = bitcast <2 x i1>* %A3 to i64* + br i1 undef, label %CF82, label %CF84.critedge + +CF84.critedge: ; preds = %CF82 + store i64 455385, i64* %PC + br label %CF84 + +CF84: ; preds = %CF84, %CF84.critedge + %L40 = load i64* %PC + store i64 -1, i64* %PC + %Sl46 = select i1 undef, i1 undef, i1 false + br i1 %Sl46, label %CF84, label %CF85 + +CF85: ; preds = %CF84 + %L47 = load i64* %PC + store i64 %E18, i64* %PC + %PC52 = bitcast <8 x i32>* %A2 to ppc_fp128* + store ppc_fp128 0xM4D436562A0416DE00000000000000000, ppc_fp128* %PC52 + %PC59 = bitcast i64* %1 to i8* + %Cmp61 = icmp slt i64 %L47, %L40 + br i1 %Cmp61, label %CF, label %CF77 + +CF77: ; preds = %CF77, %CF85 + br i1 undef, label %CF77, label %CF81 + +CF81: ; preds = %CF77 + store i8 %L17, i8* %PC59 + ret void +} diff --git a/test/CodeGen/PowerPC/set0-v8i16.ll b/test/CodeGen/PowerPC/set0-v8i16.ll new file mode 100644 index 000000000000..13d51dfc8e4f --- /dev/null +++ b/test/CodeGen/PowerPC/set0-v8i16.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD367951() { +BB: + %Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24> + %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18> + %Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer + %E27 = extractelement <16 x i1> %Cmp11, i32 5 + br label %CF76 + +CF76: ; preds = %CF80, %CF76, %BB + br i1 undef, label %CF76, label %CF80 + +CF80: ; preds = %CF76 + %Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff + br label %CF76 +} diff --git a/test/CodeGen/PowerPC/sj-ctr-loop.ll b/test/CodeGen/PowerPC/sj-ctr-loop.ll new file mode 100644 index 000000000000..1866bcd17420 --- /dev/null +++ b/test/CodeGen/PowerPC/sj-ctr-loop.ll @@ -0,0 +1,50 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.__jmp_buf_tag.1.15.17.21.25.49.53.55 = type { [64 x i64], i32, %struct.__sigset_t.0.14.16.20.24.48.52.54, [8 x i8] } +%struct.__sigset_t.0.14.16.20.24.48.52.54 = type { [16 x i64] } + +@env_sigill = external global [1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55], align 16 + +; CHECK-LABEL: @main +; CHECK-NOT: mtctr + +; Function Attrs: nounwind +define void @main() #0 { +entry: + br i1 undef, label %return, label %if.end + +if.end: ; preds = %entry + br i1 undef, label %for.body.lr.ph, label %for.end.thread + +for.end.thread: ; preds = %if.end + br label %return + +for.body.lr.ph: ; preds = %if.end + br label %for.body + +for.cond: ; preds = %for.body + %cmp2 = icmp slt i32 %inc, undef + br i1 %cmp2, label %for.body, label %for.end + +for.body: ; preds = %for.cond, %for.body.lr.ph + %i.032 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.cond ] + %0 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55]* @env_sigill to i8*)) + %inc = add nsw i32 %i.032, 1 + br i1 false, label %if.else, label %for.cond + +if.else: ; preds = %for.body + unreachable + +for.end: ; preds = %for.cond + unreachable + +return: ; preds = %for.end.thread, %entry + ret void +} + +; Function Attrs: nounwind +declare i32 @llvm.eh.sjlj.setjmp(i8*) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index 7ea35dafc3fa..414640b2b7e3 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -20,6 +20,7 @@ entry: ; CHECK: ld [[REG2:[0-9]+]], 8([[REG]]) ; CHECK: ld 1, 16([[REG]]) ; CHECK: mtctr [[REG2]] +; CHECK: ld 30, 32([[REG]]) ; CHECK: ld 2, 24([[REG]]) ; CHECK: bctr @@ -63,15 +64,16 @@ return: ; preds = %if.end, %if.then ; CHECK: std ; Make sure that we're not saving VRSAVE on non-Darwin: ; CHECK-NOT: mfspr -; CHECK: stfd -; CHECK: stvx -; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha -; CHECK: std 31, env_sigill@toc@l([[REG]]) -; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l -; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill -; CHECK: std 1, 16([[REG]]) -; CHECK: std 2, 24([[REG]]) +; CHECK-DAG: stfd +; CHECK-DAG: stvx + +; CHECK-DAG: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha +; CHECK-DAG: std 31, env_sigill@toc@l([[REG]]) +; CHECK-DAG: addi [[REGA:[0-9]+]], [[REG]], env_sigill@toc@l +; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK-DAG: std 1, 16([[REGA]]) +; CHECK-DAG: std 2, 24([[REGA]]) ; CHECK: bcl 20, 31, .LBB1_1 ; CHECK: li 3, 1 ; CHECK: #EH_SjLj_Setup .LBB1_1 @@ -99,13 +101,59 @@ return: ; preds = %if.end, %if.then ; CHECK-NOAV: blr } +define signext i32 @main2() #0 { +entry: + %a = alloca i8, align 64 + call void @bar(i8* %a) + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %0 = call i8* @llvm.frameaddress(i32 0) + store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**) + %1 = call i8* @llvm.stacksave() + store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2) + %2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*)) + %tobool = icmp ne i32 %2, 0 + br i1 %tobool, label %if.then, label %if.else + +if.then: ; preds = %entry + store i32 1, i32* %retval + br label %return + +if.else: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.else + store i32 0, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %3 = load i32* %retval + ret i32 %3 + +; CHECK: @main2 + +; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha +; CHECK: std 31, env_sigill@toc@l([[REG]]) +; CHECK: addi [[REGB:[0-9]+]], [[REG]], env_sigill@toc@l +; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK-DAG: std 1, 16([[REGB]]) +; CHECK-DAG: std 2, 24([[REGB]]) +; CHECK-DAG: std 30, 32([[REGB]]) +; CHECK: bcl 20, 31, + +; CHECK: blr +} + +declare void @bar(i8*) #3 + declare i8* @llvm.frameaddress(i32) #2 declare i8* @llvm.stacksave() #3 declare i32 @llvm.eh.sjlj.setjmp(i8*) #3 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { noreturn nounwind } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } diff --git a/test/CodeGen/PowerPC/stack-protector.ll b/test/CodeGen/PowerPC/stack-protector.ll index 810630f6978f..b81d94181cdf 100644 --- a/test/CodeGen/PowerPC/stack-protector.ll +++ b/test/CodeGen/PowerPC/stack-protector.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=ppc32 < %s -o - | grep "__stack_chk_guard" -; RUN: llc -march=ppc32 < %s -o - | grep "__stack_chk_fail" +; RUN: llc -march=ppc32 -mtriple=ppc32-unknown-linux < %s | FileCheck %s +; CHECK: __stack_chk_guard +; CHECK: __stack_chk_fail @"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00" ; <[11 x i8]*> [#uses=1] diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll new file mode 100644 index 000000000000..1c7a36aeeabf --- /dev/null +++ b/test/CodeGen/PowerPC/stack-realign.ll @@ -0,0 +1,147 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.s = type { i32, i32 } + +declare void @bar(i32*) + +define void @goo(%struct.s* byval nocapture readonly %a) { +entry: + %x = alloca [2 x i32], align 32 + %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %0 = load i32* %a1, align 4 + %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0 + store i32 %0, i32* %arrayidx, align 32 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %1 = load i32* %b, align 4 + %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1 + store i32 %1, i32* %arrayidx2, align 4 + call void @bar(i32* %arrayidx) + ret void +} + +; CHECK-LABEL: @goo + +; CHECK-DAG: mflr 0 +; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-DAG: std 30, -16(1) +; CHECK-DAG: mr 30, 1 +; CHECK-DAG: std 0, 16(1) +; CHECK-DAG: subfic 0, [[REG]], -160 +; CHECK: stdux 1, 1, 0 + +; CHECK: .cfi_offset r30, -16 +; CHECK: .cfi_offset lr, 16 + +; CHECK: std 3, 48(30) + +; CHECK: ld 1, 0(1) +; CHECK-DAG: ld 0, 16(1) +; CHECK-DAG: ld 30, -16(1) +; CHECK-DAG: mtlr 0 +; CHECK: blr + +; CHECK-FP-LABEL: @goo + +; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-FP-DAG: std 31, -8(1) +; CHECK-FP-DAG: std 30, -16(1) +; CHECK-FP-DAG: mr 30, 1 +; CHECK-FP-DAG: std 0, 16(1) +; CHECK-FP-DAG: subfic 0, [[REG]], -160 +; CHECK-FP: stdux 1, 1, 0 + +; CHECK-FP: .cfi_offset r31, -8 +; CHECK-FP: .cfi_offset r30, -16 +; CHECK-FP: .cfi_offset lr, 16 + +; CHECK-FP: mr 31, 1 + +; CHECK-FP: std 3, 48(30) + +; CHECK-FP: ld 1, 0(1) +; CHECK-FP-DAG: ld 0, 16(1) +; CHECK-FP-DAG: ld 31, -8(1) +; CHECK-FP-DAG: ld 30, -16(1) +; CHECK-FP-DAG: mtlr 0 +; CHECK-FP: blr + +; The large-frame-size case. +define void @hoo(%struct.s* byval nocapture readonly %a) { +entry: + %x = alloca [200000 x i32], align 32 + %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %0 = load i32* %a1, align 4 + %arrayidx = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 0 + store i32 %0, i32* %arrayidx, align 32 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %1 = load i32* %b, align 4 + %arrayidx2 = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 1 + store i32 %1, i32* %arrayidx2, align 4 + call void @bar(i32* %arrayidx) + ret void +} + +; CHECK-LABEL: @hoo + +; CHECK-DAG: lis [[REG1:[0-9]+]], -13 +; CHECK-DAG: rldicl [[REG3:[0-9]+]], 1, 0, 59 +; CHECK-DAG: mflr 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808 +; CHECK-DAG: std 30, -16(1) +; CHECK-DAG: mr 30, 1 +; CHECK-DAG: std 0, 16(1) +; CHECK-DAG: subfc 0, [[REG3]], [[REG2]] +; CHECK: stdux 1, 1, 0 + +; CHECK: blr + +; Make sure that the FP save area is still allocated correctly relative to +; where r30 is saved. +define void @loo(%struct.s* byval nocapture readonly %a) { +entry: + %x = alloca [2 x i32], align 32 + %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0 + %0 = load i32* %a1, align 4 + %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0 + store i32 %0, i32* %arrayidx, align 32 + %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1 + %1 = load i32* %b, align 4 + %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1 + store i32 %1, i32* %arrayidx2, align 4 + call void @bar(i32* %arrayidx) + call void asm sideeffect "", "~{f30}"() nounwind + ret void +} + +; CHECK-LABEL: @loo + +; CHECK-DAG: mflr 0 +; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-DAG: std 30, -32(1) +; CHECK-DAG: mr 30, 1 +; CHECK-DAG: std 0, 16(1) +; CHECK-DAG: subfic 0, [[REG]], -192 +; CHECK: stdux 1, 1, 0 + +; CHECK: stfd 30, -16(30) + +; CHECK: blr + +; CHECK-FP-LABEL: @loo + +; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59 +; CHECK-FP-DAG: std 31, -24(1) +; CHECK-FP-DAG: std 30, -32(1) +; CHECK-FP-DAG: mr 30, 1 +; CHECK-FP-DAG: std 0, 16(1) +; CHECK-FP-DAG: subfic 0, [[REG]], -192 +; CHECK-FP: stdux 1, 1, 0 + +; CHECK-FP: stfd 30, -16(30) + +; CHECK-FP: blr diff --git a/test/CodeGen/PowerPC/std-unal-fi.ll b/test/CodeGen/PowerPC/std-unal-fi.ll new file mode 100644 index 000000000000..8b9606e1624f --- /dev/null +++ b/test/CodeGen/PowerPC/std-unal-fi.ll @@ -0,0 +1,119 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD4932(i8) { +BB: + %A4 = alloca i8 + %A = alloca <1 x ppc_fp128> + %Shuff = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 undef, i32 29, i32 31, i32 1, i32 3, i32 5> + br label %CF + +CF: ; preds = %CF80, %CF, %BB + %L5 = load i64* undef + store i8 %0, i8* %A4 + %Shuff7 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> %Shuff, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 22, i32 24, i32 26> + %PC10 = bitcast i8* %A4 to ppc_fp128* + br i1 undef, label %CF, label %CF77 + +CF77: ; preds = %CF81, %CF83, %CF77, %CF + br i1 undef, label %CF77, label %CF82 + +CF82: ; preds = %CF82, %CF77 + %L19 = load i64* undef + store <1 x ppc_fp128> zeroinitializer, <1 x ppc_fp128>* %A + store i8 -65, i8* %A4 + br i1 undef, label %CF82, label %CF83 + +CF83: ; preds = %CF82 + %L34 = load i64* undef + br i1 undef, label %CF77, label %CF81 + +CF81: ; preds = %CF83 + %Shuff43 = shufflevector <16 x i32> %Shuff7, <16 x i32> undef, <16 x i32> <i32 15, i32 17, i32 19, i32 21, i32 23, i32 undef, i32 undef, i32 29, i32 31, i32 undef, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13> + store ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128* %PC10 + br i1 undef, label %CF77, label %CF78 + +CF78: ; preds = %CF78, %CF81 + br i1 undef, label %CF78, label %CF79 + +CF79: ; preds = %CF79, %CF78 + br i1 undef, label %CF79, label %CF80 + +CF80: ; preds = %CF79 + store i64 %L19, i64* undef + %Cmp75 = icmp uge i32 206779, undef + br i1 %Cmp75, label %CF, label %CF76 + +CF76: ; preds = %CF80 + store i64 %L5, i64* undef + store i64 %L34, i64* undef + ret void +} + +define void @autogen_SD88042(i8*, i32*, i8) { +BB: + %A4 = alloca <2 x i1> + %A = alloca <16 x float> + %L = load i8* %0 + %Sl = select i1 false, <16 x float>* %A, <16 x float>* %A + %PC = bitcast <2 x i1>* %A4 to i64* + %Sl27 = select i1 false, i8 undef, i8 %L + br label %CF + +CF: ; preds = %CF78, %CF, %BB + %PC33 = bitcast i32* %1 to i32* + br i1 undef, label %CF, label %CF77 + +CF77: ; preds = %CF80, %CF77, %CF + store <16 x float> zeroinitializer, <16 x float>* %Sl + %L58 = load i32* %PC33 + store i8 0, i8* %0 + br i1 undef, label %CF77, label %CF80 + +CF80: ; preds = %CF77 + store i64 0, i64* %PC + %E67 = extractelement <8 x i1> zeroinitializer, i32 1 + br i1 %E67, label %CF77, label %CF78 + +CF78: ; preds = %CF80 + %Cmp73 = icmp eq i32 189865, %L58 + br i1 %Cmp73, label %CF, label %CF76 + +CF76: ; preds = %CF78 + store i8 %2, i8* %0 + store i8 %Sl27, i8* %0 + ret void +} + +define void @autogen_SD37497(i8*, i32*, i64*) { +BB: + %A1 = alloca i1 + %I8 = insertelement <1 x i32> <i32 -1>, i32 454855, i32 0 + %Cmp = icmp ult <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, undef + %L10 = load i64* %2 + %E11 = extractelement <4 x i1> %Cmp, i32 2 + br label %CF72 + +CF72: ; preds = %CF74, %CF72, %BB + store double 0xB47BB29A53790718, double* undef + %E18 = extractelement <1 x i32> <i32 -1>, i32 0 + %FC22 = sitofp <1 x i32> %I8 to <1 x float> + br i1 undef, label %CF72, label %CF74 + +CF74: ; preds = %CF72 + store i8 0, i8* %0 + %PC = bitcast i1* %A1 to i64* + %L31 = load i64* %PC + store i64 477323, i64* %PC + %Sl37 = select i1 false, i32* undef, i32* %1 + %Cmp38 = icmp ugt i1 undef, undef + br i1 %Cmp38, label %CF72, label %CF73 + +CF73: ; preds = %CF74 + store i64 %L31, i64* %PC + %B55 = fdiv <1 x float> undef, %FC22 + %Sl63 = select i1 %E11, i32* undef, i32* %Sl37 + store i32 %E18, i32* %Sl63 + store i64 %L10, i64* %PC + ret void +} diff --git a/test/CodeGen/PowerPC/store-update.ll b/test/CodeGen/PowerPC/store-update.ll index 538ed24fbc46..7b9e8f720a17 100644 --- a/test/CodeGen/PowerPC/store-update.ll +++ b/test/CodeGen/PowerPC/store-update.ll @@ -3,166 +3,166 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -define i8* @stbu(i8* %base, i8 zeroext %val) nounwind { +define i8* @test_stbu(i8* %base, i8 zeroext %val) nounwind { entry: %arrayidx = getelementptr inbounds i8* %base, i64 16 store i8 %val, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbu +; CHECK: @test_stbu ; CHECK: %entry ; CHECK-NEXT: stbu ; CHECK-NEXT: blr -define i8* @stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind { +define i8* @test_stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i8* %base, i64 %offset store i8 %val, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbux +; CHECK: @test_stbux ; CHECK: %entry ; CHECK-NEXT: stbux ; CHECK-NEXT: blr -define i16* @sthu(i16* %base, i16 zeroext %val) nounwind { +define i16* @test_sthu(i16* %base, i16 zeroext %val) nounwind { entry: %arrayidx = getelementptr inbounds i16* %base, i64 16 store i16 %val, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthu +; CHECK: @test_sthu ; CHECK: %entry ; CHECK-NEXT: sthu ; CHECK-NEXT: blr -define i16* @sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind { +define i16* @test_sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i16* %base, i64 %offset store i16 %val, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthux +; CHECK: @test_sthux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: sthux ; CHECK-NEXT: blr -define i32* @stwu(i32* %base, i32 zeroext %val) nounwind { +define i32* @test_stwu(i32* %base, i32 zeroext %val) nounwind { entry: %arrayidx = getelementptr inbounds i32* %base, i64 16 store i32 %val, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwu +; CHECK: @test_stwu ; CHECK: %entry ; CHECK-NEXT: stwu ; CHECK-NEXT: blr -define i32* @stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind { +define i32* @test_stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i32* %base, i64 %offset store i32 %val, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwux +; CHECK: @test_stwux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: stwux ; CHECK-NEXT: blr -define i8* @stbu8(i8* %base, i64 %val) nounwind { +define i8* @test_stbu8(i8* %base, i64 %val) nounwind { entry: %conv = trunc i64 %val to i8 %arrayidx = getelementptr inbounds i8* %base, i64 16 store i8 %conv, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbu +; CHECK: @test_stbu8 ; CHECK: %entry ; CHECK-NEXT: stbu ; CHECK-NEXT: blr -define i8* @stbux8(i8* %base, i64 %val, i64 %offset) nounwind { +define i8* @test_stbux8(i8* %base, i64 %val, i64 %offset) nounwind { entry: %conv = trunc i64 %val to i8 %arrayidx = getelementptr inbounds i8* %base, i64 %offset store i8 %conv, i8* %arrayidx, align 1 ret i8* %arrayidx } -; CHECK: @stbux +; CHECK: @test_stbux8 ; CHECK: %entry ; CHECK-NEXT: stbux ; CHECK-NEXT: blr -define i16* @sthu8(i16* %base, i64 %val) nounwind { +define i16* @test_sthu8(i16* %base, i64 %val) nounwind { entry: %conv = trunc i64 %val to i16 %arrayidx = getelementptr inbounds i16* %base, i64 16 store i16 %conv, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthu +; CHECK: @test_sthu ; CHECK: %entry ; CHECK-NEXT: sthu ; CHECK-NEXT: blr -define i16* @sthux8(i16* %base, i64 %val, i64 %offset) nounwind { +define i16* @test_sthux8(i16* %base, i64 %val, i64 %offset) nounwind { entry: %conv = trunc i64 %val to i16 %arrayidx = getelementptr inbounds i16* %base, i64 %offset store i16 %conv, i16* %arrayidx, align 2 ret i16* %arrayidx } -; CHECK: @sthux +; CHECK: @test_sthux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: sthux ; CHECK-NEXT: blr -define i32* @stwu8(i32* %base, i64 %val) nounwind { +define i32* @test_stwu8(i32* %base, i64 %val) nounwind { entry: %conv = trunc i64 %val to i32 %arrayidx = getelementptr inbounds i32* %base, i64 16 store i32 %conv, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwu +; CHECK: @test_stwu ; CHECK: %entry ; CHECK-NEXT: stwu ; CHECK-NEXT: blr -define i32* @stwux8(i32* %base, i64 %val, i64 %offset) nounwind { +define i32* @test_stwux8(i32* %base, i64 %val, i64 %offset) nounwind { entry: %conv = trunc i64 %val to i32 %arrayidx = getelementptr inbounds i32* %base, i64 %offset store i32 %conv, i32* %arrayidx, align 4 ret i32* %arrayidx } -; CHECK: @stwux +; CHECK: @test_stwux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: stwux ; CHECK-NEXT: blr -define i64* @stdu(i64* %base, i64 %val) nounwind { +define i64* @test_stdu(i64* %base, i64 %val) nounwind { entry: %arrayidx = getelementptr inbounds i64* %base, i64 16 store i64 %val, i64* %arrayidx, align 8 ret i64* %arrayidx } -; CHECK: @stdu +; CHECK: @test_stdu ; CHECK: %entry ; CHECK-NEXT: stdu ; CHECK-NEXT: blr -define i64* @stdux(i64* %base, i64 %val, i64 %offset) nounwind { +define i64* @test_stdux(i64* %base, i64 %val, i64 %offset) nounwind { entry: %arrayidx = getelementptr inbounds i64* %base, i64 %offset store i64 %val, i64* %arrayidx, align 8 ret i64* %arrayidx } -; CHECK: @stdux +; CHECK: @test_stdux ; CHECK: %entry ; CHECK-NEXT: sldi ; CHECK-NEXT: stdux diff --git a/test/CodeGen/PowerPC/structsinmem.ll b/test/CodeGen/PowerPC/structsinmem.ll index 2a17e740ea01..5b8dead16893 100644 --- a/test/CodeGen/PowerPC/structsinmem.ll +++ b/test/CodeGen/PowerPC/structsinmem.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/structsinregs.ll b/test/CodeGen/PowerPC/structsinregs.ll index 54de6060d0f0..fb3bd7cd57e6 100644 --- a/test/CodeGen/PowerPC/structsinregs.ll +++ b/test/CodeGen/PowerPC/structsinregs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/sub-bv-types.ll b/test/CodeGen/PowerPC/sub-bv-types.ll new file mode 100644 index 000000000000..c72fae6a2194 --- /dev/null +++ b/test/CodeGen/PowerPC/sub-bv-types.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target triple = "powerpc64-unknown-linux-gnu" + +define void @autogen_SD10521() { +BB: + %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 undef, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 undef, i32 22, i32 undef, i32 26, i32 undef, i32 30> + br label %CF + +CF: ; preds = %CF78, %CF, %BB + %I27 = insertelement <16 x i16> %Shuff7, i16 1360, i32 8 + %B28 = sub <16 x i16> %I27, %Shuff7 + br i1 undef, label %CF, label %CF78 + +CF78: ; preds = %CF + %B42 = xor <16 x i16> %B28, %Shuff7 + br label %CF +} diff --git a/test/CodeGen/PowerPC/subsumes-pred-regs.ll b/test/CodeGen/PowerPC/subsumes-pred-regs.ll new file mode 100644 index 000000000000..97ac788164ab --- /dev/null +++ b/test/CodeGen/PowerPC/subsumes-pred-regs.ll @@ -0,0 +1,65 @@ +; RUN: llc < %s -mcpu=ppc64 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define zeroext i1 @test1() unnamed_addr #0 align 2 { + +; CHECK-LABEL: @test1 + +entry: + br i1 undef, label %lor.end, label %lor.rhs + +lor.rhs: ; preds = %entry + unreachable + +lor.end: ; preds = %entry + br i1 undef, label %land.rhs, label %if.then + +if.then: ; preds = %lor.end + br i1 undef, label %return, label %if.end.i24 + +if.end.i24: ; preds = %if.then + %0 = load i32* undef, align 4 + %lnot.i.i16.i23 = icmp eq i32 %0, 0 + br i1 %lnot.i.i16.i23, label %if.end7.i37, label %test.exit27.i34 + +test.exit27.i34: ; preds = %if.end.i24 + br i1 undef, label %return, label %if.end7.i37 + +if.end7.i37: ; preds = %test.exit27.i34, %if.end.i24 + %tobool.i.i36 = icmp eq i8 undef, 0 + br i1 %tobool.i.i36, label %return, label %if.then9.i39 + +if.then9.i39: ; preds = %if.end7.i37 + br i1 %lnot.i.i16.i23, label %return, label %lor.rhs.i.i49 + +; CHECK: .LBB0_7: +; CHECK: beq 1, .LBB0_10 +; CHECK: beq 0, .LBB0_10 +; CHECK: .LBB0_9: + +lor.rhs.i.i49: ; preds = %if.then9.i39 + %cmp.i.i.i.i48 = icmp ne i64 undef, 0 + br label %return + +land.rhs: ; preds = %lor.end + br i1 undef, label %return, label %if.end.i + +if.end.i: ; preds = %land.rhs + br i1 undef, label %return, label %if.then9.i + +if.then9.i: ; preds = %if.end.i + br i1 undef, label %return, label %lor.rhs.i.i + +lor.rhs.i.i: ; preds = %if.then9.i + %cmp.i.i.i.i = icmp ne i64 undef, 0 + br label %return + +return: ; preds = %lor.rhs.i.i, %if.then9.i, %if.end.i, %land.rhs, %lor.rhs.i.i49, %if.then9.i39, %if.end7.i37, %test.exit27.i34, %if.then + %retval.0 = phi i1 [ false, %if.then ], [ false, %test.exit27.i34 ], [ true, %if.end7.i37 ], [ true, %if.then9.i39 ], [ %cmp.i.i.i.i48, %lor.rhs.i.i49 ], [ false, %land.rhs ], [ true, %if.end.i ], [ true, %if.then9.i ], [ %cmp.i.i.i.i, %lor.rhs.i.i ] + ret i1 %retval.0 +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/svr4-redzone.ll b/test/CodeGen/PowerPC/svr4-redzone.ll index 91ff5797389b..7c51b67aeecb 100644 --- a/test/CodeGen/PowerPC/svr4-redzone.ll +++ b/test/CodeGen/PowerPC/svr4-redzone.ll @@ -7,11 +7,11 @@ entry: %0 = add i32 1, 2 ret void } -; PPC32: regalloc: +; PPC32-LABEL: regalloc: ; PPC32-NOT: stwu 1, -{{[0-9]+}}(1) ; PPC32: blr -; PPC64: regalloc: +; PPC64-LABEL: regalloc: ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1) ; PPC64: blr @@ -20,10 +20,10 @@ entry: %0 = alloca i8, i32 4 ret void } -; PPC32: smallstack: +; PPC32-LABEL: smallstack: ; PPC32: stwu 1, -16(1) -; PPC64: smallstack: +; PPC64-LABEL: smallstack: ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1) ; PPC64: blr @@ -32,8 +32,8 @@ entry: %0 = alloca i8, i32 230 ret void } -; PPC32: bigstack: +; PPC32-LABEL: bigstack: ; PPC32: stwu 1, -240(1) -; PPC64: bigstack: +; PPC64-LABEL: bigstack: ; PPC64: stdu 1, -352(1) diff --git a/test/CodeGen/PowerPC/tls-2.ll b/test/CodeGen/PowerPC/tls-2.ll index 20d8fe46ea17..c2faf9062469 100644 --- a/test/CodeGen/PowerPC/tls-2.ll +++ b/test/CodeGen/PowerPC/tls-2.ll @@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-freebsd10.0" @a = thread_local global i32 0, align 4 -;CHECK: localexec: +;CHECK-LABEL: localexec: define i32 @localexec() nounwind { entry: ;CHECK: addis [[REG1:[0-9]+]], 13, a@tprel@ha diff --git a/test/CodeGen/PowerPC/tls-gd-obj.ll b/test/CodeGen/PowerPC/tls-gd-obj.ll deleted file mode 100644 index ffc0db0d14cb..000000000000 --- a/test/CodeGen/PowerPC/tls-gd-obj.ll +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: llc -mcpu=pwr7 -O0 -filetype=obj -relocation-model=pic %s -o - | \ -; RUN: llvm-readobj -r | FileCheck %s - -; Test correct relocation generation for thread-local storage using -; the general dynamic model and integrated assembly. - -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" -target triple = "powerpc64-unknown-linux-gnu" - -@a = thread_local global i32 0, align 4 - -define signext i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32* @a, align 4 - ret i32 %0 -} - -; Verify generation of R_PPC64_GOT_TLSGD16_HA, R_PPC64_GOT_TLSGD16_LO, -; and R_PPC64_TLSGD for accessing external variable a, and R_PPC64_REL24 -; for the call to __tls_get_addr. -; -; CHECK: Relocations [ -; CHECK: Section (1) .text { -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSGD a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_REL24 __tls_get_addr -; CHECK: } -; CHECK: ] diff --git a/test/CodeGen/PowerPC/tls-ie-obj.ll b/test/CodeGen/PowerPC/tls-ie-obj.ll deleted file mode 100644 index 0f7a35295234..000000000000 --- a/test/CodeGen/PowerPC/tls-ie-obj.ll +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: llc -mcpu=pwr7 -O0 -filetype=obj %s -o - | \ -; RUN: llvm-readobj -r | FileCheck %s - -; Test correct relocation generation for thread-local storage -; using the initial-exec model and integrated assembly. - -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" -target triple = "powerpc64-unknown-linux-gnu" - -@a = external thread_local global i32 - -define signext i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32* @a, align 4 - ret i32 %0 -} - -; Verify generation of R_PPC64_GOT_TPREL16_DS and R_PPC64_TLS for -; accessing external variable a. -; -; CHECK: Relocations [ -; CHECK: Section (1) .text { -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLS a -; CHECK: } -; CHECK: ] diff --git a/test/CodeGen/PowerPC/tls-ld-obj.ll b/test/CodeGen/PowerPC/tls-ld-obj.ll deleted file mode 100644 index 29ee87684552..000000000000 --- a/test/CodeGen/PowerPC/tls-ld-obj.ll +++ /dev/null @@ -1,34 +0,0 @@ -; RUN: llc -mcpu=pwr7 -O0 -filetype=obj -relocation-model=pic %s -o - | \ -; RUN: llvm-readobj -r | FileCheck %s - -; Test correct relocation generation for thread-local storage using -; the local dynamic model. - -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" -target triple = "powerpc64-unknown-linux-gnu" - -@a = hidden thread_local global i32 0, align 4 - -define signext i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32* @a, align 4 - ret i32 %0 -} - -; Verify generation of R_PPC64_GOT_TLSLD16_HA, R_PPC64_GOT_TLSLD16_LO, -; R_PPC64_TLSLD, R_PPC64_DTPREL16_HA, and R_PPC64_DTPREL16_LO for -; accessing external variable a, and R_PPC64_REL24 for the call to -; __tls_get_addr. -; -; CHECK: Relocations [ -; CHECK: Section (1) .text { -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSLD a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_REL24 __tls_get_addr -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA a -; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO a -; CHECK: } -; CHECK: ] diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll index 2daa60ab37f2..4e0a822399dd 100644 --- a/test/CodeGen/PowerPC/tls.ll +++ b/test/CodeGen/PowerPC/tls.ll @@ -5,8 +5,8 @@ target triple = "powerpc64-unknown-freebsd10.0" @a = thread_local global i32 0, align 4 -;OPT0: localexec: -;OPT1: localexec: +;OPT0-LABEL: localexec: +;OPT1-LABEL: localexec: define i32 @localexec() nounwind { entry: ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha diff --git a/test/CodeGen/PowerPC/unal-altivec.ll b/test/CodeGen/PowerPC/unal-altivec.ll new file mode 100644 index 000000000000..7f333a1c508b --- /dev/null +++ b/test/CodeGen/PowerPC/unal-altivec.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -mcpu=g5 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define void @foo(float* noalias nocapture %a, float* noalias nocapture %b) #0 { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds float* %b, i64 %index + %1 = bitcast float* %0 to <4 x float>* + %wide.load = load <4 x float>* %1, align 4 + %.sum11 = or i64 %index, 4 + %2 = getelementptr float* %b, i64 %.sum11 + %3 = bitcast float* %2 to <4 x float>* + %wide.load8 = load <4 x float>* %3, align 4 + %4 = fadd <4 x float> %wide.load, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> + %5 = fadd <4 x float> %wide.load8, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> + %6 = getelementptr inbounds float* %a, i64 %index + %7 = bitcast float* %6 to <4 x float>* + store <4 x float> %4, <4 x float>* %7, align 4 + %.sum12 = or i64 %index, 4 + %8 = getelementptr float* %a, i64 %.sum12 + %9 = bitcast float* %8 to <4 x float>* + store <4 x float> %5, <4 x float>* %9, align 4 + %index.next = add i64 %index, 8 + %10 = icmp eq i64 %index.next, 16000 + br i1 %10, label %for.end, label %vector.body + +; CHECK: @foo +; CHECK-DAG: li [[C0:[0-9]+]], 0 +; CHECK-DAG: li [[C16:[0-9]+]], 16 +; CHECK-DAG: li [[C31:[0-9]+]], 31 +; CHECK-DAG: lvx [[CNST:[0-9]+]], +; CHECK: .LBB0_1: +; CHECK-DAG: lvsl [[PC:[0-9]+]], [[B1:[0-9]+]], [[C0]] +; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]] +; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]] +; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C16]] +; CHECK-DAG: lvx [[LD3:[0-9]+]], [[B3]], [[C31]] +; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[PC]] +; CHECK-DAG: vperm [[R2:[0-9]+]], [[LD2]], [[LD3]], [[PC]] +; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]] +; CHECK-DAG: vaddfp {{[0-9]+}}, [[R2]], [[CNST]] +; CHECK: blr + +for.end: ; preds = %vector.body + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/unal-altivec2.ll b/test/CodeGen/PowerPC/unal-altivec2.ll new file mode 100644 index 000000000000..7464675470f9 --- /dev/null +++ b/test/CodeGen/PowerPC/unal-altivec2.ll @@ -0,0 +1,166 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo(float* noalias nocapture %x, float* noalias nocapture readonly %y) #0 { +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry +; CHECK-LABEL: @foo +; CHECK: lvsl +; CHECK: blr + %index = phi i64 [ 0, %entry ], [ %index.next.15, %vector.body ] + %0 = getelementptr inbounds float* %y, i64 %index + %1 = bitcast float* %0 to <4 x float>* + %wide.load = load <4 x float>* %1, align 4 + %2 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load) + %3 = getelementptr inbounds float* %x, i64 %index + %4 = bitcast float* %3 to <4 x float>* + store <4 x float> %2, <4 x float>* %4, align 4 + %index.next = add i64 %index, 4 + %5 = getelementptr inbounds float* %y, i64 %index.next + %6 = bitcast float* %5 to <4 x float>* + %wide.load.1 = load <4 x float>* %6, align 4 + %7 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.1) + %8 = getelementptr inbounds float* %x, i64 %index.next + %9 = bitcast float* %8 to <4 x float>* + store <4 x float> %7, <4 x float>* %9, align 4 + %index.next.1 = add i64 %index.next, 4 + %10 = getelementptr inbounds float* %y, i64 %index.next.1 + %11 = bitcast float* %10 to <4 x float>* + %wide.load.2 = load <4 x float>* %11, align 4 + %12 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.2) + %13 = getelementptr inbounds float* %x, i64 %index.next.1 + %14 = bitcast float* %13 to <4 x float>* + store <4 x float> %12, <4 x float>* %14, align 4 + %index.next.2 = add i64 %index.next.1, 4 + %15 = getelementptr inbounds float* %y, i64 %index.next.2 + %16 = bitcast float* %15 to <4 x float>* + %wide.load.3 = load <4 x float>* %16, align 4 + %17 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.3) + %18 = getelementptr inbounds float* %x, i64 %index.next.2 + %19 = bitcast float* %18 to <4 x float>* + store <4 x float> %17, <4 x float>* %19, align 4 + %index.next.3 = add i64 %index.next.2, 4 + %20 = getelementptr inbounds float* %y, i64 %index.next.3 + %21 = bitcast float* %20 to <4 x float>* + %wide.load.4 = load <4 x float>* %21, align 4 + %22 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.4) + %23 = getelementptr inbounds float* %x, i64 %index.next.3 + %24 = bitcast float* %23 to <4 x float>* + store <4 x float> %22, <4 x float>* %24, align 4 + %index.next.4 = add i64 %index.next.3, 4 + %25 = getelementptr inbounds float* %y, i64 %index.next.4 + %26 = bitcast float* %25 to <4 x float>* + %wide.load.5 = load <4 x float>* %26, align 4 + %27 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.5) + %28 = getelementptr inbounds float* %x, i64 %index.next.4 + %29 = bitcast float* %28 to <4 x float>* + store <4 x float> %27, <4 x float>* %29, align 4 + %index.next.5 = add i64 %index.next.4, 4 + %30 = getelementptr inbounds float* %y, i64 %index.next.5 + %31 = bitcast float* %30 to <4 x float>* + %wide.load.6 = load <4 x float>* %31, align 4 + %32 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.6) + %33 = getelementptr inbounds float* %x, i64 %index.next.5 + %34 = bitcast float* %33 to <4 x float>* + store <4 x float> %32, <4 x float>* %34, align 4 + %index.next.6 = add i64 %index.next.5, 4 + %35 = getelementptr inbounds float* %y, i64 %index.next.6 + %36 = bitcast float* %35 to <4 x float>* + %wide.load.7 = load <4 x float>* %36, align 4 + %37 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.7) + %38 = getelementptr inbounds float* %x, i64 %index.next.6 + %39 = bitcast float* %38 to <4 x float>* + store <4 x float> %37, <4 x float>* %39, align 4 + %index.next.7 = add i64 %index.next.6, 4 + %40 = getelementptr inbounds float* %y, i64 %index.next.7 + %41 = bitcast float* %40 to <4 x float>* + %wide.load.8 = load <4 x float>* %41, align 4 + %42 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.8) + %43 = getelementptr inbounds float* %x, i64 %index.next.7 + %44 = bitcast float* %43 to <4 x float>* + store <4 x float> %42, <4 x float>* %44, align 4 + %index.next.8 = add i64 %index.next.7, 4 + %45 = getelementptr inbounds float* %y, i64 %index.next.8 + %46 = bitcast float* %45 to <4 x float>* + %wide.load.9 = load <4 x float>* %46, align 4 + %47 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.9) + %48 = getelementptr inbounds float* %x, i64 %index.next.8 + %49 = bitcast float* %48 to <4 x float>* + store <4 x float> %47, <4 x float>* %49, align 4 + %index.next.9 = add i64 %index.next.8, 4 + %50 = getelementptr inbounds float* %y, i64 %index.next.9 + %51 = bitcast float* %50 to <4 x float>* + %wide.load.10 = load <4 x float>* %51, align 4 + %52 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.10) + %53 = getelementptr inbounds float* %x, i64 %index.next.9 + %54 = bitcast float* %53 to <4 x float>* + store <4 x float> %52, <4 x float>* %54, align 4 + %index.next.10 = add i64 %index.next.9, 4 + %55 = getelementptr inbounds float* %y, i64 %index.next.10 + %56 = bitcast float* %55 to <4 x float>* + %wide.load.11 = load <4 x float>* %56, align 4 + %57 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.11) + %58 = getelementptr inbounds float* %x, i64 %index.next.10 + %59 = bitcast float* %58 to <4 x float>* + store <4 x float> %57, <4 x float>* %59, align 4 + %index.next.11 = add i64 %index.next.10, 4 + %60 = getelementptr inbounds float* %y, i64 %index.next.11 + %61 = bitcast float* %60 to <4 x float>* + %wide.load.12 = load <4 x float>* %61, align 4 + %62 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.12) + %63 = getelementptr inbounds float* %x, i64 %index.next.11 + %64 = bitcast float* %63 to <4 x float>* + store <4 x float> %62, <4 x float>* %64, align 4 + %index.next.12 = add i64 %index.next.11, 4 + %65 = getelementptr inbounds float* %y, i64 %index.next.12 + %66 = bitcast float* %65 to <4 x float>* + %wide.load.13 = load <4 x float>* %66, align 4 + %67 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.13) + %68 = getelementptr inbounds float* %x, i64 %index.next.12 + %69 = bitcast float* %68 to <4 x float>* + store <4 x float> %67, <4 x float>* %69, align 4 + %index.next.13 = add i64 %index.next.12, 4 + %70 = getelementptr inbounds float* %y, i64 %index.next.13 + %71 = bitcast float* %70 to <4 x float>* + %wide.load.14 = load <4 x float>* %71, align 4 + %72 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.14) + %73 = getelementptr inbounds float* %x, i64 %index.next.13 + %74 = bitcast float* %73 to <4 x float>* + store <4 x float> %72, <4 x float>* %74, align 4 + %index.next.14 = add i64 %index.next.13, 4 + %75 = getelementptr inbounds float* %y, i64 %index.next.14 + %76 = bitcast float* %75 to <4 x float>* + %wide.load.15 = load <4 x float>* %76, align 4 + %77 = call <4 x float> @llvm_cos_v4f32(<4 x float> %wide.load.15) + %78 = getelementptr inbounds float* %x, i64 %index.next.14 + %79 = bitcast float* %78 to <4 x float>* + store <4 x float> %77, <4 x float>* %79, align 4 + %index.next.15 = add i64 %index.next.14, 4 + %80 = icmp eq i64 %index.next.15, 2048 + br i1 %80, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void +} + +; Function Attrs: nounwind readonly +declare <4 x float> @llvm_cos_v4f32(<4 x float>) #1 + +define <2 x double> @bar(double* %x) { +entry: + %p = bitcast double* %x to <2 x double>* + %r = load <2 x double>* %p, align 8 + +; CHECK-LABEL: @bar +; CHECK-NOT: lvsl +; CHECK: blr + + ret <2 x double> %r +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/PowerPC/unal4-std.ll b/test/CodeGen/PowerPC/unal4-std.ll index 169bd787c0c1..9f29e31cb902 100644 --- a/test/CodeGen/PowerPC/unal4-std.ll +++ b/test/CodeGen/PowerPC/unal4-std.ll @@ -24,4 +24,4 @@ if.end210: ; preds = %entry ; CHECK: stdx {{[0-9]+}}, 0, } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/unwind-dw2-g.ll b/test/CodeGen/PowerPC/unwind-dw2-g.ll new file mode 100644 index 000000000000..260d03664295 --- /dev/null +++ b/test/CodeGen/PowerPC/unwind-dw2-g.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo() #0 { +entry: + call void @llvm.eh.unwind.init(), !dbg !9 + ret void, !dbg !10 +} + +; CHECK: @foo +; CHECK-NOT: .cfi_offset vrsave +; CHECK: blr + +; Function Attrs: nounwind +declare void @llvm.eh.unwind.init() #0 + +attributes #0 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!8, !11} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/unwind-dw2.c] [DW_LANG_C99] +!1 = metadata !{metadata !"/tmp/unwind-dw2.c", metadata !"/tmp"} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/tmp/unwind-dw2.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{null} +!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 3} +!9 = metadata !{i32 2, i32 0, metadata !4, null} +!10 = metadata !{i32 3, i32 0, metadata !4, null} +!11 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/PowerPC/unwind-dw2.ll b/test/CodeGen/PowerPC/unwind-dw2.ll new file mode 100644 index 000000000000..e58edff65d5f --- /dev/null +++ b/test/CodeGen/PowerPC/unwind-dw2.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo() #0 { +entry: + call void @llvm.eh.unwind.init() + ret void +} + +; Function Attrs: nounwind +declare void @llvm.eh.unwind.init() #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/vaddsplat.ll b/test/CodeGen/PowerPC/vaddsplat.ll index e65148aff03a..4236fabea0a6 100644 --- a/test/CodeGen/PowerPC/vaddsplat.ll +++ b/test/CodeGen/PowerPC/vaddsplat.ll @@ -16,7 +16,7 @@ define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_pos_even: +; CHECK-LABEL: test_v4i32_pos_even: ; CHECK: vspltisw [[REG1:[0-9]+]], 9 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -27,7 +27,7 @@ define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_neg_even: +; CHECK-LABEL: test_v4i32_neg_even: ; CHECK: vspltisw [[REG1:[0-9]+]], -14 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -38,7 +38,7 @@ define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_pos_even: +; CHECK-LABEL: test_v8i16_pos_even: ; CHECK: vspltish [[REG1:[0-9]+]], 15 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -49,7 +49,7 @@ define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_neg_even: +; CHECK-LABEL: test_v8i16_neg_even: ; CHECK: vspltish [[REG1:[0-9]+]], -16 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -60,7 +60,7 @@ define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_pos_even: +; CHECK-LABEL: test_v16i8_pos_even: ; CHECK: vspltisb [[REG1:[0-9]+]], 8 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -71,7 +71,7 @@ define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_neg_even: +; CHECK-LABEL: test_v16i8_neg_even: ; CHECK: vspltisb [[REG1:[0-9]+]], -9 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]] @@ -82,7 +82,7 @@ define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_pos_odd: +; CHECK-LABEL: test_v4i32_pos_odd: ; CHECK: vspltisw [[REG2:[0-9]+]], -16 ; CHECK: vspltisw [[REG1:[0-9]+]], 11 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -94,7 +94,7 @@ define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) { ret void } -; CHECK: test_v4i32_neg_odd: +; CHECK-LABEL: test_v4i32_neg_odd: ; CHECK: vspltisw [[REG2:[0-9]+]], -16 ; CHECK: vspltisw [[REG1:[0-9]+]], -11 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -106,7 +106,7 @@ define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_pos_odd: +; CHECK-LABEL: test_v8i16_pos_odd: ; CHECK: vspltish [[REG2:[0-9]+]], -16 ; CHECK: vspltish [[REG1:[0-9]+]], 15 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -118,7 +118,7 @@ define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) { ret void } -; CHECK: test_v8i16_neg_odd: +; CHECK-LABEL: test_v8i16_neg_odd: ; CHECK: vspltish [[REG2:[0-9]+]], -16 ; CHECK: vspltish [[REG1:[0-9]+]], -15 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -130,7 +130,7 @@ define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_pos_odd: +; CHECK-LABEL: test_v16i8_pos_odd: ; CHECK: vspltisb [[REG2:[0-9]+]], -16 ; CHECK: vspltisb [[REG1:[0-9]+]], 1 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]] @@ -142,7 +142,7 @@ define void @test_v16i8_neg_odd(%v16i8* %P, %v16i8* %S) { ret void } -; CHECK: test_v16i8_neg_odd: +; CHECK-LABEL: test_v16i8_neg_odd: ; CHECK: vspltisb [[REG2:[0-9]+]], -16 ; CHECK: vspltisb [[REG1:[0-9]+]], -1 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]] diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll index 90f0480d6ad2..dfd205634b1f 100644 --- a/test/CodeGen/PowerPC/varargs.ll +++ b/test/CodeGen/PowerPC/varargs.ll @@ -7,14 +7,14 @@ define i8* @test1(i8** %foo) nounwind { ret i8* %A } -; P32: test1: +; P32-LABEL: test1: ; P32: lwz r2, 0(r3) ; P32: addi r4, r2, 4 ; P32: stw r4, 0(r3) ; P32: lwz r3, 0(r2) ; P32: blr -; P64: test1: +; P64-LABEL: test1: ; P64: ld r2, 0(r3) ; P64: addi r4, r2, 8 ; P64: std r4, 0(r3) diff --git a/test/CodeGen/PowerPC/vec-abi-align.ll b/test/CodeGen/PowerPC/vec-abi-align.ll new file mode 100644 index 000000000000..3239cf6c06ab --- /dev/null +++ b/test/CodeGen/PowerPC/vec-abi-align.ll @@ -0,0 +1,60 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.s2 = type { i64, <4 x float> } + +@ve = external global <4 x float> +@n = external global i64 + +; Function Attrs: nounwind +define void @test1(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, <4 x float> inreg %vs.coerce) #0 { +entry: + store <4 x float> %vs.coerce, <4 x float>* @ve, align 16 + ret void + +; CHECK-LABEL: @test1 +; CHECK: stvx 2, +; CHECK: blr +} + +; Function Attrs: nounwind +define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 { +entry: + %m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0 + %0 = load i64* %m, align 8 + store i64 %0, i64* @n, align 8 + %v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1 + %1 = load <4 x float>* %v, align 16 + store <4 x float> %1, <4 x float>* @ve, align 16 + ret void + +; CHECK-LABEL: @test2 +; CHECK: ld {{[0-9]+}}, 112(1) +; CHECK: li [[REG16:[0-9]+]], 16 +; CHECK: addi [[REGB:[0-9]+]], 1, 112 +; CHECK: lvx 2, [[REGB]], [[REG16]] +; CHECK: blr +} + +; Function Attrs: nounwind +define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 { +entry: + %m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0 + %0 = load i64* %m, align 8 + store i64 %0, i64* @n, align 8 + %v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1 + %1 = load <4 x float>* %v, align 16 + store <4 x float> %1, <4 x float>* @ve, align 16 + ret void + +; CHECK-LABEL: @test3 +; CHECK: ld {{[0-9]+}}, 128(1) +; CHECK: li [[REG16:[0-9]+]], 16 +; CHECK: addi [[REGB:[0-9]+]], 1, 128 +; CHECK: lvx 2, [[REGB]], [[REG16]] +; CHECK: blr +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll index eb41667610cd..83e0e0263061 100644 --- a/test/CodeGen/PowerPC/vec_cmp.ll +++ b/test/CodeGen/PowerPC/vec_cmp.ll @@ -14,7 +14,7 @@ define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone { %sext = sext <2 x i1> %cmp to <2 x i8> ret <2 x i8> %sext } -; CHECK: v2si8_cmp: +; CHECK-LABEL: v2si8_cmp: ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -23,7 +23,7 @@ define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone { %sext = sext <4 x i1> %cmp to <4 x i8> ret <4 x i8> %sext } -; CHECK: v4si8_cmp: +; CHECK-LABEL: v4si8_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -32,7 +32,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone { %sext = sext <8 x i1> %cmp to <8 x i8> ret <8 x i8> %sext } -; CHECK: v8si8_cmp: +; CHECK-LABEL: v8si8_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -43,7 +43,7 @@ define <16 x i8> @v16si8_cmp_eq(<16 x i8> %x, <16 x i8> %y) nounwind readnone { %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_eq: +; CHECK-LABEL: v16si8_cmp_eq: ; CHECK: vcmpequb 2, 2, 3 define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -52,7 +52,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_ne: +; CHECK-LABEL: v16si8_cmp_ne: ; CHECK: vcmpequb [[RET:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]] @@ -62,7 +62,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_le: +; CHECK-LABEL: v16si8_cmp_le: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -73,7 +73,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_le: +; CHECK-LABEL: v16ui8_cmp_le: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -84,7 +84,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_lt: +; CHECK-LABEL: v16si8_cmp_lt: ; CHECK: vcmpgtsb 2, 3, 2 define <16 x i8> @v16ui8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -93,7 +93,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_lt: +; CHECK-LABEL: v16ui8_cmp_lt: ; CHECK: vcmpgtub 2, 3, 2 define <16 x i8> @v16si8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -102,7 +102,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_gt: +; CHECK-LABEL: v16si8_cmp_gt: ; CHECK: vcmpgtsb 2, 2, 3 define <16 x i8> @v16ui8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -111,7 +111,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_gt: +; CHECK-LABEL: v16ui8_cmp_gt: ; CHECK: vcmpgtub 2, 2, 3 define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone { @@ -120,7 +120,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16si8_cmp_ge: +; CHECK-LABEL: v16si8_cmp_ge: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -131,7 +131,7 @@ entry: %sext = sext <16 x i1> %cmp to <16 x i8> ret <16 x i8> %sext } -; CHECK: v16ui8_cmp_ge: +; CHECK-LABEL: v16ui8_cmp_ge: ; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -142,7 +142,7 @@ define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone { %sext = sext <32 x i1> %cmp to <32 x i8> ret <32 x i8> %sext } -; CHECK: v32si8_cmp: +; CHECK-LABEL: v32si8_cmp: ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -152,7 +152,7 @@ define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone { %sext = sext <2 x i1> %cmp to <2 x i16> ret <2 x i16> %sext } -; CHECK: v2si16_cmp: +; CHECK-LABEL: v2si16_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -161,7 +161,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone { %sext = sext <4 x i1> %cmp to <4 x i16> ret <4 x i16> %sext } -; CHECK: v4si16_cmp: +; CHECK-LABEL: v4si16_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -173,7 +173,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_eq: +; CHECK-LABEL: v8si16_cmp_eq: ; CHECK: vcmpequh 2, 2, 3 define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -182,7 +182,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_ne: +; CHECK-LABEL: v8si16_cmp_ne: ; CHECK: vcmpequh [[RET:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]] @@ -192,7 +192,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_le: +; CHECK-LABEL: v8si16_cmp_le: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -203,7 +203,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_le: +; CHECK-LABEL: v8ui16_cmp_le: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -214,7 +214,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_lt: +; CHECK-LABEL: v8si16_cmp_lt: ; CHECK: vcmpgtsh 2, 3, 2 define <8 x i16> @v8ui16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -223,7 +223,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_lt: +; CHECK-LABEL: v8ui16_cmp_lt: ; CHECK: vcmpgtuh 2, 3, 2 define <8 x i16> @v8si16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -232,7 +232,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_gt: +; CHECK-LABEL: v8si16_cmp_gt: ; CHECK: vcmpgtsh 2, 2, 3 define <8 x i16> @v8ui16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -241,7 +241,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_gt: +; CHECK-LABEL: v8ui16_cmp_gt: ; CHECK: vcmpgtuh 2, 2, 3 define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone { @@ -250,7 +250,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8si16_cmp_ge: +; CHECK-LABEL: v8si16_cmp_ge: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -261,7 +261,7 @@ entry: %sext = sext <8 x i1> %cmp to <8 x i16> ret <8 x i16> %sext } -; CHECK: v8ui16_cmp_ge: +; CHECK-LABEL: v8ui16_cmp_ge: ; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -272,7 +272,7 @@ define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone { %sext = sext <16 x i1> %cmp to <16 x i16> ret <16 x i16> %sext } -; CHECK: v16si16_cmp: +; CHECK-LABEL: v16si16_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -282,7 +282,7 @@ define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone { %sext = sext <32 x i1> %cmp to <32 x i16> ret <32 x i16> %sext } -; CHECK: v32si16_cmp: +; CHECK-LABEL: v32si16_cmp: ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -294,7 +294,7 @@ define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone { %sext = sext <2 x i1> %cmp to <2 x i32> ret <2 x i32> %sext } -; CHECK: v2si32_cmp: +; CHECK-LABEL: v2si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -306,7 +306,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_eq: +; CHECK-LABEL: v4si32_cmp_eq: ; CHECK: vcmpequw 2, 2, 3 define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -315,7 +315,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_ne: +; CHECK-LABEL: v4si32_cmp_ne: ; CHECK: vcmpequw [[RCMP:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RCMP]], [[RCMP]] @@ -325,7 +325,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_le: +; CHECK-LABEL: v4si32_cmp_le: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -336,7 +336,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_le: +; CHECK-LABEL: v4ui32_cmp_le: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -347,7 +347,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_lt: +; CHECK-LABEL: v4si32_cmp_lt: ; CHECK: vcmpgtsw 2, 3, 2 define <4 x i32> @v4ui32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -356,7 +356,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_lt: +; CHECK-LABEL: v4ui32_cmp_lt: ; CHECK: vcmpgtuw 2, 3, 2 define <4 x i32> @v4si32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -365,7 +365,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_gt: +; CHECK-LABEL: v4si32_cmp_gt: ; CHECK: vcmpgtsw 2, 2, 3 define <4 x i32> @v4ui32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -374,7 +374,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_gt: +; CHECK-LABEL: v4ui32_cmp_gt: ; CHECK: vcmpgtuw 2, 2, 3 define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone { @@ -383,7 +383,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4si32_cmp_ge: +; CHECK-LABEL: v4si32_cmp_ge: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -394,7 +394,7 @@ entry: %sext = sext <4 x i1> %cmp to <4 x i32> ret <4 x i32> %sext } -; CHECK: v4ui32_cmp_ge: +; CHECK-LABEL: v4ui32_cmp_ge: ; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3 ; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] @@ -405,7 +405,7 @@ define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone { %sext = sext <8 x i1> %cmp to <8 x i32> ret <8 x i32> %sext } -; CHECK: v8si32_cmp: +; CHECK-LABEL: v8si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -415,7 +415,7 @@ define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone { %sext = sext <16 x i1> %cmp to <16 x i32> ret <16 x i32> %sext } -; CHECK: v16si32_cmp: +; CHECK-LABEL: v16si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -427,7 +427,7 @@ define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone { %sext = sext <32 x i1> %cmp to <32 x i32> ret <32 x i32> %sext } -; CHECK: v32si32_cmp: +; CHECK-LABEL: v32si32_cmp: ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -445,7 +445,7 @@ entry: %0 = bitcast <2 x i32> %sext to <2 x float> ret <2 x float> %0 } -; CHECK: v2f32_cmp: +; CHECK-LABEL: v2f32_cmp: ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} @@ -458,7 +458,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_eq: +; CHECK-LABEL: v4f32_cmp_eq: ; CHECK: vcmpeqfp 2, 2, 3 define <4 x float> @v4f32_cmp_ne(<4 x float> %x, <4 x float> %y) nounwind readnone { @@ -468,7 +468,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_ne: +; CHECK-LABEL: v4f32_cmp_ne: ; CHECK: vcmpeqfp [[RET:[0-9]+]], 2, 3 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]] @@ -479,7 +479,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_le: +; CHECK-LABEL: v4f32_cmp_le: ; CHECK: vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3 ; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2 ; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] @@ -491,7 +491,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_lt: +; CHECK-LABEL: v4f32_cmp_lt: ; CHECK: vcmpgtfp 2, 3, 2 define <4 x float> @v4f32_cmp_ge(<4 x float> %x, <4 x float> %y) nounwind readnone { @@ -501,7 +501,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_ge: +; CHECK-LABEL: v4f32_cmp_ge: ; CHECK: vcmpgefp 2, 2, 3 define <4 x float> @v4f32_cmp_gt(<4 x float> %x, <4 x float> %y) nounwind readnone { @@ -511,7 +511,7 @@ entry: %0 = bitcast <4 x i32> %sext to <4 x float> ret <4 x float> %0 } -; CHECK: v4f32_cmp_gt: +; CHECK-LABEL: v4f32_cmp_gt: ; CHECK: vcmpgtfp 2, 2, 3 @@ -522,6 +522,6 @@ entry: %0 = bitcast <8 x i32> %sext to <8 x float> ret <8 x float> %0 } -; CHECK: v8f32_cmp: +; CHECK-LABEL: v8f32_cmp: ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll index e4799e50e6ad..f16b9f511f53 100644 --- a/test/CodeGen/PowerPC/vec_constants.ll +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -17,14 +17,14 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { store <4 x float> %tmp13, <4 x float>* %P3 ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: CPI } define <4 x i32> @test_30() nounwind { ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > -; CHECK: test_30: +; CHECK-LABEL: test_30: ; CHECK: vspltisw ; CHECK-NEXT: vadduwm ; CHECK-NEXT: blr @@ -33,7 +33,7 @@ define <4 x i32> @test_30() nounwind { define <4 x i32> @test_29() nounwind { ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > -; CHECK: test_29: +; CHECK-LABEL: test_29: ; CHECK: vspltisw ; CHECK-NEXT: vspltisw ; CHECK-NEXT: vsubuwm @@ -43,7 +43,7 @@ define <4 x i32> @test_29() nounwind { define <8 x i16> @test_n30() nounwind { ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > -; CHECK: test_n30: +; CHECK-LABEL: test_n30: ; CHECK: vspltish ; CHECK-NEXT: vadduhm ; CHECK-NEXT: blr @@ -52,7 +52,7 @@ define <8 x i16> @test_n30() nounwind { define <16 x i8> @test_n104() nounwind { ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > -; CHECK: test_n104: +; CHECK-LABEL: test_n104: ; CHECK: vspltisb ; CHECK-NEXT: vslb ; CHECK-NEXT: blr @@ -61,7 +61,7 @@ define <16 x i8> @test_n104() nounwind { define <4 x i32> @test_vsldoi() nounwind { ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > -; CHECK: test_vsldoi: +; CHECK-LABEL: test_vsldoi: ; CHECK: vspltisw ; CHECK-NEXT: vsldoi ; CHECK-NEXT: blr @@ -70,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind { define <8 x i16> @test_vsldoi_65023() nounwind { ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > -; CHECK: test_vsldoi_65023: +; CHECK-LABEL: test_vsldoi_65023: ; CHECK: vspltish ; CHECK-NEXT: vsldoi ; CHECK-NEXT: blr @@ -79,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind { define <4 x i32> @test_rol() nounwind { ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > -; CHECK: test_rol: +; CHECK-LABEL: test_rol: ; CHECK: vspltisw ; CHECK-NEXT: vrlw ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/vec_conv.ll b/test/CodeGen/PowerPC/vec_conv.ll index a475e9499df2..a39ae9100355 100644 --- a/test/CodeGen/PowerPC/vec_conv.ll +++ b/test/CodeGen/PowerPC/vec_conv.ll @@ -17,7 +17,7 @@ entry: store <4 x i32> %1, <4 x i32>* %y, align 16 ret void } -;CHECK: v4f32_to_v4i32: +;CHECK-LABEL: v4f32_to_v4i32: ;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0 @@ -29,7 +29,7 @@ entry: store <4 x i32> %1, <4 x i32>* %y, align 16 ret void } -;CHECK: v4f32_to_v4u32: +;CHECK-LABEL: v4f32_to_v4u32: ;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0 @@ -41,7 +41,7 @@ entry: store <4 x float> %1, <4 x float>* %y, align 16 ret void } -;CHECK: v4i32_to_v4f32: +;CHECK-LABEL: v4i32_to_v4f32: ;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0 @@ -53,5 +53,5 @@ entry: store <4 x float> %1, <4 x float>* %y, align 16 ret void } -;CHECK: v4u32_to_v4f32: +;CHECK-LABEL: v4u32_to_v4f32: ;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0 diff --git a/test/CodeGen/PowerPC/vec_extload.ll b/test/CodeGen/PowerPC/vec_extload.ll index 998645d90da6..8d16e15b8f44 100644 --- a/test/CodeGen/PowerPC/vec_extload.ll +++ b/test/CodeGen/PowerPC/vec_extload.ll @@ -5,7 +5,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; Altivec does not provides an sext intruction, so it expands +; Altivec does not provides an sext instruction, so it expands ; a set of vector stores (stvx), bytes load/sign expand/store ; (lbz/stb), and a final vector load (lvx) to load the result ; extended vector. @@ -14,7 +14,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) { %c = sext <16 x i4> %b to <16 x i8> ret <16 x i8> %c } -; CHECK: v16si8_sext_in_reg: +; CHECK-LABEL: v16si8_sext_in_reg: ; CHECK: vslb ; CHECK: vsrab ; CHECK: blr @@ -26,7 +26,7 @@ define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) { %c = zext <16 x i4> %b to <16 x i8> ret <16 x i8> %c } -; CHECK: v16si8_zext_in_reg: +; CHECK-LABEL: v16si8_zext_in_reg: ; CHECK: vspltisb [[VMASK:[0-9]+]], 15 ; CHECK-NEXT: vand 2, 2, [[VMASK]] @@ -36,7 +36,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) { %c = sext <8 x i8> %b to <8 x i16> ret <8 x i16> %c } -; CHECK: v8si16_sext_in_reg: +; CHECK-LABEL: v8si16_sext_in_reg: ; CHECK: vslh ; CHECK: vsrah ; CHECK: blr @@ -48,7 +48,7 @@ define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) { %c = zext <8 x i8> %b to <8 x i16> ret <8 x i16> %c } -; CHECK: v8si16_zext_in_reg: +; CHECK-LABEL: v8si16_zext_in_reg: ; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2) ; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]] ; CHECK-NEXT: vand 2, 2, [[VMASK]] @@ -60,7 +60,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) { %c = sext <4 x i16> %b to <4 x i32> ret <4 x i32> %c } -; CHECK: v4si32_sext_in_reg: +; CHECK-LABEL: v4si32_sext_in_reg: ; CHECK: vslw ; CHECK: vsraw ; CHECK: blr @@ -71,7 +71,7 @@ define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) { %c = zext <4 x i16> %b to <4 x i32> ret <4 x i32> %c } -; CHECK: v4si32_zext_in_reg: +; CHECK-LABEL: v4si32_zext_in_reg: ; CHECK: vspltisw [[VMASK:[0-9]+]], -16 ; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]] ; CHECK-NEXT: vand 2, 2, [[VMASK]] diff --git a/test/CodeGen/PowerPC/vec_fmuladd.ll b/test/CodeGen/PowerPC/vec_fmuladd.ll new file mode 100644 index 000000000000..5683b607934c --- /dev/null +++ b/test/CodeGen/PowerPC/vec_fmuladd.ll @@ -0,0 +1,56 @@ +; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +declare <2 x float> @llvm.fmuladd.v2f32(<2 x float> %val, <2 x float>, <2 x float>) +declare <4 x float> @llvm.fmuladd.v4f32(<4 x float> %val, <4 x float>, <4 x float>) +declare <8 x float> @llvm.fmuladd.v8f32(<8 x float> %val, <8 x float>, <8 x float>) +declare <2 x double> @llvm.fmuladd.v2f64(<2 x double> %val, <2 x double>, <2 x double>) +declare <4 x double> @llvm.fmuladd.v4f64(<4 x double> %val, <4 x double>, <4 x double>) + +define <2 x float> @v2f32_fmuladd(<2 x float> %x) nounwind readnone { +entry: + %fmuladd = call <2 x float> @llvm.fmuladd.v2f32 (<2 x float> %x, <2 x float> %x, <2 x float> %x) + ret <2 x float> %fmuladd +} +; fmuladd (<2 x float>) is promoted to fmuladd (<4 x float>) +; CHECK-LABEL: v2f32_fmuladd: +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <4 x float> @v4f32_fmuladd(<4 x float> %x) nounwind readnone { +entry: + %fmuladd = call <4 x float> @llvm.fmuladd.v4f32 (<4 x float> %x, <4 x float> %x, <4 x float> %x) + ret <4 x float> %fmuladd +} +; CHECK-LABEL: v4f32_fmuladd: +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <8 x float> @v8f32_fmuladd(<8 x float> %x) nounwind readnone { +entry: + %fmuladd = call <8 x float> @llvm.fmuladd.v8f32 (<8 x float> %x, <8 x float> %x, <8 x float> %x) + ret <8 x float> %fmuladd +} +; CHECK-LABEL: v8f32_fmuladd: +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <2 x double> @v2f64_fmuladd(<2 x double> %x) nounwind readnone { +entry: + %fmuladd = call <2 x double> @llvm.fmuladd.v2f64 (<2 x double> %x, <2 x double> %x, <2 x double> %x) + ret <2 x double> %fmuladd +} +; CHECK-LABEL: v2f64_fmuladd: +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + +define <4 x double> @v4f64_fmuladd(<4 x double> %x) nounwind readnone { +entry: + %fmuladd = call <4 x double> @llvm.fmuladd.v4f64 (<4 x double> %x, <4 x double> %x, <4 x double> %x) + ret <4 x double> %fmuladd +} +; CHECK-LABEL: v4f64_fmuladd: +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll index 53bc75dd1078..c376751d8060 100644 --- a/test/CodeGen/PowerPC/vec_mul.ll +++ b/test/CodeGen/PowerPC/vec_mul.ll @@ -6,7 +6,7 @@ define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) { %tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1] ret <4 x i32> %tmp3 } -; CHECK: test_v4i32: +; CHECK-LABEL: test_v4i32: ; CHECK: vmsumuhm ; CHECK-NOT: mullw @@ -16,7 +16,7 @@ define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) { %tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1] ret <8 x i16> %tmp3 } -; CHECK: test_v8i16: +; CHECK-LABEL: test_v8i16: ; CHECK: vmladduhm ; CHECK-NOT: mullw @@ -26,7 +26,7 @@ define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) { %tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1] ret <16 x i8> %tmp3 } -; CHECK: test_v16i8: +; CHECK-LABEL: test_v16i8: ; CHECK: vmuloub ; CHECK: vmuleub ; CHECK-NOT: mullw @@ -40,7 +40,7 @@ define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) { ; Check the creation of a negative zero float vector by creating a vector of ; all bits set and shifting it 31 bits to left, resulting a an vector of ; 4 x 0x80000000 (-0.0 as float). -; CHECK: test_float: +; CHECK-LABEL: test_float: ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1 ; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]] ; CHECK: vmaddfp diff --git a/test/CodeGen/PowerPC/vec_rounding.ll b/test/CodeGen/PowerPC/vec_rounding.ll index 7c55638620a9..ace187b3e72b 100644 --- a/test/CodeGen/PowerPC/vec_rounding.ll +++ b/test/CodeGen/PowerPC/vec_rounding.ll @@ -12,7 +12,7 @@ define <2 x double> @floor_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: floor_v2f64: +; CHECK-LABEL: floor_v2f64: ; CHECK: frim ; CHECK: frim @@ -22,7 +22,7 @@ define <4 x double> @floor_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: floor_v4f64: +; CHECK-LABEL: floor_v4f64: ; CHECK: frim ; CHECK: frim ; CHECK: frim @@ -34,7 +34,7 @@ define <2 x double> @ceil_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: ceil_v2f64: +; CHECK-LABEL: ceil_v2f64: ; CHECK: frip ; CHECK: frip @@ -44,7 +44,7 @@ define <4 x double> @ceil_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: ceil_v4f64: +; CHECK-LABEL: ceil_v4f64: ; CHECK: frip ; CHECK: frip ; CHECK: frip @@ -56,7 +56,7 @@ define <2 x double> @trunc_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: trunc_v2f64: +; CHECK-LABEL: trunc_v2f64: ; CHECK: friz ; CHECK: friz @@ -66,7 +66,7 @@ define <4 x double> @trunc_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: trunc_v4f64: +; CHECK-LABEL: trunc_v4f64: ; CHECK: friz ; CHECK: friz ; CHECK: friz @@ -78,7 +78,7 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p) %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) ret <2 x double> %t } -; CHECK: nearbyint_v2f64: +; CHECK-LABEL: nearbyint_v2f64: ; CHECK: bl nearbyint ; CHECK: bl nearbyint @@ -88,7 +88,7 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p) %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p) ret <4 x double> %t } -; CHECK: nearbyint_v4f64: +; CHECK-LABEL: nearbyint_v4f64: ; CHECK: bl nearbyint ; CHECK: bl nearbyint ; CHECK: bl nearbyint @@ -101,7 +101,7 @@ define <4 x float> @floor_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: floor_v4f32: +; CHECK-LABEL: floor_v4f32: ; CHECK: vrfim declare <8 x float> @llvm.floor.v8f32(<8 x float> %p) @@ -110,7 +110,7 @@ define <8 x float> @floor_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: floor_v8f32: +; CHECK-LABEL: floor_v8f32: ; CHECK: vrfim ; CHECK: vrfim @@ -120,7 +120,7 @@ define <4 x float> @ceil_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: ceil_v4f32: +; CHECK-LABEL: ceil_v4f32: ; CHECK: vrfip declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p) @@ -129,7 +129,7 @@ define <8 x float> @ceil_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: ceil_v8f32: +; CHECK-LABEL: ceil_v8f32: ; CHECK: vrfip ; CHECK: vrfip @@ -139,7 +139,7 @@ define <4 x float> @trunc_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: trunc_v4f32: +; CHECK-LABEL: trunc_v4f32: ; CHECK: vrfiz declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p) @@ -148,7 +148,7 @@ define <8 x float> @trunc_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: trunc_v8f32: +; CHECK-LABEL: trunc_v8f32: ; CHECK: vrfiz ; CHECK: vrfiz @@ -158,7 +158,7 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %p) %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p) ret <4 x float> %t } -; CHECK: nearbyint_v4f32: +; CHECK-LABEL: nearbyint_v4f32: ; CHECK: vrfin declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p) @@ -167,6 +167,6 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %p) %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p) ret <8 x float> %t } -; CHECK: nearbyint_v8f32: +; CHECK-LABEL: nearbyint_v8f32: ; CHECK: vrfin ; CHECK: vrfin diff --git a/test/CodeGen/PowerPC/vec_sqrt.ll b/test/CodeGen/PowerPC/vec_sqrt.ll index 055da1a229d1..a85c3ffad155 100644 --- a/test/CodeGen/PowerPC/vec_sqrt.ll +++ b/test/CodeGen/PowerPC/vec_sqrt.ll @@ -18,7 +18,7 @@ entry: ret <2 x float> %sqrt } ; sqrt (<2 x float>) is promoted to sqrt (<4 x float>) -; CHECK: v2f32_sqrt: +; CHECK-LABEL: v2f32_sqrt: ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} @@ -29,7 +29,7 @@ entry: %sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x) ret <4 x float> %sqrt } -; CHECK: v4f32_sqrt: +; CHECK-LABEL: v4f32_sqrt: ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} @@ -40,7 +40,7 @@ entry: %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x) ret <8 x float> %sqrt } -; CHECK: v8f32_sqrt: +; CHECK-LABEL: v8f32_sqrt: ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}} @@ -55,7 +55,7 @@ entry: %sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %x) ret <2 x double> %sqrt } -; CHECK: v2f64_sqrt: +; CHECK-LABEL: v2f64_sqrt: ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} @@ -64,7 +64,7 @@ entry: %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x) ret <4 x double> %sqrt } -; CHECK: v4f64_sqrt: +; CHECK-LABEL: v4f64_sqrt: ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll index e4c3b0db1726..859a85a14101 100644 --- a/test/CodeGen/PowerPC/vector.ll +++ b/test/CodeGen/PowerPC/vector.ll @@ -59,6 +59,14 @@ define void @test_div(%f8* %P, %f8* %Q, %f8* %S) { ret void } +define void @test_rem(%f8* %P, %f8* %Q, %f8* %S) { + %p = load %f8* %P ; <%f8> [#uses=1] + %q = load %f8* %Q ; <%f8> [#uses=1] + %R = frem %f8 %p, %q ; <%f8> [#uses=1] + store %f8 %R, %f8* %S + ret void +} + ;;; TEST VECTOR CONSTRUCTS define void @test_cst(%f4* %P, %f4* %S) { diff --git a/test/CodeGen/PowerPC/vrspill.ll b/test/CodeGen/PowerPC/vrspill.ll index 9fb3d03477c9..c3d1bf8f1ead 100644 --- a/test/CodeGen/PowerPC/vrspill.ll +++ b/test/CodeGen/PowerPC/vrspill.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs -fast-isel=false < %s | FileCheck %s ; This verifies that we generate correct spill/reload code for vector regs. @@ -13,7 +13,6 @@ entry: ret void } -; CHECK: stvx 2, 1, -; CHECK: lvx 2, 1, +; CHECK: stvx 2, declare void @foo(i32*) diff --git a/test/CodeGen/PowerPC/zero-not-run.ll b/test/CodeGen/PowerPC/zero-not-run.ll new file mode 100644 index 000000000000..9df0d6e004ef --- /dev/null +++ b/test/CodeGen/PowerPC/zero-not-run.ll @@ -0,0 +1,27 @@ +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define internal i32* @func_65(i32* %p_66) #0 { +entry: + br i1 undef, label %for.body, label %for.end731 + +for.body: ; preds = %entry + %0 = load i32* undef, align 4 + %or31 = or i32 %0, 319143828 + store i32 %or31, i32* undef, align 4 + %cmp32 = icmp eq i32 319143828, %or31 + %conv33 = zext i1 %cmp32 to i32 + %conv34 = sext i32 %conv33 to i64 + %call35 = call i64 @safe_mod_func_uint64_t_u_u(i64 %conv34, i64 -10) + unreachable + +for.end731: ; preds = %entry + ret i32* undef +} + +; Function Attrs: nounwind +declare i64 @safe_mod_func_uint64_t_u_u(i64, i64) #0 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } |