diff options
Diffstat (limited to 'test/CodeGen/SystemZ')
149 files changed, 4785 insertions, 1047 deletions
diff --git a/test/CodeGen/SystemZ/Large/branch-range-01.py b/test/CodeGen/SystemZ/Large/branch-range-01.py index 365d7e420818..344d26121afb 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-01.py +++ b/test/CodeGen/SystemZ/Large/branch-range-01.py @@ -70,6 +70,8 @@ branch_blocks = 10 main_size = 0xffd8 +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i32 *%stop, i32 %limit) {' print 'entry:' print ' br label %before0' @@ -101,5 +103,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-03.py b/test/CodeGen/SystemZ/Large/branch-range-03.py index 745d733211ff..75c9ea4a0510 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-03.py +++ b/test/CodeGen/SystemZ/Large/branch-range-03.py @@ -70,6 +70,8 @@ branch_blocks = 8 main_size = 0xffcc +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i8 *%stop, i32 %limit) {' print 'entry:' print ' br label %before0' @@ -103,5 +105,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-04.py b/test/CodeGen/SystemZ/Large/branch-range-04.py index a0c9c4426456..d475c9565e41 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-04.py +++ b/test/CodeGen/SystemZ/Large/branch-range-04.py @@ -74,6 +74,8 @@ branch_blocks = 8 main_size = 0xffcc +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i8 *%stop, i64 %limit) {' print 'entry:' print ' br label %before0' @@ -107,5 +109,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-05.py b/test/CodeGen/SystemZ/Large/branch-range-05.py index 69a8112162a0..0a56eff85e1a 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-05.py +++ b/test/CodeGen/SystemZ/Large/branch-range-05.py @@ -74,6 +74,8 @@ branch_blocks = 8 main_size = 0xffcc +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i8 *%stop) {' print 'entry:' print ' br label %before0' @@ -105,5 +107,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-06.py b/test/CodeGen/SystemZ/Large/branch-range-06.py index b08bc119c454..5b054345b083 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-06.py +++ b/test/CodeGen/SystemZ/Large/branch-range-06.py @@ -74,6 +74,8 @@ branch_blocks = 8 main_size = 0xffcc +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i8 *%stop) {' print 'entry:' print ' br label %before0' @@ -105,5 +107,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-09.py b/test/CodeGen/SystemZ/Large/branch-range-09.py index d4693358f502..6b568a6e6409 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-09.py +++ b/test/CodeGen/SystemZ/Large/branch-range-09.py @@ -70,6 +70,8 @@ branch_blocks = 8 main_size = 0xffcc +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i8 *%stop, i32 %limit) {' print 'entry:' print ' br label %before0' @@ -103,5 +105,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-10.py b/test/CodeGen/SystemZ/Large/branch-range-10.py index c928081f5544..c6f8945e2940 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-10.py +++ b/test/CodeGen/SystemZ/Large/branch-range-10.py @@ -74,6 +74,8 @@ branch_blocks = 8 main_size = 0xffcc +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i8 *%stop, i64 %limit) {' print 'entry:' print ' br label %before0' @@ -107,5 +109,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-11.py b/test/CodeGen/SystemZ/Large/branch-range-11.py index 85166bc15656..10466df8baa7 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-11.py +++ b/test/CodeGen/SystemZ/Large/branch-range-11.py @@ -90,6 +90,8 @@ branch_blocks = 8 main_size = 0xffc6 +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i32 *%stopa, i32 *%stopb) {' print 'entry:' print ' br label %before0' @@ -123,5 +125,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/Large/branch-range-12.py b/test/CodeGen/SystemZ/Large/branch-range-12.py index e1d9e2977d41..809483a9fcd2 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-12.py +++ b/test/CodeGen/SystemZ/Large/branch-range-12.py @@ -90,6 +90,8 @@ branch_blocks = 8 main_size = 0xffb4 +print '@global = global i32 0' + print 'define void @f1(i8 *%base, i64 *%stopa, i64 *%stopb) {' print 'entry:' print ' br label %before0' @@ -123,5 +125,6 @@ for i in xrange(branch_blocks): print '' print 'after%d:' % i +print ' %dummy = load volatile i32, i32 *@global' print ' ret void' print '}' diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll index 06c336a331d8..9ffe59567caf 100644 --- a/test/CodeGen/SystemZ/alloca-01.ll +++ b/test/CodeGen/SystemZ/alloca-01.ll @@ -1,7 +1,7 @@ ; Test variable-sized allocas and addresses based on them in cases where ; stack arguments are needed. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C diff --git a/test/CodeGen/SystemZ/and-xor-01.ll b/test/CodeGen/SystemZ/and-xor-01.ll new file mode 100644 index 000000000000..f29c7d576d9b --- /dev/null +++ b/test/CodeGen/SystemZ/and-xor-01.ll @@ -0,0 +1,14 @@ +; Testing peephole for generating shorter code for (and (xor b, -1), a) +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define i64 @f1(i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK: ngr %r3, %r2 +; CHECK: xgr %r2, %r3 +; CHECK: br %r14 + %neg = xor i64 %b, -1 + %and = and i64 %neg, %a + ret i64 %and +} + diff --git a/test/CodeGen/SystemZ/args-09.ll b/test/CodeGen/SystemZ/args-09.ll new file mode 100644 index 000000000000..333b1daec2ad --- /dev/null +++ b/test/CodeGen/SystemZ/args-09.ll @@ -0,0 +1,53 @@ +; Test the handling of i128 argument values +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-I128-1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-I128-2 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-STACK + +declare void @bar(i64, i64, i64, i64, i128, + i64, i64, i64, i64, i128) + +; There are two indirect i128 slots, one at offset 200 (the first available +; byte after the outgoing arguments) and one immediately after it at 216. +; These slots should be set up outside the glued call sequence, so would +; normally use %f0/%f2 as the first available 128-bit pair. This choice +; is hard-coded in the I128 tests. +; +; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder +; them in response to future code changes. +define void @foo() { +; CHECK-INT-LABEL: foo: +; CHECK-INT-DAG: lghi %r2, 1 +; CHECK-INT-DAG: lghi %r3, 2 +; CHECK-INT-DAG: lghi %r4, 3 +; CHECK-INT-DAG: lghi %r5, 4 +; CHECK-INT-DAG: la %r6, {{200|216}}(%r15) +; CHECK-INT: brasl %r14, bar@PLT +; +; CHECK-I128-1-LABEL: foo: +; CHECK-I128-1: aghi %r15, -232 +; CHECK-I128-1-DAG: mvghi 200(%r15), 0 +; CHECK-I128-1-DAG: mvghi 208(%r15), 0 +; CHECK-I128-1: brasl %r14, bar@PLT +; +; CHECK-I128-2-LABEL: foo: +; CHECK-I128-2: aghi %r15, -232 +; CHECK-I128-2-DAG: mvghi 216(%r15), 0 +; CHECK-I128-2-DAG: mvghi 224(%r15), 0 +; CHECK-I128-2: brasl %r14, bar@PLT +; +; CHECK-STACK-LABEL: foo: +; CHECK-STACK: aghi %r15, -232 +; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{200|216}}(%r15) +; CHECK-STACK: stg [[REGISTER]], 192(%r15) +; CHECK-STACK: mvghi 184(%r15), 8 +; CHECK-STACK: mvghi 176(%r15), 7 +; CHECK-STACK: mvghi 168(%r15), 6 +; CHECK-STACK: mvghi 160(%r15), 5 +; CHECK-STACK: brasl %r14, bar@PLT + + call void @bar (i64 1, i64 2, i64 3, i64 4, i128 0, + i64 5, i64 6, i64 7, i64 8, i128 0) + ret void +} diff --git a/test/CodeGen/SystemZ/args-10.ll b/test/CodeGen/SystemZ/args-10.ll new file mode 100644 index 000000000000..6083c4415b33 --- /dev/null +++ b/test/CodeGen/SystemZ/args-10.ll @@ -0,0 +1,50 @@ +; Test incoming i128 arguments. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Do some arithmetic so that we can see the register being used. +define void @f1(i128 *%r2, i16 %r3, i32 %r4, i64 %r5, i128 %r6) { +; CHECK-LABEL: f1: +; CHECK-DAG: lg [[REGL:%r[0-5]+]], 8(%r6) +; CHECK-DAG: lg [[REGH:%r[0-5]+]], 0(%r6) +; CHECK: algr [[REGL]], [[REGL]] +; CHECK-NEXT: alcgr [[REGH]], [[REGH]] +; CHECK-DAG: stg [[REGL]], 8(%r2) +; CHECK-DAG: stg [[REGH]], 0(%r2) +; CHECK: br %r14 + %y = add i128 %r6, %r6 + store i128 %y, i128 *%r2 + ret void +} + +; Test a case where the i128 address is passed on the stack. +define void @f2(i128 *%r2, i16 %r3, i32 %r4, i64 %r5, + i128 %r6, i64 %s1, i64 %s2, i128 %s4) { +; CHECK-LABEL: f2: +; CHECK: lg [[ADDR:%r[1-5]+]], 176(%r15) +; CHECK-DAG: lg [[REGL:%r[0-5]+]], 8([[ADDR]]) +; CHECK-DAG: lg [[REGH:%r[0-5]+]], 0([[ADDR]]) +; CHECK: algr [[REGL]], [[REGL]] +; CHECK-NEXT: alcgr [[REGH]], [[REGH]] +; CHECK-DAG: stg [[REGL]], 8(%r2) +; CHECK-DAG: stg [[REGH]], 0(%r2) +; CHECK: br %r14 + %y = add i128 %s4, %s4 + store i128 %y, i128 *%r2 + ret void +} + +; Explicit i128 return values are likewise passed indirectly. +define i128 @f14(i128 %r3) { +; CHECK-LABEL: f14: +; CHECK-DAG: lg [[REGL:%r[0-5]+]], 8(%r3) +; CHECK-DAG: lg [[REGH:%r[0-5]+]], 0(%r3) +; CHECK: algr [[REGL]], [[REGL]] +; CHECK-NEXT: alcgr [[REGH]], [[REGH]] +; CHECK-DAG: stg [[REGL]], 8(%r2) +; CHECK-DAG: stg [[REGH]], 0(%r2) +; CHECK: br %r14 + %y = add i128 %r3, %r3 + ret i128 %y +} + diff --git a/test/CodeGen/SystemZ/asm-02.ll b/test/CodeGen/SystemZ/asm-02.ll index 458bfeb49753..426d84882900 100644 --- a/test/CodeGen/SystemZ/asm-02.ll +++ b/test/CodeGen/SystemZ/asm-02.ll @@ -48,5 +48,38 @@ define void @f4(i64 %base) { ret void } -; FIXME: at the moment the precise constraint is not passed down to -; target code, so we must conservatively treat "R" as "Q". +; Check that indices are allowed +define void @f5(i64 %base, i64 %index) { +; CHECK-LABEL: f5: +; CHECK: blah 0(%r3,%r2) +; CHECK: br %r14 + %add = add i64 %base, %index + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*R" (i64 *%addr) + ret void +} + +; Check that indices and displacements are allowed simultaneously +define void @f6(i64 %base, i64 %index) { +; CHECK-LABEL: f6: +; CHECK: blah 4095(%r3,%r2) +; CHECK: br %r14 + %add = add i64 %base, 4095 + %addi = add i64 %add, %index + %addr = inttoptr i64 %addi to i64 * + call void asm "blah $0", "=*R" (i64 *%addr) + ret void +} + +; Check that LAY is used if there is an index but the displacement is too large +define void @f7(i64 %base, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: lay %r0, 4096(%r3,%r2) +; CHECK: blah 0(%r0) +; CHECK: br %r14 + %add = add i64 %base, 4096 + %addi = add i64 %add, %index + %addr = inttoptr i64 %addi to i64 * + call void asm "blah $0", "=*R" (i64 *%addr) + ret void +} diff --git a/test/CodeGen/SystemZ/asm-03.ll b/test/CodeGen/SystemZ/asm-03.ll index 2e60ad61ef40..d4fd564ce193 100644 --- a/test/CodeGen/SystemZ/asm-03.ll +++ b/test/CodeGen/SystemZ/asm-03.ll @@ -3,14 +3,48 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; Check the lowest range. define void @f1(i64 %base) { ; CHECK-LABEL: f1: +; CHECK: blah -524288(%r2) +; CHECK: br %r14 + %add = add i64 %base, -524288 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*S" (i64 *%addr) + ret void +} + +; Check the next lowest byte. +define void @f2(i64 %base) { +; CHECK-LABEL: f2: +; CHECK: agfi %r2, -524289 ; CHECK: blah 0(%r2) ; CHECK: br %r14 - %addr = inttoptr i64 %base to i64 * + %add = add i64 %base, -524289 + %addr = inttoptr i64 %add to i64 * call void asm "blah $0", "=*S" (i64 *%addr) ret void } -; FIXME: at the moment the precise constraint is not passed down to -; target code, so we must conservatively treat "S" as "Q". +; Check the highest range. +define void @f3(i64 %base) { +; CHECK-LABEL: f3: +; CHECK: blah 524287(%r2) +; CHECK: br %r14 + %add = add i64 %base, 524287 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*S" (i64 *%addr) + ret void +} + +; Check the next highest byte. +define void @f4(i64 %base) { +; CHECK-LABEL: f4: +; CHECK: agfi %r2, 524288 +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %add = add i64 %base, 524288 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*S" (i64 *%addr) + ret void +} diff --git a/test/CodeGen/SystemZ/asm-04.ll b/test/CodeGen/SystemZ/asm-04.ll index b212253dbd9c..eb91bef83769 100644 --- a/test/CodeGen/SystemZ/asm-04.ll +++ b/test/CodeGen/SystemZ/asm-04.ll @@ -3,14 +3,71 @@ ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s +; Check the lowest range. define void @f1(i64 %base) { ; CHECK-LABEL: f1: +; CHECK: blah -524288(%r2) +; CHECK: br %r14 + %add = add i64 %base, -524288 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*T" (i64 *%addr) + ret void +} + +; Check the next lowest byte. +define void @f2(i64 %base) { +; CHECK-LABEL: f2: +; CHECK: agfi %r2, -524289 ; CHECK: blah 0(%r2) ; CHECK: br %r14 - %addr = inttoptr i64 %base to i64 * + %add = add i64 %base, -524289 + %addr = inttoptr i64 %add to i64 * call void asm "blah $0", "=*T" (i64 *%addr) ret void } -; FIXME: at the moment the precise constraint is not passed down to -; target code, so we must conservatively treat "T" as "Q". +; Check the highest range. +define void @f3(i64 %base) { +; CHECK-LABEL: f3: +; CHECK: blah 524287(%r2) +; CHECK: br %r14 + %add = add i64 %base, 524287 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*T" (i64 *%addr) + ret void +} + +; Check the next highest byte. +define void @f4(i64 %base) { +; CHECK-LABEL: f4: +; CHECK: agfi %r2, 524288 +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %add = add i64 %base, 524288 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*T" (i64 *%addr) + ret void +} + +; Check that indices are allowed +define void @f5(i64 %base, i64 %index) { +; CHECK-LABEL: f5: +; CHECK: blah 0(%r3,%r2) +; CHECK: br %r14 + %add = add i64 %base, %index + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*T" (i64 *%addr) + ret void +} + +; Check that indices and displacements are allowed simultaneously +define void @f6(i64 %base, i64 %index) { +; CHECK-LABEL: f6: +; CHECK: blah 524287(%r3,%r2) +; CHECK: br %r14 + %add = add i64 %base, 524287 + %addi = add i64 %add, %index + %addr = inttoptr i64 %addi to i64 * + call void asm "blah $0", "=*T" (i64 *%addr) + ret void +} diff --git a/test/CodeGen/SystemZ/asm-05.ll b/test/CodeGen/SystemZ/asm-05.ll index db99b10853ed..9b23ac781750 100644 --- a/test/CodeGen/SystemZ/asm-05.ll +++ b/test/CodeGen/SystemZ/asm-05.ll @@ -10,6 +10,3 @@ define void @f1(i64 %base) { call void asm "blah $0", "=*m" (i64 *%addr) ret void } - -; FIXME: at the moment the precise constraint is not passed down to -; target code, so we must conservatively treat "m" as "Q". diff --git a/test/CodeGen/SystemZ/atomic-fence-01.ll b/test/CodeGen/SystemZ/atomic-fence-01.ll new file mode 100644 index 000000000000..25566db9078b --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-fence-01.ll @@ -0,0 +1,16 @@ +; Test (fast) serialization. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=Z10 +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s --check-prefix=Z196 +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s --check-prefix=ZEC12 +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z13 + +define void @test() { +; Z10: bcr 15, %r0 +; Z196: bcr 14, %r0 +; ZEC12: bcr 14, %r0 +; Z13: bcr 14, %r0 + fence seq_cst + ret void +} + diff --git a/test/CodeGen/SystemZ/atomic-fence-02.ll b/test/CodeGen/SystemZ/atomic-fence-02.ll new file mode 100644 index 000000000000..4c4375ef6696 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-fence-02.ll @@ -0,0 +1,13 @@ +; Serialization is emitted only for fence seq_cst. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @test() { +; CHECK: #MEMBARRIER + fence acquire +; CHECK: #MEMBARRIER + fence release +; CHECK: #MEMBARRIER + fence acq_rel + ret void +} diff --git a/test/CodeGen/SystemZ/atomicrmw-add-01.ll b/test/CodeGen/SystemZ/atomicrmw-add-01.ll index 25f71f31ef1b..63c28ebb9872 100644 --- a/test/CodeGen/SystemZ/atomicrmw-add-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-add-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic additions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,20 +14,20 @@ ; instructions. define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg %r1, %r2, 0, 189, 0{{$}} +; CHECK: sll [[SHIFT:%r[0-9]+]], 3 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r1) ; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) ; CHECK: ar [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0(%r1) ; CHECK: jl [[LABEL]] ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) @@ -48,20 +48,20 @@ define i8 @f1(i8 *%src, i8 %b) { ; Check the minimum signed value. We add 0x80000000 to the rotated word. define i8 @f2(i8 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: afi [[ROT]], -2147483648 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) diff --git a/test/CodeGen/SystemZ/atomicrmw-add-02.ll b/test/CodeGen/SystemZ/atomicrmw-add-02.ll index cd4e4784c372..8f5e1b4998e5 100644 --- a/test/CodeGen/SystemZ/atomicrmw-add-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-add-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic additions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,20 +14,20 @@ ; instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: ar [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) @@ -48,20 +48,20 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check the minimum signed value. We add 0x80000000 to the rotated word. define i16 @f2(i16 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: afi [[ROT]], -2147483648 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) diff --git a/test/CodeGen/SystemZ/atomicrmw-and-01.ll b/test/CodeGen/SystemZ/atomicrmw-and-01.ll index 6d2f541c3a35..c16071669f40 100644 --- a/test/CodeGen/SystemZ/atomicrmw-and-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-and-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic ANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,20 @@ ; independent of the other loop prologue instructions. define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nr [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -49,21 +48,21 @@ define i8 @f1(i8 *%src, i8 %b) { ; Check the minimum signed value. We AND the rotated word with 0x80ffffff. define i8 @f2(i8 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0 +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nilh [[ROT]], 33023 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-and-02.ll b/test/CodeGen/SystemZ/atomicrmw-and-02.ll index 572b22484b28..f827c4409fe5 100644 --- a/test/CodeGen/SystemZ/atomicrmw-and-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-and-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic ANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,21 @@ ; independent of the other loop prologue instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nr [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -49,21 +49,21 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check the minimum signed value. We AND the rotated word with 0x8000ffff. define i16 @f2(i16 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nilh [[ROT]], 32768 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll index 2b750c46e261..b304335391ee 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic min/max operations. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,23 +14,23 @@ ; independent of the other loop prologue instructions. define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 39, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -50,23 +50,23 @@ define i8 @f1(i8 *%src, i8 %b) { ; Check signed maximum. define i8 @f2(i8 *%src, i8 %b) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 39, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -86,23 +86,23 @@ define i8 @f2(i8 *%src, i8 %b) { ; Check unsigned minimum. define i8 @f3(i8 *%src, i8 %b) { ; CHECK-LABEL: f3: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 39, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f3: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -122,23 +122,23 @@ define i8 @f3(i8 *%src, i8 %b) { ; Check unsigned maximum. define i8 @f4(i8 *%src, i8 %b) { ; CHECK-LABEL: f4: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 39, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f4: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll index 98ffedf28c69..ccb51316552a 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic min/max operations. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,23 +14,23 @@ ; independent of the other loop prologue instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -50,23 +50,23 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check signed maximum. define i16 @f2(i16 *%src, i16 %b) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -86,23 +86,23 @@ define i16 @f2(i16 *%src, i16 %b) { ; Check unsigned minimum. define i16 @f3(i16 *%src, i16 %b) { ; CHECK-LABEL: f3: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f3: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -122,23 +122,23 @@ define i16 @f3(i16 *%src, i16 %b) { ; Check unsigned maximum. define i16 @f4(i16 *%src, i16 %b) { ; CHECK-LABEL: f4: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LOOP:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]] ; CHECK: risbg [[ROT]], %r3, 32, 47, 0 ; CHECK: [[KEEP]]: ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LOOP]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f4: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll index 4ab48e46fc82..b53633a5e063 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll @@ -12,8 +12,8 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: crjle %r2, %r4, [[KEEP:\..*]] ; CHECK: lr [[NEW]], %r4 ; CHECK: cs %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw min i32 *%src, i32 %b seq_cst ret i32 %res } @@ -27,8 +27,8 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: crjhe %r2, %r4, [[KEEP:\..*]] ; CHECK: lr [[NEW]], %r4 ; CHECK: cs %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw max i32 *%src, i32 %b seq_cst ret i32 %res } @@ -42,8 +42,8 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: clrjle %r2, %r4, [[KEEP:\..*]] ; CHECK: lr [[NEW]], %r4 ; CHECK: cs %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw umin i32 *%src, i32 %b seq_cst ret i32 %res } @@ -57,8 +57,8 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: clrjhe %r2, %r4, [[KEEP:\..*]] ; CHECK: lr [[NEW]], %r4 ; CHECK: cs %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw umax i32 *%src, i32 %b seq_cst ret i32 %res } @@ -68,7 +68,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f5: ; CHECK: l %r2, 4092(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i32, i32 *%src, i64 1023 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res @@ -79,7 +79,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f6: ; CHECK: ly %r2, 4096(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i32, i32 *%src, i64 1024 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res @@ -90,7 +90,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f7: ; CHECK: ly %r2, 524284(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i32, i32 *%src, i64 131071 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res @@ -102,7 +102,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: l %r2, 0(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i32, i32 *%src, i64 131072 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res @@ -113,7 +113,7 @@ define i32 @f9(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f9: ; CHECK: ly %r2, -4(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i32, i32 *%src, i64 -1 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res @@ -124,7 +124,7 @@ define i32 @f10(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f10: ; CHECK: ly %r2, -524288(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i32, i32 *%src, i64 -131072 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res @@ -136,7 +136,7 @@ define i32 @f11(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, -524292 ; CHECK: l %r2, 0(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i32, i32 *%src, i64 -131073 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res @@ -148,7 +148,7 @@ define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) { ; CHECK: agr %r3, %r4 ; CHECK: l %r2, 0(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i32 * %res = atomicrmw min i32 *%ptr, i32 %b seq_cst @@ -165,8 +165,8 @@ define i32 @f13(i32 %dummy, i32 *%ptr) { ; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]] ; CHECK: lhi [[NEW]], 42 ; CHECK: cs %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw min i32 *%ptr, i32 42 seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll index afd88a3dd42d..444dc915c0fe 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll @@ -12,8 +12,8 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: cgrjle %r2, %r4, [[KEEP:\..*]] ; CHECK: lgr [[NEW]], %r4 ; CHECK: csg %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw min i64 *%src, i64 %b seq_cst ret i64 %res } @@ -27,8 +27,8 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: cgrjhe %r2, %r4, [[KEEP:\..*]] ; CHECK: lgr [[NEW]], %r4 ; CHECK: csg %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw max i64 *%src, i64 %b seq_cst ret i64 %res } @@ -42,8 +42,8 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: clgrjle %r2, %r4, [[KEEP:\..*]] ; CHECK: lgr [[NEW]], %r4 ; CHECK: csg %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw umin i64 *%src, i64 %b seq_cst ret i64 %res } @@ -57,8 +57,8 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: clgrjhe %r2, %r4, [[KEEP:\..*]] ; CHECK: lgr [[NEW]], %r4 ; CHECK: csg %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw umax i64 *%src, i64 %b seq_cst ret i64 %res } @@ -68,7 +68,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f5: ; CHECK: lg %r2, 524280(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res @@ -80,7 +80,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: lg %r2, 0(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res @@ -91,7 +91,7 @@ define i64 @f7(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f7: ; CHECK: lg %r2, -524288(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res @@ -103,7 +103,7 @@ define i64 @f8(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, -524296 ; CHECK: lg %r2, 0(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res @@ -115,7 +115,7 @@ define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) { ; CHECK: agr %r3, %r4 ; CHECK: lg %r2, 0(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) -; CHECK: br %r14 +; CHECK: ber %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i64 * %res = atomicrmw min i64 *%ptr, i64 %b seq_cst @@ -132,8 +132,8 @@ define i64 @f10(i64 %dummy, i64 *%ptr) { ; CHECK: cgrjle %r2, [[LIMIT]], [[KEEP:\..*]] ; CHECK: lghi [[NEW]], 42 ; CHECK: csg %r2, [[NEW]], 0(%r3) -; CHECK: jl [[LOOP]] -; CHECK: br %r14 +; CHECK: ber %r14 +; CHECK: j [[LOOP]] %res = atomicrmw min i64 *%ptr, i64 42 seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll index db5bb8ff9e79..f0fbd9d59a14 100644 --- a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic NANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,22 +14,22 @@ ; independent of the other loop prologue instructions. define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nr [[ROT]], %r3 ; CHECK: xilf [[ROT]], 4278190080 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -50,22 +50,22 @@ define i8 @f1(i8 *%src, i8 %b) { ; Check the minimum signed value. We AND the rotated word with 0x80ffffff. define i8 @f2(i8 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nilh [[ROT]], 33023 ; CHECK: xilf [[ROT]], 4278190080 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll index 6141543e0db2..45b22d4a6f18 100644 --- a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic NANDs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,22 +14,22 @@ ; independent of the other loop prologue instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nr [[ROT]], %r3 ; CHECK: xilf [[ROT]], 4294901760 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -50,22 +50,22 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check the minimum signed value. We AND the rotated word with 0x8000ffff. define i16 @f2(i16 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: nilh [[ROT]], 32768 ; CHECK: xilf [[ROT]], 4294901760 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-or-01.ll b/test/CodeGen/SystemZ/atomicrmw-or-01.ll index caba621addc0..e4d790ebfcb7 100644 --- a/test/CodeGen/SystemZ/atomicrmw-or-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-or-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic ORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,21 @@ ; instructions. define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: or [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -48,21 +48,21 @@ define i8 @f1(i8 *%src, i8 %b) { ; Check the minimum signed value. We OR the rotated word with 0x80000000. define i8 @f2(i8 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: oilh [[ROT]], 32768 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-or-02.ll b/test/CodeGen/SystemZ/atomicrmw-or-02.ll index 877c642a35ae..5029e7925bb1 100644 --- a/test/CodeGen/SystemZ/atomicrmw-or-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-or-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic ORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,21 @@ ; instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: or [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -48,21 +48,21 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check the minimum signed value. We OR the rotated word with 0x80000000. define i16 @f2(i16 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: oilh [[ROT]], 32768 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll index 2c08ebd9f5fc..a12203cd7224 100644 --- a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic subtractions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,21 @@ ; instructions. define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: sr [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -48,21 +48,21 @@ define i8 @f1(i8 *%src, i8 %b) { ; Check the minimum signed value. We add 0x80000000 to the rotated word. define i8 @f2(i8 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: afi [[ROT]], -2147483648 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll index f82ebd9aaaae..1fe1bac18bef 100644 --- a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic subtractions. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,21 @@ ; instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: sr [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -48,21 +48,21 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check the minimum signed value. We add 0x80000000 to the rotated word. define i16 @f2(i16 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: afi [[ROT]], -2147483648 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll index 52575c634971..e7d47ed9c433 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic exchange. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT ; Check exchange with a variable. @@ -12,23 +12,23 @@ ; which shift %r3 left so that %b is at the high end of the word). define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: risbg [[ROT]], %r3, 32, 39, 24 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT-LABEL: f1: ; CHECK-SHIFT-NOT: %r3 -; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT: sll %r2, 3 ; CHECK-SHIFT-NOT: %r3 -; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT: rll ; CHECK-SHIFT-NOT: %r3 diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll index 04be623ada89..97d16c072bb6 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic exchange. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT ; Check exchange with a variable. @@ -12,23 +12,23 @@ ; which shift %r3 left so that %b is at the high end of the word). define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: risbg [[ROT]], %r3, 32, 47, 16 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT-LABEL: f1: ; CHECK-SHIFT-NOT: %r3 -; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT: sll %r2, 3 ; CHECK-SHIFT-NOT: %r3 -; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT-NOT: %r3 ; CHECK-SHIFT: rll ; CHECK-SHIFT-NOT: %r3 diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll index e8fef2d31d2c..49bc7d7b0634 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll @@ -1,6 +1,6 @@ ; Test 8-bit atomic XORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,21 @@ ; instructions. define i8 @f1(i8 *%src, i8 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: xr [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -48,21 +48,21 @@ define i8 @f1(i8 *%src, i8 %b) { ; Check the minimum signed value. We XOR the rotated word with 0x80000000. define i8 @f2(i8 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: xilf [[ROT]], 2147483648 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 8(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll index 9405c2ec0c08..ca60e4189bad 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll @@ -1,6 +1,6 @@ ; Test 16-bit atomic XORs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 @@ -14,21 +14,21 @@ ; instructions. define i16 @f1(i16 *%src, i16 %b) { ; CHECK-LABEL: f1: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: xr [[ROT]], %r3 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f1: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll @@ -48,21 +48,21 @@ define i16 @f1(i16 *%src, i16 %b) { ; Check the minimum signed value. We XOR the rotated word with 0x80000000. define i16 @f2(i16 *%src) { ; CHECK-LABEL: f2: -; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK: nill %r2, 65532 -; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}} +; CHECK: sll %r2, 3 +; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK: [[LABEL:\.[^:]*]]: -; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2) ; CHECK: xilf [[ROT]], 2147483648 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) -; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK: jl [[LABEL]] -; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: rll %r2, [[OLD]], 16(%r2) ; CHECK: br %r14 ; ; CHECK-SHIFT1-LABEL: f2: -; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 -; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: sll %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2 ; CHECK-SHIFT1: rll ; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) ; CHECK-SHIFT1: rll diff --git a/test/CodeGen/SystemZ/backchain.ll b/test/CodeGen/SystemZ/backchain.ll new file mode 100644 index 000000000000..45775dbf273d --- /dev/null +++ b/test/CodeGen/SystemZ/backchain.ll @@ -0,0 +1,84 @@ +; Test the backchain attribute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i8 *@llvm.stacksave() +declare void @llvm.stackrestore(i8 *) +declare void @g() + +; nothing should happen if no stack frame is needed. +define void @f1() "backchain" { +; CHECK-LABEL: f1: +; CHECK-NOT: stg + ret void +} + +; check that backchain is saved if we call someone +define void @f2() "backchain" { +; CHECK-LABEL: f2: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK: lgr %r1, %r15 +; CHECK: aghi %r15, -160 +; CHECK: stg %r1, 0(%r15) + call void @g() + call void @g() + ret void +} + +; check that backchain is saved if we have an alloca +define void @f3() "backchain" { +; CHECK-LABEL: f3: +; CHECK-NOT: stmg +; CHECK: lgr %r1, %r15 +; CHECK: aghi %r15, -168 +; CHECK: stg %r1, 0(%r15) + %ign = alloca i8, i32 4 + ret void +} + +; check that alloca copies the backchain +define void @f4(i32 %len) "backchain" { +; CHECK-LABEL: f4: +; CHECK: stmg %r11, %r15, 88(%r15) +; CHECK: lgr %r1, %r15 +; CHECK: aghi %r15, -160 +; CHECK: stg %r1, 0(%r15) +; CHECK: lgr %r11, %r15 +; CHECK: lg [[BC:%r[0-9]+]], 0(%r15) +; CHECK: lgr [[NEWSP:%r[0-9]+]], %r15 +; CHECK: lgr %r15, [[NEWSP]] +; CHECK: stg [[BC]], 0([[NEWSP]]) + %ign = alloca i8, i32 %len + ret void +} + +; check that llvm.stackrestore restores the backchain +define void @f5(i32 %count1, i32 %count2) "backchain" { +; CHECK-LABEL: f5: +; CHECK: stmg %r11, %r15, 88(%r15) +; CHECK: lgr %r1, %r15 +; CHECK: aghi %r15, -160 +; CHECK: stg %r1, 0(%r15) +; CHECK: lgr %r11, %r15 +; CHECK: lgr [[SAVESP:%r[0-9]+]], %r15 +; CHECK: lg [[BC:%r[0-9]+]], 0(%r15) +; CHECK: lgr [[NEWSP:%r[0-9]+]], %r15 +; CHECK: lgr %r15, [[NEWSP]] +; CHECK: stg [[BC]], 0([[NEWSP]]) +; CHECK: lg [[BC2:%r[0-9]+]], 0(%r15) +; CHECK: lgr %r15, [[SAVESP]] +; CHECK: stg [[BC2]], 0([[SAVESP]]) +; CHECK: lg [[BC3:%r[0-9]+]], 0(%r15) +; CHECK: lgr [[NEWSP2:%r[0-9]+]], %r15 +; CHECK: lgr %r15, [[NEWSP2]] +; CHECK: stg [[BC3]], 0([[NEWSP2]]) +; CHECK: lmg %r11, %r15, 248(%r11) +; CHECK: br %r14 + %src = call i8 *@llvm.stacksave() + %array1 = alloca i8, i32 %count1 + store volatile i8 0, i8 *%array1 + call void @llvm.stackrestore(i8 *%src) + %array2 = alloca i8, i32 %count2 + store volatile i8 0, i8 *%array2 + ret void +} diff --git a/test/CodeGen/SystemZ/branch-05.ll b/test/CodeGen/SystemZ/branch-05.ll index b2157b5ac778..4a4aa2a9eb36 100644 --- a/test/CodeGen/SystemZ/branch-05.ll +++ b/test/CodeGen/SystemZ/branch-05.ll @@ -5,7 +5,7 @@ define i32 @f1(i32 %x, i32 %y, i32 %op) { ; CHECK-LABEL: f1: ; CHECK: ahi %r4, -1 -; CHECK: clijh %r4, 5, +; CHECK: clibh %r4, 5, 0(%r14) ; CHECK: llgfr [[OP64:%r[0-5]]], %r4 ; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3 ; CHECK: larl [[BASE:%r[1-5]]] diff --git a/test/CodeGen/SystemZ/bswap-06.ll b/test/CodeGen/SystemZ/bswap-06.ll new file mode 100644 index 000000000000..19aafe2ca17b --- /dev/null +++ b/test/CodeGen/SystemZ/bswap-06.ll @@ -0,0 +1,99 @@ +; Test 16-bit byteswaps from memory to registers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i16 @llvm.bswap.i16(i16 %a) + +; Check LRVH with no displacement. +define i16 @f1(i16 *%src) { +; CHECK-LABEL: f1: +; CHECK: lrvh %r2, 0(%r2) +; CHECK: br %r14 + %a = load i16 , i16 *%src + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} + +; Check the high end of the aligned LRVH range. +define i16 @f2(i16 *%src) { +; CHECK-LABEL: f2: +; CHECK: lrvh %r2, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262143 + %a = load i16 , i16 *%ptr + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i16 @f3(i16 *%src) { +; CHECK-LABEL: f3: +; CHECK: agfi %r2, 524288 +; CHECK: lrvh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262144 + %a = load i16 , i16 *%ptr + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} + +; Check the high end of the negative aligned LRVH range. +define i16 @f4(i16 *%src) { +; CHECK-LABEL: f4: +; CHECK: lrvh %r2, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -1 + %a = load i16 , i16 *%ptr + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} + +; Check the low end of the LRVH range. +define i16 @f5(i16 *%src) { +; CHECK-LABEL: f5: +; CHECK: lrvh %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %a = load i16 , i16 *%ptr + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i16 @f6(i16 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r2, -524290 +; CHECK: lrvh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %a = load i16 , i16 *%ptr + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} + +; Check that LRVH allows an index. +define i16 @f7(i64 %src, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: lrvh %r2, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i16 * + %a = load i16 , i16 *%ptr + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} + +; Check that volatile accesses do not use LRVH, which might access the +; storage multple times. +define i16 @f8(i16 *%src) { +; CHECK-LABEL: f8: +; CHECK: lh [[REG:%r[0-5]]], 0(%r2) +; CHECK: lrvr %r2, [[REG]] +; CHECK: br %r14 + %a = load volatile i16 , i16 *%src + %swapped = call i16 @llvm.bswap.i16(i16 %a) + ret i16 %swapped +} diff --git a/test/CodeGen/SystemZ/bswap-07.ll b/test/CodeGen/SystemZ/bswap-07.ll new file mode 100644 index 000000000000..7f0a265de756 --- /dev/null +++ b/test/CodeGen/SystemZ/bswap-07.ll @@ -0,0 +1,100 @@ +; Test 32-bit byteswaps from registers to memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i16 @llvm.bswap.i16(i16 %a) + +; Check STRVH with no displacement. +define void @f1(i16 *%dst, i16 %a) { +; CHECK-LABEL: f1: +; CHECK: strvh %r3, 0(%r2) +; CHECK: br %r14 + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store i16 %swapped, i16 *%dst + ret void +} + +; Check the high end of the aligned STRVH range. +define void @f2(i16 *%dst, i16 %a) { +; CHECK-LABEL: f2: +; CHECK: strvh %r3, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%dst, i64 262143 + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store i16 %swapped, i16 *%ptr + ret void +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f3(i16 *%dst, i16 %a) { +; CHECK-LABEL: f3: +; CHECK: agfi %r2, 524288 +; CHECK: strvh %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%dst, i64 262144 + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store i16 %swapped, i16 *%ptr + ret void +} + +; Check the high end of the negative aligned STRVH range. +define void @f4(i16 *%dst, i16 %a) { +; CHECK-LABEL: f4: +; CHECK: strvh %r3, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%dst, i64 -1 + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store i16 %swapped, i16 *%ptr + ret void +} + +; Check the low end of the STRVH range. +define void @f5(i16 *%dst, i16 %a) { +; CHECK-LABEL: f5: +; CHECK: strvh %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%dst, i64 -262144 + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store i16 %swapped, i16 *%ptr + ret void +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i16 *%dst, i16 %a) { +; CHECK-LABEL: f6: +; CHECK: agfi %r2, -524290 +; CHECK: strvh %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%dst, i64 -262145 + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store i16 %swapped, i16 *%ptr + ret void +} + +; Check that STRVH allows an index. +define void @f7(i64 %src, i64 %index, i16 %a) { +; CHECK-LABEL: f7: +; CHECK: strvh %r4, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i16 * + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store i16 %swapped, i16 *%ptr + ret void +} + +; Check that volatile stores do not use STRVH, which might access the +; storage multple times. +define void @f8(i16 *%dst, i16 %a) { +; CHECK-LABEL: f8: +; CHECK: lrvr [[REG:%r[0-5]]], %r3 +; CHECK: srl [[REG]], 16 +; CHECK: sth [[REG]], 0(%r2) +; CHECK: br %r14 + %swapped = call i16 @llvm.bswap.i16(i16 %a) + store volatile i16 %swapped, i16 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/builtins.ll b/test/CodeGen/SystemZ/builtins.ll new file mode 100644 index 000000000000..86546c08488a --- /dev/null +++ b/test/CodeGen/SystemZ/builtins.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Function Attrs: nounwind readnone +declare i8* @llvm.thread.pointer() #1 + +define i8* @thread_pointer() { +; CHECK: thread_pointer: +; CHECK: ear [[REG1:%r[0-5]]], %a0 +; CHECK: sllg %r2, [[REG1]], 32 +; CHECK: ear %r2, %a1 +; CHECK: br %r14 + %1 = tail call i8* @llvm.thread.pointer() + ret i8* %1 +} diff --git a/test/CodeGen/SystemZ/call-04.ll b/test/CodeGen/SystemZ/call-04.ll new file mode 100644 index 000000000000..12e0d5966765 --- /dev/null +++ b/test/CodeGen/SystemZ/call-04.ll @@ -0,0 +1,369 @@ +; Test conditional sibling calls. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare void @fun_a() +declare void @fun_b() +declare void @fun_c(i32) + +@var = global i32 1; + +; Check a conditional sibling call. +define void @f1(i32 %val1, i32 %val2) { +; CHECK-LABEL: f1: +; CHECK: cr %r2, %r3 +; CHECK: jgl fun_a@PLT +; CHECK: br %r14 + %cond = icmp slt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call when there are two possibilities. +define void @f2(i32 %val1, i32 %val2) { +; CHECK-LABEL: f2: +; CHECK: cr %r2, %r3 +; CHECK: jghe fun_b@PLT +; CHECK: jg fun_a@PLT + %cond = icmp slt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + tail call void @fun_b() + ret void +} + +; Check a conditional sibling call with an argument - not supported. +define void @f3(i32 %val1, i32 %val2) { +; CHECK-LABEL: f3: +; CHECK: crjhe %r2, %r3 +; CHECK: jg fun_c@PLT +; CHECK: br %r14 + %cond = icmp slt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_c(i32 1) + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - unsigned compare. +define void @f4(i32 %val1, i32 %val2) { +; CHECK-LABEL: f4: +; CHECK: clr %r2, %r3 +; CHECK: jgl fun_a@PLT +; CHECK: br %r14 + %cond = icmp ult i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - 64-bit compare. +define void @f5(i64 %val1, i64 %val2) { +; CHECK-LABEL: f5: +; CHECK: cgr %r2, %r3 +; CHECK: jgl fun_a@PLT +; CHECK: br %r14 + %cond = icmp slt i64 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - unsigned 64-bit compare. +define void @f6(i64 %val1, i64 %val2) { +; CHECK-LABEL: f6: +; CHECK: clgr %r2, %r3 +; CHECK: jgl fun_a@PLT +; CHECK: br %r14 + %cond = icmp ult i64 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - less-equal compare. +define void @f7(i32 %val1, i32 %val2) { +; CHECK-LABEL: f7: +; CHECK: cr %r2, %r3 +; CHECK: jgle fun_a@PLT +; CHECK: br %r14 + %cond = icmp sle i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - high compare. +define void @f8(i32 %val1, i32 %val2) { +; CHECK-LABEL: f8: +; CHECK: cr %r2, %r3 +; CHECK: jgh fun_a@PLT +; CHECK: br %r14 + %cond = icmp sgt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - high-equal compare. +define void @f9(i32 %val1, i32 %val2) { +; CHECK-LABEL: f9: +; CHECK: cr %r2, %r3 +; CHECK: jghe fun_a@PLT +; CHECK: br %r14 + %cond = icmp sge i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - equal compare. +define void @f10(i32 %val1, i32 %val2) { +; CHECK-LABEL: f10: +; CHECK: cr %r2, %r3 +; CHECK: jge fun_a@PLT +; CHECK: br %r14 + %cond = icmp eq i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - unequal compare. +define void @f11(i32 %val1, i32 %val2) { +; CHECK-LABEL: f11: +; CHECK: cr %r2, %r3 +; CHECK: jglh fun_a@PLT +; CHECK: br %r14 + %cond = icmp ne i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate slt. +define void @f12(i32 %val1) { +; CHECK-LABEL: f12: +; CHECK: chi %r2, 4 +; CHECK: jgle fun_a@PLT +; CHECK: br %r14 + %cond = icmp slt i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate sle. +define void @f13(i32 %val1) { +; CHECK-LABEL: f13: +; CHECK: chi %r2, 5 +; CHECK: jgle fun_a@PLT +; CHECK: br %r14 + %cond = icmp sle i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate sgt. +define void @f14(i32 %val1) { +; CHECK-LABEL: f14: +; CHECK: chi %r2, 6 +; CHECK: jghe fun_a@PLT +; CHECK: br %r14 + %cond = icmp sgt i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate sge. +define void @f15(i32 %val1) { +; CHECK-LABEL: f15: +; CHECK: chi %r2, 5 +; CHECK: jghe fun_a@PLT +; CHECK: br %r14 + %cond = icmp sge i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate eq. +define void @f16(i32 %val1) { +; CHECK-LABEL: f16: +; CHECK: chi %r2, 5 +; CHECK: jge fun_a@PLT +; CHECK: br %r14 + %cond = icmp eq i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate ne. +define void @f17(i32 %val1) { +; CHECK-LABEL: f17: +; CHECK: chi %r2, 5 +; CHECK: jglh fun_a@PLT +; CHECK: br %r14 + %cond = icmp ne i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate ult. +define void @f18(i32 %val1) { +; CHECK-LABEL: f18: +; CHECK: clfi %r2, 4 +; CHECK: jgle fun_a@PLT +; CHECK: br %r14 + %cond = icmp ult i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate 64-bit slt. +define void @f19(i64 %val1) { +; CHECK-LABEL: f19: +; CHECK: cghi %r2, 4 +; CHECK: jgle fun_a@PLT +; CHECK: br %r14 + %cond = icmp slt i64 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate 64-bit ult. +define void @f20(i64 %val1) { +; CHECK-LABEL: f20: +; CHECK: clgfi %r2, 4 +; CHECK: jgle fun_a@PLT +; CHECK: br %r14 + %cond = icmp ult i64 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void @fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} diff --git a/test/CodeGen/SystemZ/call-05.ll b/test/CodeGen/SystemZ/call-05.ll new file mode 100644 index 000000000000..15704531d96a --- /dev/null +++ b/test/CodeGen/SystemZ/call-05.ll @@ -0,0 +1,467 @@ +; Test conditional sibling calls. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + + +@var = global i32 1; +@fun_a = global void()* null; +@fun_b = global void()* null; +@fun_c = global void(i32)* null; + +; Check a conditional sibling call. +define void @f1(i32 %val1, i32 %val2) { +; CHECK-LABEL: f1: +; CHECK: crbl %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp slt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call when there are two possibilities. +define void @f2(i32 %val1, i32 %val2) { +; CHECK-LABEL: f2: +; CHECK: crbl %r2, %r3, 0(%r1) +; CHECK: br %r1 + %fun_a = load volatile void() *, void()** @fun_a; + %fun_b = load volatile void() *, void()** @fun_b; + %cond = icmp slt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + tail call void %fun_b() + ret void +} + +; Check a conditional sibling call with an argument - not supported. +define void @f3(i32 %val1, i32 %val2) { +; CHECK-LABEL: f3: +; CHECK: crjhe %r2, %r3 +; CHECK: br %r1 +; CHECK: br %r14 + %fun_c = load volatile void(i32) *, void(i32)** @fun_c; + %cond = icmp slt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_c(i32 1) + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - unsigned compare. +define void @f4(i32 %val1, i32 %val2) { +; CHECK-LABEL: f4: +; CHECK: clrbl %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp ult i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - 64-bit compare. +define void @f5(i64 %val1, i64 %val2) { +; CHECK-LABEL: f5: +; CHECK: cgrbl %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp slt i64 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - unsigned 64-bit compare. +define void @f6(i64 %val1, i64 %val2) { +; CHECK-LABEL: f6: +; CHECK: clgrbl %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp ult i64 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - less-equal compare. +define void @f7(i32 %val1, i32 %val2) { +; CHECK-LABEL: f7: +; CHECK: crble %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp sle i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - high compare. +define void @f8(i32 %val1, i32 %val2) { +; CHECK-LABEL: f8: +; CHECK: crbh %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp sgt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - high-equal compare. +define void @f9(i32 %val1, i32 %val2) { +; CHECK-LABEL: f9: +; CHECK: crbhe %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp sge i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - equal compare. +define void @f10(i32 %val1, i32 %val2) { +; CHECK-LABEL: f10: +; CHECK: crbe %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp eq i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - unequal compare. +define void @f11(i32 %val1, i32 %val2) { +; CHECK-LABEL: f11: +; CHECK: crblh %r2, %r3, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp ne i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate slt. +define void @f12(i32 %val1) { +; CHECK-LABEL: f12: +; CHECK: cible %r2, 4, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp slt i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate sle. +define void @f13(i32 %val1) { +; CHECK-LABEL: f13: +; CHECK: cible %r2, 5, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp sle i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate sgt. +define void @f14(i32 %val1) { +; CHECK-LABEL: f14: +; CHECK: cibhe %r2, 6, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp sgt i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate sge. +define void @f15(i32 %val1) { +; CHECK-LABEL: f15: +; CHECK: cibhe %r2, 5, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp sge i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate eq. +define void @f16(i32 %val1) { +; CHECK-LABEL: f16: +; CHECK: cibe %r2, 5, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp eq i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate ne. +define void @f17(i32 %val1) { +; CHECK-LABEL: f17: +; CHECK: ciblh %r2, 5, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp ne i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate ult. +define void @f18(i32 %val1) { +; CHECK-LABEL: f18: +; CHECK: clible %r2, 4, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp ult i32 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate 64-bit slt. +define void @f19(i64 %val1) { +; CHECK-LABEL: f19: +; CHECK: cgible %r2, 4, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp slt i64 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - immediate 64-bit ult. +define void @f20(i64 %val1) { +; CHECK-LABEL: f20: +; CHECK: clgible %r2, 4, 0(%r1) +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = icmp ult i64 %val1, 5; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call to an argument - will fail due to +; intervening lgr. +define void @f21(i32 %val1, i32 %val2, void()* %fun) { +; CHECK-LABEL: f21: +; CHECK: crjhe %r2, %r3 +; CHECK: lgr %r1, %r4 +; CHECK: br %r1 +; CHECK: br %r14 + %cond = icmp slt i32 %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - float olt compare. +define void @f22(float %val1, float %val2) { +; CHECK-LABEL: f22: +; CHECK: cebr %f0, %f2 +; CHECK: blr %r1 +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = fcmp olt float %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - float ult compare. +define void @f23(float %val1, float %val2) { +; CHECK-LABEL: f23: +; CHECK: cebr %f0, %f2 +; CHECK: bnher %r1 +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = fcmp ult float %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - float ord compare. +define void @f24(float %val1, float %val2) { +; CHECK-LABEL: f24: +; CHECK: cebr %f0, %f2 +; CHECK: bnor %r1 +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = fcmp ord float %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} + +; Check a conditional sibling call - float uno compare. +define void @f25(float %val1, float %val2) { +; CHECK-LABEL: f25: +; CHECK: cebr %f0, %f2 +; CHECK: bor %r1 +; CHECK: br %r14 + %fun_a = load volatile void() *, void()** @fun_a; + %cond = fcmp uno float %val1, %val2; + br i1 %cond, label %a, label %b; + +a: + tail call void %fun_a() + ret void + +b: + store i32 1, i32 *@var; + ret void +} diff --git a/test/CodeGen/SystemZ/cmpxchg-01.ll b/test/CodeGen/SystemZ/cmpxchg-01.ll index 5118aadcf2ad..a74c2ff878e7 100644 --- a/test/CodeGen/SystemZ/cmpxchg-01.ll +++ b/test/CodeGen/SystemZ/cmpxchg-01.ll @@ -12,23 +12,23 @@ ; which shift %r3 left so that %b is at the high end of the word). define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) { ; CHECK-MAIN-LABEL: f1: -; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3 -; CHECK-MAIN: nill %r3, 65532 -; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3) +; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}} +; CHECK-MAIN: sll %r3, 3 +; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK-MAIN: [[LOOP:\.[^ ]*]]: -; CHECK-MAIN: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK-MAIN: rll %r2, [[OLD]], 8(%r3) ; CHECK-MAIN: risbg %r4, %r2, 32, 55, 0 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]] ; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}}) -; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3) +; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK-MAIN: jl [[LOOP]] ; CHECK-MAIN: [[EXIT]]: ; CHECK-MAIN-NOT: %r2 ; CHECK-MAIN: br %r14 ; ; CHECK-SHIFT-LABEL: f1: -; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3 +; CHECK-SHIFT: sll [[SHIFT:%r[1-9]+]], 3 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] ; CHECK-SHIFT: rll ; CHECK-SHIFT: rll {{%r[0-9]+}}, %r5, -8([[NEGSHIFT]]) diff --git a/test/CodeGen/SystemZ/cmpxchg-02.ll b/test/CodeGen/SystemZ/cmpxchg-02.ll index 9eb0628b5a30..2445c0deab14 100644 --- a/test/CodeGen/SystemZ/cmpxchg-02.ll +++ b/test/CodeGen/SystemZ/cmpxchg-02.ll @@ -12,24 +12,24 @@ ; which shift %r3 left so that %b is at the high end of the word). define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) { ; CHECK-MAIN-LABEL: f1: -; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3 -; CHECK-MAIN: nill %r3, 65532 -; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3) +; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}} +; CHECK-MAIN: sll %r3, 3 +; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]]) ; CHECK-MAIN: [[LOOP:\.[^ ]*]]: -; CHECK-MAIN: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK-MAIN: rll %r2, [[OLD]], 16(%r3) ; CHECK-MAIN: risbg %r4, %r2, 32, 47, 0 ; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]] ; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}}) -; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3) +; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]]) ; CHECK-MAIN: jl [[LOOP]] ; CHECK-MAIN: [[EXIT]]: ; CHECK-MAIN-NOT: %r2 ; CHECK-MAIN: br %r14 ; ; CHECK-SHIFT-LABEL: f1: -; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3 -; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT: sll %r3, 3 +; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], %r3 ; CHECK-SHIFT: rll ; CHECK-SHIFT: rll {{%r[0-9]+}}, %r5, -16([[NEGSHIFT]]) %pair = cmpxchg i16 *%src, i16 %cmp, i16 %swap seq_cst seq_cst diff --git a/test/CodeGen/SystemZ/cmpxchg-05.ll b/test/CodeGen/SystemZ/cmpxchg-05.ll new file mode 100644 index 000000000000..68261efa6384 --- /dev/null +++ b/test/CodeGen/SystemZ/cmpxchg-05.ll @@ -0,0 +1,81 @@ +; Test proper extension of 8-bit/16-bit cmpxchg. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; CHECK-LABEL: f1 +; CHECK: crjlh +; CHECK-NOT: llcr +; CHECK-NOT: cr +; CHECK: llgcr %r2, [[RES:%r[0-9]+]] +; CHECK-NOT: llcr +; CHECK-NOT: cr +define zeroext i8 @f1(i8* nocapture, i8 zeroext, i8 zeroext) { + %cx = cmpxchg i8* %0, i8 %1, i8 %2 seq_cst seq_cst + %res = extractvalue { i8, i1 } %cx, 0 + ret i8 %res +} + +; CHECK-LABEL: f2 +; CHECK: crjlh +; CHECK-NOT: llhr +; CHECK-NOT: cr +; CHECK: llghr %r2, [[RES:%r[0-9]+]] +; CHECK-NOT: llhr +; CHECK-NOT: cr +define zeroext i16 @f2(i16* nocapture, i16 zeroext, i16 zeroext) { + %cx = cmpxchg i16* %0, i16 %1, i16 %2 seq_cst seq_cst + %res = extractvalue { i16, i1 } %cx, 0 + ret i16 %res +} + +; CHECK-LABEL: f3 +; CHECK: crjlh +; CHECK-NOT: llcr +; CHECK-NOT: cr +; CHECK: lgbr %r2, [[RES:%r[0-9]+]] +; CHECK-NOT: llcr +; CHECK-NOT: cr +define signext i8 @f3(i8* nocapture, i8 signext, i8 signext) { + %cx = cmpxchg i8* %0, i8 %1, i8 %2 seq_cst seq_cst + %res = extractvalue { i8, i1 } %cx, 0 + ret i8 %res +} + +; CHECK-LABEL: f4 +; CHECK: crjlh +; CHECK-NOT: llhr +; CHECK-NOT: cr +; CHECK: lghr %r2, [[RES:%r[0-9]+]] +; CHECK-NOT: llhr +; CHECK-NOT: cr +define signext i16 @f4(i16* nocapture, i16 signext, i16 signext) { + %cx = cmpxchg i16* %0, i16 %1, i16 %2 seq_cst seq_cst + %res = extractvalue { i16, i1 } %cx, 0 + ret i16 %res +} + +; Now use the comparison result. +; CHECK-LABEL: f5 +; CHECK: llcr [[REG:%r[0-9]+]], [[RES:%r[0-9]+]] +; CHECK: cr [[REG]], %r3 +define zeroext i8 @f5(i8* nocapture, i8 zeroext, i8 zeroext) { + %cx = cmpxchg i8* %0, i8 %1, i8 %2 seq_cst seq_cst + %res = extractvalue { i8, i1 } %cx, 1 + %xres = sext i1 %res to i8 + ret i8 %xres +} + +; Now use the comparison result and zero-extended old value. +; CHECK-LABEL: f6 +; CHECK: llcr [[REG:%r[0-9]+]], [[RES:%r[0-9]+]] +; CHECK: st [[REG]], 0(%r5) +; CHECK: cr [[REG]], %r3 +define zeroext i8 @f6(i8* nocapture, i8 zeroext, i8 zeroext, i32*) { + %cx = cmpxchg i8* %0, i8 %1, i8 %2 seq_cst seq_cst + %old = extractvalue { i8, i1 } %cx, 0 + %xold = zext i8 %old to i32 + store i32 %xold, i32* %3 + %res = extractvalue { i8, i1 } %cx, 1 + %xres = sext i1 %res to i8 + ret i8 %xres +} diff --git a/test/CodeGen/SystemZ/cond-li.ll b/test/CodeGen/SystemZ/cond-li.ll new file mode 100644 index 000000000000..a3e2f3fd1252 --- /dev/null +++ b/test/CodeGen/SystemZ/cond-li.ll @@ -0,0 +1,23 @@ +; Test LOCHI/LOCGHI +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; CHECK-LABEL: bar1: +; CHECK: lhi [[REG:%r[0-5]]], 42 +; CHECK: chi %r2, 0 +; CHECK: lochie [[REG]], 0 +define signext i32 @bar1(i32 signext %x) { + %cmp = icmp ne i32 %x, 0 + %.x = select i1 %cmp, i32 42, i32 0 + ret i32 %.x +} + +; CHECK-LABEL: bar2: +; CHECK: ltgr [[REG:%r[0-5]]], %r2 +; CHECK: lghi %r2, 42 +; CHECK: locghie %r2, 0 +define signext i64 @bar2(i64 signext %x) { + %cmp = icmp ne i64 %x, 0 + %.x = select i1 %cmp, i64 42, i64 0 + ret i64 %.x +} diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll index ec7fc4a31fcd..a682d222add5 100644 --- a/test/CodeGen/SystemZ/cond-store-01.ll +++ b/test/CodeGen/SystemZ/cond-store-01.ll @@ -9,10 +9,9 @@ declare void @foo(i8 *) define void @f1(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK-LABEL: f1: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -25,10 +24,9 @@ define void @f1(i8 *%ptr, i8 %alt, i32 %limit) { define void @f2(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK-LABEL: f2: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -42,10 +40,9 @@ define void @f2(i8 *%ptr, i8 %alt, i32 %limit) { define void @f3(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f3: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -60,10 +57,9 @@ define void @f3(i8 *%ptr, i32 %alt, i32 %limit) { define void @f4(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f4: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -79,10 +75,9 @@ define void @f4(i8 *%ptr, i32 %alt, i32 %limit) { define void @f5(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f5: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -97,10 +92,9 @@ define void @f5(i8 *%ptr, i32 %alt, i32 %limit) { define void @f6(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f6: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -116,10 +110,9 @@ define void @f6(i8 *%ptr, i32 %alt, i32 %limit) { define void @f7(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f7: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -134,10 +127,9 @@ define void @f7(i8 *%ptr, i64 %alt, i32 %limit) { define void @f8(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f8: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -153,10 +145,9 @@ define void @f8(i8 *%ptr, i64 %alt, i32 %limit) { define void @f9(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f9: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -171,10 +162,9 @@ define void @f9(i8 *%ptr, i64 %alt, i32 %limit) { define void @f10(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f10: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i8 , i8 *%ptr @@ -189,10 +179,9 @@ define void @f10(i8 *%ptr, i64 %alt, i32 %limit) { define void @f11(i8 *%base, i8 %alt, i32 %limit) { ; CHECK-LABEL: f11: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stc %r3, 4095(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i8, i8 *%base, i64 4095 %cond = icmp ult i32 %limit, 420 @@ -206,10 +195,9 @@ define void @f11(i8 *%base, i8 %alt, i32 %limit) { define void @f12(i8 *%base, i8 %alt, i32 %limit) { ; CHECK-LABEL: f12: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stcy %r3, 4096(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i8, i8 *%base, i64 4096 %cond = icmp ult i32 %limit, 420 @@ -223,10 +211,9 @@ define void @f12(i8 *%base, i8 %alt, i32 %limit) { define void @f13(i8 *%base, i8 %alt, i32 %limit) { ; CHECK-LABEL: f13: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stcy %r3, 524287(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i8, i8 *%base, i64 524287 %cond = icmp ult i32 %limit, 420 @@ -241,11 +228,10 @@ define void @f13(i8 *%base, i8 %alt, i32 %limit) { define void @f14(i8 *%base, i8 %alt, i32 %limit) { ; CHECK-LABEL: f14: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, 524288 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i8, i8 *%base, i64 524288 %cond = icmp ult i32 %limit, 420 @@ -259,10 +245,9 @@ define void @f14(i8 *%base, i8 %alt, i32 %limit) { define void @f15(i8 *%base, i8 %alt, i32 %limit) { ; CHECK-LABEL: f15: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stcy %r3, -524288(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i8, i8 *%base, i64 -524288 %cond = icmp ult i32 %limit, 420 @@ -277,11 +262,10 @@ define void @f15(i8 *%base, i8 %alt, i32 %limit) { define void @f16(i8 *%base, i8 %alt, i32 %limit) { ; CHECK-LABEL: f16: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, -524289 ; CHECK: stc %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i8, i8 *%base, i64 -524289 %cond = icmp ult i32 %limit, 420 @@ -295,10 +279,9 @@ define void @f16(i8 *%base, i8 %alt, i32 %limit) { define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) { ; CHECK-LABEL: f17: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stcy %r4, 4096(%r3,%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll index 22bdfa3c27dc..5cb024d8b4e8 100644 --- a/test/CodeGen/SystemZ/cond-store-02.ll +++ b/test/CodeGen/SystemZ/cond-store-02.ll @@ -9,10 +9,9 @@ declare void @foo(i16 *) define void @f1(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK-LABEL: f1: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -25,10 +24,9 @@ define void @f1(i16 *%ptr, i16 %alt, i32 %limit) { define void @f2(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK-LABEL: f2: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -42,10 +40,9 @@ define void @f2(i16 *%ptr, i16 %alt, i32 %limit) { define void @f3(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f3: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -60,10 +57,9 @@ define void @f3(i16 *%ptr, i32 %alt, i32 %limit) { define void @f4(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f4: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -79,10 +75,9 @@ define void @f4(i16 *%ptr, i32 %alt, i32 %limit) { define void @f5(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f5: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -97,10 +92,9 @@ define void @f5(i16 *%ptr, i32 %alt, i32 %limit) { define void @f6(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f6: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -116,10 +110,9 @@ define void @f6(i16 *%ptr, i32 %alt, i32 %limit) { define void @f7(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f7: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -134,10 +127,9 @@ define void @f7(i16 *%ptr, i64 %alt, i32 %limit) { define void @f8(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f8: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -153,10 +145,9 @@ define void @f8(i16 *%ptr, i64 %alt, i32 %limit) { define void @f9(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f9: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -171,10 +162,9 @@ define void @f9(i16 *%ptr, i64 %alt, i32 %limit) { define void @f10(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f10: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i16 , i16 *%ptr @@ -189,10 +179,9 @@ define void @f10(i16 *%ptr, i64 %alt, i32 %limit) { define void @f11(i16 *%base, i16 %alt, i32 %limit) { ; CHECK-LABEL: f11: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sth %r3, 4094(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 2047 %cond = icmp ult i32 %limit, 420 @@ -206,10 +195,9 @@ define void @f11(i16 *%base, i16 %alt, i32 %limit) { define void @f12(i16 *%base, i16 %alt, i32 %limit) { ; CHECK-LABEL: f12: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sthy %r3, 4096(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 2048 %cond = icmp ult i32 %limit, 420 @@ -223,10 +211,9 @@ define void @f12(i16 *%base, i16 %alt, i32 %limit) { define void @f13(i16 *%base, i16 %alt, i32 %limit) { ; CHECK-LABEL: f13: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sthy %r3, 524286(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 262143 %cond = icmp ult i32 %limit, 420 @@ -241,11 +228,10 @@ define void @f13(i16 *%base, i16 %alt, i32 %limit) { define void @f14(i16 *%base, i16 %alt, i32 %limit) { ; CHECK-LABEL: f14: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, 524288 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 262144 %cond = icmp ult i32 %limit, 420 @@ -259,10 +245,9 @@ define void @f14(i16 *%base, i16 %alt, i32 %limit) { define void @f15(i16 *%base, i16 %alt, i32 %limit) { ; CHECK-LABEL: f15: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sthy %r3, -524288(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 -262144 %cond = icmp ult i32 %limit, 420 @@ -277,11 +262,10 @@ define void @f15(i16 *%base, i16 %alt, i32 %limit) { define void @f16(i16 *%base, i16 %alt, i32 %limit) { ; CHECK-LABEL: f16: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, -524290 ; CHECK: sth %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 -262145 %cond = icmp ult i32 %limit, 420 @@ -295,10 +279,9 @@ define void @f16(i16 *%base, i16 %alt, i32 %limit) { define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) { ; CHECK-LABEL: f17: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sthy %r4, 4096(%r3,%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll index 7207164a6314..46cdbff312c4 100644 --- a/test/CodeGen/SystemZ/cond-store-03.ll +++ b/test/CodeGen/SystemZ/cond-store-03.ll @@ -8,10 +8,9 @@ declare void @foo(i32 *) define void @f1(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f1: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i32 , i32 *%ptr @@ -24,10 +23,9 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) { define void @f2(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK-LABEL: f2: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i32 , i32 *%ptr @@ -41,10 +39,9 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) { define void @f3(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f3: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i32 , i32 *%ptr @@ -59,10 +56,9 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) { define void @f4(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f4: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i32 , i32 *%ptr @@ -78,10 +74,9 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) { define void @f5(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f5: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i32 , i32 *%ptr @@ -96,10 +91,9 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) { define void @f6(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f6: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i32 , i32 *%ptr @@ -114,10 +108,9 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) { define void @f7(i32 *%base, i32 %alt, i32 %limit) { ; CHECK-LABEL: f7: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: st %r3, 4092(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1023 %cond = icmp ult i32 %limit, 420 @@ -131,10 +124,9 @@ define void @f7(i32 *%base, i32 %alt, i32 %limit) { define void @f8(i32 *%base, i32 %alt, i32 %limit) { ; CHECK-LABEL: f8: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sty %r3, 4096(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1024 %cond = icmp ult i32 %limit, 420 @@ -148,10 +140,9 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) { define void @f9(i32 *%base, i32 %alt, i32 %limit) { ; CHECK-LABEL: f9: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sty %r3, 524284(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131071 %cond = icmp ult i32 %limit, 420 @@ -166,11 +157,10 @@ define void @f9(i32 *%base, i32 %alt, i32 %limit) { define void @f10(i32 *%base, i32 %alt, i32 %limit) { ; CHECK-LABEL: f10: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, 524288 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131072 %cond = icmp ult i32 %limit, 420 @@ -184,10 +174,9 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) { define void @f11(i32 *%base, i32 %alt, i32 %limit) { ; CHECK-LABEL: f11: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sty %r3, -524288(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131072 %cond = icmp ult i32 %limit, 420 @@ -202,11 +191,10 @@ define void @f11(i32 *%base, i32 %alt, i32 %limit) { define void @f12(i32 *%base, i32 %alt, i32 %limit) { ; CHECK-LABEL: f12: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, -524292 ; CHECK: st %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131073 %cond = icmp ult i32 %limit, 420 @@ -220,10 +208,9 @@ define void @f12(i32 *%base, i32 %alt, i32 %limit) { define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) { ; CHECK-LABEL: f13: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: sty %r4, 4096(%r3,%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll index 7e25bb5c14a0..70124f9ecee4 100644 --- a/test/CodeGen/SystemZ/cond-store-04.ll +++ b/test/CodeGen/SystemZ/cond-store-04.ll @@ -8,10 +8,9 @@ declare void @foo(i64 *) define void @f1(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f1: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stg %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i64 , i64 *%ptr @@ -24,10 +23,9 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) { define void @f2(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK-LABEL: f2: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: stg %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load i64 , i64 *%ptr @@ -40,10 +38,9 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) { define void @f3(i64 *%base, i64 %alt, i32 %limit) { ; CHECK-LABEL: f3: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stg %r3, 524280(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 65535 %cond = icmp ult i32 %limit, 420 @@ -58,11 +55,10 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) { define void @f4(i64 *%base, i64 %alt, i32 %limit) { ; CHECK-LABEL: f4: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, 524288 ; CHECK: stg %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 65536 %cond = icmp ult i32 %limit, 420 @@ -76,10 +72,9 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) { define void @f5(i64 *%base, i64 %alt, i32 %limit) { ; CHECK-LABEL: f5: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stg %r3, -524288(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -65536 %cond = icmp ult i32 %limit, 420 @@ -94,11 +89,10 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) { define void @f6(i64 *%base, i64 %alt, i32 %limit) { ; CHECK-LABEL: f6: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, -524296 ; CHECK: stg %r3, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -65537 %cond = icmp ult i32 %limit, 420 @@ -112,10 +106,9 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) { define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) { ; CHECK-LABEL: f7: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stg %r4, 524287(%r3,%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %add1 = add i64 %base, %index %add2 = add i64 %add1, 524287 diff --git a/test/CodeGen/SystemZ/cond-store-05.ll b/test/CodeGen/SystemZ/cond-store-05.ll index 0cc068380e07..51a9f6c42ab0 100644 --- a/test/CodeGen/SystemZ/cond-store-05.ll +++ b/test/CodeGen/SystemZ/cond-store-05.ll @@ -8,10 +8,9 @@ declare void @foo(float *) define void @f1(float *%ptr, float %alt, i32 %limit) { ; CHECK-LABEL: f1: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: ste %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load float , float *%ptr @@ -24,10 +23,9 @@ define void @f1(float *%ptr, float %alt, i32 %limit) { define void @f2(float *%ptr, float %alt, i32 %limit) { ; CHECK-LABEL: f2: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: ste %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load float , float *%ptr @@ -40,10 +38,9 @@ define void @f2(float *%ptr, float %alt, i32 %limit) { define void @f3(float *%base, float %alt, i32 %limit) { ; CHECK-LABEL: f3: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: ste %f0, 4092(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 1023 %cond = icmp ult i32 %limit, 420 @@ -57,10 +54,9 @@ define void @f3(float *%base, float %alt, i32 %limit) { define void @f4(float *%base, float %alt, i32 %limit) { ; CHECK-LABEL: f4: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stey %f0, 4096(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 1024 %cond = icmp ult i32 %limit, 420 @@ -74,10 +70,9 @@ define void @f4(float *%base, float %alt, i32 %limit) { define void @f5(float *%base, float %alt, i32 %limit) { ; CHECK-LABEL: f5: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stey %f0, 524284(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 131071 %cond = icmp ult i32 %limit, 420 @@ -92,11 +87,10 @@ define void @f5(float *%base, float %alt, i32 %limit) { define void @f6(float *%base, float %alt, i32 %limit) { ; CHECK-LABEL: f6: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, 524288 ; CHECK: ste %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 131072 %cond = icmp ult i32 %limit, 420 @@ -110,10 +104,9 @@ define void @f6(float *%base, float %alt, i32 %limit) { define void @f7(float *%base, float %alt, i32 %limit) { ; CHECK-LABEL: f7: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stey %f0, -524288(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 -131072 %cond = icmp ult i32 %limit, 420 @@ -128,11 +121,10 @@ define void @f7(float *%base, float %alt, i32 %limit) { define void @f8(float *%base, float %alt, i32 %limit) { ; CHECK-LABEL: f8: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, -524292 ; CHECK: ste %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 -131073 %cond = icmp ult i32 %limit, 420 @@ -146,10 +138,9 @@ define void @f8(float *%base, float %alt, i32 %limit) { define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) { ; CHECK-LABEL: f9: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stey %f0, 4096(%r3,%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 diff --git a/test/CodeGen/SystemZ/cond-store-06.ll b/test/CodeGen/SystemZ/cond-store-06.ll index 01948b811504..1eac79401bd3 100644 --- a/test/CodeGen/SystemZ/cond-store-06.ll +++ b/test/CodeGen/SystemZ/cond-store-06.ll @@ -8,10 +8,9 @@ declare void @foo(double *) define void @f1(double *%ptr, double %alt, i32 %limit) { ; CHECK-LABEL: f1: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: std %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load double , double *%ptr @@ -24,10 +23,9 @@ define void @f1(double *%ptr, double %alt, i32 %limit) { define void @f2(double *%ptr, double %alt, i32 %limit) { ; CHECK-LABEL: f2: ; CHECK-NOT: %r2 -; CHECK: jhe [[LABEL:[^ ]*]] +; CHECK: bher %r14 ; CHECK-NOT: %r2 ; CHECK: std %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 %orig = load double , double *%ptr @@ -40,10 +38,9 @@ define void @f2(double *%ptr, double %alt, i32 %limit) { define void @f3(double *%base, double %alt, i32 %limit) { ; CHECK-LABEL: f3: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: std %f0, 4088(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr double, double *%base, i64 511 %cond = icmp ult i32 %limit, 420 @@ -57,10 +54,9 @@ define void @f3(double *%base, double %alt, i32 %limit) { define void @f4(double *%base, double %alt, i32 %limit) { ; CHECK-LABEL: f4: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stdy %f0, 4096(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr double, double *%base, i64 512 %cond = icmp ult i32 %limit, 420 @@ -74,10 +70,9 @@ define void @f4(double *%base, double %alt, i32 %limit) { define void @f5(double *%base, double %alt, i32 %limit) { ; CHECK-LABEL: f5: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stdy %f0, 524280(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr double, double *%base, i64 65535 %cond = icmp ult i32 %limit, 420 @@ -92,11 +87,10 @@ define void @f5(double *%base, double %alt, i32 %limit) { define void @f6(double *%base, double %alt, i32 %limit) { ; CHECK-LABEL: f6: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, 524288 ; CHECK: std %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr double, double *%base, i64 65536 %cond = icmp ult i32 %limit, 420 @@ -110,10 +104,9 @@ define void @f6(double *%base, double %alt, i32 %limit) { define void @f7(double *%base, double %alt, i32 %limit) { ; CHECK-LABEL: f7: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stdy %f0, -524288(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr double, double *%base, i64 -65536 %cond = icmp ult i32 %limit, 420 @@ -128,11 +121,10 @@ define void @f7(double *%base, double %alt, i32 %limit) { define void @f8(double *%base, double %alt, i32 %limit) { ; CHECK-LABEL: f8: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: agfi %r2, -524296 ; CHECK: std %f0, 0(%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %ptr = getelementptr double, double *%base, i64 -65537 %cond = icmp ult i32 %limit, 420 @@ -146,10 +138,9 @@ define void @f8(double *%base, double %alt, i32 %limit) { define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) { ; CHECK-LABEL: f9: ; CHECK-NOT: %r2 -; CHECK: jl [[LABEL:[^ ]*]] +; CHECK: blr %r14 ; CHECK-NOT: %r2 ; CHECK: stdy %f0, 524287(%r3,%r2) -; CHECK: [[LABEL]]: ; CHECK: br %r14 %add1 = add i64 %base, %index %add2 = add i64 %add1, 524287 diff --git a/test/CodeGen/SystemZ/dyn-alloca-offset.ll b/test/CodeGen/SystemZ/dyn-alloca-offset.ll new file mode 100644 index 000000000000..b9997ac0ec9e --- /dev/null +++ b/test/CodeGen/SystemZ/dyn-alloca-offset.ll @@ -0,0 +1,42 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i64 @llvm.get.dynamic.area.offset.i64() + +declare void @use(i64) + +define void @f1() { +; CHECK-LABEL: f1 +; CHECK: la %r2, 160 +; CHECK: brasl %r14, use +; CHECK: br %r14 + %tmp = alloca i64, align 32 + %dynamic_area_offset = call i64 @llvm.get.dynamic.area.offset.i64() + call void @use(i64 %dynamic_area_offset) + ret void +} + +define void @f2(i64 %arg) { +; CHECK-LABEL: f2 +; CHECK: la %r2, 160(%r2) +; CHECK: brasl %r14, use +; CHECK: br %r14 + %tmp = alloca i64, align 32 + %dynamic_area_offset = call i64 @llvm.get.dynamic.area.offset.i64() + %param = add i64 %dynamic_area_offset, %arg + call void @use(i64 %param) + ret void +} + +declare void @eatsalot(i64, i64, i64, i64, i64, i64) + +define void @f3() { +; CHECK-LABEL: f3 +; CHECK: la %r2, 168 +; CHECK: brasl %r14, use +; CHECK: br %r14 + %tmp = alloca i64, align 32 + call void @eatsalot(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0) + %dynamic_area_offset = call i64 @llvm.get.dynamic.area.offset.i64() + call void @use(i64 %dynamic_area_offset) + ret void +} diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll index ed58103e59a5..075c7aa3dd84 100644 --- a/test/CodeGen/SystemZ/fp-cmp-01.ll +++ b/test/CodeGen/SystemZ/fp-cmp-01.ll @@ -9,7 +9,7 @@ declare float @foo() define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) { ; CHECK-LABEL: f1: ; CHECK: cebr %f0, %f2 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %cond = fcmp oeq float %f1, %f2 @@ -21,7 +21,7 @@ define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) { define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f2 = load float , float *%ptr @@ -34,7 +34,7 @@ define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) { define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) { ; CHECK-LABEL: f3: ; CHECK: ceb %f0, 4092(%r4) -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 1023 @@ -50,7 +50,7 @@ define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) { ; CHECK-LABEL: f4: ; CHECK: aghi %r4, 4096 ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 1024 @@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) { ; CHECK-LABEL: f5: ; CHECK: aghi %r4, -4 ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %ptr = getelementptr float, float *%base, i64 -1 @@ -80,7 +80,7 @@ define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) { ; CHECK-LABEL: f6: ; CHECK: sllg %r1, %r5, 2 ; CHECK: ceb %f0, 400(%r1,%r4) -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %ptr1 = getelementptr float, float *%base, i64 %index @@ -153,7 +153,7 @@ define float @f7(float *%ptr0) { define i64 @f8(i64 %a, i64 %b, float %f) { ; CHECK-LABEL: f8: ; CHECK: ltebr %f0, %f0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %cond = fcmp oeq float %f, 0.0 @@ -166,7 +166,7 @@ define i64 @f8(i64 %a, i64 %b, float %f) { define i64 @f9(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f9: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: je {{\.L.*}} +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -179,7 +179,7 @@ define i64 @f9(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f10(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f10: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jlh {{\.L.*}} +; CHECK-NEXT: blhr %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -192,7 +192,7 @@ define i64 @f10(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f11(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f11: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -205,7 +205,7 @@ define i64 @f11(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f12(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f12: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jhe {{\.L.*}} +; CHECK-NEXT: bher %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -218,7 +218,7 @@ define i64 @f12(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f13(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f13: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jle {{\.L.*}} +; CHECK-NEXT: bler %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -231,7 +231,7 @@ define i64 @f13(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f14(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f14: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jl {{\.L.*}} +; CHECK-NEXT: blr %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -244,7 +244,7 @@ define i64 @f14(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f15(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f15: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jnlh {{\.L.*}} +; CHECK-NEXT: bnlhr %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -257,7 +257,7 @@ define i64 @f15(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f16(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f16: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jne {{\.L.*}} +; CHECK-NEXT: bner %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -270,7 +270,7 @@ define i64 @f16(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f17(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f17: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jnle {{\.L.*}} +; CHECK-NEXT: bnler %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -283,7 +283,7 @@ define i64 @f17(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f18(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f18: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jnl {{\.L.*}} +; CHECK-NEXT: bnlr %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -296,7 +296,7 @@ define i64 @f18(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f19(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f19: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jnh {{\.L.*}} +; CHECK-NEXT: bnhr %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr @@ -309,7 +309,7 @@ define i64 @f19(i64 %a, i64 %b, float %f2, float *%ptr) { define i64 @f20(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-LABEL: f20: ; CHECK: ceb %f0, 0(%r4) -; CHECK-NEXT: jnhe {{\.L.*}} +; CHECK-NEXT: bnher %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f1 = load float , float *%ptr diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll index 0808ddd8db48..8341f553b895 100644 --- a/test/CodeGen/SystemZ/fp-cmp-02.ll +++ b/test/CodeGen/SystemZ/fp-cmp-02.ll @@ -12,7 +12,7 @@ declare double @foo() define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) { ; CHECK-LABEL: f1: ; CHECK: cdbr %f0, %f2 -; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR-NEXT: ber %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 @@ -25,7 +25,7 @@ define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) { define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cdb %f0, 0(%r4) -; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR-NEXT: ber %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 @@ -39,7 +39,7 @@ define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) { define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) { ; CHECK-LABEL: f3: ; CHECK: cdb %f0, 4088(%r4) -; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR-NEXT: ber %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 @@ -56,7 +56,7 @@ define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) { ; CHECK-LABEL: f4: ; CHECK: aghi %r4, 4096 ; CHECK: cdb %f0, 0(%r4) -; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR-NEXT: ber %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 @@ -72,7 +72,7 @@ define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) { ; CHECK-LABEL: f5: ; CHECK: aghi %r4, -8 ; CHECK: cdb %f0, 0(%r4) -; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR-NEXT: ber %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 @@ -88,7 +88,7 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) { ; CHECK-LABEL: f6: ; CHECK: sllg %r1, %r5, 3 ; CHECK: cdb %f0, 800(%r1,%r4) -; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR-NEXT: ber %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 @@ -162,7 +162,7 @@ define double @f7(double *%ptr0) { define i64 @f8(i64 %a, i64 %b, double %f) { ; CHECK-LABEL: f8: ; CHECK-SCALAR: ltdbr %f0, %f0 -; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR-NEXT: ber %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR: ltdbr %f0, %f0 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3 @@ -176,7 +176,7 @@ define i64 @f8(i64 %a, i64 %b, double %f) { define i64 @f9(i64 %a, i64 %b, double %f2, double *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cdb %f0, 0(%r4) -; CHECK-SCALAR-NEXT: jl +; CHECK-SCALAR-NEXT: blr %r14 ; CHECK-SCALAR: lgr %r2, %r3 ; CHECK-VECTOR-NEXT: locgrnl %r2, %r3 ; CHECK: br %r14 diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll index 862c5e9b65b8..545414005446 100644 --- a/test/CodeGen/SystemZ/fp-cmp-03.ll +++ b/test/CodeGen/SystemZ/fp-cmp-03.ll @@ -10,7 +10,7 @@ define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) { ; CHECK: ld %f1, 0(%r4) ; CHECK: ld %f3, 8(%r4) ; CHECK: cxbr %f1, %f0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f2x = fpext float %f2 to fp128 @@ -26,7 +26,7 @@ define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) { ; CHECK: ld %f0, 0(%r4) ; CHECK: ld %f2, 8(%r4) ; CHECK: ltxbr %f0, %f0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f = load fp128 , fp128 *%ptr diff --git a/test/CodeGen/SystemZ/fp-cmp-04.ll b/test/CodeGen/SystemZ/fp-cmp-04.ll index 05c6dfe7e8e4..17f10456ecb9 100644 --- a/test/CodeGen/SystemZ/fp-cmp-04.ll +++ b/test/CodeGen/SystemZ/fp-cmp-04.ll @@ -9,7 +9,7 @@ declare float @llvm.fabs.f32(float %f) define float @f1(float %a, float %b, float *%dest) { ; CHECK-LABEL: f1: ; CHECK: aebr %f0, %f2 -; CHECK-NEXT: je .L{{.*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %res = fadd float %a, %b @@ -28,7 +28,7 @@ exit: define float @f2(float %a, float %b, float *%dest) { ; CHECK-LABEL: f2: ; CHECK: aebr %f0, %f2 -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = fadd float %a, %b @@ -47,7 +47,7 @@ exit: define float @f3(float %a, float %b, float *%dest) { ; CHECK-LABEL: f3: ; CHECK: aebr %f0, %f2 -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %res = fadd float %a, %b @@ -66,7 +66,7 @@ exit: define float @f4(float %a, float %b, float *%dest) { ; CHECK-LABEL: f4: ; CHECK: aebr %f0, %f2 -; CHECK-NEXT: jnlh .L{{.*}} +; CHECK-NEXT: bnlhr %r14 ; CHECK: br %r14 entry: %res = fadd float %a, %b @@ -85,7 +85,7 @@ exit: define float @f5(float %a, float %b, float *%dest) { ; CHECK-LABEL: f5: ; CHECK: seb %f0, 0(%r2) -; CHECK-NEXT: jnhe .L{{.*}} +; CHECK-NEXT: bnher %r14 ; CHECK: br %r14 entry: %cur = load float , float *%dest @@ -105,7 +105,7 @@ exit: define float @f6(float %dummy, float %a, float *%dest) { ; CHECK-LABEL: f6: ; CHECK: lpebr %f0, %f2 -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %res = call float @llvm.fabs.f32(float %a) @@ -124,7 +124,7 @@ exit: define float @f7(float %dummy, float %a, float *%dest) { ; CHECK-LABEL: f7: ; CHECK: lnebr %f0, %f2 -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %abs = call float @llvm.fabs.f32(float %a) @@ -144,7 +144,7 @@ exit: define float @f8(float %dummy, float %a, float *%dest) { ; CHECK-LABEL: f8: ; CHECK: lcebr %f0, %f2 -; CHECK-NEXT: jle .L{{.*}} +; CHECK-NEXT: bler %r14 ; CHECK: br %r14 entry: %res = fsub float -0.0, %a @@ -164,7 +164,7 @@ define float @f9(float %a, float %b, float *%dest) { ; CHECK-LABEL: f9: ; CHECK: meebr %f0, %f2 ; CHECK-NEXT: ltebr %f0, %f0 -; CHECK-NEXT: jlh .L{{.*}} +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %res = fmul float %a, %b @@ -186,7 +186,7 @@ define float @f10(float %a, float %b, float %c, float *%dest) { ; CHECK: aebr %f0, %f2 ; CHECK-NEXT: debr %f0, %f4 ; CHECK-NEXT: ltebr %f0, %f0 -; CHECK-NEXT: jne .L{{.*}} +; CHECK-NEXT: bner %r14 ; CHECK: br %r14 entry: %add = fadd float %a, %b @@ -210,7 +210,7 @@ define float @f11(float %a, float %b, float %c, float *%dest1, float *%dest2) { ; CHECK-NEXT: sebr %f4, %f0 ; CHECK-NEXT: ste %f4, 0(%r2) ; CHECK-NEXT: ltebr %f0, %f0 -; CHECK-NEXT: je .L{{.*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %add = fadd float %a, %b @@ -234,7 +234,7 @@ define float @f12(float %dummy, float %val, float *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %f0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{f0}"(float %val) @@ -256,7 +256,7 @@ define double @f13(double %dummy, double %val, double *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %f0 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{f0}"(double %val) @@ -281,7 +281,7 @@ define void @f14(fp128 *%ptr1, fp128 *%ptr2) { ; CHECK-NEXT: mxbr ; CHECK-NEXT: std ; CHECK-NEXT: std -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val1 = load fp128 , fp128 *%ptr1 @@ -309,7 +309,7 @@ define float @f15(float %val, float %dummy, float *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %f2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{f2}"(float %val) @@ -332,7 +332,7 @@ define double @f16(double %val, double %dummy, double *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %f2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{f2}"(double %val) @@ -351,7 +351,7 @@ exit: define float @f17(float %a, float %b, float *%dest) { ; CHECK-LABEL: f17: ; CHECK: aebr %f0, %f2 -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = fadd float %a, %b @@ -371,7 +371,7 @@ exit: define float @f18(float %dummy, float %a, float *%dest) { ; CHECK-LABEL: f18: ; CHECK: lnebr %f0, %f2 -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %abs = call float @llvm.fabs.f32(float %a) @@ -391,7 +391,7 @@ exit: define float @f19(float %dummy, float %a, float *%dest) { ; CHECK-LABEL: f19: ; CHECK: lcebr %f0, %f2 -; CHECK-NEXT: jle .L{{.*}} +; CHECK-NEXT: bler %r14 ; CHECK: br %r14 entry: %res = fsub float -0.0, %a diff --git a/test/CodeGen/SystemZ/fp-cmp-05.ll b/test/CodeGen/SystemZ/fp-cmp-05.ll index c8eb18c6e6ba..92b5056cfbbe 100644 --- a/test/CodeGen/SystemZ/fp-cmp-05.ll +++ b/test/CodeGen/SystemZ/fp-cmp-05.ll @@ -10,7 +10,7 @@ define float @f1(float %a, float %b, float %f) { ; CHECK-LABEL: f1: ; CHECK: lcebr -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 %neg = fsub float -0.0, %f %cond = fcmp oeq float %neg, 0.0 %res = select i1 %cond, float %a, float %b @@ -21,7 +21,7 @@ define float @f1(float %a, float %b, float %f) { define double @f2(double %a, double %b, double %f) { ; CHECK-LABEL: f2: ; CHECK: lcdbr -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 %neg = fsub double -0.0, %f %cond = fcmp oeq double %neg, 0.0 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ declare float @llvm.fabs.f32(float %f) define float @f3(float %a, float %b, float %f) { ; CHECK-LABEL: f3: ; CHECK: lnebr -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 %abs = call float @llvm.fabs.f32(float %f) %neg = fsub float -0.0, %abs %cond = fcmp oeq float %neg, 0.0 @@ -47,7 +47,7 @@ declare double @llvm.fabs.f64(double %f) define double @f4(double %a, double %b, double %f) { ; CHECK-LABEL: f4: ; CHECK: lndbr -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 %abs = call double @llvm.fabs.f64(double %f) %neg = fsub double -0.0, %abs %cond = fcmp oeq double %neg, 0.0 @@ -60,7 +60,7 @@ define double @f4(double %a, double %b, double %f) { define float @f5(float %a, float %b, float %f) { ; CHECK-LABEL: f5: ; CHECK: lpebr -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 %abs = call float @llvm.fabs.f32(float %f) %cond = fcmp oeq float %abs, 0.0 %res = select i1 %cond, float %a, float %b @@ -71,7 +71,7 @@ define float @f5(float %a, float %b, float %f) { define double @f6(double %a, double %b, double %f) { ; CHECK-LABEL: f6: ; CHECK: lpdbr -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 %abs = call double @llvm.fabs.f64(double %f) %cond = fcmp oeq double %abs, 0.0 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/fp-copysign-01.ll b/test/CodeGen/SystemZ/fp-copysign-01.ll index 57ad76fcbb2a..321027911abb 100644 --- a/test/CodeGen/SystemZ/fp-copysign-01.ll +++ b/test/CodeGen/SystemZ/fp-copysign-01.ll @@ -11,7 +11,7 @@ declare fp128 @copysignl(fp128, fp128) readnone define float @f1(float %a, float %b) { ; CHECK-LABEL: f1: ; CHECK-NOT: %f2 -; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: cpsdr %f0, %f2, %f0 ; CHECK: br %r14 %res = call float @copysignf(float %a, float %b) readnone ret float %res @@ -21,7 +21,7 @@ define float @f1(float %a, float %b) { define float @f2(float %a, double %bd) { ; CHECK-LABEL: f2: ; CHECK-NOT: %f2 -; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: cpsdr %f0, %f2, %f0 ; CHECK: br %r14 %b = fptrunc double %bd to float %res = call float @copysignf(float %a, float %b) readnone @@ -33,7 +33,7 @@ define float @f3(float %a, fp128 *%bptr) { ; CHECK-LABEL: f3: ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2) ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2) -; CHECK: cpsdr %f0, %f0, [[BHIGH]] +; CHECK: cpsdr %f0, [[BHIGH]], %f0 ; CHECK: br %r14 %bl = load volatile fp128 , fp128 *%bptr %b = fptrunc fp128 %bl to float @@ -45,7 +45,7 @@ define float @f3(float %a, fp128 *%bptr) { define double @f4(double %a, float %bf) { ; CHECK-LABEL: f4: ; CHECK-NOT: %f2 -; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: cpsdr %f0, %f2, %f0 ; CHECK: br %r14 %b = fpext float %bf to double %res = call double @copysign(double %a, double %b) readnone @@ -56,7 +56,7 @@ define double @f4(double %a, float %bf) { define double @f5(double %a, double %b) { ; CHECK-LABEL: f5: ; CHECK-NOT: %f2 -; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: cpsdr %f0, %f2, %f0 ; CHECK: br %r14 %res = call double @copysign(double %a, double %b) readnone ret double %res @@ -67,7 +67,7 @@ define double @f6(double %a, fp128 *%bptr) { ; CHECK-LABEL: f6: ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2) ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2) -; CHECK: cpsdr %f0, %f0, [[BHIGH]] +; CHECK: cpsdr %f0, [[BHIGH]], %f0 ; CHECK: br %r14 %bl = load volatile fp128 , fp128 *%bptr %b = fptrunc fp128 %bl to double @@ -82,7 +82,7 @@ define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) { ; CHECK-LABEL: f7: ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3) ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3) -; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0 +; CHECK: cpsdr [[AHIGH]], %f0, [[AHIGH]] ; CHECK: std [[AHIGH]], 0(%r2) ; CHECK: std [[ALOW]], 8(%r2) ; CHECK: br %r14 @@ -98,7 +98,7 @@ define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) { ; CHECK-LABEL: f8: ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3) ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3) -; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0 +; CHECK: cpsdr [[AHIGH]], %f0, [[AHIGH]] ; CHECK: std [[AHIGH]], 0(%r2) ; CHECK: std [[ALOW]], 8(%r2) ; CHECK: br %r14 @@ -116,7 +116,7 @@ define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) { ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3) ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3) ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r4) -; CHECK: cpsdr [[AHIGH]], [[AHIGH]], [[BHIGH]] +; CHECK: cpsdr [[AHIGH]], [[BHIGH]], [[AHIGH]] ; CHECK: std [[AHIGH]], 0(%r2) ; CHECK: std [[ALOW]], 8(%r2) ; CHECK: br %r14 diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll index 843b1b6a6e64..55c09e5d7796 100644 --- a/test/CodeGen/SystemZ/fp-move-01.ll +++ b/test/CodeGen/SystemZ/fp-move-01.ll @@ -1,7 +1,6 @@ ; Test moves between FPRs. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test f32 moves. define float @f1(float %a, float %b) { diff --git a/test/CodeGen/SystemZ/fp-move-09.ll b/test/CodeGen/SystemZ/fp-move-09.ll index 5e8dce272c23..6cc92eebd2a3 100644 --- a/test/CodeGen/SystemZ/fp-move-09.ll +++ b/test/CodeGen/SystemZ/fp-move-09.ll @@ -32,7 +32,8 @@ define void @f2(float %val, i8 *%ptr) { ; Like f2, but with a conditional store. define void @f3(float %val, i8 *%ptr, i32 %which) { ; CHECK-LABEL: f3: -; CHECK: cijlh %r3, 0, +; CHECK: ciblh %r3, 0, 0(%r14) + ; CHECK: lgdr [[REG:%r[0-5]]], %f0 ; CHECK: stch [[REG]], 0(%r2) ; CHECK: br %r14 @@ -48,7 +49,7 @@ define void @f3(float %val, i8 *%ptr, i32 %which) { ; ...and again with 16-bit memory. define void @f4(float %val, i16 *%ptr, i32 %which) { ; CHECK-LABEL: f4: -; CHECK: cijlh %r3, 0, +; CHECK: ciblh %r3, 0, 0(%r14) ; CHECK: lgdr [[REG:%r[0-5]]], %f0 ; CHECK: sthh [[REG]], 0(%r2) ; CHECK: br %r14 diff --git a/test/CodeGen/SystemZ/fp-move-10.ll b/test/CodeGen/SystemZ/fp-move-10.ll index 602397d58a8d..b7e64042d10a 100644 --- a/test/CodeGen/SystemZ/fp-move-10.ll +++ b/test/CodeGen/SystemZ/fp-move-10.ll @@ -31,7 +31,7 @@ define void @f2(float %val, i8 *%ptr) { ; Like f2, but with a conditional store. define void @f3(float %val, i8 *%ptr, i32 %which) { ; CHECK-LABEL: f3: -; CHECK-DAG: cijlh %r3, 0, +; CHECK-DAG: ciblh %r3, 0, 0(%r14) ; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0 ; CHECK: stc [[REG]], 0(%r2) ; CHECK: br %r14 @@ -47,7 +47,7 @@ define void @f3(float %val, i8 *%ptr, i32 %which) { ; ...and again with 16-bit memory. define void @f4(float %val, i16 *%ptr, i32 %which) { ; CHECK-LABEL: f4: -; CHECK-DAG: cijlh %r3, 0, +; CHECK-DAG: ciblh %r3, 0, 0(%r14) ; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0 ; CHECK: sth [[REG]], 0(%r2) ; CHECK: br %r14 diff --git a/test/CodeGen/SystemZ/fp-move-12.ll b/test/CodeGen/SystemZ/fp-move-12.ll new file mode 100644 index 000000000000..131f7c374ca2 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-12.ll @@ -0,0 +1,33 @@ +; Test moves between FPRs on z13. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test that we use LDR instead of LER. +define float @f1(float %a, float %b) { +; CHECK-LABEL: f1: +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + ret float %b +} + +; Test f64 moves. +define double @f2(double %a, double %b) { +; CHECK-LABEL: f2: +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + ret double %b +} + +; Test f128 moves. Since f128s are passed by reference, we need to force +; a copy by other means. +define void @f3(fp128 *%x) { +; CHECK-LABEL: f3: +; CHECK: lxr +; CHECK: axbr +; CHECK: br %r14 + %val = load volatile fp128 , fp128 *%x + %sum = fadd fp128 %val, %val + store volatile fp128 %sum, fp128 *%x + store volatile fp128 %val, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-sqrt-01.ll b/test/CodeGen/SystemZ/fp-sqrt-01.ll index e8bf65bdc981..3680207e7f20 100644 --- a/test/CodeGen/SystemZ/fp-sqrt-01.ll +++ b/test/CodeGen/SystemZ/fp-sqrt-01.ll @@ -159,9 +159,7 @@ define float @f8(float %dummy, float %val) { ; CHECK-LABEL: f8: ; CHECK: sqebr %f0, %f2 ; CHECK: cebr %f0, %f0 -; CHECK: jo [[LABEL:\.L.*]] -; CHECK: br %r14 -; CHECK: [[LABEL]]: +; CHECK: bnor %r14 ; CHECK: ler %f0, %f2 ; CHECK: jg sqrtf@PLT %res = tail call float @sqrtf(float %val) diff --git a/test/CodeGen/SystemZ/fp-sqrt-02.ll b/test/CodeGen/SystemZ/fp-sqrt-02.ll index a162466064e8..a72629443f6d 100644 --- a/test/CodeGen/SystemZ/fp-sqrt-02.ll +++ b/test/CodeGen/SystemZ/fp-sqrt-02.ll @@ -161,9 +161,7 @@ define double @f8(double %dummy, double %val) { ; CHECK-LABEL: f8: ; CHECK: sqdbr %f0, %f2 ; CHECK: cdbr %f0, %f0 -; CHECK: jo [[LABEL:\.L.*]] -; CHECK: br %r14 -; CHECK: [[LABEL]]: +; CHECK: bnor %r14 ; CHECK: ldr %f0, %f2 ; CHECK: jg sqrt@PLT %res = tail call double @sqrt(double %val) diff --git a/test/CodeGen/SystemZ/frameaddr-01.ll b/test/CodeGen/SystemZ/frameaddr-01.ll new file mode 100644 index 000000000000..4dfdf308e8a6 --- /dev/null +++ b/test/CodeGen/SystemZ/frameaddr-01.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; The current function's frame address is the address of +; the optional back chain slot. +define i8* @fp0() nounwind { +entry: +; CHECK-LABEL: fp0: +; CHECK: la %r2, 0(%r15) +; CHECK: br %r14 + %0 = tail call i8* @llvm.frameaddress(i32 0) + ret i8* %0 +} + +; Check that the frame address is correct in a presence +; of a stack frame. +define i8* @fp0f() nounwind { +entry: +; CHECK-LABEL: fp0f: +; CHECK: aghi %r15, -168 +; CHECK: la %r2, 168(%r15) +; CHECK: aghi %r15, 168 +; CHECK: br %r14 + %0 = alloca i64, align 8 + %1 = tail call i8* @llvm.frameaddress(i32 0) + ret i8* %1 +} + +declare i8* @llvm.frameaddress(i32) nounwind readnone diff --git a/test/CodeGen/SystemZ/htm-intrinsics.ll b/test/CodeGen/SystemZ/htm-intrinsics.ll index 6441ef94b406..107059f5cd83 100644 --- a/test/CodeGen/SystemZ/htm-intrinsics.ll +++ b/test/CodeGen/SystemZ/htm-intrinsics.ll @@ -67,7 +67,7 @@ define void @test_tbegin_nofloat3(i32 *%ptr) { ; CHECK-NOT: stmg ; CHECK-NOT: std ; CHECK: tbegin 0, 65292 -; CHECK: jnh {{\.L*}} +; CHECK: bnhr %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) @@ -90,7 +90,7 @@ define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) { ; CHECK: tbegin 0, 65292 ; CHECK: ipm %r2 ; CHECK: srl %r2, 28 -; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: ciblh %r2, 2, 0(%r14) ; CHECK: mvhi 0(%r3), 0 ; CHECK: br %r14 %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) @@ -198,7 +198,7 @@ define i32 @test_tend1() { define void @test_tend3(i32 *%ptr) { ; CHECK-LABEL: test_tend3: ; CHECK: tend -; CHECK: je {{\.L*}} +; CHECK: ber %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %res = call i32 @llvm.s390.tend() @@ -219,7 +219,7 @@ define i32 @test_tend2(i32 %pad, i32 *%ptr) { ; CHECK: tend ; CHECK: ipm %r2 ; CHECK: srl %r2, 28 -; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: ciblh %r2, 2, 0(%r14) ; CHECK: mvhi 0(%r3), 0 ; CHECK: br %r14 %res = call i32 @llvm.s390.tend() diff --git a/test/CodeGen/SystemZ/int-cmp-01.ll b/test/CodeGen/SystemZ/int-cmp-01.ll index 97b697db3bdb..12060b157fa3 100644 --- a/test/CodeGen/SystemZ/int-cmp-01.ll +++ b/test/CodeGen/SystemZ/int-cmp-01.ll @@ -154,7 +154,7 @@ define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) { define double @f11(double %a, double %b, i32 %rhs, i16 *%src) { ; CHECK-LABEL: f11: ; CHECK: ch %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %half = load i16 , i16 *%src diff --git a/test/CodeGen/SystemZ/int-cmp-02.ll b/test/CodeGen/SystemZ/int-cmp-02.ll index d5aef0f0f977..d3cd7275ec58 100644 --- a/test/CodeGen/SystemZ/int-cmp-02.ll +++ b/test/CodeGen/SystemZ/int-cmp-02.ll @@ -7,7 +7,7 @@ declare i32 @foo() ; Check register comparison. define double @f1(double %a, double %b, i32 %i1, i32 %i2) { ; CHECK-LABEL: f1: -; CHECK: crjl %r2, %r3 +; CHECK: crbl %r2, %r3, 0(%r14) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, %i2 @@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) { define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: c %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = load i32 , i32 *%ptr @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { define double @f3(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f3: ; CHECK: c %r2, 4092(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1023 @@ -46,7 +46,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) { define double @f4(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f4: ; CHECK: cy %r2, 4096(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1024 @@ -60,7 +60,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) { define double @f5(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f5: ; CHECK: cy %r2, 524284(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131071 @@ -76,7 +76,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f6: ; CHECK: agfi %r3, 524288 ; CHECK: c %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131072 @@ -90,7 +90,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) { define double @f7(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f7: ; CHECK: cy %r2, -4(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -1 @@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) { define double @f8(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f8: ; CHECK: cy %r2, -524288(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131072 @@ -120,7 +120,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f9: ; CHECK: agfi %r3, -524292 ; CHECK: c %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131073 @@ -134,7 +134,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) { define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f10: ; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -150,7 +150,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f11: ; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -186,7 +186,7 @@ while.end: define double @f13(double %a, double %b, i32 %i2, i32 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: c %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i1 = load i32 , i32 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-03.ll b/test/CodeGen/SystemZ/int-cmp-03.ll index 0246666f06fe..7a0007e67248 100644 --- a/test/CodeGen/SystemZ/int-cmp-03.ll +++ b/test/CodeGen/SystemZ/int-cmp-03.ll @@ -5,7 +5,7 @@ ; Check register comparison. define double @f1(double %a, double %b, i32 %i1, i32 %i2) { ; CHECK-LABEL: f1: -; CHECK: clrjl %r2, %r3 +; CHECK: clrbl %r2, %r3, 0(%r14) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i32 %i1, %i2 @@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) { define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cl %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = load i32 , i32 *%ptr @@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { define double @f3(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f3: ; CHECK: cl %r2, 4092(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1023 @@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) { define double @f4(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f4: ; CHECK: cly %r2, 4096(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1024 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) { define double @f5(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f5: ; CHECK: cly %r2, 524284(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131071 @@ -74,7 +74,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f6: ; CHECK: agfi %r3, 524288 ; CHECK: cl %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131072 @@ -88,7 +88,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) { define double @f7(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f7: ; CHECK: cly %r2, -4(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -1 @@ -102,7 +102,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) { define double @f8(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f8: ; CHECK: cly %r2, -524288(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131072 @@ -118,7 +118,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f9: ; CHECK: agfi %r3, -524292 ; CHECK: cl %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131073 @@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) { define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f10: ; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -148,7 +148,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f11: ; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -164,7 +164,7 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) { define double @f12(double %a, double %b, i32 %i2, i32 *%ptr) { ; CHECK-LABEL: f12: ; CHECK: cl %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i1 = load i32 , i32 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll index 90f05ea38680..8f3c8031c085 100644 --- a/test/CodeGen/SystemZ/int-cmp-04.ll +++ b/test/CodeGen/SystemZ/int-cmp-04.ll @@ -110,7 +110,7 @@ define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) { define double @f8(double %a, double %b, i64 %rhs, i16 *%src) { ; CHECK-LABEL: f8: ; CHECK: cgh %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %half = load i16 , i16 *%src diff --git a/test/CodeGen/SystemZ/int-cmp-05.ll b/test/CodeGen/SystemZ/int-cmp-05.ll index 70640b607bcd..679dcc8985a3 100644 --- a/test/CodeGen/SystemZ/int-cmp-05.ll +++ b/test/CodeGen/SystemZ/int-cmp-05.ll @@ -8,7 +8,7 @@ declare i64 @foo() define double @f1(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f1: ; CHECK: cgfr %r2, %r3 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = sext i32 %unext to i64 @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i64 %i1, i32 %unext) { define double @f3(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f3: ; CHECK: cgfr %r2, %r3 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = sext i32 %unext to i64 @@ -45,7 +45,7 @@ define double @f3(double %a, double %b, i64 %i1, i32 %unext) { define double @f4(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f4: ; CHECK: cgfr %r2, %r3 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = sext i32 %unext to i64 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i64 %i1, i32 %unext) { define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: cgf %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr @@ -84,7 +84,7 @@ define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) { define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f7: ; CHECK: cgf %r2, 0(%r3) -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr @@ -98,7 +98,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) { define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cgf %r2, 0(%r3) -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr @@ -112,7 +112,7 @@ define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) { define double @f9(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f9: ; CHECK: cgf %r2, 524284(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131071 @@ -129,7 +129,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f10: ; CHECK: agfi %r3, 524288 ; CHECK: cgf %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131072 @@ -144,7 +144,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%base) { define double @f11(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f11: ; CHECK: cgf %r2, -4(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -1 @@ -159,7 +159,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%base) { define double @f12(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f12: ; CHECK: cgf %r2, -524288(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131072 @@ -176,7 +176,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f13: ; CHECK: agfi %r3, -524292 ; CHECK: cgf %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131073 @@ -191,7 +191,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) { define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f14: ; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -295,7 +295,7 @@ define i64 @f15(i32 *%ptr0) { define double @f16(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f16: ; CHECK: cgfr %r2, %r3 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = sext i32 %unext to i64 @@ -308,7 +308,7 @@ define double @f16(double %a, double %b, i64 %i1, i32 %unext) { define double @f17(double %a, double %b, i64 %i2, i32 *%ptr) { ; CHECK-LABEL: f17: ; CHECK: cgf %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-06.ll b/test/CodeGen/SystemZ/int-cmp-06.ll index 16c2ade83553..7b6a9aec6287 100644 --- a/test/CodeGen/SystemZ/int-cmp-06.ll +++ b/test/CodeGen/SystemZ/int-cmp-06.ll @@ -8,7 +8,7 @@ declare i64 @foo() define double @f1(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f1: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = zext i32 %unext to i64 @@ -21,7 +21,7 @@ define double @f1(double %a, double %b, i64 %i1, i32 %unext) { define double @f2(double %a, double %b, i64 %i1, i64 %unext) { ; CHECK-LABEL: f2: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = and i64 %unext, 4294967295 @@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 %unext) { define double @f5(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f5: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = zext i32 %unext to i64 @@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 %unext) { define double @f6(double %a, double %b, i64 %i1, i64 %unext) { ; CHECK-LABEL: f6: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = and i64 %unext, 4294967295 @@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 %unext) { define double @f7(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f7: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = zext i32 %unext to i64 @@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 %unext) { define double @f8(double %a, double %b, i64 %i1, i64 %unext) { ; CHECK-LABEL: f8: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = and i64 %unext, 4294967295 @@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %unext) { define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: clgf %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr @@ -134,7 +134,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) { define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f11: ; CHECK: clgf %r2, 0(%r3) -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr @@ -148,7 +148,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) { define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f12: ; CHECK: clgf %r2, 0(%r3) -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr @@ -162,7 +162,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) { define double @f13(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f13: ; CHECK: clgf %r2, 524284(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131071 @@ -179,7 +179,7 @@ define double @f14(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f14: ; CHECK: agfi %r3, 524288 ; CHECK: clgf %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 131072 @@ -194,7 +194,7 @@ define double @f14(double %a, double %b, i64 %i1, i32 *%base) { define double @f15(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f15: ; CHECK: clgf %r2, -4(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -1 @@ -209,7 +209,7 @@ define double @f15(double %a, double %b, i64 %i1, i32 *%base) { define double @f16(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f16: ; CHECK: clgf %r2, -524288(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131072 @@ -226,7 +226,7 @@ define double @f17(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-LABEL: f17: ; CHECK: agfi %r3, -524292 ; CHECK: clgf %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -131073 @@ -241,7 +241,7 @@ define double @f17(double %a, double %b, i64 %i1, i32 *%base) { define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f18: ; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -345,7 +345,7 @@ define i64 @f19(i32 *%ptr0) { define double @f20(double %a, double %b, i64 %i1, i32 %unext) { ; CHECK-LABEL: f20: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = zext i32 %unext to i64 @@ -358,7 +358,7 @@ define double @f20(double %a, double %b, i64 %i1, i32 %unext) { define double @f21(double %a, double %b, i64 %i1, i64 %unext) { ; CHECK-LABEL: f21: ; CHECK: clgfr %r2, %r3 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = and i64 %unext, 4294967295 @@ -371,7 +371,7 @@ define double @f21(double %a, double %b, i64 %i1, i64 %unext) { define double @f22(double %a, double %b, i64 %i2, i32 *%ptr) { ; CHECK-LABEL: f22: ; CHECK: clgf %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %unext = load i32 , i32 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-07.ll b/test/CodeGen/SystemZ/int-cmp-07.ll index 0a787c9ea01d..8611662190c5 100644 --- a/test/CodeGen/SystemZ/int-cmp-07.ll +++ b/test/CodeGen/SystemZ/int-cmp-07.ll @@ -5,7 +5,7 @@ ; Check CGR. define double @f1(double %a, double %b, i64 %i1, i64 %i2) { ; CHECK-LABEL: f1: -; CHECK: cgrjl %r2, %r3 +; CHECK: cgrbl %r2, %r3, 0(%r14) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, %i2 @@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) { define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cg %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = load i64 , i64 *%ptr @@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { define double @f3(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f3: ; CHECK: cg %r2, 524280(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 65535 @@ -46,7 +46,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f4: ; CHECK: agfi %r3, 524288 ; CHECK: cg %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 65536 @@ -60,7 +60,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) { define double @f5(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f5: ; CHECK: cg %r2, -8(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -1 @@ -74,7 +74,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) { define double @f6(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f6: ; CHECK: cg %r2, -524288(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -65536 @@ -90,7 +90,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f7: ; CHECK: agfi %r3, -524296 ; CHECK: cg %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -65537 @@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) { define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f8: ; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -120,7 +120,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cg %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i1 = load i64 , i64 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-08.ll b/test/CodeGen/SystemZ/int-cmp-08.ll index 384b41b549b9..fc60993df0e8 100644 --- a/test/CodeGen/SystemZ/int-cmp-08.ll +++ b/test/CodeGen/SystemZ/int-cmp-08.ll @@ -5,7 +5,7 @@ ; Check CLGR. define double @f1(double %a, double %b, i64 %i1, i64 %i2) { ; CHECK-LABEL: f1: -; CHECK: clgrjl %r2, %r3 +; CHECK: clgrbl %r2, %r3, 0(%r14) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i64 %i1, %i2 @@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) { define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clg %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i2 = load i64 , i64 *%ptr @@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { define double @f3(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f3: ; CHECK: clg %r2, 524280(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 65535 @@ -46,7 +46,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f4: ; CHECK: agfi %r3, 524288 ; CHECK: clg %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 65536 @@ -60,7 +60,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) { define double @f5(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f5: ; CHECK: clg %r2, -8(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -1 @@ -74,7 +74,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) { define double @f6(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f6: ; CHECK: clg %r2, -524288(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -65536 @@ -90,7 +90,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f7: ; CHECK: agfi %r3, -524296 ; CHECK: clg %r2, 0(%r3) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -65537 @@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) { define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { ; CHECK-LABEL: f8: ; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}}) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add1 = add i64 %base, %index @@ -120,7 +120,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: clg %r2, 0(%r3) -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %i1 = load i64 , i64 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-09.ll b/test/CodeGen/SystemZ/int-cmp-09.ll index 0eb8c6688c0c..cd0ace2a9a94 100644 --- a/test/CodeGen/SystemZ/int-cmp-09.ll +++ b/test/CodeGen/SystemZ/int-cmp-09.ll @@ -9,7 +9,8 @@ define double @f1(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, 0 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -20,7 +21,8 @@ define double @f2(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, 2 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -31,7 +33,8 @@ define double @f3(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, 127 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -43,7 +46,8 @@ define double @f4(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, 128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -55,7 +59,8 @@ define double @f5(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, 32767 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -67,7 +72,8 @@ define double @f6(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, 32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -79,7 +85,8 @@ define double @f7(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i32 %i1, 2147483647 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -91,7 +98,8 @@ define double @f8(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i32 %i1, 2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -102,7 +110,8 @@ define double @f9(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, -1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -113,7 +122,8 @@ define double @f10(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, -128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -125,7 +135,8 @@ define double @f11(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, -129 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -137,7 +148,8 @@ define double @f12(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, -32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -149,7 +161,8 @@ define double @f13(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, -32769 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -161,7 +174,8 @@ define double @f14(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i32 %i1, -2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -173,7 +187,8 @@ define double @f15(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i32 %i1, -2147483649 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -184,7 +199,8 @@ define double @f16(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i32 %i1, 1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -195,7 +211,8 @@ define double @f17(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp sge i32 %i1, 1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -206,7 +223,8 @@ define double @f18(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp sgt i32 %i1, -1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -217,6 +235,7 @@ define double @f19(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp sle i32 %i1, -1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } diff --git a/test/CodeGen/SystemZ/int-cmp-10.ll b/test/CodeGen/SystemZ/int-cmp-10.ll index 4d4c4bbd20d1..e2a0c1aa6948 100644 --- a/test/CodeGen/SystemZ/int-cmp-10.ll +++ b/test/CodeGen/SystemZ/int-cmp-10.ll @@ -10,7 +10,8 @@ define double @f1(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ugt i32 %i1, 1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -21,7 +22,8 @@ define double @f2(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i32 %i1, 255 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -33,7 +35,8 @@ define double @f3(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i32 %i1, 256 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -45,6 +48,7 @@ define double @f4(double %a, double %b, i32 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i32 %i1, 4294967280 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } diff --git a/test/CodeGen/SystemZ/int-cmp-11.ll b/test/CodeGen/SystemZ/int-cmp-11.ll index c74135a5d393..8fd9d8c3d479 100644 --- a/test/CodeGen/SystemZ/int-cmp-11.ll +++ b/test/CodeGen/SystemZ/int-cmp-11.ll @@ -9,7 +9,8 @@ define double @f1(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 0 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -20,7 +21,8 @@ define double @f2(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -31,7 +33,8 @@ define double @f3(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 127 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -43,7 +46,8 @@ define double @f4(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -55,7 +59,8 @@ define double @f5(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 32767 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -67,7 +72,8 @@ define double @f6(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -79,7 +85,8 @@ define double @f7(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 2147483647 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -90,7 +97,8 @@ define double @f8(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, 2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -101,7 +109,8 @@ define double @f9(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, -1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -112,7 +121,8 @@ define double @f10(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, -128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -124,7 +134,8 @@ define double @f11(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, -129 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -136,7 +147,8 @@ define double @f12(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, -32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -148,7 +160,8 @@ define double @f13(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, -32769 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -160,7 +173,8 @@ define double @f14(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, -2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -171,6 +185,7 @@ define double @f15(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp slt i64 %i1, -2147483649 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } diff --git a/test/CodeGen/SystemZ/int-cmp-12.ll b/test/CodeGen/SystemZ/int-cmp-12.ll index d9c6a9fc4efc..3d5b5749aea8 100644 --- a/test/CodeGen/SystemZ/int-cmp-12.ll +++ b/test/CodeGen/SystemZ/int-cmp-12.ll @@ -10,7 +10,8 @@ define double @f1(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ugt i64 %i1, 1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -21,7 +22,8 @@ define double @f2(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i64 %i1, 255 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -33,7 +35,8 @@ define double @f3(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i64 %i1, 256 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -45,7 +48,8 @@ define double @f4(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i64 %i1, 4294967295 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -57,7 +61,8 @@ define double @f5(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i64 %i1, 4294967296 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } ; Check the next value up, which must use a register comparison. @@ -67,6 +72,7 @@ define double @f6(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i64 %i1, 4294967297 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } diff --git a/test/CodeGen/SystemZ/int-cmp-13.ll b/test/CodeGen/SystemZ/int-cmp-13.ll index 53af0c868a25..fda4496a961a 100644 --- a/test/CodeGen/SystemZ/int-cmp-13.ll +++ b/test/CodeGen/SystemZ/int-cmp-13.ll @@ -9,7 +9,8 @@ define double @f1(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 0 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -20,7 +21,8 @@ define double @f2(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 127 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -32,7 +34,8 @@ define double @f3(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -44,7 +47,8 @@ define double @f4(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 32767 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -56,7 +60,8 @@ define double @f5(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -68,7 +73,8 @@ define double @f6(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 2147483647 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -80,7 +86,8 @@ define double @f7(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -92,7 +99,8 @@ define double @f8(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 4294967295 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -103,7 +111,8 @@ define double @f9(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, 4294967296 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -114,7 +123,8 @@ define double @f10(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, -1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -125,7 +135,8 @@ define double @f11(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, -128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -137,7 +148,8 @@ define double @f12(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, -129 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -149,7 +161,8 @@ define double @f13(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, -32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -161,7 +174,8 @@ define double @f14(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, -32769 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -173,7 +187,8 @@ define double @f15(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, -2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -184,6 +199,7 @@ define double @f16(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp eq i64 %i1, -2147483649 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } diff --git a/test/CodeGen/SystemZ/int-cmp-14.ll b/test/CodeGen/SystemZ/int-cmp-14.ll index 4dbd0ece3af6..d63aaa333889 100644 --- a/test/CodeGen/SystemZ/int-cmp-14.ll +++ b/test/CodeGen/SystemZ/int-cmp-14.ll @@ -9,7 +9,8 @@ define double @f1(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 0 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -20,7 +21,8 @@ define double @f2(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 127 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -32,7 +34,8 @@ define double @f3(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -44,7 +47,8 @@ define double @f4(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 32767 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -56,7 +60,8 @@ define double @f5(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -68,7 +73,8 @@ define double @f6(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 2147483647 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -80,7 +86,8 @@ define double @f7(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -92,7 +99,8 @@ define double @f8(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 4294967295 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -103,7 +111,8 @@ define double @f9(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, 4294967296 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -114,7 +123,8 @@ define double @f10(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, -1 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -125,7 +135,8 @@ define double @f11(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, -128 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -137,7 +148,8 @@ define double @f12(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, -129 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -149,7 +161,8 @@ define double @f13(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, -32768 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -161,7 +174,8 @@ define double @f14(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, -32769 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -173,7 +187,8 @@ define double @f15(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, -2147483648 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } @@ -184,6 +199,7 @@ define double @f16(double %a, double %b, i64 %i1) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ne i64 %i1, -2147483649 - %res = select i1 %cond, double %a, double %b + %tmp = select i1 %cond, double %a, double %b + %res = fadd double %tmp, 1.0 ret double %res } diff --git a/test/CodeGen/SystemZ/int-cmp-15.ll b/test/CodeGen/SystemZ/int-cmp-15.ll index 3c1e052bc35f..a8a391b62cfc 100644 --- a/test/CodeGen/SystemZ/int-cmp-15.ll +++ b/test/CodeGen/SystemZ/int-cmp-15.ll @@ -6,7 +6,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cli 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp ugt i8 %val, 1 @@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cli 0(%r2), 254 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 254 @@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp slt i8 %val, 0 @@ -42,7 +42,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp sle i8 %val, -1 @@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp sge i8 %val, 0 @@ -66,7 +66,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp sgt i8 %val, -1 @@ -78,7 +78,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, -128 @@ -90,7 +90,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, 0 @@ -102,7 +102,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, 127 @@ -114,7 +114,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, 255 diff --git a/test/CodeGen/SystemZ/int-cmp-16.ll b/test/CodeGen/SystemZ/int-cmp-16.ll index 37508b5e740f..78ac8ca4e710 100644 --- a/test/CodeGen/SystemZ/int-cmp-16.ll +++ b/test/CodeGen/SystemZ/int-cmp-16.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 diff --git a/test/CodeGen/SystemZ/int-cmp-17.ll b/test/CodeGen/SystemZ/int-cmp-17.ll index a22fb604d453..c58af56ce8da 100644 --- a/test/CodeGen/SystemZ/int-cmp-17.ll +++ b/test/CodeGen/SystemZ/int-cmp-17.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 diff --git a/test/CodeGen/SystemZ/int-cmp-18.ll b/test/CodeGen/SystemZ/int-cmp-18.ll index f4bc5c0e5ce9..547645c1aa6b 100644 --- a/test/CodeGen/SystemZ/int-cmp-18.ll +++ b/test/CodeGen/SystemZ/int-cmp-18.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 diff --git a/test/CodeGen/SystemZ/int-cmp-19.ll b/test/CodeGen/SystemZ/int-cmp-19.ll index 0a23f06a0581..2a6a97919940 100644 --- a/test/CodeGen/SystemZ/int-cmp-19.ll +++ b/test/CodeGen/SystemZ/int-cmp-19.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: cli 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cli 0(%r2), 255 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 diff --git a/test/CodeGen/SystemZ/int-cmp-20.ll b/test/CodeGen/SystemZ/int-cmp-20.ll index 2acff55af59c..55f7efc08a19 100644 --- a/test/CodeGen/SystemZ/int-cmp-20.ll +++ b/test/CodeGen/SystemZ/int-cmp-20.ll @@ -8,7 +8,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cli 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -22,7 +22,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cli 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -36,7 +36,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: cli 0(%r2), 254 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -50,7 +50,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: cli 0(%r2), 254 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -105,7 +105,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cli 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: cli 0(%r2), 254 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 @@ -171,7 +171,7 @@ define double @f12(double %a, double %b, i8 *%ptr) { define double @f13(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -184,7 +184,7 @@ define double @f13(double %a, double %b, i8 *%ptr) { define double @f14(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f14: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -197,7 +197,7 @@ define double @f14(double %a, double %b, i8 *%ptr) { define double @f15(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f15: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 @@ -210,7 +210,7 @@ define double @f15(double %a, double %b, i8 *%ptr) { define double @f16(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f16: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 diff --git a/test/CodeGen/SystemZ/int-cmp-21.ll b/test/CodeGen/SystemZ/int-cmp-21.ll index 5be97324f643..4ba63a02d594 100644 --- a/test/CodeGen/SystemZ/int-cmp-21.ll +++ b/test/CodeGen/SystemZ/int-cmp-21.ll @@ -8,7 +8,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cli 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -22,7 +22,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cli 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -36,7 +36,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: cli 0(%r2), 254 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -50,7 +50,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: cli 0(%r2), 254 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -105,7 +105,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cli 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: cli 0(%r2), 254 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 @@ -171,7 +171,7 @@ define double @f12(double %a, double %b, i8 *%ptr) { define double @f13(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -184,7 +184,7 @@ define double @f13(double %a, double %b, i8 *%ptr) { define double @f14(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f14: ; CHECK: cli 0(%r2), 128 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -197,7 +197,7 @@ define double @f14(double %a, double %b, i8 *%ptr) { define double @f15(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f15: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 @@ -210,7 +210,7 @@ define double @f15(double %a, double %b, i8 *%ptr) { define double @f16(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f16: ; CHECK: cli 0(%r2), 127 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 diff --git a/test/CodeGen/SystemZ/int-cmp-22.ll b/test/CodeGen/SystemZ/int-cmp-22.ll index f29023cf02ae..47372658165e 100644 --- a/test/CodeGen/SystemZ/int-cmp-22.ll +++ b/test/CodeGen/SystemZ/int-cmp-22.ll @@ -6,7 +6,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: chhsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: chhsi 0(%r2), 0 -; CHECK-NEXT: jle +; CHECK-NEXT: bler %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: chhsi 0(%r2), 32766 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -45,7 +45,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: chhsi 0(%r2), -1 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: chhsi 0(%r2), -32766 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { define double @f6(double %a, double %b, i16 %i1, i16 *%base) { ; CHECK-LABEL: f6: ; CHECK: chhsi 4094(%r3), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 2047 @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%base) { ; CHECK-LABEL: f7: ; CHECK: aghi %r2, 4096 ; CHECK: chhsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 2048 @@ -101,7 +101,7 @@ define double @f8(double %a, double %b, i16 *%base) { ; CHECK-LABEL: f8: ; CHECK: aghi %r2, -2 ; CHECK: chhsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 -1 @@ -116,7 +116,7 @@ define double @f9(double %a, double %b, i64 %base, i64 %index) { ; CHECK-LABEL: f9: ; CHECK: agr {{%r2, %r3|%r3, %r2}} ; CHECK: chhsi 0({{%r[23]}}), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add = add i64 %base, %index diff --git a/test/CodeGen/SystemZ/int-cmp-23.ll b/test/CodeGen/SystemZ/int-cmp-23.ll index df6b62616a79..a1126e13ca98 100644 --- a/test/CodeGen/SystemZ/int-cmp-23.ll +++ b/test/CodeGen/SystemZ/int-cmp-23.ll @@ -6,7 +6,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 65534 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { define double @f3(double %a, double %b, i16 %i1, i16 *%base) { ; CHECK-LABEL: f3: ; CHECK: clhhsi 4094(%r3), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 2047 @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%base) { ; CHECK-LABEL: f4: ; CHECK: aghi %r2, 4096 ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 2048 @@ -62,7 +62,7 @@ define double @f5(double %a, double %b, i16 *%base) { ; CHECK-LABEL: f5: ; CHECK: aghi %r2, -2 ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i16, i16 *%base, i64 -1 @@ -77,7 +77,7 @@ define double @f6(double %a, double %b, i64 %base, i64 %index) { ; CHECK-LABEL: f6: ; CHECK: agr {{%r2, %r3|%r3, %r2}} ; CHECK: clhhsi 0({{%r[23]}}), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add = add i64 %base, %index diff --git a/test/CodeGen/SystemZ/int-cmp-24.ll b/test/CodeGen/SystemZ/int-cmp-24.ll index e1141a78ddda..d7bfeb270f37 100644 --- a/test/CodeGen/SystemZ/int-cmp-24.ll +++ b/test/CodeGen/SystemZ/int-cmp-24.ll @@ -6,7 +6,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: clhhsi 0(%r2), 32768 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -45,7 +45,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: clhhsi 0(%r2), 32767 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-25.ll b/test/CodeGen/SystemZ/int-cmp-25.ll index 268530316506..4da5fd8e0381 100644 --- a/test/CodeGen/SystemZ/int-cmp-25.ll +++ b/test/CodeGen/SystemZ/int-cmp-25.ll @@ -6,7 +6,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: clhhsi 0(%r2), 32768 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr @@ -45,7 +45,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: clhhsi 0(%r2), 32767 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i16 , i16 *%ptr diff --git a/test/CodeGen/SystemZ/int-cmp-26.ll b/test/CodeGen/SystemZ/int-cmp-26.ll index ba93f081e9b9..e280c7f6c03a 100644 --- a/test/CodeGen/SystemZ/int-cmp-26.ll +++ b/test/CodeGen/SystemZ/int-cmp-26.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: clhhsi 0(%r2), 32767 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: clhhsi 0(%r2), 32768 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 diff --git a/test/CodeGen/SystemZ/int-cmp-27.ll b/test/CodeGen/SystemZ/int-cmp-27.ll index 9a503c9254a2..afbdbaf45f24 100644 --- a/test/CodeGen/SystemZ/int-cmp-27.ll +++ b/test/CodeGen/SystemZ/int-cmp-27.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: clhhsi 0(%r2), 32767 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: clhhsi 0(%r2), 32768 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 diff --git a/test/CodeGen/SystemZ/int-cmp-28.ll b/test/CodeGen/SystemZ/int-cmp-28.ll index 68f1cd28c62d..3fbfb1f679ed 100644 --- a/test/CodeGen/SystemZ/int-cmp-28.ll +++ b/test/CodeGen/SystemZ/int-cmp-28.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: clhhsi 0(%r2), 32767 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: clhhsi 0(%r2), 32768 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 diff --git a/test/CodeGen/SystemZ/int-cmp-29.ll b/test/CodeGen/SystemZ/int-cmp-29.ll index 4fb2e8577699..e90f434ec744 100644 --- a/test/CodeGen/SystemZ/int-cmp-29.ll +++ b/test/CodeGen/SystemZ/int-cmp-29.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: clhhsi 0(%r2), 0 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: clhhsi 0(%r2), 32767 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -97,7 +97,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: clhhsi 0(%r2), 65535 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: clhhsi 0(%r2), 32768 -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 diff --git a/test/CodeGen/SystemZ/int-cmp-30.ll b/test/CodeGen/SystemZ/int-cmp-30.ll index 043ff484c145..bac0fe516959 100644 --- a/test/CodeGen/SystemZ/int-cmp-30.ll +++ b/test/CodeGen/SystemZ/int-cmp-30.ll @@ -8,7 +8,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -22,7 +22,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -36,7 +36,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: clhhsi 0(%r2), 65534 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -50,7 +50,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: clhhsi 0(%r2), 65534 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -106,7 +106,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -120,7 +120,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: chhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -134,7 +134,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: clhhsi 0(%r2), 65534 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 @@ -148,7 +148,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { define double @f11(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f11: ; CHECK: chhsi 0(%r2), -2 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -175,7 +175,7 @@ define double @f12(double %a, double %b, i16 *%ptr) { define double @f13(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: chhsi 0(%r2), 32766 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 @@ -202,7 +202,7 @@ define double @f14(double %a, double %b, i16 *%ptr) { define double @f15(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f15: ; CHECK: chhsi 0(%r2), -32767 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 diff --git a/test/CodeGen/SystemZ/int-cmp-31.ll b/test/CodeGen/SystemZ/int-cmp-31.ll index 298b446e7f1d..45c5c789dd50 100644 --- a/test/CodeGen/SystemZ/int-cmp-31.ll +++ b/test/CodeGen/SystemZ/int-cmp-31.ll @@ -8,7 +8,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -22,7 +22,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -36,7 +36,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: clhhsi 0(%r2), 65534 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -50,7 +50,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: clhhsi 0(%r2), 65534 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -106,7 +106,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: clhhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -120,7 +120,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: chhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -134,7 +134,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: clhhsi 0(%r2), 65534 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 @@ -148,7 +148,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { define double @f11(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f11: ; CHECK: chhsi 0(%r2), -2 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -175,7 +175,7 @@ define double @f12(double %a, double %b, i16 *%ptr) { define double @f13(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: chhsi 0(%r2), 32766 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 @@ -202,7 +202,7 @@ define double @f14(double %a, double %b, i16 *%ptr) { define double @f15(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f15: ; CHECK: chhsi 0(%r2), -32767 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 diff --git a/test/CodeGen/SystemZ/int-cmp-32.ll b/test/CodeGen/SystemZ/int-cmp-32.ll index da0e2d7562dd..dae09b446651 100644 --- a/test/CodeGen/SystemZ/int-cmp-32.ll +++ b/test/CodeGen/SystemZ/int-cmp-32.ll @@ -6,7 +6,7 @@ define double @f1(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: chsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i32 *%ptr) { define double @f2(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: chsi 0(%r2), 0 -; CHECK-NEXT: jle +; CHECK-NEXT: bler %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i32 *%ptr) { define double @f3(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: chsi 0(%r2), 32767 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i32 *%ptr) { define double @f5(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: chsi 0(%r2), -1 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i32 *%ptr) { define double @f6(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: chsi 0(%r2), -32768 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i32 *%ptr) { define double @f8(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: chsi 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -106,7 +106,7 @@ define double @f8(double %a, double %b, i32 *%ptr) { define double @f9(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: chsi 0(%r2), 1 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -119,7 +119,7 @@ define double @f9(double %a, double %b, i32 *%ptr) { define double @f10(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: chsi 0(%r2), 32767 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -143,7 +143,7 @@ define double @f11(double %a, double %b, i32 *%ptr) { define double @f12(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f12: ; CHECK: chsi 0(%r2), -1 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -156,7 +156,7 @@ define double @f12(double %a, double %b, i32 *%ptr) { define double @f13(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: chsi 0(%r2), -32768 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -180,7 +180,7 @@ define double @f14(double %a, double %b, i32 *%ptr) { define double @f15(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f15: ; CHECK: chsi 4092(%r3), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1023 @@ -195,7 +195,7 @@ define double @f16(double %a, double %b, i32 *%base) { ; CHECK-LABEL: f16: ; CHECK: aghi %r2, 4096 ; CHECK: chsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1024 @@ -210,7 +210,7 @@ define double @f17(double %a, double %b, i32 *%base) { ; CHECK-LABEL: f17: ; CHECK: aghi %r2, -4 ; CHECK: chsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -1 @@ -225,7 +225,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) { ; CHECK-LABEL: f18: ; CHECK: agr {{%r2, %r3|%r3, %r2}} ; CHECK: chsi 0({{%r[23]}}), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add = add i64 %base, %index diff --git a/test/CodeGen/SystemZ/int-cmp-33.ll b/test/CodeGen/SystemZ/int-cmp-33.ll index 94f3e705391e..ec02147ee525 100644 --- a/test/CodeGen/SystemZ/int-cmp-33.ll +++ b/test/CodeGen/SystemZ/int-cmp-33.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clfhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i32 *%ptr) { define double @f2(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clfhsi 0(%r2), 65535 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -45,7 +45,7 @@ define double @f3(double %a, double %b, i32 *%ptr) { define double @f4(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: clfhsi 0(%r2), 32768 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i32 *%ptr) { define double @f5(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: clfhsi 0(%r2), 65535 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i32 , i32 *%ptr @@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i32 *%ptr) { define double @f7(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-LABEL: f7: ; CHECK: clfhsi 4092(%r3), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1023 @@ -97,7 +97,7 @@ define double @f8(double %a, double %b, i32 *%base) { ; CHECK-LABEL: f8: ; CHECK: aghi %r2, 4096 ; CHECK: clfhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 1024 @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i32 *%base) { ; CHECK-LABEL: f9: ; CHECK: aghi %r2, -4 ; CHECK: clfhsi 0(%r2), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i32, i32 *%base, i64 -1 @@ -127,7 +127,7 @@ define double @f10(double %a, double %b, i64 %base, i64 %index) { ; CHECK-LABEL: f10: ; CHECK: agr {{%r2, %r3|%r3, %r2}} ; CHECK: clfhsi 0({{%r[23]}}), 1 -; CHECK-NEXT: jh +; CHECK-NEXT: bhr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add = add i64 %base, %index diff --git a/test/CodeGen/SystemZ/int-cmp-34.ll b/test/CodeGen/SystemZ/int-cmp-34.ll index 114b694a3b09..2dbc04e4ec0c 100644 --- a/test/CodeGen/SystemZ/int-cmp-34.ll +++ b/test/CodeGen/SystemZ/int-cmp-34.ll @@ -6,7 +6,7 @@ define double @f1(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: cghsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i64 *%ptr) { define double @f2(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cghsi 0(%r2), 0 -; CHECK-NEXT: jle +; CHECK-NEXT: bler %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i64 *%ptr) { define double @f3(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: cghsi 0(%r2), 32767 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i64 *%ptr) { define double @f5(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: cghsi 0(%r2), -1 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i64 *%ptr) { define double @f6(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: cghsi 0(%r2), -32768 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i64 *%ptr) { define double @f8(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: cghsi 0(%r2), 0 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -106,7 +106,7 @@ define double @f8(double %a, double %b, i64 *%ptr) { define double @f9(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cghsi 0(%r2), 1 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -119,7 +119,7 @@ define double @f9(double %a, double %b, i64 *%ptr) { define double @f10(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: cghsi 0(%r2), 32767 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -143,7 +143,7 @@ define double @f11(double %a, double %b, i64 *%ptr) { define double @f12(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f12: ; CHECK: cghsi 0(%r2), -1 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -156,7 +156,7 @@ define double @f12(double %a, double %b, i64 *%ptr) { define double @f13(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: cghsi 0(%r2), -32768 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -180,7 +180,7 @@ define double @f14(double %a, double %b, i64 *%ptr) { define double @f15(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f15: ; CHECK: cghsi 4088(%r3), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 511 @@ -195,7 +195,7 @@ define double @f16(double %a, double %b, i64 *%base) { ; CHECK-LABEL: f16: ; CHECK: aghi %r2, 4096 ; CHECK: cghsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 512 @@ -210,7 +210,7 @@ define double @f17(double %a, double %b, i64 *%base) { ; CHECK-LABEL: f17: ; CHECK: aghi %r2, -8 ; CHECK: cghsi 0(%r2), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -1 @@ -225,7 +225,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) { ; CHECK-LABEL: f18: ; CHECK: agr {{%r2, %r3|%r3, %r2}} ; CHECK: cghsi 0({{%r[23]}}), 0 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add = add i64 %base, %index diff --git a/test/CodeGen/SystemZ/int-cmp-35.ll b/test/CodeGen/SystemZ/int-cmp-35.ll index 0eaf4fa0a075..de362af2bea2 100644 --- a/test/CodeGen/SystemZ/int-cmp-35.ll +++ b/test/CodeGen/SystemZ/int-cmp-35.ll @@ -7,7 +7,7 @@ define double @f1(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: clghsi 0(%r2), 2 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i64 *%ptr) { define double @f2(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: clghsi 0(%r2), 65535 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -45,7 +45,7 @@ define double @f3(double %a, double %b, i64 *%ptr) { define double @f4(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: clghsi 0(%r2), 32768 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i64 *%ptr) { define double @f5(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: clghsi 0(%r2), 65535 -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %val = load i64 , i64 *%ptr @@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i64 *%ptr) { define double @f7(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-LABEL: f7: ; CHECK: clghsi 4088(%r3), 2 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 511 @@ -97,7 +97,7 @@ define double @f8(double %a, double %b, i64 *%base) { ; CHECK-LABEL: f8: ; CHECK: aghi %r2, 4096 ; CHECK: clghsi 0(%r2), 2 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 512 @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i64 *%base) { ; CHECK-LABEL: f9: ; CHECK: aghi %r2, -8 ; CHECK: clghsi 0(%r2), 2 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %ptr = getelementptr i64, i64 *%base, i64 -1 @@ -127,7 +127,7 @@ define double @f10(double %a, double %b, i64 %base, i64 %index) { ; CHECK-LABEL: f10: ; CHECK: agr {{%r2, %r3|%r3, %r2}} ; CHECK: clghsi 0({{%r[23]}}), 2 -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %add = add i64 %base, %index diff --git a/test/CodeGen/SystemZ/int-cmp-36.ll b/test/CodeGen/SystemZ/int-cmp-36.ll index 113d2c1587e0..b17fedd03db2 100644 --- a/test/CodeGen/SystemZ/int-cmp-36.ll +++ b/test/CodeGen/SystemZ/int-cmp-36.ll @@ -10,7 +10,7 @@ define i32 @f1(i32 %src1) { ; CHECK-LABEL: f1: ; CHECK: chrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g @@ -47,7 +47,7 @@ exit: define i32 @f3(i32 %src1) { ; CHECK-LABEL: f3: ; CHECK: chrl %r2, g -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g @@ -66,7 +66,7 @@ exit: define i32 @f4(i32 %src1) { ; CHECK-LABEL: f4: ; CHECK: chrl %r2, g -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g @@ -86,7 +86,7 @@ define i32 @f5(i32 %src1) { ; CHECK-LABEL: f5: ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT ; CHECK: ch %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@h, align 1 @@ -105,7 +105,7 @@ exit: define i32 @f6(i32 %src2) { ; CHECK-LABEL: f6: ; CHECK: chrl %r2, g -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll index ac5d39f96511..aabb8a2fd3e3 100644 --- a/test/CodeGen/SystemZ/int-cmp-37.ll +++ b/test/CodeGen/SystemZ/int-cmp-37.ll @@ -21,7 +21,8 @@ mulb: %mul = mul i32 %src1, %src1 br label %exit exit: - %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i32 %tmp, 1 ret i32 %res } @@ -39,7 +40,8 @@ mulb: %mul = mul i32 %src1, %src1 br label %exit exit: - %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i32 %tmp, 1 ret i32 %res } @@ -58,7 +60,8 @@ mulb: %mul = mul i32 %src1, %src1 br label %exit exit: - %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i32 %tmp, 1 ret i32 %res } @@ -77,7 +80,8 @@ mulb: %mul = mul i32 %src1, %src1 br label %exit exit: - %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i32 %tmp, 1 ret i32 %res } @@ -97,7 +101,8 @@ mulb: %mul = mul i32 %src1, %src1 br label %exit exit: - %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i32 %tmp, 1 ret i32 %res } @@ -116,6 +121,7 @@ mulb: %mul = mul i32 %src2, %src2 br label %exit exit: - %res = phi i32 [ %src2, %entry ], [ %mul, %mulb ] + %tmp = phi i32 [ %src2, %entry ], [ %mul, %mulb ] + %res = add i32 %tmp, 1 ret i32 %res } diff --git a/test/CodeGen/SystemZ/int-cmp-38.ll b/test/CodeGen/SystemZ/int-cmp-38.ll index 0d8913b02861..f8b754bf5ea2 100644 --- a/test/CodeGen/SystemZ/int-cmp-38.ll +++ b/test/CodeGen/SystemZ/int-cmp-38.ll @@ -10,7 +10,7 @@ define i32 @f1(i32 %src1) { ; CHECK-LABEL: f1: ; CHECK: crl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %src2 = load i32 , i32 *@g @@ -28,7 +28,7 @@ exit: define i32 @f2(i32 %src1) { ; CHECK-LABEL: f2: ; CHECK: clrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %src2 = load i32 , i32 *@g @@ -46,7 +46,7 @@ exit: define i32 @f3(i32 %src1) { ; CHECK-LABEL: f3: ; CHECK: c{{l?}}rl %r2, g -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %src2 = load i32 , i32 *@g @@ -64,7 +64,7 @@ exit: define i32 @f4(i32 %src1) { ; CHECK-LABEL: f4: ; CHECK: c{{l?}}rl %r2, g -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %src2 = load i32 , i32 *@g @@ -83,7 +83,7 @@ define i32 @f5(i32 %src1) { ; CHECK-LABEL: f5: ; CHECK: larl [[REG:%r[0-5]]], h ; CHECK: c %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %src2 = load i32 , i32 *@h, align 2 @@ -102,7 +102,7 @@ define i32 @f6(i32 %src1) { ; CHECK-LABEL: f6: ; CHECK: larl [[REG:%r[0-5]]], h ; CHECK: cl %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %src2 = load i32 , i32 *@h, align 2 @@ -120,7 +120,7 @@ exit: define i32 @f7(i32 %src2) { ; CHECK-LABEL: f7: ; CHECK: crl %r2, g -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %src1 = load i32 , i32 *@g diff --git a/test/CodeGen/SystemZ/int-cmp-39.ll b/test/CodeGen/SystemZ/int-cmp-39.ll index 5e3abceeca45..2e38e4bb5955 100644 --- a/test/CodeGen/SystemZ/int-cmp-39.ll +++ b/test/CodeGen/SystemZ/int-cmp-39.ll @@ -10,7 +10,7 @@ define i64 @f1(i64 %src1) { ; CHECK-LABEL: f1: ; CHECK: cghrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g @@ -47,7 +47,7 @@ exit: define i64 @f3(i64 %src1) { ; CHECK-LABEL: f3: ; CHECK: cghrl %r2, g -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g @@ -66,7 +66,7 @@ exit: define i64 @f4(i64 %src1) { ; CHECK-LABEL: f4: ; CHECK: cghrl %r2, g -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g @@ -86,7 +86,7 @@ define i64 @f5(i64 %src1) { ; CHECK-LABEL: f5: ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT ; CHECK: cgh %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@h, align 1 @@ -105,7 +105,7 @@ exit: define i64 @f6(i64 %src2) { ; CHECK-LABEL: f6: ; CHECK: cghrl %r2, g -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %val = load i16 , i16 *@g diff --git a/test/CodeGen/SystemZ/int-cmp-40.ll b/test/CodeGen/SystemZ/int-cmp-40.ll index 92696d71fc48..fc38940ce397 100644 --- a/test/CodeGen/SystemZ/int-cmp-40.ll +++ b/test/CodeGen/SystemZ/int-cmp-40.ll @@ -21,7 +21,8 @@ mulb: %mul = mul i64 %src1, %src1 br label %exit exit: - %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i64 %tmp, 1 ret i64 %res } @@ -39,7 +40,8 @@ mulb: %mul = mul i64 %src1, %src1 br label %exit exit: - %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i64 %tmp, 1 ret i64 %res } @@ -58,7 +60,8 @@ mulb: %mul = mul i64 %src1, %src1 br label %exit exit: - %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i64 %tmp, 1 ret i64 %res } @@ -77,7 +80,8 @@ mulb: %mul = mul i64 %src1, %src1 br label %exit exit: - %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i64 %tmp, 1 ret i64 %res } @@ -97,7 +101,8 @@ mulb: %mul = mul i64 %src1, %src1 br label %exit exit: - %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + %res = add i64 %tmp, 1 ret i64 %res } @@ -116,6 +121,7 @@ mulb: %mul = mul i64 %src2, %src2 br label %exit exit: - %res = phi i64 [ %src2, %entry ], [ %mul, %mulb ] + %tmp = phi i64 [ %src2, %entry ], [ %mul, %mulb ] + %res = add i64 %tmp, 1 ret i64 %res } diff --git a/test/CodeGen/SystemZ/int-cmp-41.ll b/test/CodeGen/SystemZ/int-cmp-41.ll index f4f5b4a0cf16..035de5733e94 100644 --- a/test/CodeGen/SystemZ/int-cmp-41.ll +++ b/test/CodeGen/SystemZ/int-cmp-41.ll @@ -10,7 +10,7 @@ define i64 @f1(i64 %src1) { ; CHECK-LABEL: f1: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -47,7 +47,7 @@ exit: define i64 @f3(i64 %src1) { ; CHECK-LABEL: f3: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -66,7 +66,7 @@ exit: define i64 @f4(i64 %src1) { ; CHECK-LABEL: f4: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -86,7 +86,7 @@ define i64 @f5(i64 %src1) { ; CHECK-LABEL: f5: ; CHECK: larl [[REG:%r[0-5]]], h ; CHECK: cgf %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@h, align 2 @@ -105,7 +105,7 @@ exit: define i64 @f6(i64 %src2) { ; CHECK-LABEL: f6: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g diff --git a/test/CodeGen/SystemZ/int-cmp-42.ll b/test/CodeGen/SystemZ/int-cmp-42.ll index ca87b865ad14..7fa5d720fc51 100644 --- a/test/CodeGen/SystemZ/int-cmp-42.ll +++ b/test/CodeGen/SystemZ/int-cmp-42.ll @@ -10,7 +10,7 @@ define i64 @f1(i64 %src1) { ; CHECK-LABEL: f1: ; CHECK: clgfrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -47,7 +47,7 @@ exit: define i64 @f3(i64 %src1) { ; CHECK-LABEL: f3: ; CHECK: clgfrl %r2, g -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -66,7 +66,7 @@ exit: define i64 @f4(i64 %src1) { ; CHECK-LABEL: f4: ; CHECK: clgfrl %r2, g -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -86,7 +86,7 @@ define i64 @f5(i64 %src1) { ; CHECK-LABEL: f5: ; CHECK: larl [[REG:%r[0-5]]], h ; CHECK: clgf %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@h, align 2 @@ -105,7 +105,7 @@ exit: define i64 @f6(i64 %src2) { ; CHECK-LABEL: f6: ; CHECK: clgfrl %r2, g -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g diff --git a/test/CodeGen/SystemZ/int-cmp-43.ll b/test/CodeGen/SystemZ/int-cmp-43.ll index 108b041fa377..700db89435b6 100644 --- a/test/CodeGen/SystemZ/int-cmp-43.ll +++ b/test/CodeGen/SystemZ/int-cmp-43.ll @@ -10,7 +10,7 @@ define i64 @f1(i64 %src1) { ; CHECK-LABEL: f1: ; CHECK: cgrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %src2 = load i64 , i64 *@g @@ -28,7 +28,7 @@ exit: define i64 @f2(i64 %src1) { ; CHECK-LABEL: f2: ; CHECK: clgrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %src2 = load i64 , i64 *@g @@ -46,7 +46,7 @@ exit: define i64 @f3(i64 %src1) { ; CHECK-LABEL: f3: ; CHECK: c{{l?}}grl %r2, g -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %src2 = load i64 , i64 *@g @@ -64,7 +64,7 @@ exit: define i64 @f4(i64 %src1) { ; CHECK-LABEL: f4: ; CHECK: c{{l?}}grl %r2, g -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %src2 = load i64 , i64 *@g @@ -83,7 +83,7 @@ define i64 @f5(i64 %src1) { ; CHECK-LABEL: f5: ; CHECK: larl [[REG:%r[0-5]]], h ; CHECK: cg %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %src2 = load i64 , i64 *@h, align 4 @@ -101,7 +101,7 @@ exit: define i64 @f6(i64 %src2) { ; CHECK-LABEL: f6: ; CHECK: cgrl %r2, g -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %src1 = load i64 , i64 *@g diff --git a/test/CodeGen/SystemZ/int-cmp-44.ll b/test/CodeGen/SystemZ/int-cmp-44.ll index a87dccd4ac2a..1b9a4ae353fe 100644 --- a/test/CodeGen/SystemZ/int-cmp-44.ll +++ b/test/CodeGen/SystemZ/int-cmp-44.ll @@ -11,7 +11,7 @@ declare void @foo() define i32 @f1(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f1: ; CHECK: afi %r2, 1000000 -; CHECK-NEXT: je .L{{.*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %res = add i32 %a, 1000000 @@ -30,7 +30,7 @@ exit: define i32 @f2(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f2: ; CHECK: afi %r2, 1000000 -; CHECK-NEXT: jne .L{{.*}} +; CHECK-NEXT: bner %r14 ; CHECK: br %r14 entry: %res = add i32 %a, 1000000 @@ -49,7 +49,7 @@ exit: define i32 @f3(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f3: ; CHECK: afi %r2, 1000000 -; CHECK-NEXT: cijl %r2, 0, .L{{.*}} +; CHECK-NEXT: cibl %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %res = add i32 %a, 1000000 @@ -68,7 +68,7 @@ exit: define i32 @f4(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f4: ; CHECK: afi %r2, 1000000 -; CHECK-NEXT: cijle %r2, 0, .L{{.*}} +; CHECK-NEXT: cible %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %res = add i32 %a, 1000000 @@ -87,7 +87,7 @@ exit: define i32 @f5(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f5: ; CHECK: afi %r2, 1000000 -; CHECK-NEXT: cijh %r2, 0, .L{{.*}} +; CHECK-NEXT: cibh %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %res = add i32 %a, 1000000 @@ -106,7 +106,7 @@ exit: define i32 @f6(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f6: ; CHECK: afi %r2, 1000000 -; CHECK-NEXT: cijhe %r2, 0, .L{{.*}} +; CHECK-NEXT: cibhe %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %res = add i32 %a, 1000000 @@ -125,7 +125,7 @@ exit: define i32 @f7(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f7: ; CHECK: s %r2, 0(%r4) -; CHECK-NEXT: jne .L{{.*}} +; CHECK-NEXT: bner %r14 ; CHECK: br %r14 entry: %cur = load i32 , i32 *%dest @@ -145,7 +145,7 @@ exit: define i32 @f8(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f8: ; CHECK: s %r2, 0(%r4) -; CHECK-NEXT: cijl %r2, 0, .L{{.*}} +; CHECK-NEXT: cibl %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %cur = load i32 , i32 *%dest @@ -166,7 +166,7 @@ exit: define i32 @f9(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f9: ; CHECK: nr %r2, %r3 -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = and i32 %a, %b @@ -185,7 +185,7 @@ exit: define i32 @f10(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f10: ; CHECK: nr %r2, %r3 -; CHECK-NEXT: cijl %r2, 0, .L{{.*}} +; CHECK-NEXT: cibl %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %res = and i32 %a, %b @@ -205,7 +205,7 @@ exit: define i32 @f11(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f11: ; CHECK: nilf %r2, 100000001 -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = and i32 %a, 100000001 @@ -225,7 +225,7 @@ exit: define i32 @f12(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f12: ; CHECK: nill %r2, 65436 -; CHECK-NEXT: cijlh %r2, 0, .L{{.*}} +; CHECK-NEXT: ciblh %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %res = and i32 %a, -100 @@ -244,7 +244,7 @@ exit: define i32 @f13(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f13: ; CHECK: sra %r2, 0(%r3) -; CHECK-NEXT: je .L{{.*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %res = ashr i32 %a, %b @@ -263,7 +263,7 @@ exit: define i32 @f14(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f14: ; CHECK: sra %r2, 0(%r3) -; CHECK-NEXT: jlh .L{{.*}} +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %res = ashr i32 %a, %b @@ -282,7 +282,7 @@ exit: define i32 @f15(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f15: ; CHECK: sra %r2, 0(%r3) -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = ashr i32 %a, %b @@ -301,7 +301,7 @@ exit: define i32 @f16(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f16: ; CHECK: sra %r2, 0(%r3) -; CHECK-NEXT: jle .L{{.*}} +; CHECK-NEXT: bler %r14 ; CHECK: br %r14 entry: %res = ashr i32 %a, %b @@ -320,7 +320,7 @@ exit: define i32 @f17(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f17: ; CHECK: sra %r2, 0(%r3) -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %res = ashr i32 %a, %b @@ -339,7 +339,7 @@ exit: define i32 @f18(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f18: ; CHECK: sra %r2, 0(%r3) -; CHECK-NEXT: jhe .L{{.*}} +; CHECK-NEXT: bher %r14 ; CHECK: br %r14 entry: %res = ashr i32 %a, %b @@ -359,7 +359,7 @@ exit: define i64 @f19(i64 %a, i64 %b, i64 *%dest) { ; CHECK-LABEL: f19: ; CHECK: risbg %r2, %r3, 0, 190, 0 -; CHECK-NEXT: je .L{{.*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %res = and i64 %b, -2 @@ -378,7 +378,7 @@ exit: define i64 @f20(i64 %a, i64 %b, i64 *%dest) { ; CHECK-LABEL: f20: ; CHECK: risbg %r2, %r3, 0, 190, 0 -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = and i64 %b, -2 @@ -401,7 +401,7 @@ define i32 @f21(i32 %a, i32 %b, i32 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: cije %r2, 0, .L{{.*}} +; CHECK-NEXT: cibe %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %add = add i32 %a, 1000000 @@ -424,7 +424,7 @@ define i32 @f22(i32 %a, i32 %b, i32 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: cije %r2, 0, .L{{.*}} +; CHECK-NEXT: cibe %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %add = add i32 %a, 1000000 @@ -445,7 +445,7 @@ define i32 @f23(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) { ; CHECK-LABEL: f23: ; CHECK: afi %r2, 1000000 ; CHECK-NEXT: st %r2, 0(%r4) -; CHECK-NEXT: jne .L{{.*}} +; CHECK-NEXT: bner %r14 ; CHECK: br %r14 entry: %res = add i32 %a, 1000000 @@ -491,7 +491,7 @@ define void @f25(i32 %a, i32 *%ptr) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jne .L{{.*}} +; CHECK-NEXT: bner %r14 ; CHECK: br %r14 entry: %add = add i32 %a, 1000000 @@ -514,7 +514,7 @@ define void @f26(i32 %a, i32 *%ptr) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: cijlh %r2, 0, .L{{.*}} +; CHECK-NEXT: ciblh %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %add = add i32 %a, 1000000 @@ -537,7 +537,7 @@ define i32 @f27(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) { ; CHECK: afi %r2, 1000000 ; CHECK-NEXT: sr %r3, %r2 ; CHECK-NEXT: st %r3, 0(%r4) -; CHECK-NEXT: cije %r2, 0, .L{{.*}} +; CHECK-NEXT: cibe %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %add = add i32 %a, 1000000 @@ -558,7 +558,7 @@ exit: define void @f28(i64 %a, i64 *%dest) { ; CHECK-LABEL: f28: ; CHECK: xi 0(%r2), 15 -; CHECK: cgije %r2, 0, .L{{.*}} +; CHECK: cgibe %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %ptr = inttoptr i64 %a to i8 * @@ -580,7 +580,7 @@ exit: define i32 @f29(i64 %base, i64 %index, i32 *%dest) { ; CHECK-LABEL: f29: ; CHECK: lt %r2, 0({{%r2,%r3|%r3,%r2}}) -; CHECK-NEXT: jle .L{{.*}} +; CHECK-NEXT: bler %r14 ; CHECK: br %r14 entry: %add = add i64 %base, %index @@ -601,7 +601,7 @@ exit: define i32 @f30(i64 %base, i64 %index, i32 *%dest) { ; CHECK-LABEL: f30: ; CHECK: lt %r2, 100000({{%r2,%r3|%r3,%r2}}) -; CHECK-NEXT: jle .L{{.*}} +; CHECK-NEXT: bler %r14 ; CHECK: br %r14 entry: %add1 = add i64 %base, %index @@ -623,7 +623,7 @@ exit: define i64 @f31(i64 %base, i64 %index, i64 *%dest) { ; CHECK-LABEL: f31: ; CHECK: ltg %r2, 0({{%r2,%r3|%r3,%r2}}) -; CHECK-NEXT: jhe .L{{.*}} +; CHECK-NEXT: bher %r14 ; CHECK: br %r14 entry: %add = add i64 %base, %index @@ -644,7 +644,7 @@ exit: define i64 @f32(i64 %base, i64 %index, i64 *%dest) { ; CHECK-LABEL: f32: ; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}}) -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %add = add i64 %base, %index @@ -669,7 +669,7 @@ define i32 @f33(i32 %dummy, i32 %val, i32 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{r2}"(i32 %val) @@ -691,7 +691,7 @@ define i64 @f34(i64 %dummy, i64 %val, i64 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{r2}"(i64 %val) @@ -713,7 +713,7 @@ define i64 @f35(i64 %dummy, i32 %val, i64 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %ext = sext i32 %val to i64 @@ -737,7 +737,7 @@ define i32 @f36(i32 %val, i32 %dummy, i32 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r3 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{r3}"(i32 %val) @@ -760,7 +760,7 @@ define i64 @f37(i64 %val, i64 %dummy, i64 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r3 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: call void asm sideeffect "blah $0", "{r3}"(i64 %val) @@ -783,7 +783,7 @@ define i32 @f38(i32 %val, i64 %dummy, i32 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r3 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jl .L{{.*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %ext = sext i32 %val to i64 @@ -806,7 +806,7 @@ define i64 @f39(i64 %dummy, i64 %a, i64 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %val = trunc i64 %a to i32 @@ -830,7 +830,7 @@ define i64 @f40(i64 %dummy, i64 %a, i64 *%dest) { ; CHECK-NEXT: #APP ; CHECK-NEXT: blah %r2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %shl = shl i64 %a, 32 @@ -851,7 +851,7 @@ exit: define i32 @f41(i32 %a, i32 %b, i32 *%dest) { ; CHECK-LABEL: f41: ; CHECK: s %r2, 0(%r4) -; CHECK-NEXT: jne .L{{.*}} +; CHECK-NEXT: bner %r14 ; CHECK: br %r14 entry: %cur = load i32 , i32 *%dest @@ -871,7 +871,7 @@ exit: define i64 @f42(i64 %base, i64 %index, i64 *%dest) { ; CHECK-LABEL: f42: ; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}}) -; CHECK-NEXT: jh .L{{.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %add = add i64 %base, %index diff --git a/test/CodeGen/SystemZ/int-cmp-46.ll b/test/CodeGen/SystemZ/int-cmp-46.ll index f311942b9f86..8374cd3bec50 100644 --- a/test/CodeGen/SystemZ/int-cmp-46.ll +++ b/test/CodeGen/SystemZ/int-cmp-46.ll @@ -8,7 +8,7 @@ define void @f1(i32 %a) { ; CHECK-LABEL: f1: ; CHECK: tmll %r2, 1 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 1 @@ -27,7 +27,7 @@ exit: define void @f2(i32 %a) { ; CHECK-LABEL: f2: ; CHECK: tmll %r2, 65535 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 65535 @@ -46,7 +46,7 @@ exit: define void @f3(i32 %a) { ; CHECK-LABEL: f3: ; CHECK: tmlh %r2, 1 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 65536 @@ -83,7 +83,7 @@ exit: define void @f5(i32 %a) { ; CHECK-LABEL: f5: ; CHECK: tmlh %r2, 65535 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 4294901760 @@ -103,7 +103,7 @@ exit: define void @f6(i32 %a) { ; CHECK-LABEL: f6: ; CHECK: tmll %r2, 240 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 240 @@ -122,7 +122,7 @@ exit: define void @f7(i32 %a) { ; CHECK-LABEL: f7: ; CHECK: tmll %r2, 240 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 240 @@ -142,7 +142,7 @@ exit: define void @f8(i32 %a) { ; CHECK-LABEL: f8: ; CHECK: tmll %r2, 240 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 240 @@ -161,7 +161,7 @@ exit: define void @f9(i32 %a) { ; CHECK-LABEL: f9: ; CHECK: tmll %r2, 240 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 240 @@ -181,7 +181,7 @@ exit: define void @f10(i32 %a) { ; CHECK-LABEL: f10: ; CHECK: tmll %r2, 35 -; CHECK: jle {{\.L.*}} +; CHECK: bler %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 35 @@ -200,7 +200,7 @@ exit: define void @f11(i32 %a) { ; CHECK-LABEL: f11: ; CHECK: tmll %r2, 35 -; CHECK: jle {{\.L.*}} +; CHECK: bler %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 35 @@ -220,7 +220,7 @@ exit: define void @f12(i32 %a) { ; CHECK-LABEL: f12: ; CHECK: tmll %r2, 140 -; CHECK: jnle {{\.L.*}} +; CHECK: bnler %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 140 @@ -239,7 +239,7 @@ exit: define void @f13(i32 %a) { ; CHECK-LABEL: f13: ; CHECK: tmll %r2, 140 -; CHECK: jnle {{\.L.*}} +; CHECK: bnler %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 140 @@ -258,7 +258,7 @@ exit: define void @f14(i32 %a) { ; CHECK-LABEL: f14: ; CHECK: tmll %r2, 101 -; CHECK: jo {{\.L.*}} +; CHECK: bor %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 101 @@ -277,7 +277,7 @@ exit: define void @f15(i32 %a) { ; CHECK-LABEL: f15: ; CHECK: tmll %r2, 65519 -; CHECK: jno {{\.L.*}} +; CHECK: bnor %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 65519 @@ -297,7 +297,7 @@ exit: define void @f16(i32 %a) { ; CHECK-LABEL: f16: ; CHECK: tmll %r2, 130 -; CHECK: jno {{\.L.*}} +; CHECK: bnor %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 130 @@ -316,7 +316,7 @@ exit: define void @f17(i32 %a) { ; CHECK-LABEL: f17: ; CHECK: tmll %r2, 130 -; CHECK: jno {{\.L.*}} +; CHECK: bnor %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 130 @@ -336,7 +336,7 @@ exit: define void @f18(i32 %a) { ; CHECK-LABEL: f18: ; CHECK: tmll %r2, 194 -; CHECK: jo {{\.L.*}} +; CHECK: bor %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 194 @@ -355,7 +355,7 @@ exit: define void @f19(i32 %a) { ; CHECK-LABEL: f19: ; CHECK: tmll %r2, 194 -; CHECK: jo {{\.L.*}} +; CHECK: bor %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 194 @@ -375,7 +375,7 @@ exit: define void @f20(i32 %a) { ; CHECK-LABEL: f20: ; CHECK: tmll %r2, 20 -; CHECK: jl {{\.L.*}} +; CHECK: blr %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 20 @@ -395,7 +395,7 @@ exit: define void @f21(i32 %a) { ; CHECK-LABEL: f21: ; CHECK: tmll %r2, 20 -; CHECK: jnl {{\.L.*}} +; CHECK: bnlr %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 20 @@ -415,7 +415,7 @@ exit: define void @f22(i32 %a) { ; CHECK-LABEL: f22: ; CHECK: tmll %r2, 20 -; CHECK: jh {{\.L.*}} +; CHECK: bhr %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 20 @@ -435,7 +435,7 @@ exit: define void @f23(i32 %a) { ; CHECK-LABEL: f23: ; CHECK: tmll %r2, 20 -; CHECK: jnh {{\.L.*}} +; CHECK: bnhr %r14 ; CHECK: br %r14 entry: %and = and i32 %a, 20 @@ -454,7 +454,7 @@ exit: define void @f24(i32 %a) { ; CHECK-LABEL: f24: ; CHECK: tmll %r2, 255 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %shl = shl i32 %a, 12 @@ -474,7 +474,7 @@ exit: define void @f25(i32 %a) { ; CHECK-LABEL: f25: ; CHECK: tmlh %r2, 512 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %shr = lshr i32 %a, 25 diff --git a/test/CodeGen/SystemZ/int-cmp-47.ll b/test/CodeGen/SystemZ/int-cmp-47.ll index 274350d24de1..dc87284ff5f5 100644 --- a/test/CodeGen/SystemZ/int-cmp-47.ll +++ b/test/CodeGen/SystemZ/int-cmp-47.ll @@ -9,7 +9,7 @@ define void @f1(i64 %a) { ; CHECK-LABEL: f1: ; CHECK: tmll %r2, 1 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 1 @@ -28,7 +28,7 @@ exit: define void @f2(i64 %a) { ; CHECK-LABEL: f2: ; CHECK: tmll %r2, 65535 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 65535 @@ -47,7 +47,7 @@ exit: define void @f3(i64 %a) { ; CHECK-LABEL: f3: ; CHECK: tmlh %r2, 1 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 65536 @@ -84,7 +84,7 @@ exit: define void @f5(i64 %a) { ; CHECK-LABEL: f5: ; CHECK: tmlh %r2, 65535 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 4294901760 @@ -103,7 +103,7 @@ exit: define void @f6(i64 %a) { ; CHECK-LABEL: f6: ; CHECK: tmhl %r2, 1 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 4294967296 @@ -140,7 +140,7 @@ exit: define void @f8(i64 %a) { ; CHECK-LABEL: f8: ; CHECK: tmhl %r2, 65535 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 281470681743360 @@ -159,7 +159,7 @@ exit: define void @f9(i64 %a) { ; CHECK-LABEL: f9: ; CHECK: tmhh %r2, 1 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 281474976710656 @@ -178,7 +178,7 @@ exit: define void @f10(i64 %a) { ; CHECK-LABEL: f10: ; CHECK: tmhh %r2, 65535 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %and = and i64 %a, 18446462598732840960 @@ -197,7 +197,7 @@ exit: define void @f11(i64 %a) { ; CHECK-LABEL: f11: ; CHECK: tmhl %r2, 32768 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %shl = shl i64 %a, 1 @@ -217,7 +217,7 @@ exit: define void @f12(i64 %a) { ; CHECK-LABEL: f12: ; CHECK: tmhh %r2, 256 -; CHECK: jne {{\.L.*}} +; CHECK: bner %r14 ; CHECK: br %r14 entry: %shr = lshr i64 %a, 56 @@ -237,7 +237,7 @@ exit: define void @f13(i64 %a) { ; CHECK-LABEL: f13: ; CHECK: tmhh %r2, 49152 -; CHECK: jno {{\.L.*}} +; CHECK: bnor %r14 ; CHECK: br %r14 entry: %cmp = icmp ult i64 %a, 13835058055282163712 @@ -255,7 +255,7 @@ exit: define void @f14(i64 %a) { ; CHECK-LABEL: f14: ; CHECK: tmhh %r2, 49152 -; CHECK: jno {{\.L.*}} +; CHECK: bnor %r14 ; CHECK: br %r14 entry: %cmp = icmp ule i64 %a, 13835058055282163711 @@ -273,7 +273,7 @@ exit: define void @f15(i64 %a) { ; CHECK-LABEL: f15: ; CHECK: tmhh %r2, 49152 -; CHECK: jo {{\.L.*}} +; CHECK: bor %r14 ; CHECK: br %r14 entry: %cmp = icmp ugt i64 %a, 13835058055282163711 @@ -291,7 +291,7 @@ exit: define void @f16(i64 %a) { ; CHECK-LABEL: f16: ; CHECK: tmhh %r2, 49152 -; CHECK: jo {{\.L.*}} +; CHECK: bor %r14 ; CHECK: br %r14 entry: %cmp = icmp uge i64 %a, 13835058055282163712 @@ -329,7 +329,7 @@ exit: define void @f18(i64 %a) { ; CHECK-LABEL: f18: ; CHECK-NOT: tmhh -; CHECK: cgijhe %r2, 0, +; CHECK: cgibhe %r2, 0, 0(%r14) ; CHECK: br %r14 entry: %cmp = icmp ult i64 %a, 9223372036854775808 diff --git a/test/CodeGen/SystemZ/int-cmp-48.ll b/test/CodeGen/SystemZ/int-cmp-48.ll index e26694753e7c..277423b8cc0c 100644 --- a/test/CodeGen/SystemZ/int-cmp-48.ll +++ b/test/CodeGen/SystemZ/int-cmp-48.ll @@ -8,7 +8,7 @@ define void @f1(i8 *%src) { ; CHECK-LABEL: f1: ; CHECK: tm 0(%r2), 1 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %byte = load i8 , i8 *%src @@ -31,7 +31,7 @@ define void @f2(i8 *%src) { ; CHECK: llc [[REG:%r[0-5]]], 0(%r2) ; CHECK: mvi 0(%r2), 0 ; CHECK: tmll [[REG]], 1 -; CHECK: je {{\.L.*}} +; CHECK: ber %r14 ; CHECK: br %r14 entry: %byte = load i8 , i8 *%src diff --git a/test/CodeGen/SystemZ/memchr-01.ll b/test/CodeGen/SystemZ/memchr-01.ll index f7509c4f256b..f4d381b37f26 100644 --- a/test/CodeGen/SystemZ/memchr-01.ll +++ b/test/CodeGen/SystemZ/memchr-01.ll @@ -13,7 +13,7 @@ define i8 *@f1(i8 *%src, i16 %char, i32 %len) { ; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: srst %r2, [[REG]] ; CHECK-NEXT: jo [[LABEL]] -; CHECK: jl {{\.L.*}} +; CHECK: blr %r14 ; CHECK: lghi %r2, 0 ; CHECK: br %r14 %res = call i8 *@memchr(i8 *%src, i16 %char, i32 %len) diff --git a/test/CodeGen/SystemZ/memchr-02.ll b/test/CodeGen/SystemZ/memchr-02.ll index 71b2cf02b352..0cfca2af1e98 100644 --- a/test/CodeGen/SystemZ/memchr-02.ll +++ b/test/CodeGen/SystemZ/memchr-02.ll @@ -12,7 +12,7 @@ define i8 *@f1(i64 %len, i8 *%src, i32 %char) { ; CHECK: [[LABEL:\.[^:]*]]: ; CHECK: srst %r2, %r3 ; CHECK-NEXT: jo [[LABEL]] -; CHECK: jl {{\.L.*}} +; CHECK: blr %r14 ; CHECK: lghi %r2, 0 ; CHECK: br %r14 %res = call i8 *@memchr(i8 *%src, i32 %char, i64 %len) diff --git a/test/CodeGen/SystemZ/memchr-nobuiltin.ll b/test/CodeGen/SystemZ/memchr-nobuiltin.ll new file mode 100644 index 000000000000..f94e1162ae4e --- /dev/null +++ b/test/CodeGen/SystemZ/memchr-nobuiltin.ll @@ -0,0 +1,16 @@ +; Test that memchr won't be converted to SRST if calls are +; marked with nobuiltin, eg. for sanitizers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i8 *@memchr(i8 *%src, i16 %char, i32 %len) + +; Test a simple forwarded call. +define i8 *@f1(i8 *%src, i16 %char, i32 %len) { +; CHECK-LABEL: f1: +; CHECK-NOT: srst +; CHECK: brasl %r14, memchr +; CHECK: br %r14 + %res = call i8 *@memchr(i8 *%src, i16 %char, i32 %len) nobuiltin + ret i8 *%res +} diff --git a/test/CodeGen/SystemZ/memcmp-01.ll b/test/CodeGen/SystemZ/memcmp-01.ll index a01441946937..ac980e49d60b 100644 --- a/test/CodeGen/SystemZ/memcmp-01.ll +++ b/test/CodeGen/SystemZ/memcmp-01.ll @@ -29,7 +29,7 @@ define i32 @f2(i8 *%src1, i8 *%src2) { define void @f3(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK-LABEL: f3: ; CHECK: clc 0(3,%r2), 0(%r3) -; CHECK-NEXT: je {{\..*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 3) %cmp = icmp eq i32 %res, 0 @@ -47,7 +47,7 @@ exit: define void @f4(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK-LABEL: f4: ; CHECK: clc 0(4,%r2), 0(%r3) -; CHECK-NEXT: jlh {{\..*}} +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 4) @@ -66,7 +66,7 @@ exit: define void @f5(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK-LABEL: f5: ; CHECK: clc 0(5,%r2), 0(%r3) -; CHECK-NEXT: jl {{\..*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 5) @@ -85,7 +85,7 @@ exit: define void @f6(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK-LABEL: f6: ; CHECK: clc 0(6,%r2), 0(%r3) -; CHECK-NEXT: jh {{\..*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 6) @@ -108,7 +108,7 @@ define i32 @f7(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK: ipm [[REG:%r[0-5]]] ; CHECK: srl [[REG]], 28 ; CHECK: rll %r2, [[REG]], 31 -; CHECK: jl {{.L*}} +; CHECK: blr %r14 ; CHECK: br %r14 entry: %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 256) @@ -143,7 +143,7 @@ define void @f9(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK: jlh [[LABEL:\..*]] ; CHECK: clc 256(1,%r2), 256(%r3) ; CHECK: [[LABEL]]: -; CHECK-NEXT: jl .L +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 257) diff --git a/test/CodeGen/SystemZ/memcmp-02.ll b/test/CodeGen/SystemZ/memcmp-02.ll index 74b090dcdd8e..da11170def79 100644 --- a/test/CodeGen/SystemZ/memcmp-02.ll +++ b/test/CodeGen/SystemZ/memcmp-02.ll @@ -30,7 +30,7 @@ define i64 @f2(i8 *%src1, i8 *%src2) { define void @f3(i8 *%src1, i8 *%src2, i64 *%dest) { ; CHECK-LABEL: f3: ; CHECK: clc 0(3,%r2), 0(%r3) -; CHECK-NEXT: je {{\..*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 3) %cmp = icmp eq i64 %res, 0 @@ -48,7 +48,7 @@ exit: define void @f4(i8 *%src1, i8 *%src2, i64 *%dest) { ; CHECK-LABEL: f4: ; CHECK: clc 0(4,%r2), 0(%r3) -; CHECK-NEXT: jlh {{\..*}} +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 4) @@ -67,7 +67,7 @@ exit: define void @f5(i8 *%src1, i8 *%src2, i64 *%dest) { ; CHECK-LABEL: f5: ; CHECK: clc 0(5,%r2), 0(%r3) -; CHECK-NEXT: jl {{\..*}} +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 5) @@ -86,7 +86,7 @@ exit: define void @f6(i8 *%src1, i8 *%src2, i64 *%dest) { ; CHECK-LABEL: f6: ; CHECK: clc 0(6,%r2), 0(%r3) -; CHECK-NEXT: jh {{\..*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 6) @@ -110,7 +110,7 @@ define i64 @f7(i8 *%src1, i8 *%src2, i64 *%dest) { ; CHECK: srl [[REG]], 28 ; CHECK: rll [[REG]], [[REG]], 31 ; CHECK: lgfr %r2, [[REG]] -; CHECK: jl {{.L*}} +; CHECK: blr %r14 ; CHECK: br %r14 entry: %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 256) diff --git a/test/CodeGen/SystemZ/memcmp-nobuiltin.ll b/test/CodeGen/SystemZ/memcmp-nobuiltin.ll new file mode 100644 index 000000000000..5703552289f3 --- /dev/null +++ b/test/CodeGen/SystemZ/memcmp-nobuiltin.ll @@ -0,0 +1,191 @@ +; Test that memcmp won't be converted to CLC if calls are +; marked with nobuiltin, eg. for sanitizers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare signext i32 @memcmp(i8 *%src1, i8 *%src2, i64 %size) + +; Zero-length comparisons should be optimized away. +define i32 @f1(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f1: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 0) nobuiltin + ret i32 %res +} + +; Check a case where the result is used as an integer. +define i32 @f2(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f2: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 2) nobuiltin + ret i32 %res +} + +; Check a case where the result is tested for equality. +define void @f3(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f3: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 3) nobuiltin + %cmp = icmp eq i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret void +} + +; Check a case where the result is tested for inequality. +define void @f4(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f4: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 +entry: + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 4) nobuiltin + %cmp = icmp ne i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret void +} + +; Check a case where the result is tested via slt. +define void @f5(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f5: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 +entry: + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 5) nobuiltin + %cmp = icmp slt i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret void +} + +; Check a case where the result is tested for sgt. +define void @f6(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f6: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 +entry: + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 6) nobuiltin + %cmp = icmp sgt i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret void +} + +; Check the upper end of the CLC range. Here the result is used both as +; an integer and for branching. +define i32 @f7(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f7: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 +entry: + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 256) nobuiltin + %cmp = icmp slt i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret i32 %res +} + +; 257 bytes needs two CLCs. +define i32 @f8(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f8: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 257) nobuiltin + ret i32 %res +} + +; Test a comparison of 258 bytes in which the CC result can be used directly. +define void @f9(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f9: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 +entry: + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 257) nobuiltin + %cmp = icmp slt i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret void +} + +; Test the largest size that can use two CLCs. +define i32 @f10(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f10: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 512) nobuiltin + ret i32 %res +} + +; Test the smallest size that needs 3 CLCs. +define i32 @f11(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f11: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 513) nobuiltin + ret i32 %res +} + +; Test the largest size than can use 3 CLCs. +define i32 @f12(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f12: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 768) nobuiltin + ret i32 %res +} + +; The next size up uses a loop instead. We leave the more complicated +; loop tests to memcpy-01.ll, which shares the same form. +define i32 @f13(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f13: +; CHECK-NOT: clc +; CHECK: brasl %r14, memcmp +; CHECK: br %r14 + %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 769) nobuiltin + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/pie.ll b/test/CodeGen/SystemZ/pie.ll new file mode 100644 index 000000000000..8fc261454464 --- /dev/null +++ b/test/CodeGen/SystemZ/pie.ll @@ -0,0 +1,13 @@ +; RUN: llc -mtriple=s390x-linux-gnu -relocation-model=pic < %s | FileCheck %s + +@foo = global i32 42 + +define i32* @get_foo() { + ret i32* @foo +} + +; CHECK: larl %r2, foo{{$}} + +!llvm.module.flags = !{!0} + +!0 = !{i32 1, !"PIE Level", i32 2} diff --git a/test/CodeGen/SystemZ/ret-addr-01.ll b/test/CodeGen/SystemZ/ret-addr-01.ll new file mode 100644 index 000000000000..9c3b246af578 --- /dev/null +++ b/test/CodeGen/SystemZ/ret-addr-01.ll @@ -0,0 +1,15 @@ +; Test support for the llvm.returnaddress intrinsic. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; The current function's return address is in the link register. +define i8* @rt0() norecurse nounwind readnone { +entry: +; CHECK-LABEL: rt0: +; CHECK: lgr %r2, %r14 +; CHECK: br %r14 + %0 = tail call i8* @llvm.returnaddress(i32 0) + ret i8* %0 +} + +declare i8* @llvm.returnaddress(i32) nounwind readnone diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll index d75e8e4b11a6..1c4315343de0 100644 --- a/test/CodeGen/SystemZ/risbg-01.ll +++ b/test/CodeGen/SystemZ/risbg-01.ll @@ -480,3 +480,24 @@ define i64 @f42(i1 %x) { %ext2 = zext i8 %ext to i64 ret i64 %ext2 } + +; Check that we get the case where a 64-bit shift is used by a 32-bit and. +define signext i32 @f43(i64 %x) { +; CHECK-LABEL: f43: +; CHECK: risbg [[REG:%r[0-5]]], %r2, 32, 189, 52 +; CHECK: lgfr %r2, [[REG]] + %shr3 = lshr i64 %x, 12 + %shr3.tr = trunc i64 %shr3 to i32 + %conv = and i32 %shr3.tr, -4 + ret i32 %conv +} + +; Check that we don't get the case where the 32-bit and mask is not contiguous +define signext i32 @f44(i64 %x) { +; CHECK-LABEL: f44: +; CHECK: srlg [[REG:%r[0-5]]], %r2, 12 + %shr4 = lshr i64 %x, 12 + %conv = trunc i64 %shr4 to i32 + %and = and i32 %conv, 10 + ret i32 %and +} diff --git a/test/CodeGen/SystemZ/risbg-02.ll b/test/CodeGen/SystemZ/risbg-02.ll index 5ccfab028b02..094005acae4b 100644 --- a/test/CodeGen/SystemZ/risbg-02.ll +++ b/test/CodeGen/SystemZ/risbg-02.ll @@ -91,3 +91,28 @@ define i64 @f8(i64 %a, i64 %b) { %or = or i64 %anda, %shrb ret i64 %or } + +; Check that we can get the case where a 64-bit shift feeds a 32-bit or of +; ands with complement masks. +define signext i32 @f9(i64 %x, i32 signext %y) { +; CHECK-LABEL: f9: +; CHECK: risbg [[REG:%r[0-5]]], %r2, 48, 63, 16 +; CHECK: lgfr %r2, [[REG]] + %shr6 = lshr i64 %x, 48 + %conv = trunc i64 %shr6 to i32 + %and1 = and i32 %y, -65536 + %or = or i32 %conv, %and1 + ret i32 %or +} + +; Check that we don't get the case where a 64-bit shift feeds a 32-bit or of +; ands with incompatible masks. +define signext i32 @f10(i64 %x, i32 signext %y) { +; CHECK-LABEL: f10: +; CHECK: nilf %r3, 4278190080 + %shr6 = lshr i64 %x, 48 + %conv = trunc i64 %shr6 to i32 + %and1 = and i32 %y, -16777216 + %or = or i32 %conv, %and1 + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/rot-01.ll b/test/CodeGen/SystemZ/rot-01.ll new file mode 100644 index 000000000000..ea275e68df54 --- /dev/null +++ b/test/CodeGen/SystemZ/rot-01.ll @@ -0,0 +1,35 @@ +; Test shortening of NILL to NILF when the result is used as a rotate amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 32-bit rotate. +define i32 @f1(i32 %val, i32 %amt) { +; CHECK-LABEL: f1: +; CHECK: nill %r3, 31 +; CHECK: rll %r2, %r2, 0(%r3) + %mod = urem i32 %amt, 32 + + %inv = sub i32 32, %mod + %parta = shl i32 %val, %mod + %partb = lshr i32 %val, %inv + + %rotl = or i32 %parta, %partb + + ret i32 %rotl +} + +; Test 64-bit rotate. +define i64 @f2(i64 %val, i64 %amt) { +; CHECK-LABEL: f2: +; CHECK: nill %r3, 31 +; CHECK: rllg %r2, %r2, 0(%r3) + %mod = urem i64 %amt, 32 + + %inv = sub i64 64, %mod + %parta = shl i64 %val, %mod + %partb = lshr i64 %val, %inv + + %rotl = or i64 %parta, %partb + + ret i64 %rotl +} diff --git a/test/CodeGen/SystemZ/rot-02.ll b/test/CodeGen/SystemZ/rot-02.ll new file mode 100644 index 000000000000..12b09f131850 --- /dev/null +++ b/test/CodeGen/SystemZ/rot-02.ll @@ -0,0 +1,86 @@ +; Test removal of AND operations that don't affect last 6 bits of rotate amount +; operand. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test that AND is not removed when some lower 6 bits are not set. +define i32 @f1(i32 %val, i32 %amt) { +; CHECK-LABEL: f1: +; CHECK: nil{{[lf]}} %r3, 31 +; CHECK: rll %r2, %r2, 0(%r3) + %and = and i32 %amt, 31 + + %inv = sub i32 32, %and + %parta = shl i32 %val, %and + %partb = lshr i32 %val, %inv + + %rotl = or i32 %parta, %partb + + ret i32 %rotl +} + +; Test removal of AND mask with only bottom 6 bits set. +define i32 @f2(i32 %val, i32 %amt) { +; CHECK-LABEL: f2: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: rll %r2, %r2, 0(%r3) + %and = and i32 %amt, 63 + + %inv = sub i32 32, %and + %parta = shl i32 %val, %and + %partb = lshr i32 %val, %inv + + %rotl = or i32 %parta, %partb + + ret i32 %rotl +} + +; Test removal of AND mask including but not limited to bottom 6 bits. +define i32 @f3(i32 %val, i32 %amt) { +; CHECK-LABEL: f3: +; CHECK-NOT: nil{{[lf]}} %r3, 255 +; CHECK: rll %r2, %r2, 0(%r3) + %and = and i32 %amt, 255 + + %inv = sub i32 32, %and + %parta = shl i32 %val, %and + %partb = lshr i32 %val, %inv + + %rotl = or i32 %parta, %partb + + ret i32 %rotl +} + +; Test removal of AND mask from RLLG. +define i64 @f4(i64 %val, i64 %amt) { +; CHECK-LABEL: f4: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: rllg %r2, %r2, 0(%r3) + %and = and i64 %amt, 63 + + %inv = sub i64 64, %and + %parta = shl i64 %val, %and + %partb = lshr i64 %val, %inv + + %rotl = or i64 %parta, %partb + + ret i64 %rotl +} + +; Test that AND is not entirely removed if the result is reused. +define i32 @f5(i32 %val, i32 %amt) { +; CHECK-LABEL: f5: +; CHECK: rll %r2, %r2, 0(%r3) +; CHECK: nil{{[lf]}} %r3, 63 +; CHECK: ar %r2, %r3 + %and = and i32 %amt, 63 + + %inv = sub i32 32, %and + %parta = shl i32 %val, %and + %partb = lshr i32 %val, %inv + + %rotl = or i32 %parta, %partb + + %reuse = add i32 %and, %rotl + ret i32 %reuse +} diff --git a/test/CodeGen/SystemZ/shift-11.ll b/test/CodeGen/SystemZ/shift-11.ll new file mode 100644 index 000000000000..9741fa5a0b55 --- /dev/null +++ b/test/CodeGen/SystemZ/shift-11.ll @@ -0,0 +1,63 @@ +; Test shortening of NILL to NILF when the result is used as a shift amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test logical shift right. +define i32 @f1(i32 %a, i32 %sh) { +; CHECK-LABEL: f1: +; CHECK: nill %r3, 31 +; CHECK: srl %r2, 0(%r3) + %and = and i32 %sh, 31 + %shift = lshr i32 %a, %and + ret i32 %shift +} + +; Test arithmetic shift right. +define i32 @f2(i32 %a, i32 %sh) { +; CHECK-LABEL: f2: +; CHECK: nill %r3, 31 +; CHECK: sra %r2, 0(%r3) + %and = and i32 %sh, 31 + %shift = ashr i32 %a, %and + ret i32 %shift +} + +; Test shift left. +define i32 @f3(i32 %a, i32 %sh) { +; CHECK-LABEL: f3: +; CHECK: nill %r3, 31 +; CHECK: sll %r2, 0(%r3) + %and = and i32 %sh, 31 + %shift = shl i32 %a, %and + ret i32 %shift +} + +; Test 64-bit logical shift right. +define i64 @f4(i64 %a, i64 %sh) { +; CHECK-LABEL: f4: +; CHECK: nill %r3, 31 +; CHECK: srlg %r2, %r2, 0(%r3) + %and = and i64 %sh, 31 + %shift = lshr i64 %a, %and + ret i64 %shift +} + +; Test 64-bit arithmetic shift right. +define i64 @f5(i64 %a, i64 %sh) { +; CHECK-LABEL: f5: +; CHECK: nill %r3, 31 +; CHECK: srag %r2, %r2, 0(%r3) + %and = and i64 %sh, 31 + %shift = ashr i64 %a, %and + ret i64 %shift +} + +; Test 64-bit shift left. +define i64 @f6(i64 %a, i64 %sh) { +; CHECK-LABEL: f6: +; CHECK: nill %r3, 31 +; CHECK: sllg %r2, %r2, 0(%r3) + %and = and i64 %sh, 31 + %shift = shl i64 %a, %and + ret i64 %shift +} diff --git a/test/CodeGen/SystemZ/shift-12.ll b/test/CodeGen/SystemZ/shift-12.ll new file mode 100644 index 000000000000..4ebc42b44a47 --- /dev/null +++ b/test/CodeGen/SystemZ/shift-12.ll @@ -0,0 +1,106 @@ +; Test removal of AND operations that don't affect last 6 bits of shift amount +; operand. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test that AND is not removed when some lower 6 bits are not set. +define i32 @f1(i32 %a, i32 %sh) { +; CHECK-LABEL: f1: +; CHECK: nil{{[lf]}} %r3, 31 +; CHECK: sll %r2, 0(%r3) + %and = and i32 %sh, 31 + %shift = shl i32 %a, %and + ret i32 %shift +} + +; Test removal of AND mask with only bottom 6 bits set. +define i32 @f2(i32 %a, i32 %sh) { +; CHECK-LABEL: f2: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: sll %r2, 0(%r3) + %and = and i32 %sh, 63 + %shift = shl i32 %a, %and + ret i32 %shift +} + +; Test removal of AND mask including but not limited to bottom 6 bits. +define i32 @f3(i32 %a, i32 %sh) { +; CHECK-LABEL: f3: +; CHECK-NOT: nil{{[lf]}} %r3, 255 +; CHECK: sll %r2, 0(%r3) + %and = and i32 %sh, 255 + %shift = shl i32 %a, %and + ret i32 %shift +} + +; Test removal of AND mask from SRA. +define i32 @f4(i32 %a, i32 %sh) { +; CHECK-LABEL: f4: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: sra %r2, 0(%r3) + %and = and i32 %sh, 63 + %shift = ashr i32 %a, %and + ret i32 %shift +} + +; Test removal of AND mask from SRL. +define i32 @f5(i32 %a, i32 %sh) { +; CHECK-LABEL: f5: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: srl %r2, 0(%r3) + %and = and i32 %sh, 63 + %shift = lshr i32 %a, %and + ret i32 %shift +} + +; Test removal of AND mask from SLLG. +define i64 @f6(i64 %a, i64 %sh) { +; CHECK-LABEL: f6: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: sllg %r2, %r2, 0(%r3) + %and = and i64 %sh, 63 + %shift = shl i64 %a, %and + ret i64 %shift +} + +; Test removal of AND mask from SRAG. +define i64 @f7(i64 %a, i64 %sh) { +; CHECK-LABEL: f7: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: srag %r2, %r2, 0(%r3) + %and = and i64 %sh, 63 + %shift = ashr i64 %a, %and + ret i64 %shift +} + +; Test removal of AND mask from SRLG. +define i64 @f8(i64 %a, i64 %sh) { +; CHECK-LABEL: f8: +; CHECK-NOT: nil{{[lf]}} %r3, 63 +; CHECK: srlg %r2, %r2, 0(%r3) + %and = and i64 %sh, 63 + %shift = lshr i64 %a, %and + ret i64 %shift +} + +; Test that AND with two register operands is not affected. +define i32 @f9(i32 %a, i32 %b, i32 %sh) { +; CHECK-LABEL: f9: +; CHECK: nr %r3, %r4 +; CHECK: sll %r2, 0(%r3) + %and = and i32 %sh, %b + %shift = shl i32 %a, %and + ret i32 %shift +} + +; Test that AND is not entirely removed if the result is reused. +define i32 @f10(i32 %a, i32 %sh) { +; CHECK-LABEL: f10: +; CHECK: sll %r2, 0(%r3) +; CHECK: nil{{[lf]}} %r3, 63 +; CHECK: ar %r2, %r3 + %and = and i32 %sh, 63 + %shift = shl i32 %a, %and + %reuse = add i32 %and, %shift + ret i32 %reuse +} diff --git a/test/CodeGen/SystemZ/stack-guard.ll b/test/CodeGen/SystemZ/stack-guard.ll new file mode 100644 index 000000000000..0889e7ba941e --- /dev/null +++ b/test/CodeGen/SystemZ/stack-guard.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; CHECK-LABEL: @test_stack_guard +; CHECK: ear [[REG1:%r[1-9][0-9]?]], %a0 +; CHECK: sllg [[REG1]], [[REG1]], 32 +; CHECK: ear [[REG1]], %a1 +; CHECK: lg [[REG1]], 40([[REG1]]) +; CHECK: stg [[REG1]], {{[0-9]*}}(%r15) +; CHECK: brasl %r14, foo3@PLT +; CHECK: ear [[REG2:%r[1-9][0-9]?]], %a0 +; CHECK: sllg [[REG2]], [[REG2]], 32 +; CHECK: ear [[REG2]], %a1 +; CHECK: lg [[REG2]], 40([[REG2]]) +; CHECK: sg [[REG2]], {{[0-9]*}}(%r15) + +define i32 @test_stack_guard() #0 { +entry: + %a1 = alloca [256 x i32], align 4 + %0 = bitcast [256 x i32]* %a1 to i8* + call void @llvm.lifetime.start(i64 1024, i8* %0) + %arraydecay = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i64 0, i64 0 + call void @foo3(i32* %arraydecay) + call void @llvm.lifetime.end(i64 1024, i8* %0) + ret i32 0 +} + +; Function Attrs: nounwind +declare void @llvm.lifetime.start(i64, i8* nocapture) + +declare void @foo3(i32*) + +; Function Attrs: nounwind +declare void @llvm.lifetime.end(i64, i8* nocapture) + +attributes #0 = { sspstrong } diff --git a/test/CodeGen/SystemZ/strcmp-01.ll b/test/CodeGen/SystemZ/strcmp-01.ll index 122c160babaf..a30663a13f1f 100644 --- a/test/CodeGen/SystemZ/strcmp-01.ll +++ b/test/CodeGen/SystemZ/strcmp-01.ll @@ -28,7 +28,7 @@ define void @f2(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK: clst %r2, %r3 ; CHECK-NEXT: jo [[LABEL]] ; CHECK-NEXT: BB#{{[0-9]+}} -; CHECK-NEXT: je {{\.L.*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %res = call i32 @strcmp(i8 *%src1, i8 *%src2) %cmp = icmp eq i32 %res, 0 @@ -54,7 +54,7 @@ define i32 @f3(i8 *%src1, i8 *%src2, i32 *%dest) { ; CHECK-NEXT: ipm [[REG:%r[0-5]]] ; CHECK: srl [[REG]], 28 ; CHECK: rll %r2, [[REG]], 31 -; CHECK: jl {{\.L*}} +; CHECK: blr %r14 ; CHECK: br %r14 entry: %res = call i32 @strcmp(i8 *%src1, i8 *%src2) diff --git a/test/CodeGen/SystemZ/strcmp-02.ll b/test/CodeGen/SystemZ/strcmp-02.ll index 27bd00b47fd3..99d7d9cfa692 100644 --- a/test/CodeGen/SystemZ/strcmp-02.ll +++ b/test/CodeGen/SystemZ/strcmp-02.ll @@ -29,7 +29,7 @@ define void @f2(i8 *%src1, i8 *%src2, i64 *%dest) { ; CHECK: clst %r2, %r3 ; CHECK-NEXT: jo [[LABEL]] ; CHECK-NEXT: BB#{{[0-9]+}} -; CHECK-NEXT: je {{\.L.*}} +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 %res = call i64 @strcmp(i8 *%src1, i8 *%src2) %cmp = icmp eq i64 %res, 0 @@ -56,7 +56,7 @@ define i64 @f3(i8 *%src1, i8 *%src2, i64 *%dest) { ; CHECK: srl [[REG]], 28 ; CHECK: rll [[REG]], [[REG]], 31 ; CHECK: lgfr %r2, [[REG]] -; CHECK: jl {{\.L*}} +; CHECK: blr %r14 ; CHECK: br %r14 entry: %res = call i64 @strcmp(i8 *%src1, i8 *%src2) diff --git a/test/CodeGen/SystemZ/strcmp-nobuiltin.ll b/test/CodeGen/SystemZ/strcmp-nobuiltin.ll new file mode 100644 index 000000000000..187348881a6d --- /dev/null +++ b/test/CodeGen/SystemZ/strcmp-nobuiltin.ll @@ -0,0 +1,54 @@ +; Test that strcmp won't be converted to CLST if calls are +; marked with nobuiltin, eg. for sanitizers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare signext i32 @strcmp(i8 *%src1, i8 *%src2) + +; Check a case where the result is used as an integer. +define i32 @f1(i8 *%src1, i8 *%src2) { +; CHECK-LABEL: f1: +; CHECK-NOT: clst +; CHECK: brasl %r14, strcmp +; CHECK: br %r14 + %res = call i32 @strcmp(i8 *%src1, i8 *%src2) nobuiltin + ret i32 %res +} + +; Check a case where the result is tested for equality. +define void @f2(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f2: +; CHECK-NOT: clst +; CHECK: brasl %r14, strcmp +; CHECK: br %r14 + %res = call i32 @strcmp(i8 *%src1, i8 *%src2) nobuiltin + %cmp = icmp eq i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret void +} + +; Test a case where the result is used both as an integer and for +; branching. +define i32 @f3(i8 *%src1, i8 *%src2, i32 *%dest) { +; CHECK-LABEL: f3: +; CHECK-NOT: clst +; CHECK: brasl %r14, strcmp +; CHECK: br %r14 +entry: + %res = call i32 @strcmp(i8 *%src1, i8 *%src2) nobuiltin + %cmp = icmp slt i32 %res, 0 + br i1 %cmp, label %exit, label %store + +store: + store i32 0, i32 *%dest + br label %exit + +exit: + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/strcpy-nobuiltin.ll b/test/CodeGen/SystemZ/strcpy-nobuiltin.ll new file mode 100644 index 000000000000..746fd67e0840 --- /dev/null +++ b/test/CodeGen/SystemZ/strcpy-nobuiltin.ll @@ -0,0 +1,42 @@ +; Test that strcmp won't be converted to MVST if calls are +; marked with nobuiltin, eg. for sanitizers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i8 *@strcpy(i8 *%dest, i8 *%src) +declare i8 *@stpcpy(i8 *%dest, i8 *%src) + +; Check strcpy. +define i8 *@f1(i8 *%dest, i8 *%src) { +; CHECK-LABEL: f1: +; CHECK-NOT: mvst +; CHECK: brasl %r14, strcpy +; CHECK: br %r14 + %res = call i8 *@strcpy(i8 *%dest, i8 *%src) nobuiltin + ret i8 *%res +} + +; Check stpcpy. +define i8 *@f2(i8 *%dest, i8 *%src) { +; CHECK-LABEL: f2: +; CHECK-NOT: mvst +; CHECK: brasl %r14, stpcpy +; CHECK: br %r14 + %res = call i8 *@stpcpy(i8 *%dest, i8 *%src) nobuiltin + ret i8 *%res +} + +; Check correct operation with other loads and stores. The load must +; come before the loop and the store afterwards. +define i32 @f3(i32 %dummy, i8 *%dest, i8 *%src, i32 *%resptr, i32 *%storeptr) { +; CHECK-LABEL: f3: +; CHECK-DAG: l [[REG1:%r[0-9]+]], 0(%r5) +; CHECK-NOT: mvst +; CHECK: brasl %r14, strcpy +; CHECK: mvhi 0(%r6), 0 +; CHECK: br %r14 + %res = load i32 , i32 *%resptr + %unused = call i8 *@strcpy(i8 *%dest, i8 *%src) nobuiltin + store i32 0, i32 *%storeptr + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/strlen-nobuiltin.ll b/test/CodeGen/SystemZ/strlen-nobuiltin.ll new file mode 100644 index 000000000000..c16e601def35 --- /dev/null +++ b/test/CodeGen/SystemZ/strlen-nobuiltin.ll @@ -0,0 +1,25 @@ +; Test that strlen/strnlen won't be converted to SRST if calls are +; marked with nobuiltin, eg. for sanitizers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i64 @strlen(i8 *%src) +declare i64 @strnlen(i8 *%src, i64 %len) + +define i64 @f1(i32 %dummy, i8 *%src) { +; CHECK-LABEL: f1: +; CHECK: brasl %r14, strlen +; CHECK: br %r14 + %res = call i64 @strlen(i8 *%src) nobuiltin + ret i64 %res +} + +; Likewise for strnlen. +define i64 @f2(i64 %len, i8 *%src) { +; CHECK-LABEL: f2: +; CHECK-NOT: srst +; CHECK: brasl %r14, strnlen +; CHECK: br %r14 + %res = call i64 @strnlen(i8 *%src, i64 %len) nobuiltin + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/swift-return.ll b/test/CodeGen/SystemZ/swift-return.ll new file mode 100644 index 000000000000..e72d6def84e8 --- /dev/null +++ b/test/CodeGen/SystemZ/swift-return.ll @@ -0,0 +1,203 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs | FileCheck --check-prefix=CHECK-O0 %s + +@var = global i32 0 + +; Test how llvm handles return type of {i16, i8}. The return value will be +; passed in %r2 and %r3. +; CHECK-LABEL: test: +; CHECK: st %r2 +; CHECK: brasl %r14, gen +; CHECK-DAG: lhr %r2, %r2 +; CHECK-DAG: lbr %[[REG1:r[0-9]+]], %r3 +; CHECK: ar %r2, %[[REG1]] +; CHECK-O0-LABEL: test +; CHECK-O0: st %r2 +; CHECK-O0: brasl %r14, gen +; CHECK-O0-DAG: lhr %[[REG1:r[0-9]+]], %r2 +; CHECK-O0-DAG: lbr %[[REG2:r[0-9]+]], %r3 +; CHECK-O0: ar %[[REG1]], %[[REG2]] +; CHECK-O0: lr %r2, %[[REG1]] +define i16 @test(i32 %key) { +entry: + %key.addr = alloca i32, align 4 + store i32 %key, i32* %key.addr, align 4 + %0 = load i32, i32* %key.addr, align 4 + %call = call swiftcc { i16, i8 } @gen(i32 %0) + %v3 = extractvalue { i16, i8 } %call, 0 + %v1 = sext i16 %v3 to i32 + %v5 = extractvalue { i16, i8 } %call, 1 + %v2 = sext i8 %v5 to i32 + %add = add nsw i32 %v1, %v2 + %conv = trunc i32 %add to i16 + ret i16 %conv +} + +declare swiftcc { i16, i8 } @gen(i32) + +; If we can't pass every return value in registers, we will pass everything +; in memroy. The caller provides space for the return value and passes +; the address in %r2. The first input argument will be in %r3. +; CHECK-LABEL: test2: +; CHECK: lr %[[REG1:r[0-9]+]], %r2 +; CHECK-DAG: la %r2, 160(%r15) +; CHECK-DAG: lr %r3, %[[REG1]] +; CHECK: brasl %r14, gen2 +; CHECK: l %r2, 160(%r15) +; CHECK: a %r2, 164(%r15) +; CHECK: a %r2, 168(%r15) +; CHECK: a %r2, 172(%r15) +; CHECK: a %r2, 176(%r15) +; CHECK-O0-LABEL: test2: +; CHECK-O0: la %[[REG1:r[0-9]+]], 168(%r15) +; CHECK-O0: st %r2, [[SPILL1:[0-9]+]](%r15) +; CHECK-O0: lgr %r2, %[[REG1]] +; CHECK-O0: l %r3, [[SPILL1]](%r15) +; CHECK-O0: brasl %r14, gen2 +; CHECK-O0-DAG: l %r{{.*}}, 184(%r15) +; CHECK-O0-DAG: l %r{{.*}}, 180(%r15) +; CHECK-O0-DAG: l %r{{.*}}, 176(%r15) +; CHECK-O0-DAG: l %r{{.*}}, 172(%r15) +; CHECK-O0-DAG: l %r{{.*}}, 168(%r15) +; CHECK-O0: ar +; CHECK-O0: ar +; CHECK-O0: ar +; CHECK-O0: ar +; CHECK-O0: lr %r2 +define i32 @test2(i32 %key) #0 { +entry: + %key.addr = alloca i32, align 4 + store i32 %key, i32* %key.addr, align 4 + %0 = load i32, i32* %key.addr, align 4 + %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0) + + %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0 + %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1 + %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2 + %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3 + %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4 + + %add = add nsw i32 %v3, %v5 + %add1 = add nsw i32 %add, %v6 + %add2 = add nsw i32 %add1, %v7 + %add3 = add nsw i32 %add2, %v8 + ret i32 %add3 +} + +; The address of the return value is passed in %r2. +; On return, %r2 will contain the adddress that has been passed in by the caller in %r2. +; CHECK-LABEL: gen2: +; CHECK: st %r3, 16(%r2) +; CHECK: st %r3, 12(%r2) +; CHECK: st %r3, 8(%r2) +; CHECK: st %r3, 4(%r2) +; CHECK: st %r3, 0(%r2) +; CHECK-O0-LABEL: gen2: +; CHECK-O0-DAG: st %r3, 16(%r2) +; CHECK-O0-DAG: st %r3, 12(%r2) +; CHECK-O0-DAG: st %r3, 8(%r2) +; CHECK-O0-DAG: st %r3, 4(%r2) +; CHECK-O0-DAG: st %r3, 0(%r2) +define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) { + %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0 + %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1 + %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2 + %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3 + %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4 + ret { i32, i32, i32, i32, i32 } %Z4 +} + +; The return value {i32, i32, i32, i32} will be returned via registers +; %r2, %r3, %r4, %r5. +; CHECK-LABEL: test3: +; CHECK: brasl %r14, gen3 +; CHECK: ar %r2, %r3 +; CHECK: ar %r2, %r4 +; CHECK: ar %r2, %r5 +; CHECK-O0-LABEL: test3: +; CHECK-O0: brasl %r14, gen3 +; CHECK-O0: ar %r2, %r3 +; CHECK-O0: ar %r2, %r4 +; CHECK-O0: ar %r2, %r5 +define i32 @test3(i32 %key) #0 { +entry: + %key.addr = alloca i32, align 4 + store i32 %key, i32* %key.addr, align 4 + %0 = load i32, i32* %key.addr, align 4 + %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0) + + %v3 = extractvalue { i32, i32, i32, i32 } %call, 0 + %v5 = extractvalue { i32, i32, i32, i32 } %call, 1 + %v6 = extractvalue { i32, i32, i32, i32 } %call, 2 + %v7 = extractvalue { i32, i32, i32, i32 } %call, 3 + + %add = add nsw i32 %v3, %v5 + %add1 = add nsw i32 %add, %v6 + %add2 = add nsw i32 %add1, %v7 + ret i32 %add2 +} + +declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key) + +; The return value {float, float, float, float} will be returned via registers +; %f0, %f2, %f4, %f6. +; CHECK-LABEL: test4: +; CHECK: brasl %r14, gen4 +; CHECK: aebr %f0, %f2 +; CHECK: aebr %f0, %f4 +; CHECK: aebr %f0, %f6 +; CHECK-O0-LABEL: test4: +; CHECK-O0: brasl %r14, gen4 +; CHECK-O0: aebr %f0, %f2 +; CHECK-O0: aebr %f0, %f4 +; CHECK-O0: aebr %f0, %f6 +define float @test4(float %key) #0 { +entry: + %key.addr = alloca float, align 4 + store float %key, float* %key.addr, align 4 + %0 = load float, float* %key.addr, align 4 + %call = call swiftcc { float, float, float, float } @gen4(float %0) + + %v3 = extractvalue { float, float, float, float } %call, 0 + %v5 = extractvalue { float, float, float, float } %call, 1 + %v6 = extractvalue { float, float, float, float } %call, 2 + %v7 = extractvalue { float, float, float, float } %call, 3 + + %add = fadd float %v3, %v5 + %add1 = fadd float %add, %v6 + %add2 = fadd float %add1, %v7 + ret float %add2 +} + +declare swiftcc { float, float, float, float } @gen4(float %key) + +; CHECK-LABEL: consume_i1_ret: +; CHECK: brasl %r14, produce_i1_ret +; CHECK: nilf %r2, 1 +; CHECK: nilf %r3, 1 +; CHECK: nilf %r4, 1 +; CHECK: nilf %r5, 1 +; CHECK-O0-LABEL: consume_i1_ret: +; CHECK-O0: brasl %r14, produce_i1_ret +; CHECK-O0: nilf %r2, 1 +; CHECK-O0: nilf %r3, 1 +; CHECK-O0: nilf %r4, 1 +; CHECK-O0: nilf %r5, 1 +define void @consume_i1_ret() { + %call = call swiftcc { i1, i1, i1, i1 } @produce_i1_ret() + %v3 = extractvalue { i1, i1, i1, i1 } %call, 0 + %v5 = extractvalue { i1, i1, i1, i1 } %call, 1 + %v6 = extractvalue { i1, i1, i1, i1 } %call, 2 + %v7 = extractvalue { i1, i1, i1, i1 } %call, 3 + %val = zext i1 %v3 to i32 + store i32 %val, i32* @var + %val2 = zext i1 %v5 to i32 + store i32 %val2, i32* @var + %val3 = zext i1 %v6 to i32 + store i32 %val3, i32* @var + %val4 = zext i1 %v7 to i32 + store i32 %val4, i32* @var + ret void +} + +declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret() diff --git a/test/CodeGen/SystemZ/swifterror.ll b/test/CodeGen/SystemZ/swifterror.ll new file mode 100644 index 000000000000..90d55eef4aef --- /dev/null +++ b/test/CodeGen/SystemZ/swifterror.ll @@ -0,0 +1,358 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu| FileCheck %s +; RUN: llc < %s -O0 -mtriple=s390x-linux-gnu | FileCheck --check-prefix=CHECK-O0 %s + +declare i8* @malloc(i64) +declare void @free(i8*) +%swift_error = type {i64, i8} + +; This tests the basic usage of a swifterror parameter. "foo" is the function +; that takes a swifterror parameter and "caller" is the caller of "foo". +define float @foo(%swift_error** swifterror %error_ptr_ref) { +; CHECK-LABEL: foo: +; CHECK: lghi %r2, 16 +; CHECK: brasl %r14, malloc +; CHECK: mvi 8(%r2), 1 +; CHECK: lgr %r9, %r2 +; CHECK-O0-LABEL: foo: +; CHECK-O0: lghi %r2, 16 +; CHECK-O0: brasl %r14, malloc +; CHECK-O0: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK-O0: mvi 8(%r2), 1 +; CHECK-O0: lgr %r9, %r[[REG1]] +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + ret float 1.0 +} + +; "caller" calls "foo" that takes a swifterror parameter. +define float @caller(i8* %error_ref) { +; CHECK-LABEL: caller: +; Make a copy of error_ref because r2 is getting clobbered +; CHECK: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK: lghi %r9, 0 +; CHECK: brasl %r14, foo +; CHECK: cgijlh %r9, 0, +; Access part of the error object and save it to error_ref +; CHECK: lb %r[[REG2:[0-9]+]], 8(%r9) +; CHECK: stc %r[[REG2]], 0(%r[[REG1]]) +; CHECK: lgr %r2, %r9 +; CHECK: brasl %r14, free +; CHECK-O0-LABEL: caller: +; CHECK-O0: lghi %r9, 0 +; CHECK-O0: brasl %r14, foo +; CHECK-O0: cghi %r9, 0 +; CHECK-O0: jlh +entry: + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + %call = call float @foo(%swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "caller2" is the caller of "foo", it calls "foo" inside a loop. +define float @caller2(i8* %error_ref) { +; CHECK-LABEL: caller2: +; Make a copy of error_ref because r2 is getting clobbered +; CHECK: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK: lghi %r9, 0 +; CHECK: brasl %r14, foo +; CHECK: cgijlh %r9, 0, +; CHECK: ceb %f0, +; CHECK: jnh +; Access part of the error object and save it to error_ref +; CHECK: lb %r[[REG2:[0-9]+]], 8(%r9) +; CHECK: stc %r[[REG2]], 0(%r[[REG1]]) +; CHECK: lgr %r2, %r9 +; CHECK: brasl %r14, free +; CHECK-O0-LABEL: caller2: +; CHECK-O0: lghi %r9, 0 +; CHECK-O0: brasl %r14, foo +; CHECK-O0: cghi %r9, 0 +; CHECK-O0: jlh +entry: + %error_ptr_ref = alloca swifterror %swift_error* + br label %bb_loop +bb_loop: + store %swift_error* null, %swift_error** %error_ptr_ref + %call = call float @foo(%swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %cmp = fcmp ogt float %call, 1.000000e+00 + br i1 %cmp, label %bb_end, label %bb_loop +bb_end: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "foo_if" is a function that takes a swifterror parameter, it sets swifterror +; under a certain condition. +define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) { +; CHECK-LABEL: foo_if: +; CHECK: cije %r2, 0 +; CHECK: lghi %r2, 16 +; CHECK: brasl %r14, malloc +; CHECK: mvi 8(%r2), 1 +; CHECK: lgr %r9, %r2 +; CHECK-NOT: %r9 +; CHECK: br %r14 +; CHECK-O0-LABEL: foo_if: +; CHECK-O0: chi %r2, 0 +; spill to stack +; CHECK-O0: stg %r9, [[OFFS:[0-9]+]](%r15) +; CHECK-O0: je +; CHECK-O0: lghi %r2, 16 +; CHECK-O0: brasl %r14, malloc +; CHECK-O0: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK-O0: mvi 8(%r2), 1 +; CHECK-O0: lgr %r9, %r[[REG1]] +; CHECK-O0: br %r14 +; reload from stack +; CHECK-O0: lg %r9, [[OFFS]](%r15) +; CHECK-O0: br %r14 +entry: + %cond = icmp ne i32 %cc, 0 + br i1 %cond, label %gen_error, label %normal + +gen_error: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + ret float 1.0 + +normal: + ret float 0.0 +} + +; "foo_loop" is a function that takes a swifterror parameter, it sets swifterror +; under a certain condition inside a loop. +define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) { +; CHECK-LABEL: foo_loop: +; CHECK: lr %r[[REG1:[0-9]+]], %r2 +; CHECK: cije %r[[REG1]], 0 +; CHECK: lghi %r2, 16 +; CHECK: brasl %r14, malloc +; CHECK: mvi 8(%r2), 1 +; CHECK: ceb %f8, +; CHECK: jnh +; CHECK: lgr %r9, %r2 +; CHECK: br %r14 +; CHECK-O0-LABEL: foo_loop: +; spill to stack +; CHECK-O0: stg %r9, [[OFFS:[0-9]+]](%r15) +; CHECK-O0: chi %r{{.*}}, 0 +; CHECK-O0: je +; CHECK-O0: lghi %r2, 16 +; CHECK-O0: brasl %r14, malloc +; CHECK-O0: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK-O0: mvi 8(%r2), 1 +; CHECK-O0: jnh +; reload from stack +; CHECK-O0: lg %r9, [[OFFS:[0-9]+]](%r15) +; CHECK-O0: br %r14 +entry: + br label %bb_loop + +bb_loop: + %cond = icmp ne i32 %cc, 0 + br i1 %cond, label %gen_error, label %bb_cont + +gen_error: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + br label %bb_cont + +bb_cont: + %cmp = fcmp ogt float %cc2, 1.000000e+00 + br i1 %cmp, label %bb_end, label %bb_loop +bb_end: + ret float 0.0 +} + +%struct.S = type { i32, i32, i32, i32, i32, i32 } + +; "foo_sret" is a function that takes a swifterror parameter, it also has a sret +; parameter. +define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +; CHECK-LABEL: foo_sret: +; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK-DAG: lr %r[[REG2:[0-9]+]], %r3 +; CHECK: lghi %r2, 16 +; CHECK: brasl %r14, malloc +; CHECK: mvi 8(%r2), 1 +; CHECK: st %r[[REG2]], 4(%r[[REG1]]) +; CHECK: lgr %r9, %r2 +; CHECK-NOT: %r9 +; CHECK: br %r14 + +; CHECK-O0-LABEL: foo_sret: +; CHECK-O0: lghi %r{{.*}}, 16 +; spill sret to stack +; CHECK-O0: stg %r2, [[OFFS1:[0-9]+]](%r15) +; CHECK-O0: lgr %r2, %r{{.*}} +; CHECK-O0: st %r3, [[OFFS2:[0-9]+]](%r15) +; CHECK-O0: brasl %r14, malloc +; CHECK-O0: lgr {{.*}}, %r2 +; CHECK-O0: mvi 8(%r2), 1 +; CHECK-O0-DAG: lg %r[[REG1:[0-9]+]], [[OFFS1]](%r15) +; CHECK-O0-DAG: l %r[[REG2:[0-9]+]], [[OFFS2]](%r15) +; CHECK-O0: st %r[[REG2]], 4(%r[[REG1]]) +; CHECK-O0: lgr %r9, {{.*}} +; CHECK-O0: br %r14 +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + %v2 = getelementptr inbounds %struct.S, %struct.S* %agg.result, i32 0, i32 1 + store i32 %val1, i32* %v2 + ret void +} + +; "caller3" calls "foo_sret" that takes a swifterror parameter. +define float @caller3(i8* %error_ref) { +; CHECK-LABEL: caller3: +; Make a copy of error_ref because r2 is getting clobbered +; CHECK: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK: lhi %r3, 1 +; CHECK: lghi %r9, 0 +; CHECK: brasl %r14, foo_sret +; CHECK: cgijlh %r9, 0, +; Access part of the error object and save it to error_ref +; CHECK: lb %r0, 8(%r9) +; CHECK: stc %r0, 0(%r[[REG1]]) +; CHECK: lgr %r2, %r9 +; CHECK: brasl %r14, free + +; CHECK-O0-LABEL: caller3: +; CHECK-O0: lghi %r9, 0 +; CHECK-O0: lhi %r3, 1 +; CHECK-O0: stg %r2, {{.*}}(%r15) +; CHECK-O0: lgr %r2, {{.*}} +; CHECK-O0: brasl %r14, foo_sret +; CHECK-O0: lgr {{.*}}, %r9 +; CHECK-O0: cghi %r9, 0 +; CHECK-O0: jlh +; Access part of the error object and save it to error_ref +; CHECK-O0: lb %r0, 8(%r{{.*}}) +; CHECK-O0: stc %r0, 0(%r{{.*}}) +; reload from stack +; CHECK-O0: lg %r2, {{.*}}(%r15) +; CHECK-O0: brasl %r14, free +entry: + %s = alloca %struct.S, align 8 + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; This is a caller with multiple swifterror values, it calls "foo" twice, each +; time with a different swifterror value, from "alloca swifterror". +define float @caller_with_multiple_swifterror_values(i8* %error_ref, i8* %error_ref2) { +; CHECK-LABEL: caller_with_multiple_swifterror_values: +; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2 +; CHECK-DAG: lgr %r[[REG2:[0-9]+]], %r3 +; The first swifterror value: +; CHECK: lghi %r9, 0 +; CHECK: brasl %r14, foo +; CHECK: cgijlh %r9, 0, +; Access part of the error object and save it to error_ref +; CHECK: lb %r0, 8(%r9) +; CHECK: stc %r0, 0(%r[[REG1]]) +; CHECK: lgr %r2, %r9 +; CHECK: brasl %r14, free + +; The second swifterror value: +; CHECK: lghi %r9, 0 +; CHECK: brasl %r14, foo +; CHECK: cgijlh %r9, 0, +; Access part of the error object and save it to error_ref +; CHECK: lb %r0, 8(%r9) +; CHECK: stc %r0, 0(%r[[REG2]]) +; CHECK: lgr %r2, %r9 +; CHECK: brasl %r14, free + +; CHECK-O0-LABEL: caller_with_multiple_swifterror_values: + +; The first swifterror value: +; CHECK-O0: lghi %r9, 0 +; CHECK-O0: brasl %r14, foo +; CHECK-O0: jlh + +; The second swifterror value: +; CHECK-O0: lghi %r9, 0 +; CHECK-O0: brasl %r14, foo +; CHECK-O0: jlh +entry: + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + %call = call float @foo(%swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + + %error_ptr_ref2 = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref2 + %call2 = call float @foo(%swift_error** swifterror %error_ptr_ref2) + %error_from_foo2 = load %swift_error*, %swift_error** %error_ptr_ref2 + %had_error_from_foo2 = icmp ne %swift_error* %error_from_foo2, null + %bitcast2 = bitcast %swift_error* %error_from_foo2 to i8* + br i1 %had_error_from_foo2, label %handler2, label %cont2 +cont2: + %v2 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo2, i64 0, i32 1 + %t2 = load i8, i8* %v2 + store i8 %t2, i8* %error_ref2 + br label %handler2 +handler2: + call void @free(i8* %bitcast2) + + ret float 1.0 +} diff --git a/test/CodeGen/SystemZ/swiftself.ll b/test/CodeGen/SystemZ/swiftself.ll new file mode 100644 index 000000000000..ee6104ad2039 --- /dev/null +++ b/test/CodeGen/SystemZ/swiftself.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Parameter with swiftself should be allocated to r10. +; CHECK-LABEL: swiftself_param: +; CHECK: lgr %r2, %r10 +define i8 *@swiftself_param(i8* swiftself %addr0) { + ret i8 *%addr0 +} + +; Check that r10 is used to pass a swiftself argument. +; CHECK-LABEL: call_swiftself: +; CHECK: lgr %r10, %r2 +; CHECK: brasl %r14, swiftself_param +define i8 *@call_swiftself(i8* %arg) { + %res = call i8 *@swiftself_param(i8* swiftself %arg) + ret i8 *%res +} + +; r10 should be saved by the callee even if used for swiftself +; CHECK-LABEL: swiftself_clobber: +; CHECK: stmg %r10, +; ... +; CHECK: lmg %r10, +; CHECK: br %r14 +define i8 *@swiftself_clobber(i8* swiftself %addr0) { + call void asm sideeffect "", "~{r10}"() + ret i8 *%addr0 +} + +; Demonstrate that we do not need any loads when calling multiple functions +; with swiftself argument. +; CHECK-LABEL: swiftself_passthrough: +; CHECK-NOT: lg{{.*}}r10, +; CHECK: brasl %r14, swiftself_param +; CHECK-NOT: lg{{.*}}r10, +; CHECK-NEXT: brasl %r14, swiftself_param +define void @swiftself_passthrough(i8* swiftself %addr0) { + call i8 *@swiftself_param(i8* swiftself %addr0) + call i8 *@swiftself_param(i8* swiftself %addr0) + ret void +} + +; Normally, we can use a tail call if the callee swiftself is the same as the +; caller one. Not yet supported on SystemZ. +; CHECK-LABEL: swiftself_tail: +; CHECK: lgr %r[[REG1:[0-9]+]], %r10 +; CHECK: lgr %r10, %r[[REG1]] +; CHECK: brasl %r14, swiftself_param +; CHECK: br %r14 +define i8* @swiftself_tail(i8* swiftself %addr0) { + call void asm sideeffect "", "~{r10}"() + %res = tail call i8* @swiftself_param(i8* swiftself %addr0) + ret i8* %res +} + +; We can not use a tail call if the callee swiftself is not the same as the +; caller one. +; CHECK-LABEL: swiftself_notail: +; CHECK: lgr %r10, %r2 +; CHECK: brasl %r14, swiftself_param +; CHECK: lmg %r10, +; CHECK: br %r14 +define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind { + %res = tail call i8* @swiftself_param(i8* swiftself %addr1) + ret i8* %res +} diff --git a/test/CodeGen/SystemZ/tdc-01.ll b/test/CodeGen/SystemZ/tdc-01.ll new file mode 100644 index 000000000000..052d895b798f --- /dev/null +++ b/test/CodeGen/SystemZ/tdc-01.ll @@ -0,0 +1,95 @@ +; Test the Test Data Class instruction, selected manually via the intrinsic. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i32 @llvm.s390.tdc.f32(float, i64) +declare i32 @llvm.s390.tdc.f64(double, i64) +declare i32 @llvm.s390.tdc.f128(fp128, i64) + +; Check using as i32 - f32 +define i32 @f1(float %x) { +; CHECK-LABEL: f1 +; CHECK: tceb %f0, 123 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 + %res = call i32 @llvm.s390.tdc.f32(float %x, i64 123) + ret i32 %res +} + +; Check using as i32 - f64 +define i32 @f2(double %x) { +; CHECK-LABEL: f2 +; CHECK: tcdb %f0, 123 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 + %res = call i32 @llvm.s390.tdc.f64(double %x, i64 123) + ret i32 %res +} + +; Check using as i32 - f128 +define i32 @f3(fp128 %x) { +; CHECK-LABEL: f3 +; CHECK: ld %f0, 0(%r2) +; CHECK: ld %f2, 8(%r2) +; CHECK: tcxb %f0, 123 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 + %res = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 123) + ret i32 %res +} + +declare void @g() + +; Check branch +define void @f4(float %x) { +; CHECK-LABEL: f4 +; CHECK: tceb %f0, 123 +; CHECK: jgl g +; CHECK: br %r14 + %res = call i32 @llvm.s390.tdc.f32(float %x, i64 123) + %cond = icmp ne i32 %res, 0 + br i1 %cond, label %call, label %exit + +call: + tail call void @g() + br label %exit + +exit: + ret void +} + +; Check branch negated +define void @f5(float %x) { +; CHECK-LABEL: f5 +; CHECK: tceb %f0, 123 +; CHECK: jge g +; CHECK: br %r14 + %res = call i32 @llvm.s390.tdc.f32(float %x, i64 123) + %cond = icmp eq i32 %res, 0 + br i1 %cond, label %call, label %exit + +call: + tail call void @g() + br label %exit + +exit: + ret void +} + +; Check non-const mask +define void @f6(float %x, i64 %y) { +; CHECK-LABEL: f6 +; CHECK: tceb %f0, 0(%r2) +; CHECK: jge g +; CHECK: br %r14 + %res = call i32 @llvm.s390.tdc.f32(float %x, i64 %y) + %cond = icmp eq i32 %res, 0 + br i1 %cond, label %call, label %exit + +call: + tail call void @g() + br label %exit + +exit: + ret void +} diff --git a/test/CodeGen/SystemZ/tdc-02.ll b/test/CodeGen/SystemZ/tdc-02.ll new file mode 100644 index 000000000000..c0c4ac84349e --- /dev/null +++ b/test/CodeGen/SystemZ/tdc-02.ll @@ -0,0 +1,96 @@ +; Test the Test Data Class instruction logic operation folding. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i32 @llvm.s390.tdc.f32(float, i64) +declare i32 @llvm.s390.tdc.f64(double, i64) +declare i32 @llvm.s390.tdc.f128(fp128, i64) + +; Check using or i1 +define i32 @f1(float %x) { +; CHECK-LABEL: f1 +; CHECK: tceb %f0, 7 +; CHECK-NEXT: ipm [[REG1:%r[0-9]+]] +; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36 + %a = call i32 @llvm.s390.tdc.f32(float %x, i64 3) + %b = call i32 @llvm.s390.tdc.f32(float %x, i64 6) + %a1 = icmp ne i32 %a, 0 + %b1 = icmp ne i32 %b, 0 + %res = or i1 %a1, %b1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Check using and i1 +define i32 @f2(double %x) { +; CHECK-LABEL: f2 +; CHECK: tcdb %f0, 2 +; CHECK-NEXT: ipm [[REG1:%r[0-9]+]] +; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36 + %a = call i32 @llvm.s390.tdc.f64(double %x, i64 3) + %b = call i32 @llvm.s390.tdc.f64(double %x, i64 6) + %a1 = icmp ne i32 %a, 0 + %b1 = icmp ne i32 %b, 0 + %res = and i1 %a1, %b1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Check using xor i1 +define i32 @f3(fp128 %x) { +; CHECK-LABEL: f3 +; CHECK: tcxb %f0, 5 +; CHECK-NEXT: ipm [[REG1:%r[0-9]+]] +; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36 + %a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3) + %b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6) + %a1 = icmp ne i32 %a, 0 + %b1 = icmp ne i32 %b, 0 + %res = xor i1 %a1, %b1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Check using xor i1 - negated test +define i32 @f4(fp128 %x) { +; CHECK-LABEL: f4 +; CHECK: tcxb %f0, 4090 +; CHECK-NEXT: ipm [[REG1:%r[0-9]+]] +; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36 + %a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3) + %b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6) + %a1 = icmp ne i32 %a, 0 + %b1 = icmp eq i32 %b, 0 + %res = xor i1 %a1, %b1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Check different first args +define i32 @f5(float %x, float %y) { +; CHECK-LABEL: f5 +; CHECK-NOT: tceb {{%f[0-9]+}}, 5 +; CHECK-DAG: tceb %f0, 3 +; CHECK-DAG: tceb %f2, 6 + %a = call i32 @llvm.s390.tdc.f32(float %x, i64 3) + %b = call i32 @llvm.s390.tdc.f32(float %y, i64 6) + %a1 = icmp ne i32 %a, 0 + %b1 = icmp ne i32 %b, 0 + %res = xor i1 %a1, %b1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Non-const mask (not supported) +define i32 @f6(float %x, i64 %y) { +; CHECK-LABEL: f6 +; CHECK-DAG: tceb %f0, 0(%r2) +; CHECK-DAG: tceb %f0, 6 + %a = call i32 @llvm.s390.tdc.f32(float %x, i64 %y) + %b = call i32 @llvm.s390.tdc.f32(float %x, i64 6) + %a1 = icmp ne i32 %a, 0 + %b1 = icmp ne i32 %b, 0 + %res = xor i1 %a1, %b1 + %xres = zext i1 %res to i32 + ret i32 %xres +} diff --git a/test/CodeGen/SystemZ/tdc-03.ll b/test/CodeGen/SystemZ/tdc-03.ll new file mode 100644 index 000000000000..95708f1effc6 --- /dev/null +++ b/test/CodeGen/SystemZ/tdc-03.ll @@ -0,0 +1,139 @@ +; Test the Test Data Class instruction logic operation conversion from +; compares. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare float @llvm.fabs.f32(float) +declare double @llvm.fabs.f64(double) +declare fp128 @llvm.fabs.f128(fp128) + +; Compare with 0 (unworthy) +define i32 @f1(float %x) { +; CHECK-LABEL: f1 +; CHECK-NOT: tceb +; CHECK: ltebr {{%f[0-9]+}}, %f0 +; CHECK-NOT: tceb + %res = fcmp ugt float %x, 0.0 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs with 0 (unworthy) +define i32 @f2(float %x) { +; CHECK-LABEL: f2 +; CHECK-NOT: tceb +; CHECK: lpebr {{%f[0-9]+}}, %f0 +; CHECK-NOT: tceb + %y = call float @llvm.fabs.f32(float %x) + %res = fcmp ugt float %y, 0.0 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare with inf (unworthy) +define i32 @f3(float %x) { +; CHECK-LABEL: f3 +; CHECK-NOT: tceb +; CHECK: ceb %f0, 0(%r{{[0-9]+}}) +; CHECK-NOT: tceb + %res = fcmp ult float %x, 0x7ff0000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs with inf +define i32 @f4(float %x) { +; CHECK-LABEL: f4 +; CHECK: tceb %f0, 4047 + %y = call float @llvm.fabs.f32(float %x) + %res = fcmp ult float %y, 0x7ff0000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare with minnorm (unworthy) +define i32 @f5(float %x) { +; CHECK-LABEL: f5 +; CHECK-NOT: tceb +; CHECK: ceb %f0, 0(%r{{[0-9]+}}) +; CHECK-NOT: tceb + %res = fcmp ult float %x, 0x3810000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs with minnorm +define i32 @f6(float %x) { +; CHECK-LABEL: f6 +; CHECK: tceb %f0, 3279 + %y = call float @llvm.fabs.f32(float %x) + %res = fcmp ult float %y, 0x3810000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs with minnorm, unsupported condition +define i32 @f7(float %x) { +; CHECK-LABEL: f7 +; CHECK-NOT: tceb +; CHECK: lpdfr [[REG:%f[0-9]+]], %f0 +; CHECK: ceb [[REG]], 0(%r{{[0-9]+}}) +; CHECK-NOT: tceb + %y = call float @llvm.fabs.f32(float %x) + %res = fcmp ugt float %y, 0x3810000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs with unsupported constant +define i32 @f8(float %x) { +; CHECK-LABEL: f8 +; CHECK-NOT: tceb +; CHECK: lpdfr [[REG:%f[0-9]+]], %f0 +; CHECK: ceb [[REG]], 0(%r{{[0-9]+}}) +; CHECK-NOT: tceb + %y = call float @llvm.fabs.f32(float %x) + %res = fcmp ult float %y, 0x3ff0000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs with minnorm - double +define i32 @f9(double %x) { +; CHECK-LABEL: f9 +; CHECK: tcdb %f0, 3279 + %y = call double @llvm.fabs.f64(double %x) + %res = fcmp ult double %y, 0x0010000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs with minnorm - long double +define i32 @f10(fp128 %x) { +; CHECK-LABEL: f10 +; CHECK: tcxb %f0, 3279 + %y = call fp128 @llvm.fabs.f128(fp128 %x) + %res = fcmp ult fp128 %y, 0xL00000000000000000001000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs for one with inf - clang's isfinite +define i32 @f11(double %x) { +; CHECK-LABEL: f11 +; CHECK: tcdb %f0, 4032 + %y = call double @llvm.fabs.f64(double %x) + %res = fcmp one double %y, 0x7ff0000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare fabs for oeq with inf - clang's isinf +define i32 @f12(double %x) { +; CHECK-LABEL: f12 +; CHECK: tcdb %f0, 48 + %y = call double @llvm.fabs.f64(double %x) + %res = fcmp oeq double %y, 0x7ff0000000000000 + %xres = zext i1 %res to i32 + ret i32 %xres +} diff --git a/test/CodeGen/SystemZ/tdc-04.ll b/test/CodeGen/SystemZ/tdc-04.ll new file mode 100644 index 000000000000..929285b0ba8f --- /dev/null +++ b/test/CodeGen/SystemZ/tdc-04.ll @@ -0,0 +1,85 @@ +; Test the Test Data Class instruction logic operation conversion from +; signbit extraction. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; + +; Extract sign bit. +define i32 @f1(float %x) { +; CHECK-LABEL: f1 +; CHECK: tceb %f0, 1365 + %cast = bitcast float %x to i32 + %res = icmp slt i32 %cast, 0 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Extract negated sign bit. +define i32 @f2(float %x) { +; CHECK-LABEL: f2 +; CHECK: tceb %f0, 2730 + %cast = bitcast float %x to i32 + %res = icmp sgt i32 %cast, -1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Extract sign bit. +define i32 @f3(double %x) { +; CHECK-LABEL: f3 +; CHECK: tcdb %f0, 1365 + %cast = bitcast double %x to i64 + %res = icmp slt i64 %cast, 0 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Extract negated sign bit. +define i32 @f4(double %x) { +; CHECK-LABEL: f4 +; CHECK: tcdb %f0, 2730 + %cast = bitcast double %x to i64 + %res = icmp sgt i64 %cast, -1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Extract sign bit. +define i32 @f5(fp128 %x) { +; CHECK-LABEL: f5 +; CHECK: tcxb %f0, 1365 + %cast = bitcast fp128 %x to i128 + %res = icmp slt i128 %cast, 0 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Extract negated sign bit. +define i32 @f6(fp128 %x) { +; CHECK-LABEL: f6 +; CHECK: tcxb %f0, 2730 + %cast = bitcast fp128 %x to i128 + %res = icmp sgt i128 %cast, -1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Wrong const. +define i32 @f7(float %x) { +; CHECK-LABEL: f7 +; CHECK-NOT: tceb + %cast = bitcast float %x to i32 + %res = icmp slt i32 %cast, -1 + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Wrong pred. +define i32 @f8(float %x) { +; CHECK-LABEL: f8 +; CHECK-NOT: tceb + %cast = bitcast float %x to i32 + %res = icmp eq i32 %cast, 0 + %xres = zext i1 %res to i32 + ret i32 %xres +} diff --git a/test/CodeGen/SystemZ/tdc-05.ll b/test/CodeGen/SystemZ/tdc-05.ll new file mode 100644 index 000000000000..c639a9b7b475 --- /dev/null +++ b/test/CodeGen/SystemZ/tdc-05.ll @@ -0,0 +1,97 @@ +; Test the Test Data Class instruction logic operation conversion from +; compares, combined with signbit or other compares to ensure worthiness. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; + +declare float @llvm.fabs.f32(float) +declare double @llvm.fabs.f64(double) +declare fp128 @llvm.fabs.f128(fp128) + +; Compare with 0, extract sign bit +define i32 @f1(float %x) { +; CHECK-LABEL: f1 +; CHECK: tceb %f0, 2047 + %cast = bitcast float %x to i32 + %sign = icmp slt i32 %cast, 0 + %fcmp = fcmp ugt float %x, 0.0 + %res = or i1 %sign, %fcmp + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare with inf, extract negated sign bit +define i32 @f2(float %x) { +; CHECK-LABEL: f2 +; CHECK: tceb %f0, 2698 + %cast = bitcast float %x to i32 + %sign = icmp sgt i32 %cast, -1 + %fcmp = fcmp ult float %x, 0x7ff0000000000000 + %res = and i1 %sign, %fcmp + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Compare with minnorm, extract negated sign bit +define i32 @f3(float %x) { +; CHECK-LABEL: f3 +; CHECK: tceb %f0, 2176 + %cast = bitcast float %x to i32 + %sign = icmp sgt i32 %cast, -1 + %fcmp = fcmp olt float %x, 0x3810000000000000 + %res = and i1 %sign, %fcmp + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Test float isnormal, from clang. +define i32 @f4(float %x) { +; CHECK-LABEL: f4 +; CHECK: tceb %f0, 768 + %y = call float @llvm.fabs.f32(float %x) + %ord = fcmp ord float %x, 0.0 + %a = fcmp ult float %y, 0x7ff0000000000000 + %b = fcmp uge float %y, 0x3810000000000000 + %c = and i1 %a, %b + %res = and i1 %ord, %c + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Check for negative 0. +define i32 @f5(float %x) { +; CHECK-LABEL: f5 +; CHECK: tceb %f0, 1024 + %cast = bitcast float %x to i32 + %sign = icmp slt i32 %cast, 0 + %fcmp = fcmp oeq float %x, 0.0 + %res = and i1 %sign, %fcmp + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Test isnormal, from clang. +define i32 @f6(double %x) { +; CHECK-LABEL: f6 +; CHECK: tcdb %f0, 768 + %y = call double @llvm.fabs.f64(double %x) + %ord = fcmp ord double %x, 0.0 + %a = fcmp ult double %y, 0x7ff0000000000000 + %b = fcmp uge double %y, 0x0010000000000000 + %c = and i1 %ord, %a + %res = and i1 %b, %c + %xres = zext i1 %res to i32 + ret i32 %xres +} + +; Test isinf || isnan, from clang. +define i32 @f7(double %x) { +; CHECK-LABEL: f7 +; CHECK: tcdb %f0, 63 + %y = call double @llvm.fabs.f64(double %x) + %a = fcmp oeq double %y, 0x7ff0000000000000 + %b = fcmp uno double %x, 0.0 + %res = or i1 %a, %b + %xres = zext i1 %res to i32 + ret i32 %xres +} diff --git a/test/CodeGen/SystemZ/tdc-06.ll b/test/CodeGen/SystemZ/tdc-06.ll new file mode 100644 index 000000000000..11fb1e2916e0 --- /dev/null +++ b/test/CodeGen/SystemZ/tdc-06.ll @@ -0,0 +1,48 @@ +; Test the Test Data Class instruction, as used by fpclassify. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; + +declare float @llvm.fabs.f32(float) +declare double @llvm.fabs.f64(double) +declare fp128 @llvm.fabs.f128(fp128) + +define i32 @fpc(double %x) { +entry: +; CHECK-LABEL: fpc +; CHECK: lhi %r2, 5 +; CHECK: ltdbr %f0, %f0 +; CHECK: je [[RET:.L.*]] + %testeq = fcmp oeq double %x, 0.000000e+00 + br i1 %testeq, label %ret, label %nonzero + +nonzero: +; CHECK: lhi %r2, 1 +; CHECK: cdbr %f0, %f0 +; CHECK: jo [[RET]] + %testnan = fcmp uno double %x, 0.000000e+00 + br i1 %testnan, label %ret, label %nonzeroord + +nonzeroord: +; CHECK: lhi %r2, 2 +; CHECK: tcdb %f0, 48 +; CHECK: jl [[RET]] + %abs = tail call double @llvm.fabs.f64(double %x) + %testinf = fcmp oeq double %abs, 0x7FF0000000000000 + br i1 %testinf, label %ret, label %finite + +finite: +; CHECK: lhi %r2, 3 +; CHECK: tcdb %f0, 831 +; CHECK: blr %r14 +; CHECK: lhi %r2, 4 + %testnormal = fcmp uge double %abs, 0x10000000000000 + %finres = select i1 %testnormal, i32 3, i32 4 + br label %ret + +ret: +; CHECK: [[RET]]: +; CHECK: br %r14 + %res = phi i32 [ 5, %entry ], [ 1, %nonzero ], [ 2, %nonzeroord ], [ %finres, %finite ] + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/trap-01.ll b/test/CodeGen/SystemZ/trap-01.ll new file mode 100644 index 000000000000..3a766d9e8e3b --- /dev/null +++ b/test/CodeGen/SystemZ/trap-01.ll @@ -0,0 +1,179 @@ +; Test traps and conditional traps +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare void @llvm.trap() + +; Check unconditional traps +define i32 @f0() { +; CHECK-LABEL: f0: +; CHECK-LABEL: .Ltmp0 +; CHECK: j .Ltmp0+2 +entry: + tail call void @llvm.trap() + ret i32 0 +} + +; Check conditional compare immediate and trap +define i32 @f1(i32 signext %a) { +; CHECK-LABEL: f1: +; CHECK: cithe %r2, 15 +; CHECK: lhi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp sgt i32 %a, 14 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i32 0 +} + +; Check conditional compare grande immediate and trap +define i64 @f2(i64 signext %a) { +; CHECK-LABEL: f2: +; CHECK: cgitle %r2, 14 +; CHECK: lghi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp slt i64 %a, 15 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i64 0 +} + +; Check conditional compare logical immediate and trap +define i32 @f3(i32 zeroext %a) { +; CHECK-LABEL: f3: +; CHECK: clfithe %r2, 15 +; CHECK: lhi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp ugt i32 %a, 14 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i32 0 +} + +; Check conditional compare grande logical immediate and trap +define i64 @f4(i64 zeroext %a) { +; CHECK-LABEL: f4: +; CHECK: clgitle %r2, 14 +; CHECK: lghi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp ult i64 %a, 15 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i64 0 +} + +; Check conditional compare and trap +define i32 @f5(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: f5: +; CHECK: crte %r2, %r3 +; CHECK: lhi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp eq i32 %a, %b + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i32 0 +} + +; Check conditional compare grande and trap +define i64 @f6(i64 signext %a, i64 signext %b) { +; CHECK-LABEL: f6: +; CHECK: cgrtl %r2, %r3 +; CHECK: lghi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp slt i64 %a, %b + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i64 0 +} + +; Check conditional compare logical and trap +define i32 @f7(i32 zeroext %a, i32 zeroext %b) { +; CHECK-LABEL: f7: +; CHECK: clrth %r2, %r3 +; CHECK: lhi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp ugt i32 %a, %b + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i32 0 +} + +; Check conditional compare logical grande and trap +define i64 @f8(i64 zeroext %a, i64 zeroext %b) { +; CHECK-LABEL: f8: +; CHECK: clgrtl %r2, %r3 +; CHECK: lghi %r2, 0 +; CHECK: br %r14 +entry: + %cmp = icmp ult i64 %a, %b + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret i64 0 +} + +; Check conditional traps that don't have a valid Compare and Trap +define double @f9(double %a, double %b) { +; CHECK-LABEL: f9: +; CHECK: cdbr %f0, %f2 +; CHECK-LABEL: .Ltmp1 +; CHECK: je .Ltmp1+2 +; CHECK: lzdr %f0 +; CHECK: br %r14 +entry: + %cmp = fcmp oeq double %a, %b + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @llvm.trap() + unreachable + +if.end: ; preds = %entry + ret double 0.000000e+00 +} diff --git a/test/CodeGen/SystemZ/vec-extract-02.ll b/test/CodeGen/SystemZ/vec-extract-02.ll index c91e852fcf45..a87b7d52771b 100644 --- a/test/CodeGen/SystemZ/vec-extract-02.ll +++ b/test/CodeGen/SystemZ/vec-extract-02.ll @@ -6,7 +6,7 @@ ; The index must be extended from i32 to i64. define i32 @f1(<4 x i32> *%ptr, i32 %index) { ; CHECK-LABEL: f1: -; CHECK: risbg {{%r[0-5]}}, %r3, 30, 189, 2 +; CHECK: risbgn {{%r[0-5]}}, %r3, 30, 189, 2 ; CHECK: l %r2, ; CHECK: br %r14 %vec = load <4 x i32>, <4 x i32> *%ptr diff --git a/test/CodeGen/SystemZ/vec-intrinsics.ll b/test/CodeGen/SystemZ/vec-intrinsics.ll index 55527787da4c..6f5eb0691aa8 100644 --- a/test/CodeGen/SystemZ/vec-intrinsics.ll +++ b/test/CodeGen/SystemZ/vec-intrinsics.ll @@ -396,7 +396,7 @@ define <16 x i8> @test_vpkshs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { define <16 x i8> @test_vpkshs_all_store(<8 x i16> %a, <8 x i16> %b, i32 *%ptr) { ; CHECK-LABEL: test_vpkshs_all_store: ; CHECK: vpkshs %v24, %v24, %v26 -; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK-NEXT: {{bnor|bler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b) @@ -432,7 +432,7 @@ define <8 x i16> @test_vpksfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { define <8 x i16> @test_vpksfs_any_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) { ; CHECK-LABEL: test_vpksfs_any_store: ; CHECK: vpksfs %v24, %v24, %v26 -; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK-NEXT: {{bher|ber}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b) @@ -469,7 +469,7 @@ define <4 x i32> @test_vpksgs_none_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { ; CHECK-LABEL: test_vpksgs_none_store: ; CHECK: vpksgs %v24, %v24, %v26 -; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK-NEXT: {{bnher|bner}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b) @@ -533,7 +533,7 @@ define <16 x i8> @test_vpklshs_all_store(<8 x i16> %a, <8 x i16> %b, i32 *%ptr) { ; CHECK-LABEL: test_vpklshs_all_store: ; CHECK: vpklshs %v24, %v24, %v26 -; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK-NEXT: {{bnor|bler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b) @@ -570,7 +570,7 @@ define <8 x i16> @test_vpklsfs_any_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) { ; CHECK-LABEL: test_vpklsfs_any_store: ; CHECK: vpklsfs %v24, %v24, %v26 -; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK-NEXT: {{bher|ber}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b) @@ -607,7 +607,7 @@ define <4 x i32> @test_vpklsgs_none_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { ; CHECK-LABEL: test_vpklsgs_none_store: ; CHECK: vpklsgs %v24, %v24, %v26 -; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK-NEXT: {{bnher|bner}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b) @@ -1705,7 +1705,7 @@ define void @test_vtm_all_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { ; CHECK-LABEL: test_vtm_all_store: ; CHECK-NOT: %r ; CHECK: vtm %v24, %v26 -; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK-NEXT: {{bnor|bler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b) @@ -1752,7 +1752,7 @@ define <16 x i8> @test_vceqbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { ; CHECK-LABEL: test_vceqbs_any_store: ; CHECK-NOT: %r ; CHECK: vceqbs %v24, %v24, %v26 -; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK-NEXT: {{bor|bnler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b) @@ -1801,7 +1801,7 @@ define <8 x i16> @test_vceqhs_notall_store(<8 x i16> %a, <8 x i16> %b, ; CHECK-LABEL: test_vceqhs_notall_store: ; CHECK-NOT: %r ; CHECK: vceqhs %v24, %v24, %v26 -; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK-NEXT: {{bher|ber}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b) @@ -1850,7 +1850,7 @@ define <4 x i32> @test_vceqfs_none_store(<4 x i32> %a, <4 x i32> %b, ; CHECK-LABEL: test_vceqfs_none_store: ; CHECK-NOT: %r ; CHECK: vceqfs %v24, %v24, %v26 -; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK-NEXT: {{bnor|bler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b) @@ -1899,7 +1899,7 @@ define <2 x i64> @test_vceqgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { ; CHECK-LABEL: test_vceqgs_all_store: ; CHECK-NOT: %r ; CHECK: vceqgs %v24, %v24, %v26 -; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK-NEXT: {{bnher|bner}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b) @@ -1948,7 +1948,7 @@ define <16 x i8> @test_vchbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { ; CHECK-LABEL: test_vchbs_any_store: ; CHECK-NOT: %r ; CHECK: vchbs %v24, %v24, %v26 -; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK-NEXT: {{bor|bnler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b) @@ -1997,7 +1997,7 @@ define <8 x i16> @test_vchhs_notall_store(<8 x i16> %a, <8 x i16> %b, ; CHECK-LABEL: test_vchhs_notall_store: ; CHECK-NOT: %r ; CHECK: vchhs %v24, %v24, %v26 -; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK-NEXT: {{bher|ber}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b) @@ -2045,7 +2045,7 @@ define <4 x i32> @test_vchfs_none_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) { ; CHECK-LABEL: test_vchfs_none_store: ; CHECK-NOT: %r ; CHECK: vchfs %v24, %v24, %v26 -; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK-NEXT: {{bnor|bler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b) @@ -2094,7 +2094,7 @@ define <2 x i64> @test_vchgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { ; CHECK-LABEL: test_vchgs_all_store: ; CHECK-NOT: %r ; CHECK: vchgs %v24, %v24, %v26 -; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK-NEXT: {{bnher|bner}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b) @@ -2143,7 +2143,7 @@ define <16 x i8> @test_vchlbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { ; CHECK-LABEL: test_vchlbs_any_store: ; CHECK-NOT: %r ; CHECK: vchlbs %v24, %v24, %v26 -; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK-NEXT: {{bor|bnler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b) @@ -2192,7 +2192,7 @@ define <8 x i16> @test_vchlhs_notall_store(<8 x i16> %a, <8 x i16> %b, ; CHECK-LABEL: test_vchlhs_notall_store: ; CHECK-NOT: %r ; CHECK: vchlhs %v24, %v24, %v26 -; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK-NEXT: {{bher|ber}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b) @@ -2241,7 +2241,7 @@ define <4 x i32> @test_vchlfs_none_store(<4 x i32> %a, <4 x i32> %b, ; CHECK-LABEL: test_vchlfs_none_store: ; CHECK-NOT: %r ; CHECK: vchlfs %v24, %v24, %v26 -; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK-NEXT: {{bnor|bler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b) @@ -2290,7 +2290,7 @@ define <2 x i64> @test_vchlgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { ; CHECK-LABEL: test_vchlgs_all_store: ; CHECK-NOT: %r ; CHECK: vchlgs %v24, %v24, %v26 -; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK-NEXT: {{bnher|bner}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b) @@ -3166,7 +3166,7 @@ define <2 x i64> @test_vfcedbs_any_store(<2 x double> %a, <2 x double> %b, ; CHECK-LABEL: test_vfcedbs_any_store: ; CHECK-NOT: %r ; CHECK: vfcedbs %v24, %v24, %v26 -; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK-NEXT: {{bor|bnler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a, @@ -3218,7 +3218,7 @@ define <2 x i64> @test_vfchdbs_notall_store(<2 x double> %a, <2 x double> %b, ; CHECK-LABEL: test_vfchdbs_notall_store: ; CHECK-NOT: %r ; CHECK: vfchdbs %v24, %v24, %v26 -; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK-NEXT: {{bher|ber}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a, @@ -3270,7 +3270,7 @@ define <2 x i64> @test_vfchedbs_none_store(<2 x double> %a, <2 x double> %b, ; CHECK-LABEL: test_vfchedbs_none_store: ; CHECK-NOT: %r ; CHECK: vfchedbs %v24, %v24, %v26 -; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK-NEXT: {{bnor|bler}} %r14 ; CHECK: mvhi 0(%r2), 0 ; CHECK: br %r14 %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a, diff --git a/test/CodeGen/SystemZ/vec-sub-01.ll b/test/CodeGen/SystemZ/vec-sub-01.ll index 4afad8bef659..9829bd024332 100644 --- a/test/CodeGen/SystemZ/vec-sub-01.ll +++ b/test/CodeGen/SystemZ/vec-sub-01.ll @@ -52,7 +52,7 @@ define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) { ; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2 ; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3 ; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3 -; CHECK-DAG: ler %f[[A1copy:[0-5]]], %f[[A1]] +; CHECK-DAG: ldr %f[[A1copy:[0-5]]], %f[[A1]] ; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]] ; CHECK-DAG: sebr %f[[B1]], %f[[B2]] ; CHECK-DAG: sebr %f[[C1]], %f[[C2]] |