diff options
Diffstat (limited to 'test/CodeGen/SystemZ')
378 files changed, 21951 insertions, 4250 deletions
diff --git a/test/CodeGen/SystemZ/Large/branch-range-01.py b/test/CodeGen/SystemZ/Large/branch-range-01.py index edb631d8c6d5..365d7e420818 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-01.py +++ b/test/CodeGen/SystemZ/Large/branch-range-01.py @@ -78,8 +78,8 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bstop%d = getelementptr i32 *%%stop, i64 %d' % (i, i) - print ' %%bcur%d = load i32 *%%bstop%d' % (i, i) + print ' %%bstop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i) + print ' %%bcur%d = load i32 , i32 *%%bstop%d' % (i, i) print ' %%btest%d = icmp eq i32 %%limit, %%bcur%d' % (i, i) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) print '' @@ -90,12 +90,12 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%astop%d = getelementptr i32 *%%stop, i64 %d' % (i, i + 25) - print ' %%acur%d = load i32 *%%astop%d' % (i, i) + print ' %%astop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i + 25) + print ' %%acur%d = load i32 , i32 *%%astop%d' % (i, i) print ' %%atest%d = icmp eq i32 %%limit, %%acur%d' % (i, i) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) print '' diff --git a/test/CodeGen/SystemZ/Large/branch-range-02.py b/test/CodeGen/SystemZ/Large/branch-range-02.py index 743e12de0f1f..7f7b09954a61 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-02.py +++ b/test/CodeGen/SystemZ/Large/branch-range-02.py @@ -71,8 +71,8 @@ for i in xrange(blocks): other = 'end' if 2 * i < blocks else 'b0' print 'b%d:' % i print ' store volatile i8 %d, i8 *%%base' % value - print ' %%astop%d = getelementptr i32 *%%stop, i64 %d' % (i, i) - print ' %%acur%d = load i32 *%%astop%d' % (i, i) + print ' %%astop%d = getelementptr i32, i32 *%%stop, i64 %d' % (i, i) + print ' %%acur%d = load i32 , i32 *%%astop%d' % (i, i) print ' %%atest%d = icmp eq i32 %%limit, %%acur%d' % (i, i) print ' br i1 %%atest%d, label %%%s, label %%%s' % (i, other, next) diff --git a/test/CodeGen/SystemZ/Large/branch-range-03.py b/test/CodeGen/SystemZ/Large/branch-range-03.py index 5c9a93b87f73..745d733211ff 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-03.py +++ b/test/CodeGen/SystemZ/Large/branch-range-03.py @@ -78,8 +78,8 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i) - print ' %%bcur%d = load i8 *%%bstop%d' % (i, i) + print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i) + print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i) print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i) print ' %%btest%d = icmp eq i32 %%limit, %%bext%d' % (i, i) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -91,12 +91,12 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25) - print ' %%acur%d = load i8 *%%astop%d' % (i, i) + print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25) + print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i) print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i) print ' %%atest%d = icmp eq i32 %%limit, %%aext%d' % (i, i) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/branch-range-04.py b/test/CodeGen/SystemZ/Large/branch-range-04.py index 2c9090fa2067..a0c9c4426456 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-04.py +++ b/test/CodeGen/SystemZ/Large/branch-range-04.py @@ -82,8 +82,8 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i) - print ' %%bcur%d = load i8 *%%bstop%d' % (i, i) + print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i) + print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i) print ' %%bext%d = sext i8 %%bcur%d to i64' % (i, i) print ' %%btest%d = icmp eq i64 %%limit, %%bext%d' % (i, i) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -95,12 +95,12 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25) - print ' %%acur%d = load i8 *%%astop%d' % (i, i) + print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25) + print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i) print ' %%aext%d = sext i8 %%acur%d to i64' % (i, i) print ' %%atest%d = icmp eq i64 %%limit, %%aext%d' % (i, i) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/branch-range-05.py b/test/CodeGen/SystemZ/Large/branch-range-05.py index 52f4a961c88f..69a8112162a0 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-05.py +++ b/test/CodeGen/SystemZ/Large/branch-range-05.py @@ -82,7 +82,7 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bcur%d = load i8 *%%stop' % i + print ' %%bcur%d = load i8 , i8 *%%stop' % i print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i) print ' %%btest%d = icmp slt i32 %%bext%d, %d' % (i, i, i + 50) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -94,11 +94,11 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%acur%d = load i8 *%%stop' % i + print ' %%acur%d = load i8 , i8 *%%stop' % i print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i) print ' %%atest%d = icmp slt i32 %%aext%d, %d' % (i, i, i + 100) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/branch-range-06.py b/test/CodeGen/SystemZ/Large/branch-range-06.py index c34ebac4ce36..b08bc119c454 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-06.py +++ b/test/CodeGen/SystemZ/Large/branch-range-06.py @@ -82,7 +82,7 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bcur%d = load i8 *%%stop' % i + print ' %%bcur%d = load i8 , i8 *%%stop' % i print ' %%bext%d = sext i8 %%bcur%d to i64' % (i, i) print ' %%btest%d = icmp slt i64 %%bext%d, %d' % (i, i, i + 50) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -94,11 +94,11 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%acur%d = load i8 *%%stop' % i + print ' %%acur%d = load i8 , i8 *%%stop' % i print ' %%aext%d = sext i8 %%acur%d to i64' % (i, i) print ' %%atest%d = icmp slt i64 %%aext%d, %d' % (i, i, i + 100) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/branch-range-07.py b/test/CodeGen/SystemZ/Large/branch-range-07.py index 90c442092e82..c5fef10577f6 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-07.py +++ b/test/CodeGen/SystemZ/Large/branch-range-07.py @@ -39,8 +39,8 @@ print 'define void @f1(i8 *%base, i32 *%counts) {' print 'entry:' for i in xrange(branch_blocks - 1, -1, -1): - print ' %%countptr%d = getelementptr i32 *%%counts, i64 %d' % (i, i) - print ' %%initcount%d = load i32 *%%countptr%d' % (i, i) + print ' %%countptr%d = getelementptr i32, i32 *%%counts, i64 %d' % (i, i) + print ' %%initcount%d = load i32 , i32 *%%countptr%d' % (i, i) print ' br label %%loop%d' % i print 'loop%d:' % i @@ -54,7 +54,7 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): diff --git a/test/CodeGen/SystemZ/Large/branch-range-08.py b/test/CodeGen/SystemZ/Large/branch-range-08.py index ac1b1370a3e3..8b6b67398337 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-08.py +++ b/test/CodeGen/SystemZ/Large/branch-range-08.py @@ -40,8 +40,8 @@ print 'define void @f1(i8 *%base, i64 *%counts) {' print 'entry:' for i in xrange(branch_blocks - 1, -1, -1): - print ' %%countptr%d = getelementptr i64 *%%counts, i64 %d' % (i, i) - print ' %%initcount%d = load i64 *%%countptr%d' % (i, i) + print ' %%countptr%d = getelementptr i64, i64 *%%counts, i64 %d' % (i, i) + print ' %%initcount%d = load i64 , i64 *%%countptr%d' % (i, i) print ' br label %%loop%d' % i print 'loop%d:' % i @@ -55,7 +55,7 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): diff --git a/test/CodeGen/SystemZ/Large/branch-range-09.py b/test/CodeGen/SystemZ/Large/branch-range-09.py index bc712cb164ea..d4693358f502 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-09.py +++ b/test/CodeGen/SystemZ/Large/branch-range-09.py @@ -78,8 +78,8 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i) - print ' %%bcur%d = load i8 *%%bstop%d' % (i, i) + print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i) + print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i) print ' %%bext%d = sext i8 %%bcur%d to i32' % (i, i) print ' %%btest%d = icmp ult i32 %%limit, %%bext%d' % (i, i) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -91,12 +91,12 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25) - print ' %%acur%d = load i8 *%%astop%d' % (i, i) + print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25) + print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i) print ' %%aext%d = sext i8 %%acur%d to i32' % (i, i) print ' %%atest%d = icmp ult i32 %%limit, %%aext%d' % (i, i) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/branch-range-10.py b/test/CodeGen/SystemZ/Large/branch-range-10.py index 8c483c33724c..c928081f5544 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-10.py +++ b/test/CodeGen/SystemZ/Large/branch-range-10.py @@ -82,8 +82,8 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bstop%d = getelementptr i8 *%%stop, i64 %d' % (i, i) - print ' %%bcur%d = load i8 *%%bstop%d' % (i, i) + print ' %%bstop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i) + print ' %%bcur%d = load i8 , i8 *%%bstop%d' % (i, i) print ' %%bext%d = sext i8 %%bcur%d to i64' % (i, i) print ' %%btest%d = icmp ult i64 %%limit, %%bext%d' % (i, i) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -95,12 +95,12 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%astop%d = getelementptr i8 *%%stop, i64 %d' % (i, i + 25) - print ' %%acur%d = load i8 *%%astop%d' % (i, i) + print ' %%astop%d = getelementptr i8, i8 *%%stop, i64 %d' % (i, i + 25) + print ' %%acur%d = load i8 , i8 *%%astop%d' % (i, i) print ' %%aext%d = sext i8 %%acur%d to i64' % (i, i) print ' %%atest%d = icmp ult i64 %%limit, %%aext%d' % (i, i) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/branch-range-11.py b/test/CodeGen/SystemZ/Large/branch-range-11.py index 054610380e31..85166bc15656 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-11.py +++ b/test/CodeGen/SystemZ/Large/branch-range-11.py @@ -98,8 +98,8 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bcur%da = load i32 *%%stopa' % i - print ' %%bcur%db = load i32 *%%stopb' % i + print ' %%bcur%da = load i32 , i32 *%%stopa' % i + print ' %%bcur%db = load i32 , i32 *%%stopb' % i print ' %%bsub%d = sub i32 %%bcur%da, %%bcur%db' % (i, i, i) print ' %%btest%d = icmp ult i32 %%bsub%d, %d' % (i, i, i + 50) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -111,12 +111,12 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%acur%da = load i32 *%%stopa' % i - print ' %%acur%db = load i32 *%%stopb' % i + print ' %%acur%da = load i32 , i32 *%%stopa' % i + print ' %%acur%db = load i32 , i32 *%%stopb' % i print ' %%asub%d = sub i32 %%acur%da, %%acur%db' % (i, i, i) print ' %%atest%d = icmp ult i32 %%asub%d, %d' % (i, i, i + 100) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/branch-range-12.py b/test/CodeGen/SystemZ/Large/branch-range-12.py index 626c8998d5d4..e1d9e2977d41 100644 --- a/test/CodeGen/SystemZ/Large/branch-range-12.py +++ b/test/CodeGen/SystemZ/Large/branch-range-12.py @@ -98,8 +98,8 @@ print '' for i in xrange(branch_blocks): next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main' print 'before%d:' % i - print ' %%bcur%da = load i64 *%%stopa' % i - print ' %%bcur%db = load i64 *%%stopb' % i + print ' %%bcur%da = load i64 , i64 *%%stopa' % i + print ' %%bcur%db = load i64 , i64 *%%stopb' % i print ' %%bsub%d = sub i64 %%bcur%da, %%bcur%db' % (i, i, i) print ' %%btest%d = icmp ult i64 %%bsub%d, %d' % (i, i, i + 50) print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next) @@ -111,12 +111,12 @@ for i in xrange(0, main_size, 6): a, b = b, a + b offset = 4096 + b % 500000 value = a % 256 - print ' %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset) + print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset) print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i) for i in xrange(branch_blocks): - print ' %%acur%da = load i64 *%%stopa' % i - print ' %%acur%db = load i64 *%%stopb' % i + print ' %%acur%da = load i64 , i64 *%%stopa' % i + print ' %%acur%db = load i64 , i64 *%%stopb' % i print ' %%asub%d = sub i64 %%acur%da, %%acur%db' % (i, i, i) print ' %%atest%d = icmp ult i64 %%asub%d, %d' % (i, i, i + 100) print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i) diff --git a/test/CodeGen/SystemZ/Large/lit.local.cfg b/test/CodeGen/SystemZ/Large/lit.local.cfg index 4f22a970c3a6..d9d464726135 100644 --- a/test/CodeGen/SystemZ/Large/lit.local.cfg +++ b/test/CodeGen/SystemZ/Large/lit.local.cfg @@ -1,8 +1,8 @@ config.suffixes = ['.py'] # These tests take on the order of seconds to run, so skip them unless -# running natively. -if config.root.host_arch not in ['SystemZ']: +# we're running long tests. +if 'long_tests' not in config.available_features: config.unsupported = True if not 'SystemZ' in config.root.targets: diff --git a/test/CodeGen/SystemZ/Large/spill-01.py b/test/CodeGen/SystemZ/Large/spill-01.py index 3c1d0b611bb4..f59f607d5beb 100644 --- a/test/CodeGen/SystemZ/Large/spill-01.py +++ b/test/CodeGen/SystemZ/Large/spill-01.py @@ -25,8 +25,8 @@ print '' print 'define void @f1(i64 *%base0, i64 *%base1) {' for i in range(count): - print ' %%ptr%d = getelementptr i64 *%%base%d, i64 %d' % (i, i % 2, i / 2) - print ' %%val%d = load i64 *%%ptr%d' % (i, i) + print ' %%ptr%d = getelementptr i64, i64 *%%base%d, i64 %d' % (i, i % 2, i / 2) + print ' %%val%d = load i64 , i64 *%%ptr%d' % (i, i) print '' print ' call void @foo()' diff --git a/test/CodeGen/SystemZ/Large/spill-02.py b/test/CodeGen/SystemZ/Large/spill-02.py index 0aa43d18054b..4ccfa11a0d3e 100644 --- a/test/CodeGen/SystemZ/Large/spill-02.py +++ b/test/CodeGen/SystemZ/Large/spill-02.py @@ -29,7 +29,7 @@ print 'entry:' # Make the allocation big, so that it goes at the top of the frame. print ' %array = alloca [1000 x i64]' -print ' %area = getelementptr [1000 x i64] *%array, i64 0, i64 0' +print ' %area = getelementptr [1000 x i64], [1000 x i64] *%array, i64 0, i64 0' print ' %%base = call i64 *@foo(i64 *%%area%s)' % (', i64 0' * args) print '' @@ -37,8 +37,8 @@ print '' # another for %base, so we need 14 live values. count = 14 for i in range(count): - print ' %%ptr%d = getelementptr i64 *%%base, i64 %d' % (i, i / 2) - print ' %%val%d = load volatile i64 *%%ptr%d' % (i, i) + print ' %%ptr%d = getelementptr i64, i64 *%%base, i64 %d' % (i, i / 2) + print ' %%val%d = load volatile i64 , i64 *%%ptr%d' % (i, i) print '' # Encourage the register allocator to give preference to these %vals diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll index d0960cdb1047..736efe8887d6 100644 --- a/test/CodeGen/SystemZ/addr-01.ll +++ b/test/CodeGen/SystemZ/addr-01.ll @@ -10,7 +10,7 @@ define void @f1(i64 %addr, i64 %index) { ; CHECK: br %r14 %add = add i64 %addr, %index %ptr = inttoptr i64 %add to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } @@ -22,7 +22,7 @@ define void @f2(i64 %addr, i64 %index) { %add1 = add i64 %addr, %index %add2 = add i64 %add1, 100 %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } @@ -34,7 +34,7 @@ define void @f3(i64 %addr, i64 %index) { %add1 = add i64 %addr, 100 %add2 = add i64 %add1, %index %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } @@ -46,7 +46,7 @@ define void @f4(i64 %addr, i64 %index) { %add1 = add i64 %addr, %index %add2 = sub i64 %add1, 100 %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } @@ -58,7 +58,7 @@ define void @f5(i64 %addr, i64 %index) { %add1 = sub i64 %addr, 100 %add2 = add i64 %add1, %index %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } @@ -72,7 +72,7 @@ define void @f6(i64 %addr, i64 %index) { %or = or i64 %aligned, 6 %add = add i64 %or, %index %ptr = inttoptr i64 %add to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } @@ -85,7 +85,7 @@ define void @f7(i64 %addr, i64 %index) { %or = or i64 %addr, 6 %add = add i64 %or, %index %ptr = inttoptr i64 %add to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } @@ -102,6 +102,6 @@ define void @f8(i64 %addr, i64 %index) { %add = add i64 %aligned, %index %or = or i64 %add, 6 %ptr = inttoptr i64 %or to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/addr-02.ll b/test/CodeGen/SystemZ/addr-02.ll index 56c48794b072..7e9b2f18ef82 100644 --- a/test/CodeGen/SystemZ/addr-02.ll +++ b/test/CodeGen/SystemZ/addr-02.ll @@ -11,7 +11,7 @@ define void @f1(i64 %addr, i64 %index, i8 **%dst) { ; CHECK: br %r14 %add = add i64 %addr, %index %ptr = inttoptr i64 %add to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } @@ -24,7 +24,7 @@ define void @f2(i64 %addr, i64 %index, i8 **%dst) { %add1 = add i64 %addr, %index %add2 = add i64 %add1, 100 %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } @@ -37,7 +37,7 @@ define void @f3(i64 %addr, i64 %index, i8 **%dst) { %add1 = add i64 %addr, 100 %add2 = add i64 %add1, %index %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } @@ -50,7 +50,7 @@ define void @f4(i64 %addr, i64 %index, i8 **%dst) { %add1 = add i64 %addr, %index %add2 = sub i64 %add1, 100 %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } @@ -63,7 +63,7 @@ define void @f5(i64 %addr, i64 %index, i8 **%dst) { %add1 = sub i64 %addr, 100 %add2 = add i64 %add1, %index %ptr = inttoptr i64 %add2 to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } @@ -78,7 +78,7 @@ define void @f6(i64 %addr, i64 %index, i8 **%dst) { %or = or i64 %aligned, 6 %add = add i64 %or, %index %ptr = inttoptr i64 %add to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } @@ -92,7 +92,7 @@ define void @f7(i64 %addr, i64 %index, i8 **%dst) { %or = or i64 %addr, 6 %add = add i64 %or, %index %ptr = inttoptr i64 %add to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } @@ -110,7 +110,7 @@ define void @f8(i64 %addr, i64 %index, i8 **%dst) { %add = add i64 %aligned, %index %or = or i64 %add, 6 %ptr = inttoptr i64 %or to i8 * - %a = load volatile i8 *%ptr + %a = load volatile i8 , i8 *%ptr store volatile i8 *%ptr, i8 **%dst ret void } diff --git a/test/CodeGen/SystemZ/addr-03.ll b/test/CodeGen/SystemZ/addr-03.ll index 1146926a4c2e..b2fd400c6bda 100644 --- a/test/CodeGen/SystemZ/addr-03.ll +++ b/test/CodeGen/SystemZ/addr-03.ll @@ -7,7 +7,7 @@ define void @f1() { ; CHECK: lb %r0, 0 ; CHECK: br %r14 %ptr = inttoptr i64 0 to i8 * - %val = load volatile i8 *%ptr + %val = load volatile i8 , i8 *%ptr ret void } @@ -16,7 +16,7 @@ define void @f2() { ; CHECK: lb %r0, -524288 ; CHECK: br %r14 %ptr = inttoptr i64 -524288 to i8 * - %val = load volatile i8 *%ptr + %val = load volatile i8 , i8 *%ptr ret void } @@ -25,7 +25,7 @@ define void @f3() { ; CHECK-NOT: lb %r0, -524289 ; CHECK: br %r14 %ptr = inttoptr i64 -524289 to i8 * - %val = load volatile i8 *%ptr + %val = load volatile i8 , i8 *%ptr ret void } @@ -34,7 +34,7 @@ define void @f4() { ; CHECK: lb %r0, 524287 ; CHECK: br %r14 %ptr = inttoptr i64 524287 to i8 * - %val = load volatile i8 *%ptr + %val = load volatile i8 , i8 *%ptr ret void } @@ -43,6 +43,6 @@ define void @f5() { ; CHECK-NOT: lb %r0, 524288 ; CHECK: br %r14 %ptr = inttoptr i64 524288 to i8 * - %val = load volatile i8 *%ptr + %val = load volatile i8 , i8 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/alias-01.ll b/test/CodeGen/SystemZ/alias-01.ll index 89a731830187..852d18e8de79 100644 --- a/test/CodeGen/SystemZ/alias-01.ll +++ b/test/CodeGen/SystemZ/alias-01.ll @@ -7,7 +7,7 @@ define void @f1(<16 x i32> *%src1, <16 x float> *%dest) { ; CHECK-LABEL: f1: ; CHECK-NOT: %r15 ; CHECK: br %r14 - %val = load <16 x i32> *%src1, !tbaa !1 + %val = load <16 x i32> , <16 x i32> *%src1, !tbaa !1 %add = add <16 x i32> %val, %val %res = bitcast <16 x i32> %add to <16 x float> store <16 x float> %res, <16 x float> *%dest, !tbaa !2 diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll index 2ddefd70cc9d..06c336a331d8 100644 --- a/test/CodeGen/SystemZ/alloca-01.ll +++ b/test/CodeGen/SystemZ/alloca-01.ll @@ -52,13 +52,13 @@ define i64 @f1(i64 %length, i64 %index) { ; CHECK-FP: lgr %r11, %r15 ; CHECK-FP: lmg %r6, %r15, 224(%r11) %a = alloca i8, i64 %length - %b = getelementptr i8 *%a, i64 1 + %b = getelementptr i8, i8 *%a, i64 1 %cindex = add i64 %index, 3919 - %c = getelementptr i8 *%a, i64 %cindex + %c = getelementptr i8, i8 *%a, i64 %cindex %dindex = add i64 %index, 3920 - %d = getelementptr i8 *%a, i64 %dindex + %d = getelementptr i8, i8 *%a, i64 %dindex %eindex = add i64 %index, 4095 - %e = getelementptr i8 *%a, i64 %eindex + %e = getelementptr i8, i8 *%a, i64 %eindex %count = call i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 0, i64 0) %res = add i64 %count, 1 ret i64 %res diff --git a/test/CodeGen/SystemZ/alloca-02.ll b/test/CodeGen/SystemZ/alloca-02.ll index b5787b102358..092ad86e8529 100644 --- a/test/CodeGen/SystemZ/alloca-02.ll +++ b/test/CodeGen/SystemZ/alloca-02.ll @@ -38,13 +38,13 @@ define i64 @f1(i64 %length, i64 %index) { ; CHECK-E: stcy [[TMP]], 4096({{%r3,%r2|%r2,%r3}}) %a = alloca i8, i64 %length store volatile i8 0, i8 *%a - %b = getelementptr i8 *%a, i64 4095 + %b = getelementptr i8, i8 *%a, i64 4095 store volatile i8 1, i8 *%b - %c = getelementptr i8 *%a, i64 %index + %c = getelementptr i8, i8 *%a, i64 %index store volatile i8 2, i8 *%c - %d = getelementptr i8 *%c, i64 4095 + %d = getelementptr i8, i8 *%c, i64 4095 store volatile i8 3, i8 *%d - %e = getelementptr i8 *%d, i64 1 + %e = getelementptr i8, i8 *%d, i64 1 store volatile i8 4, i8 *%e %count = call i64 @bar(i8 *%a) %res = add i64 %count, 1 diff --git a/test/CodeGen/SystemZ/and-01.ll b/test/CodeGen/SystemZ/and-01.ll index 3b230ba1081f..56fe2799fdc0 100644 --- a/test/CodeGen/SystemZ/and-01.ll +++ b/test/CodeGen/SystemZ/and-01.ll @@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: n %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %and = and i32 %a, %b ret i32 %and } @@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: n %r2, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1023 + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: ny %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1024 + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: ny %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: n %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: ny %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) { ; CHECK-LABEL: f8: ; CHECK: ny %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: n %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %and = and i32 %a, %b ret i32 %and } @@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: n %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/and-03.ll b/test/CodeGen/SystemZ/and-03.ll index a0560d46e4ea..5c15d2462b89 100644 --- a/test/CodeGen/SystemZ/and-03.ll +++ b/test/CodeGen/SystemZ/and-03.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: ng %r2, 0(%r3) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %and = and i64 %a, %b ret i64 %and } @@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) { ; CHECK-LABEL: f3: ; CHECK: ng %r2, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %and = and i64 %a, %b ret i64 %and } @@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: ng %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %and = and i64 %a, %b ret i64 %and } @@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: ng %r2, -8(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %and = and i64 %a, %b ret i64 %and } @@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) { ; CHECK-LABEL: f6: ; CHECK: ng %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %and = and i64 %a, %b ret i64 %and } @@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) { ; CHECK: agfi %r3, -524296 ; CHECK: ng %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %and = and i64 %a, %b ret i64 %and } @@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %and = and i64 %a, %b ret i64 %and } @@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: ng %r2, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/and-05.ll b/test/CodeGen/SystemZ/and-05.ll index dafd9d5c51b0..488ec5bc9ae6 100644 --- a/test/CodeGen/SystemZ/and-05.ll +++ b/test/CodeGen/SystemZ/and-05.ll @@ -7,7 +7,7 @@ define void @f1(i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: ni 0(%r2), 1 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %and = and i8 %val, -255 store i8 %and, i8 *%ptr ret void @@ -18,7 +18,7 @@ define void @f2(i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %and = and i8 %val, -2 store i8 %and, i8 *%ptr ret void @@ -29,7 +29,7 @@ define void @f3(i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: ni 0(%r2), 1 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %and = and i8 %val, 1 store i8 %and, i8 *%ptr ret void @@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %and = and i8 %val, 254 store i8 %and, i8 *%ptr ret void @@ -51,8 +51,8 @@ define void @f5(i8 *%src) { ; CHECK-LABEL: f5: ; CHECK: ni 4095(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4095 + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -63,8 +63,8 @@ define void @f6(i8 *%src) { ; CHECK-LABEL: f6: ; CHECK: niy 4096(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4096 + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -75,8 +75,8 @@ define void @f7(i8 *%src) { ; CHECK-LABEL: f7: ; CHECK: niy 524287(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -89,8 +89,8 @@ define void @f8(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: ni 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -101,8 +101,8 @@ define void @f9(i8 *%src) { ; CHECK-LABEL: f9: ; CHECK: niy -1(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -113,8 +113,8 @@ define void @f10(i8 *%src) { ; CHECK-LABEL: f10: ; CHECK: niy -524288(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -127,8 +127,8 @@ define void @f11(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: ni 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -143,7 +143,7 @@ define void @f12(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4095 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void @@ -158,7 +158,7 @@ define void @f13(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %and = and i8 %val, 127 store i8 %and, i8 *%ptr ret void diff --git a/test/CodeGen/SystemZ/and-06.ll b/test/CodeGen/SystemZ/and-06.ll index f796618dd4f4..537ee100589a 100644 --- a/test/CodeGen/SystemZ/and-06.ll +++ b/test/CodeGen/SystemZ/and-06.ll @@ -8,7 +8,7 @@ define void @f1(i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %and = and i32 %ext, -2 %trunc = trunc i32 %and to i8 @@ -21,7 +21,7 @@ define void @f2(i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %and = and i64 %ext, -2 %trunc = trunc i64 %and to i8 @@ -34,7 +34,7 @@ define void @f3(i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %and = and i32 %ext, 254 %trunc = trunc i32 %and to i8 @@ -47,7 +47,7 @@ define void @f4(i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %and = and i64 %ext, 254 %trunc = trunc i64 %and to i8 @@ -60,7 +60,7 @@ define void @f5(i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %and = and i32 %ext, -2 %trunc = trunc i32 %and to i8 @@ -73,7 +73,7 @@ define void @f6(i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %and = and i64 %ext, -2 %trunc = trunc i64 %and to i8 @@ -86,7 +86,7 @@ define void @f7(i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %and = and i32 %ext, 254 %trunc = trunc i32 %and to i8 @@ -99,7 +99,7 @@ define void @f8(i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: ni 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %and = and i64 %ext, 254 %trunc = trunc i64 %and to i8 diff --git a/test/CodeGen/SystemZ/and-08.ll b/test/CodeGen/SystemZ/and-08.ll index a328c4ea2046..0622950243ed 100644 --- a/test/CodeGen/SystemZ/and-08.ll +++ b/test/CodeGen/SystemZ/and-08.ll @@ -12,9 +12,9 @@ define void @f1(i8 *%ptr1) { ; CHECK-LABEL: f1: ; CHECK: nc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 - %old = load i8 *%ptr2 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 + %old = load i8 , i8 *%ptr2 %and = and i8 %val, %old store i8 %and, i8 *%ptr2 ret void @@ -25,9 +25,9 @@ define void @f2(i8 *%ptr1) { ; CHECK-LABEL: f2: ; CHECK: nc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 - %old = load i8 *%ptr2 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 + %old = load i8 , i8 *%ptr2 %and = and i8 %old, %val store i8 %and, i8 *%ptr2 ret void @@ -39,10 +39,10 @@ define void @f3(i8 *%ptr1) { ; CHECK-LABEL: f3: ; CHECK: nc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %extval = zext i8 %val to i32 - %old = load i8 *%ptr2 + %old = load i8 , i8 *%ptr2 %extold = sext i8 %old to i32 %and = and i32 %extval, %extold %trunc = trunc i32 %and to i8 @@ -55,10 +55,10 @@ define void @f4(i8 *%ptr1) { ; CHECK-LABEL: f4: ; CHECK: nc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %extval = sext i8 %val to i32 - %old = load i8 *%ptr2 + %old = load i8 , i8 *%ptr2 %extold = zext i8 %old to i32 %and = and i32 %extval, %extold %trunc = trunc i32 %and to i8 @@ -71,10 +71,10 @@ define void @f5(i8 *%ptr1) { ; CHECK-LABEL: f5: ; CHECK: nc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %extval = sext i8 %val to i32 - %old = load i8 *%ptr2 + %old = load i8 , i8 *%ptr2 %extold = sext i8 %old to i32 %and = and i32 %extval, %extold %trunc = trunc i32 %and to i8 @@ -87,10 +87,10 @@ define void @f6(i8 *%ptr1) { ; CHECK-LABEL: f6: ; CHECK: nc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %extval = zext i8 %val to i32 - %old = load i8 *%ptr2 + %old = load i8 , i8 *%ptr2 %extold = zext i8 %old to i32 %and = and i32 %extval, %extold %trunc = trunc i32 %and to i8 @@ -104,10 +104,10 @@ define void @f7(i8 *%ptr1) { ; CHECK-LABEL: f7: ; CHECK: nc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %extval = sext i8 %val to i64 - %old = load i8 *%ptr2 + %old = load i8 , i8 *%ptr2 %extold = zext i8 %old to i64 %and = and i64 %extval, %extold %trunc = trunc i64 %and to i8 @@ -120,9 +120,9 @@ define void @f8(i16 *%ptr1) { ; CHECK-LABEL: f8: ; CHECK: nc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 - %old = load i16 *%ptr2 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 + %old = load i16 , i16 *%ptr2 %and = and i16 %val, %old store i16 %and, i16 *%ptr2 ret void @@ -133,10 +133,10 @@ define void @f9(i16 *%ptr1) { ; CHECK-LABEL: f9: ; CHECK: nc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 %extval = zext i16 %val to i32 - %old = load i16 *%ptr2 + %old = load i16 , i16 *%ptr2 %extold = sext i16 %old to i32 %and = and i32 %extval, %extold %trunc = trunc i32 %and to i16 @@ -149,10 +149,10 @@ define void @f10(i16 *%ptr1) { ; CHECK-LABEL: f10: ; CHECK: nc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 %extval = sext i16 %val to i64 - %old = load i16 *%ptr2 + %old = load i16 , i16 *%ptr2 %extold = zext i16 %old to i64 %and = and i64 %extval, %extold %trunc = trunc i64 %and to i16 @@ -165,9 +165,9 @@ define void @f11(i32 *%ptr1) { ; CHECK-LABEL: f11: ; CHECK: nc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i32 *%ptr1, i64 1 - %val = load i32 *%ptr1 - %old = load i32 *%ptr2 + %ptr2 = getelementptr i32, i32 *%ptr1, i64 1 + %val = load i32 , i32 *%ptr1 + %old = load i32 , i32 *%ptr2 %and = and i32 %old, %val store i32 %and, i32 *%ptr2 ret void @@ -178,10 +178,10 @@ define void @f12(i32 *%ptr1) { ; CHECK-LABEL: f12: ; CHECK: nc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i32 *%ptr1, i64 1 - %val = load i32 *%ptr1 + %ptr2 = getelementptr i32, i32 *%ptr1, i64 1 + %val = load i32 , i32 *%ptr1 %extval = sext i32 %val to i64 - %old = load i32 *%ptr2 + %old = load i32 , i32 *%ptr2 %extold = zext i32 %old to i64 %and = and i64 %extval, %extold %trunc = trunc i64 %and to i32 @@ -194,9 +194,9 @@ define void @f13(i64 *%ptr1) { ; CHECK-LABEL: f13: ; CHECK: nc 8(8,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1 - %old = load i64 *%ptr2 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2 %and = and i64 %old, %val store i64 %and, i64 *%ptr2 ret void @@ -207,9 +207,9 @@ define void @f14(i64 *%ptr1) { ; CHECK-LABEL: f14: ; CHECK-NOT: nc ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load volatile i64 *%ptr1 - %old = load i64 *%ptr2 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load volatile i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2 %and = and i64 %old, %val store i64 %and, i64 *%ptr2 ret void @@ -220,9 +220,9 @@ define void @f15(i64 *%ptr1) { ; CHECK-LABEL: f15: ; CHECK-NOT: nc ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1 - %old = load volatile i64 *%ptr2 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1 + %old = load volatile i64 , i64 *%ptr2 %and = and i64 %old, %val store i64 %and, i64 *%ptr2 ret void @@ -233,9 +233,9 @@ define void @f16(i64 *%ptr1) { ; CHECK-LABEL: f16: ; CHECK-NOT: nc ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1 - %old = load i64 *%ptr2 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2 %and = and i64 %old, %val store volatile i64 %and, i64 *%ptr2 ret void @@ -248,8 +248,8 @@ define void @f17(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f17: ; CHECK-NOT: nc ; CHECK: br %r14 - %val = load i64 *%ptr1 - %old = load i64 *%ptr2 + %val = load i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2 %and = and i64 %old, %val store i64 %and, i64 *%ptr2 ret void @@ -260,8 +260,8 @@ define void @f18(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f18: ; CHECK-NOT: nc ; CHECK: br %r14 - %val = load i64 *%ptr1, align 2 - %old = load i64 *%ptr2 + %val = load i64 , i64 *%ptr1, align 2 + %old = load i64 , i64 *%ptr2 %and = and i64 %old, %val store i64 %and, i64 *%ptr2 ret void @@ -272,8 +272,8 @@ define void @f19(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f19: ; CHECK-NOT: nc ; CHECK: br %r14 - %val = load i64 *%ptr1, align 2 - %old = load i64 *%ptr2 + %val = load i64 , i64 *%ptr1, align 2 + %old = load i64 , i64 *%ptr2 %and = and i64 %val, %old store i64 %and, i64 *%ptr2 ret void @@ -284,8 +284,8 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f20: ; CHECK-NOT: nc ; CHECK: br %r14 - %val = load i64 *%ptr1 - %old = load i64 *%ptr2, align 2 + %val = load i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2, align 2 %and = and i64 %val, %old store i64 %and, i64 *%ptr2, align 2 ret void @@ -299,8 +299,8 @@ define void @f21(i64 %base) { %add = add i64 %base, 1 %ptr1 = inttoptr i64 %base to i64 * %ptr2 = inttoptr i64 %add to i64 * - %val = load i64 *%ptr1 - %old = load i64 *%ptr2, align 1 + %val = load i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2, align 1 %and = and i64 %old, %val store i64 %and, i64 *%ptr2, align 1 ret void @@ -313,8 +313,8 @@ define void @f22(i8 *%ptr) { ; CHECK-DAG: larl [[DST:%r[0-5]]], g1dst ; CHECK: nc 0(1,[[DST]]), 0([[SRC]]) ; CHECK: br %r14 - %val = load i8 *@g1src - %old = load i8 *@g1dst + %val = load i8 , i8 *@g1src + %old = load i8 , i8 *@g1dst %and = and i8 %val, %old store i8 %and, i8 *@g1dst ret void @@ -327,8 +327,8 @@ define void @f23(i16 *%ptr) { ; CHECK-DAG: larl [[DST:%r[0-5]]], g2dst ; CHECK: nc 0(2,[[DST]]), 0([[SRC]]) ; CHECK: br %r14 - %val = load i16 *@g2src - %old = load i16 *@g2dst + %val = load i16 , i16 *@g2src + %old = load i16 , i16 *@g2dst %and = and i16 %val, %old store i16 %and, i16 *@g2dst ret void @@ -339,9 +339,9 @@ define void @f24(i64 *%ptr1) { ; CHECK-LABEL: f24: ; CHECK: nc 8(8,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1, align 1 - %old = load i64 *%ptr2, align 1 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1, align 1 + %old = load i64 , i64 *%ptr2, align 1 %and = and i64 %old, %val store i64 %and, i64 *%ptr2, align 1 ret void @@ -352,8 +352,8 @@ define void @f25(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f25: ; CHECK: nc 0(8,%r3), 0(%r2) ; CHECK: br %r14 - %val = load i64 *%ptr1, align 2, !tbaa !3 - %old = load i64 *%ptr2, align 2, !tbaa !4 + %val = load i64 , i64 *%ptr1, align 2, !tbaa !3 + %old = load i64 , i64 *%ptr2, align 2, !tbaa !4 %and = and i64 %old, %val store i64 %and, i64 *%ptr2, align 2, !tbaa !4 ret void @@ -364,8 +364,8 @@ define void @f26(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f26: ; CHECK-NOT: nc ; CHECK: br %r14 - %val = load i64 *%ptr1, align 2, !tbaa !3 - %old = load i64 *%ptr2, align 2, !tbaa !3 + %val = load i64 , i64 *%ptr1, align 2, !tbaa !3 + %old = load i64 , i64 *%ptr2, align 2, !tbaa !3 %and = and i64 %old, %val store i64 %and, i64 *%ptr2, align 2, !tbaa !3 ret void diff --git a/test/CodeGen/SystemZ/asm-18.ll b/test/CodeGen/SystemZ/asm-18.ll index 71e145a285ff..999984be88d4 100644 --- a/test/CodeGen/SystemZ/asm-18.ll +++ b/test/CodeGen/SystemZ/asm-18.ll @@ -16,12 +16,12 @@ define void @f1(i32 *%ptr1, i32 *%ptr2) { ; CHECK-DAG: stfh [[REG3]], 4096(%r2) ; CHECK-DAG: sty [[REG4]], 524284(%r3) ; CHECK: br %r14 - %ptr3 = getelementptr i32 *%ptr1, i64 1024 - %ptr4 = getelementptr i32 *%ptr2, i64 131071 - %old1 = load i32 *%ptr1 - %old2 = load i32 *%ptr2 - %old3 = load i32 *%ptr3 - %old4 = load i32 *%ptr4 + %ptr3 = getelementptr i32, i32 *%ptr1, i64 1024 + %ptr4 = getelementptr i32, i32 *%ptr2, i64 131071 + %old1 = load i32 , i32 *%ptr1 + %old2 = load i32 , i32 *%ptr2 + %old3 = load i32 , i32 *%ptr3 + %old4 = load i32 , i32 *%ptr4 %res = call { i32, i32, i32, i32 } asm "blah $0, $1, $2, $3", "=h,=r,=h,=r,0,1,2,3"(i32 %old1, i32 %old2, i32 %old3, i32 %old4) %new1 = extractvalue { i32, i32, i32, i32 } %res, 0 @@ -60,12 +60,12 @@ define void @f3(i8 *%ptr1, i8 *%ptr2) { ; CHECK-DAG: lb [[REG4:%r[0-5]]], 524287(%r3) ; CHECK: blah [[REG1]], [[REG2]] ; CHECK: br %r14 - %ptr3 = getelementptr i8 *%ptr1, i64 4096 - %ptr4 = getelementptr i8 *%ptr2, i64 524287 - %val1 = load i8 *%ptr1 - %val2 = load i8 *%ptr2 - %val3 = load i8 *%ptr3 - %val4 = load i8 *%ptr4 + %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096 + %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287 + %val1 = load i8 , i8 *%ptr1 + %val2 = load i8 , i8 *%ptr2 + %val3 = load i8 , i8 *%ptr3 + %val4 = load i8 , i8 *%ptr4 %ext1 = sext i8 %val1 to i32 %ext2 = sext i8 %val2 to i32 %ext3 = sext i8 %val3 to i32 @@ -84,12 +84,12 @@ define void @f4(i16 *%ptr1, i16 *%ptr2) { ; CHECK-DAG: lhy [[REG4:%r[0-5]]], 524286(%r3) ; CHECK: blah [[REG1]], [[REG2]] ; CHECK: br %r14 - %ptr3 = getelementptr i16 *%ptr1, i64 2048 - %ptr4 = getelementptr i16 *%ptr2, i64 262143 - %val1 = load i16 *%ptr1 - %val2 = load i16 *%ptr2 - %val3 = load i16 *%ptr3 - %val4 = load i16 *%ptr4 + %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048 + %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143 + %val1 = load i16 , i16 *%ptr1 + %val2 = load i16 , i16 *%ptr2 + %val3 = load i16 , i16 *%ptr3 + %val4 = load i16 , i16 *%ptr4 %ext1 = sext i16 %val1 to i32 %ext2 = sext i16 %val2 to i32 %ext3 = sext i16 %val3 to i32 @@ -108,12 +108,12 @@ define void @f5(i8 *%ptr1, i8 *%ptr2) { ; CHECK-DAG: llc [[REG4:%r[0-5]]], 524287(%r3) ; CHECK: blah [[REG1]], [[REG2]] ; CHECK: br %r14 - %ptr3 = getelementptr i8 *%ptr1, i64 4096 - %ptr4 = getelementptr i8 *%ptr2, i64 524287 - %val1 = load i8 *%ptr1 - %val2 = load i8 *%ptr2 - %val3 = load i8 *%ptr3 - %val4 = load i8 *%ptr4 + %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096 + %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287 + %val1 = load i8 , i8 *%ptr1 + %val2 = load i8 , i8 *%ptr2 + %val3 = load i8 , i8 *%ptr3 + %val4 = load i8 , i8 *%ptr4 %ext1 = zext i8 %val1 to i32 %ext2 = zext i8 %val2 to i32 %ext3 = zext i8 %val3 to i32 @@ -132,12 +132,12 @@ define void @f6(i16 *%ptr1, i16 *%ptr2) { ; CHECK-DAG: llh [[REG4:%r[0-5]]], 524286(%r3) ; CHECK: blah [[REG1]], [[REG2]] ; CHECK: br %r14 - %ptr3 = getelementptr i16 *%ptr1, i64 2048 - %ptr4 = getelementptr i16 *%ptr2, i64 262143 - %val1 = load i16 *%ptr1 - %val2 = load i16 *%ptr2 - %val3 = load i16 *%ptr3 - %val4 = load i16 *%ptr4 + %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048 + %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143 + %val1 = load i16 , i16 *%ptr1 + %val2 = load i16 , i16 *%ptr2 + %val3 = load i16 , i16 *%ptr3 + %val4 = load i16 , i16 *%ptr4 %ext1 = zext i16 %val1 to i32 %ext2 = zext i16 %val2 to i32 %ext3 = zext i16 %val3 to i32 @@ -161,8 +161,8 @@ define void @f7(i8 *%ptr1, i8 *%ptr2) { %res2 = extractvalue { i32, i32 } %res, 1 %trunc1 = trunc i32 %res1 to i8 %trunc2 = trunc i32 %res2 to i8 - %ptr3 = getelementptr i8 *%ptr1, i64 4096 - %ptr4 = getelementptr i8 *%ptr2, i64 524287 + %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096 + %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287 store i8 %trunc1, i8 *%ptr1 store i8 %trunc2, i8 *%ptr2 store i8 %trunc1, i8 *%ptr3 @@ -184,8 +184,8 @@ define void @f8(i16 *%ptr1, i16 *%ptr2) { %res2 = extractvalue { i32, i32 } %res, 1 %trunc1 = trunc i32 %res1 to i16 %trunc2 = trunc i32 %res2 to i16 - %ptr3 = getelementptr i16 *%ptr1, i64 2048 - %ptr4 = getelementptr i16 *%ptr2, i64 262143 + %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048 + %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143 store i16 %trunc1, i16 *%ptr1 store i16 %trunc2, i16 *%ptr2 store i16 %trunc1, i16 *%ptr3 @@ -713,11 +713,11 @@ define void @f33(i32 *%ptr1, i32 *%ptr2) { ; CHECK: clhf [[REG2]], 0(%r3) ; CHECK: br %r14 %res1 = call i32 asm "stepa $0", "=h"() - %load1 = load i32 *%ptr1 + %load1 = load i32 , i32 *%ptr1 %cmp1 = icmp sle i32 %res1, %load1 %sel1 = select i1 %cmp1, i32 0, i32 1 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1) - %load2 = load i32 *%ptr2 + %load2 = load i32 , i32 *%ptr2 %cmp2 = icmp ule i32 %res2, %load2 %sel2 = select i1 %cmp2, i32 0, i32 1 store i32 %sel2, i32 *%ptr1 @@ -733,11 +733,11 @@ define void @f34(i32 *%ptr1, i32 *%ptr2) { ; CHECK: cl [[REG2]], 0(%r3) ; CHECK: br %r14 %res1 = call i32 asm "stepa $0", "=r"() - %load1 = load i32 *%ptr1 + %load1 = load i32 , i32 *%ptr1 %cmp1 = icmp sle i32 %res1, %load1 %sel1 = select i1 %cmp1, i32 0, i32 1 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1) - %load2 = load i32 *%ptr2 + %load2 = load i32 , i32 *%ptr2 %cmp2 = icmp ule i32 %res2, %load2 %sel2 = select i1 %cmp2, i32 0, i32 1 store i32 %sel2, i32 *%ptr1 diff --git a/test/CodeGen/SystemZ/atomic-load-01.ll b/test/CodeGen/SystemZ/atomic-load-01.ll index f3acd605b012..b2f4ebe6639e 100644 --- a/test/CodeGen/SystemZ/atomic-load-01.ll +++ b/test/CodeGen/SystemZ/atomic-load-01.ll @@ -7,6 +7,6 @@ define i8 @f1(i8 *%src) { ; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: lb %r2, 0(%r2) ; CHECK: br %r14 - %val = load atomic i8 *%src seq_cst, align 1 + %val = load atomic i8 , i8 *%src seq_cst, align 1 ret i8 %val } diff --git a/test/CodeGen/SystemZ/atomic-load-02.ll b/test/CodeGen/SystemZ/atomic-load-02.ll index d9bec60f4c1b..b2b60f3d0160 100644 --- a/test/CodeGen/SystemZ/atomic-load-02.ll +++ b/test/CodeGen/SystemZ/atomic-load-02.ll @@ -7,6 +7,6 @@ define i16 @f1(i16 *%src) { ; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: lh %r2, 0(%r2) ; CHECK: br %r14 - %val = load atomic i16 *%src seq_cst, align 2 + %val = load atomic i16 , i16 *%src seq_cst, align 2 ret i16 %val } diff --git a/test/CodeGen/SystemZ/atomic-load-03.ll b/test/CodeGen/SystemZ/atomic-load-03.ll index 7e5eb9249a93..d83c430bd0af 100644 --- a/test/CodeGen/SystemZ/atomic-load-03.ll +++ b/test/CodeGen/SystemZ/atomic-load-03.ll @@ -7,6 +7,6 @@ define i32 @f1(i32 *%src) { ; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: l %r2, 0(%r2) ; CHECK: br %r14 - %val = load atomic i32 *%src seq_cst, align 4 + %val = load atomic i32 , i32 *%src seq_cst, align 4 ret i32 %val } diff --git a/test/CodeGen/SystemZ/atomic-load-04.ll b/test/CodeGen/SystemZ/atomic-load-04.ll index c7a9a98a425d..dc6b271e00e5 100644 --- a/test/CodeGen/SystemZ/atomic-load-04.ll +++ b/test/CodeGen/SystemZ/atomic-load-04.ll @@ -7,6 +7,6 @@ define i64 @f1(i64 *%src) { ; CHECK: bcr 1{{[45]}}, %r0 ; CHECK: lg %r2, 0(%r2) ; CHECK: br %r14 - %val = load atomic i64 *%src seq_cst, align 8 + %val = load atomic i64 , i64 *%src seq_cst, align 8 ret i64 %val } diff --git a/test/CodeGen/SystemZ/atomicrmw-add-05.ll b/test/CodeGen/SystemZ/atomicrmw-add-05.ll index 956c0d9642cd..f722f79bd42f 100644 --- a/test/CodeGen/SystemZ/atomicrmw-add-05.ll +++ b/test/CodeGen/SystemZ/atomicrmw-add-05.ll @@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f3: ; CHECK: laa %r2, %r4, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131071 + %ptr = getelementptr i32, i32 *%src, i32 131071 %res = atomicrmw add i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: laa %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131072 + %ptr = getelementptr i32, i32 *%src, i32 131072 %res = atomicrmw add i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f5: ; CHECK: laa %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131072 + %ptr = getelementptr i32, i32 *%src, i32 -131072 %res = atomicrmw add i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, -524292 ; CHECK: laa %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131073 + %ptr = getelementptr i32, i32 *%src, i32 -131073 %res = atomicrmw add i32 *%ptr, i32 %b seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-add-06.ll b/test/CodeGen/SystemZ/atomicrmw-add-06.ll index f508858d1562..ef77dc018340 100644 --- a/test/CodeGen/SystemZ/atomicrmw-add-06.ll +++ b/test/CodeGen/SystemZ/atomicrmw-add-06.ll @@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f3: ; CHECK: laag %r2, %r4, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw add i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: laag %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw add i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f5: ; CHECK: laag %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw add i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, -524296 ; CHECK: laag %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw add i64 *%ptr, i64 %b seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-and-05.ll b/test/CodeGen/SystemZ/atomicrmw-and-05.ll index f0b999c60431..b8ccbe2f4e50 100644 --- a/test/CodeGen/SystemZ/atomicrmw-and-05.ll +++ b/test/CodeGen/SystemZ/atomicrmw-and-05.ll @@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f3: ; CHECK: lan %r2, %r4, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131071 + %ptr = getelementptr i32, i32 *%src, i32 131071 %res = atomicrmw and i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: lan %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131072 + %ptr = getelementptr i32, i32 *%src, i32 131072 %res = atomicrmw and i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f5: ; CHECK: lan %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131072 + %ptr = getelementptr i32, i32 *%src, i32 -131072 %res = atomicrmw and i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, -524292 ; CHECK: lan %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131073 + %ptr = getelementptr i32, i32 *%src, i32 -131073 %res = atomicrmw and i32 *%ptr, i32 %b seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-and-06.ll b/test/CodeGen/SystemZ/atomicrmw-and-06.ll index e5b71945d57c..9885cdec1f1f 100644 --- a/test/CodeGen/SystemZ/atomicrmw-and-06.ll +++ b/test/CodeGen/SystemZ/atomicrmw-and-06.ll @@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f3: ; CHECK: lang %r2, %r4, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw and i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: lang %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw and i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f5: ; CHECK: lang %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw and i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, -524296 ; CHECK: lang %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw and i64 *%ptr, i64 %b seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll index f2152c6f28bc..4ab48e46fc82 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll @@ -69,7 +69,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: l %r2, 4092(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 + %ptr = getelementptr i32, i32 *%src, i64 1023 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -80,7 +80,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, 4096(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 + %ptr = getelementptr i32, i32 *%src, i64 1024 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -91,7 +91,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, 524284(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 + %ptr = getelementptr i32, i32 *%src, i64 131071 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -103,7 +103,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: l %r2, 0(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 + %ptr = getelementptr i32, i32 *%src, i64 131072 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -114,7 +114,7 @@ define i32 @f9(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, -4(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 + %ptr = getelementptr i32, i32 *%src, i64 -1 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -125,7 +125,7 @@ define i32 @f10(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, -524288(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 + %ptr = getelementptr i32, i32 *%src, i64 -131072 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -137,7 +137,7 @@ define i32 @f11(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: l %r2, 0(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 + %ptr = getelementptr i32, i32 *%src, i64 -131073 %res = atomicrmw min i32 *%ptr, i32 %b seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll index 037eb1aa9367..afd88a3dd42d 100644 --- a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll @@ -69,7 +69,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, 524280(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -81,7 +81,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, 0(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -92,7 +92,7 @@ define i64 @f7(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, -524288(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -104,7 +104,7 @@ define i64 @f8(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, 0(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw min i64 *%ptr, i64 %b seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-or-05.ll b/test/CodeGen/SystemZ/atomicrmw-or-05.ll index b38654ca6f07..54b5be431473 100644 --- a/test/CodeGen/SystemZ/atomicrmw-or-05.ll +++ b/test/CodeGen/SystemZ/atomicrmw-or-05.ll @@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f3: ; CHECK: lao %r2, %r4, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131071 + %ptr = getelementptr i32, i32 *%src, i32 131071 %res = atomicrmw or i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: lao %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131072 + %ptr = getelementptr i32, i32 *%src, i32 131072 %res = atomicrmw or i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f5: ; CHECK: lao %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131072 + %ptr = getelementptr i32, i32 *%src, i32 -131072 %res = atomicrmw or i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, -524292 ; CHECK: lao %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131073 + %ptr = getelementptr i32, i32 *%src, i32 -131073 %res = atomicrmw or i32 *%ptr, i32 %b seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-or-06.ll b/test/CodeGen/SystemZ/atomicrmw-or-06.ll index 30874abfe4a2..3f7a05c7324d 100644 --- a/test/CodeGen/SystemZ/atomicrmw-or-06.ll +++ b/test/CodeGen/SystemZ/atomicrmw-or-06.ll @@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f3: ; CHECK: laog %r2, %r4, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw or i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: laog %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw or i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f5: ; CHECK: laog %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw or i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, -524296 ; CHECK: laog %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw or i64 *%ptr, i64 %b seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-05.ll b/test/CodeGen/SystemZ/atomicrmw-sub-05.ll index 7668f0e2a7ac..e505f373ac73 100644 --- a/test/CodeGen/SystemZ/atomicrmw-sub-05.ll +++ b/test/CodeGen/SystemZ/atomicrmw-sub-05.ll @@ -28,7 +28,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: lcr [[NEG:%r[0-5]]], %r4 ; CHECK: laa %r2, [[NEG]], 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131071 + %ptr = getelementptr i32, i32 *%src, i32 131071 %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -40,7 +40,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-DAG: agfi %r3, 524288 ; CHECK: laa %r2, [[NEG]], 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131072 + %ptr = getelementptr i32, i32 *%src, i32 131072 %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -51,7 +51,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: lcr [[NEG:%r[0-5]]], %r4 ; CHECK: laa %r2, [[NEG]], -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131072 + %ptr = getelementptr i32, i32 *%src, i32 -131072 %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -63,7 +63,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-DAG: agfi %r3, -524292 ; CHECK: laa %r2, [[NEG]], 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131073 + %ptr = getelementptr i32, i32 *%src, i32 -131073 %res = atomicrmw sub i32 *%ptr, i32 %b seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-06.ll b/test/CodeGen/SystemZ/atomicrmw-sub-06.ll index 5d11bdf96cde..7330cfa5aef3 100644 --- a/test/CodeGen/SystemZ/atomicrmw-sub-06.ll +++ b/test/CodeGen/SystemZ/atomicrmw-sub-06.ll @@ -28,7 +28,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 ; CHECK: laag %r2, [[NEG]], 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -40,7 +40,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-DAG: agfi %r3, 524288 ; CHECK: laag %r2, [[NEG]], 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -51,7 +51,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lcgr [[NEG:%r[0-5]]], %r4 ; CHECK: laag %r2, [[NEG]], -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -63,7 +63,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-DAG: agfi %r3, -524296 ; CHECK: laag %r2, [[NEG]], 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw sub i64 *%ptr, i64 %b seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll index a602a02a189e..0e49a9f1ede7 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll @@ -20,7 +20,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: l %r2, 4092(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 + %ptr = getelementptr i32, i32 *%src, i64 1023 %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -31,7 +31,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, 4096(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 + %ptr = getelementptr i32, i32 *%src, i64 1024 %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -42,7 +42,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, 524284(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 + %ptr = getelementptr i32, i32 *%src, i64 131071 %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -54,7 +54,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: l %r2, 0(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 + %ptr = getelementptr i32, i32 *%src, i64 131072 %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -65,7 +65,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, -4(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 + %ptr = getelementptr i32, i32 *%src, i64 -1 %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -76,7 +76,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: ly %r2, -524288(%r3) ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 + %ptr = getelementptr i32, i32 *%src, i64 -131072 %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -88,7 +88,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: l %r2, 0(%r3) ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 + %ptr = getelementptr i32, i32 *%src, i64 -131073 %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll index 80c0eeb7121b..7afc50e238fc 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll @@ -20,7 +20,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, 524280(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -32,7 +32,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, 0(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -43,7 +43,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, -524288(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -55,7 +55,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: lg %r2, 0(%r3) ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-05.ll b/test/CodeGen/SystemZ/atomicrmw-xor-05.ll index e9e7d30b3578..e821f7ee8ae4 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xor-05.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xor-05.ll @@ -26,7 +26,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f3: ; CHECK: lax %r2, %r4, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131071 + %ptr = getelementptr i32, i32 *%src, i32 131071 %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -37,7 +37,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: lax %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 131072 + %ptr = getelementptr i32, i32 *%src, i32 131072 %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -47,7 +47,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-LABEL: f5: ; CHECK: lax %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131072 + %ptr = getelementptr i32, i32 *%src, i32 -131072 %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst ret i32 %res } @@ -58,7 +58,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { ; CHECK: agfi %r3, -524292 ; CHECK: lax %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i32 -131073 + %ptr = getelementptr i32, i32 *%src, i32 -131073 %res = atomicrmw xor i32 *%ptr, i32 %b seq_cst ret i32 %res } diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-06.ll b/test/CodeGen/SystemZ/atomicrmw-xor-06.ll index 0870c6476f61..630ff6a60977 100644 --- a/test/CodeGen/SystemZ/atomicrmw-xor-06.ll +++ b/test/CodeGen/SystemZ/atomicrmw-xor-06.ll @@ -26,7 +26,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f3: ; CHECK: laxg %r2, %r4, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -37,7 +37,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, 524288 ; CHECK: laxg %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -47,7 +47,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { ; CHECK-LABEL: f5: ; CHECK: laxg %r2, %r4, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst ret i64 %res } @@ -58,7 +58,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { ; CHECK: agfi %r3, -524296 ; CHECK: laxg %r2, %r4, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %res = atomicrmw xor i64 *%ptr, i64 %b seq_cst ret i64 %res } diff --git a/test/CodeGen/SystemZ/branch-02.ll b/test/CodeGen/SystemZ/branch-02.ll index 38b5d27049d8..5a30cad66918 100644 --- a/test/CodeGen/SystemZ/branch-02.ll +++ b/test/CodeGen/SystemZ/branch-02.ll @@ -12,7 +12,7 @@ define void @f1(i32 *%src, i32 %target) { ; CHECK-NEXT: je .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp eq i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -27,7 +27,7 @@ define void @f2(i32 *%src, i32 %target) { ; CHECK-NEXT: jlh .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp ne i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -42,7 +42,7 @@ define void @f3(i32 *%src, i32 %target) { ; CHECK-NEXT: jle .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp sle i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -57,7 +57,7 @@ define void @f4(i32 *%src, i32 %target) { ; CHECK-NEXT: jl .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp slt i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -72,7 +72,7 @@ define void @f5(i32 *%src, i32 %target) { ; CHECK-NEXT: jh .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp sgt i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -87,7 +87,7 @@ define void @f6(i32 *%src, i32 %target) { ; CHECK-NEXT: jhe .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp sge i32 %target, %val br i1 %cond, label %loop, label %exit exit: diff --git a/test/CodeGen/SystemZ/branch-03.ll b/test/CodeGen/SystemZ/branch-03.ll index ef31a9c696ea..a258e850ea3e 100644 --- a/test/CodeGen/SystemZ/branch-03.ll +++ b/test/CodeGen/SystemZ/branch-03.ll @@ -10,7 +10,7 @@ define void @f1(i32 *%src, i32 %target) { ; CHECK-NEXT: jle .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp ule i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -25,7 +25,7 @@ define void @f2(i32 *%src, i32 %target) { ; CHECK-NEXT: jl .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp ult i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -40,7 +40,7 @@ define void @f3(i32 *%src, i32 %target) { ; CHECK-NEXT: jh .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp ugt i32 %target, %val br i1 %cond, label %loop, label %exit exit: @@ -55,7 +55,7 @@ define void @f4(i32 *%src, i32 %target) { ; CHECK-NEXT: jhe .L[[LABEL]] br label %loop loop: - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cond = icmp uge i32 %target, %val br i1 %cond, label %loop, label %exit exit: diff --git a/test/CodeGen/SystemZ/branch-04.ll b/test/CodeGen/SystemZ/branch-04.ll index fafb234616f1..8df2ca029f5f 100644 --- a/test/CodeGen/SystemZ/branch-04.ll +++ b/test/CodeGen/SystemZ/branch-04.ll @@ -11,7 +11,7 @@ define void @f1(float *%src, float %target) { ; CHECK-NEXT: je .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp oeq float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -26,7 +26,7 @@ define void @f2(float *%src, float %target) { ; CHECK-NEXT: jlh .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp one float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -41,7 +41,7 @@ define void @f3(float *%src, float %target) { ; CHECK-NEXT: jle .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp ole float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -56,7 +56,7 @@ define void @f4(float *%src, float %target) { ; CHECK-NEXT: jl .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp olt float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -71,7 +71,7 @@ define void @f5(float *%src, float %target) { ; CHECK-NEXT: jh .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp ogt float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -86,7 +86,7 @@ define void @f6(float *%src, float %target) { ; CHECK-NEXT: jhe .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp oge float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -101,7 +101,7 @@ define void @f7(float *%src, float %target) { ; CHECK-NEXT: jnlh .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp ueq float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -116,7 +116,7 @@ define void @f8(float *%src, float %target) { ; CHECK-NEXT: jne .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp une float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -131,7 +131,7 @@ define void @f9(float *%src, float %target) { ; CHECK-NEXT: jnh .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp ule float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -146,7 +146,7 @@ define void @f10(float *%src, float %target) { ; CHECK-NEXT: jnhe .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp ult float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -161,7 +161,7 @@ define void @f11(float *%src, float %target) { ; CHECK-NEXT: jnle .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp ugt float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -176,7 +176,7 @@ define void @f12(float *%src, float %target) { ; CHECK-NEXT: jnl .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp uge float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -193,7 +193,7 @@ define void @f13(float *%src, float %target) { ; CHECK-NEXT: jno .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp ord float %target, %val br i1 %cond, label %loop, label %exit exit: @@ -210,7 +210,7 @@ define void @f14(float *%src, float %target) { ; CHECK-NEXT: jo .L[[LABEL]] br label %loop loop: - %val = load volatile float *%src + %val = load volatile float , float *%src %cond = fcmp uno float %target, %val br i1 %cond, label %loop, label %exit exit: diff --git a/test/CodeGen/SystemZ/branch-06.ll b/test/CodeGen/SystemZ/branch-06.ll index 2fa23b744afb..4549b1295cf8 100644 --- a/test/CodeGen/SystemZ/branch-06.ll +++ b/test/CodeGen/SystemZ/branch-06.ll @@ -100,7 +100,7 @@ define void @f7(i8 *%targetptr) { br label %loop loop: %val = call i32 @foo() - %byte = load i8 *%targetptr + %byte = load i8 , i8 *%targetptr %target = zext i8 %byte to i32 %cond = icmp eq i32 %val, %target br i1 %cond, label %loop, label %exit @@ -118,7 +118,7 @@ define void @f8(i16 *%targetptr) { br label %loop loop: %val = call i32 @foo() - %half = load i16 *%targetptr + %half = load i16 , i16 *%targetptr %target = zext i16 %half to i32 %cond = icmp eq i32 %val, %target br i1 %cond, label %loop, label %exit @@ -136,7 +136,7 @@ define void @f9(i16 *%targetptr) { br label %loop loop: %val = call i32 @foo() - %half = load i16 *@g1 + %half = load i16 , i16 *@g1 %target = zext i16 %half to i32 %cond = icmp eq i32 %val, %target br i1 %cond, label %loop, label %exit @@ -156,9 +156,9 @@ define void @f10(i8 *%targetptr1) { br label %loop loop: %val = call i32 @foo() - %targetptr2 = getelementptr i8 *%targetptr1, i64 1 - %byte1 = load i8 *%targetptr1 - %byte2 = load i8 *%targetptr2 + %targetptr2 = getelementptr i8, i8 *%targetptr1, i64 1 + %byte1 = load i8 , i8 *%targetptr1 + %byte2 = load i8 , i8 *%targetptr2 %ext1 = zext i8 %byte1 to i32 %ext2 = zext i8 %byte2 to i32 %cond = icmp ult i32 %ext1, %ext2 @@ -178,9 +178,9 @@ define void @f11(i16 *%targetptr1) { br label %loop loop: %val = call i32 @foo() - %targetptr2 = getelementptr i16 *%targetptr1, i64 1 - %half1 = load i16 *%targetptr1 - %half2 = load i16 *%targetptr2 + %targetptr2 = getelementptr i16, i16 *%targetptr1, i64 1 + %half1 = load i16 , i16 *%targetptr1 + %half2 = load i16 , i16 *%targetptr2 %ext1 = zext i16 %half1 to i32 %ext2 = zext i16 %half2 to i32 %cond = icmp ult i32 %ext1, %ext2 diff --git a/test/CodeGen/SystemZ/branch-08.ll b/test/CodeGen/SystemZ/branch-08.ll index 6741d29aec03..0aa48063d071 100644 --- a/test/CodeGen/SystemZ/branch-08.ll +++ b/test/CodeGen/SystemZ/branch-08.ll @@ -14,7 +14,7 @@ define i32 @f1(i32 %a, i32 *%bptr) { ; CHECK: .L[[LABEL]]: ; CHECK: brasl %r14, foo@PLT entry: - %b = load i32 *%bptr + %b = load i32 , i32 *%bptr %cmp = icmp ult i32 %a, %b br i1 %cmp, label %callit, label %return diff --git a/test/CodeGen/SystemZ/bswap-02.ll b/test/CodeGen/SystemZ/bswap-02.ll index db69ea53dfe1..9c964569dfd5 100644 --- a/test/CodeGen/SystemZ/bswap-02.ll +++ b/test/CodeGen/SystemZ/bswap-02.ll @@ -9,7 +9,7 @@ define i32 @f1(i32 *%src) { ; CHECK-LABEL: f1: ; CHECK: lrv %r2, 0(%r2) ; CHECK: br %r14 - %a = load i32 *%src + %a = load i32 , i32 *%src %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -19,8 +19,8 @@ define i32 @f2(i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: lrv %r2, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %a = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %a = load i32 , i32 *%ptr %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -32,8 +32,8 @@ define i32 @f3(i32 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lrv %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %a = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %a = load i32 , i32 *%ptr %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -43,8 +43,8 @@ define i32 @f4(i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: lrv %r2, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %a = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %a = load i32 , i32 *%ptr %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -54,8 +54,8 @@ define i32 @f5(i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: lrv %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %a = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %a = load i32 , i32 *%ptr %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -67,8 +67,8 @@ define i32 @f6(i32 *%src) { ; CHECK: agfi %r2, -524292 ; CHECK: lrv %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %a = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %a = load i32 , i32 *%ptr %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -81,7 +81,7 @@ define i32 @f7(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i32 * - %a = load i32 *%ptr + %a = load i32 , i32 *%ptr %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -93,7 +93,7 @@ define i32 @f8(i32 *%src) { ; CHECK: l [[REG:%r[0-5]]], 0(%r2) ; CHECK: lrvr %r2, [[REG]] ; CHECK: br %r14 - %a = load volatile i32 *%src + %a = load volatile i32 , i32 *%src %swapped = call i32 @llvm.bswap.i32(i32 %a) ret i32 %swapped } @@ -104,22 +104,22 @@ define void @f9(i32 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: lrv {{%r[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr %swapped0 = call i32 @llvm.bswap.i32(i32 %val0) %swapped1 = call i32 @llvm.bswap.i32(i32 %val1) diff --git a/test/CodeGen/SystemZ/bswap-03.ll b/test/CodeGen/SystemZ/bswap-03.ll index d9e5ad1b52f6..ea62c4f71df6 100644 --- a/test/CodeGen/SystemZ/bswap-03.ll +++ b/test/CodeGen/SystemZ/bswap-03.ll @@ -9,7 +9,7 @@ define i64 @f1(i64 *%src) { ; CHECK-LABEL: f1: ; CHECK: lrvg %r2, 0(%r2) ; CHECK: br %r14 - %a = load i64 *%src + %a = load i64 , i64 *%src %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -19,8 +19,8 @@ define i64 @f2(i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: lrvg %r2, 524280(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %a = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %a = load i64 , i64 *%ptr %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -32,8 +32,8 @@ define i64 @f3(i64 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lrvg %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %a = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %a = load i64 , i64 *%ptr %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -43,8 +43,8 @@ define i64 @f4(i64 *%src) { ; CHECK-LABEL: f4: ; CHECK: lrvg %r2, -8(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %a = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %a = load i64 , i64 *%ptr %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -54,8 +54,8 @@ define i64 @f5(i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: lrvg %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %a = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %a = load i64 , i64 *%ptr %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -67,8 +67,8 @@ define i64 @f6(i64 *%src) { ; CHECK: agfi %r2, -524296 ; CHECK: lrvg %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %a = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %a = load i64 , i64 *%ptr %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -81,7 +81,7 @@ define i64 @f7(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i64 * - %a = load i64 *%ptr + %a = load i64 , i64 *%ptr %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -93,7 +93,7 @@ define i64 @f8(i64 *%src) { ; CHECK: lg [[REG:%r[0-5]]], 0(%r2) ; CHECK: lrvgr %r2, [[REG]] ; CHECK: br %r14 - %a = load volatile i64 *%src + %a = load volatile i64 , i64 *%src %swapped = call i64 @llvm.bswap.i64(i64 %a) ret i64 %swapped } @@ -104,22 +104,22 @@ define void @f9(i64 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: lrvg {{%r[0-9]+}}, 160(%r15) ; CHECK: br %r14 - %val0 = load volatile i64 *%ptr - %val1 = load volatile i64 *%ptr - %val2 = load volatile i64 *%ptr - %val3 = load volatile i64 *%ptr - %val4 = load volatile i64 *%ptr - %val5 = load volatile i64 *%ptr - %val6 = load volatile i64 *%ptr - %val7 = load volatile i64 *%ptr - %val8 = load volatile i64 *%ptr - %val9 = load volatile i64 *%ptr - %val10 = load volatile i64 *%ptr - %val11 = load volatile i64 *%ptr - %val12 = load volatile i64 *%ptr - %val13 = load volatile i64 *%ptr - %val14 = load volatile i64 *%ptr - %val15 = load volatile i64 *%ptr + %val0 = load volatile i64 , i64 *%ptr + %val1 = load volatile i64 , i64 *%ptr + %val2 = load volatile i64 , i64 *%ptr + %val3 = load volatile i64 , i64 *%ptr + %val4 = load volatile i64 , i64 *%ptr + %val5 = load volatile i64 , i64 *%ptr + %val6 = load volatile i64 , i64 *%ptr + %val7 = load volatile i64 , i64 *%ptr + %val8 = load volatile i64 , i64 *%ptr + %val9 = load volatile i64 , i64 *%ptr + %val10 = load volatile i64 , i64 *%ptr + %val11 = load volatile i64 , i64 *%ptr + %val12 = load volatile i64 , i64 *%ptr + %val13 = load volatile i64 , i64 *%ptr + %val14 = load volatile i64 , i64 *%ptr + %val15 = load volatile i64 , i64 *%ptr %swapped0 = call i64 @llvm.bswap.i64(i64 %val0) %swapped1 = call i64 @llvm.bswap.i64(i64 %val1) diff --git a/test/CodeGen/SystemZ/bswap-04.ll b/test/CodeGen/SystemZ/bswap-04.ll index 29d5a7b07212..ce4395210f1f 100644 --- a/test/CodeGen/SystemZ/bswap-04.ll +++ b/test/CodeGen/SystemZ/bswap-04.ll @@ -19,7 +19,7 @@ define void @f2(i32 *%dst, i32 %a) { ; CHECK-LABEL: f2: ; CHECK: strv %r3, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 131071 + %ptr = getelementptr i32, i32 *%dst, i64 131071 %swapped = call i32 @llvm.bswap.i32(i32 %a) store i32 %swapped, i32 *%ptr ret void @@ -32,7 +32,7 @@ define void @f3(i32 *%dst, i32 %a) { ; CHECK: agfi %r2, 524288 ; CHECK: strv %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 131072 + %ptr = getelementptr i32, i32 *%dst, i64 131072 %swapped = call i32 @llvm.bswap.i32(i32 %a) store i32 %swapped, i32 *%ptr ret void @@ -43,7 +43,7 @@ define void @f4(i32 *%dst, i32 %a) { ; CHECK-LABEL: f4: ; CHECK: strv %r3, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 -1 + %ptr = getelementptr i32, i32 *%dst, i64 -1 %swapped = call i32 @llvm.bswap.i32(i32 %a) store i32 %swapped, i32 *%ptr ret void @@ -54,7 +54,7 @@ define void @f5(i32 *%dst, i32 %a) { ; CHECK-LABEL: f5: ; CHECK: strv %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 -131072 + %ptr = getelementptr i32, i32 *%dst, i64 -131072 %swapped = call i32 @llvm.bswap.i32(i32 %a) store i32 %swapped, i32 *%ptr ret void @@ -67,7 +67,7 @@ define void @f6(i32 *%dst, i32 %a) { ; CHECK: agfi %r2, -524292 ; CHECK: strv %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 -131073 + %ptr = getelementptr i32, i32 *%dst, i64 -131073 %swapped = call i32 @llvm.bswap.i32(i32 %a) store i32 %swapped, i32 *%ptr ret void diff --git a/test/CodeGen/SystemZ/bswap-05.ll b/test/CodeGen/SystemZ/bswap-05.ll index 5c8361e26cea..5f90ef3b9b65 100644 --- a/test/CodeGen/SystemZ/bswap-05.ll +++ b/test/CodeGen/SystemZ/bswap-05.ll @@ -19,7 +19,7 @@ define void @f2(i64 *%dst, i64 %a) { ; CHECK-LABEL: f2: ; CHECK: strvg %r3, 524280(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 65535 + %ptr = getelementptr i64, i64 *%dst, i64 65535 %swapped = call i64 @llvm.bswap.i64(i64 %a) store i64 %swapped, i64 *%ptr ret void @@ -32,7 +32,7 @@ define void @f3(i64 *%dst, i64 %a) { ; CHECK: agfi %r2, 524288 ; CHECK: strvg %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 65536 + %ptr = getelementptr i64, i64 *%dst, i64 65536 %swapped = call i64 @llvm.bswap.i64(i64 %a) store i64 %swapped, i64 *%ptr ret void @@ -43,7 +43,7 @@ define void @f4(i64 *%dst, i64 %a) { ; CHECK-LABEL: f4: ; CHECK: strvg %r3, -8(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 -1 + %ptr = getelementptr i64, i64 *%dst, i64 -1 %swapped = call i64 @llvm.bswap.i64(i64 %a) store i64 %swapped, i64 *%ptr ret void @@ -54,7 +54,7 @@ define void @f5(i64 *%dst, i64 %a) { ; CHECK-LABEL: f5: ; CHECK: strvg %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 -65536 + %ptr = getelementptr i64, i64 *%dst, i64 -65536 %swapped = call i64 @llvm.bswap.i64(i64 %a) store i64 %swapped, i64 *%ptr ret void @@ -67,7 +67,7 @@ define void @f6(i64 *%dst, i64 %a) { ; CHECK: agfi %r2, -524296 ; CHECK: strvg %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 -65537 + %ptr = getelementptr i64, i64 *%dst, i64 -65537 %swapped = call i64 @llvm.bswap.i64(i64 %a) store i64 %swapped, i64 *%ptr ret void diff --git a/test/CodeGen/SystemZ/cmpxchg-03.ll b/test/CodeGen/SystemZ/cmpxchg-03.ll index c5fab4dc0439..c6e1955a50fd 100644 --- a/test/CodeGen/SystemZ/cmpxchg-03.ll +++ b/test/CodeGen/SystemZ/cmpxchg-03.ll @@ -17,7 +17,7 @@ define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: cs %r2, %r3, 4092(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 + %ptr = getelementptr i32, i32 *%src, i64 1023 %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst %val = extractvalue { i32, i1 } %pair, 0 ret i32 %val @@ -28,7 +28,7 @@ define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: csy %r2, %r3, 4096(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 + %ptr = getelementptr i32, i32 *%src, i64 1024 %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst %val = extractvalue { i32, i1 } %pair, 0 ret i32 %val @@ -39,7 +39,7 @@ define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: csy %r2, %r3, 524284(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 + %ptr = getelementptr i32, i32 *%src, i64 131071 %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst %val = extractvalue { i32, i1 } %pair, 0 ret i32 %val @@ -52,7 +52,7 @@ define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: cs %r2, %r3, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 + %ptr = getelementptr i32, i32 *%src, i64 131072 %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst %val = extractvalue { i32, i1 } %pair, 0 ret i32 %val @@ -63,7 +63,7 @@ define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: csy %r2, %r3, -4(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 + %ptr = getelementptr i32, i32 *%src, i64 -1 %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst %val = extractvalue { i32, i1 } %pair, 0 ret i32 %val @@ -74,7 +74,7 @@ define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: csy %r2, %r3, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 + %ptr = getelementptr i32, i32 *%src, i64 -131072 %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst %val = extractvalue { i32, i1 } %pair, 0 ret i32 %val @@ -87,7 +87,7 @@ define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) { ; CHECK: agfi %r4, -524292 ; CHECK: cs %r2, %r3, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 + %ptr = getelementptr i32, i32 *%src, i64 -131073 %pair = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst seq_cst %val = extractvalue { i32, i1 } %pair, 0 ret i32 %val diff --git a/test/CodeGen/SystemZ/cmpxchg-04.ll b/test/CodeGen/SystemZ/cmpxchg-04.ll index ba1493e1853e..b0560876b876 100644 --- a/test/CodeGen/SystemZ/cmpxchg-04.ll +++ b/test/CodeGen/SystemZ/cmpxchg-04.ll @@ -17,7 +17,7 @@ define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: csg %r2, %r3, 524280(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 + %ptr = getelementptr i64, i64 *%src, i64 65535 %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst %val = extractvalue { i64, i1 } %pairval, 0 ret i64 %val @@ -30,7 +30,7 @@ define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: csg %r2, %r3, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 + %ptr = getelementptr i64, i64 *%src, i64 65536 %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst %val = extractvalue { i64, i1 } %pairval, 0 ret i64 %val @@ -41,7 +41,7 @@ define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) { ; CHECK-LABEL: f4: ; CHECK: csg %r2, %r3, -8(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 + %ptr = getelementptr i64, i64 *%src, i64 -1 %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst %val = extractvalue { i64, i1 } %pairval, 0 ret i64 %val @@ -52,7 +52,7 @@ define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: csg %r2, %r3, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 + %ptr = getelementptr i64, i64 *%src, i64 -65536 %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst %val = extractvalue { i64, i1 } %pairval, 0 ret i64 %val @@ -65,7 +65,7 @@ define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) { ; CHECK: agfi %r4, -524296 ; CHECK: csg %r2, %r3, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 + %ptr = getelementptr i64, i64 *%src, i64 -65537 %pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst %val = extractvalue { i64, i1 } %pairval, 0 ret i64 %val diff --git a/test/CodeGen/SystemZ/cond-load-01.ll b/test/CodeGen/SystemZ/cond-load-01.ll index 1030226798d1..97d4027126b8 100644 --- a/test/CodeGen/SystemZ/cond-load-01.ll +++ b/test/CodeGen/SystemZ/cond-load-01.ll @@ -11,7 +11,7 @@ define i32 @f1(i32 %easy, i32 *%ptr, i32 %limit) { ; CHECK: loche %r2, 0(%r3) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %easy, i32 %other ret i32 %res } @@ -23,7 +23,7 @@ define i32 @f2(i32 %easy, i32 *%ptr, i32 %limit) { ; CHECK: locl %r2, 0(%r3) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %other, i32 %easy ret i32 %res } @@ -34,9 +34,9 @@ define i32 @f3(i32 %easy, i32 *%base, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: loche %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 + %ptr = getelementptr i32, i32 *%base, i64 131071 %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %easy, i32 %other ret i32 %res } @@ -48,9 +48,9 @@ define i32 @f4(i32 %easy, i32 *%base, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: loche %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 + %ptr = getelementptr i32, i32 *%base, i64 131072 %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %easy, i32 %other ret i32 %res } @@ -61,9 +61,9 @@ define i32 @f5(i32 %easy, i32 *%base, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: loche %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 + %ptr = getelementptr i32, i32 *%base, i64 -131072 %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %easy, i32 %other ret i32 %res } @@ -75,9 +75,9 @@ define i32 @f6(i32 %easy, i32 *%base, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: loche %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 + %ptr = getelementptr i32, i32 *%base, i64 -131073 %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %easy, i32 %other ret i32 %res } @@ -91,7 +91,7 @@ define i32 @f7(i32 %alt, i32 %limit) { %ptr = alloca i32 %easy = call i32 @foo(i32 *%ptr) %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %easy, i32 %other ret i32 %res } @@ -105,7 +105,7 @@ define i32 @f8(i32 %easy, i32 %limit, i64 %base, i64 %index) { %add = add i64 %base, %index %ptr = inttoptr i64 %add to i32 * %cond = icmp ult i32 %limit, 42 - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr %res = select i1 %cond, i32 %easy, i32 %other ret i32 %res } @@ -121,7 +121,7 @@ entry: br i1 %cmp, label %load, label %exit load: - %other = load i32 *%ptr + %other = load i32 , i32 *%ptr br label %exit exit: diff --git a/test/CodeGen/SystemZ/cond-load-02.ll b/test/CodeGen/SystemZ/cond-load-02.ll index e97f4728bc0b..d0fe65e2fe0e 100644 --- a/test/CodeGen/SystemZ/cond-load-02.ll +++ b/test/CodeGen/SystemZ/cond-load-02.ll @@ -11,7 +11,7 @@ define i64 @f1(i64 %easy, i64 *%ptr, i64 %limit) { ; CHECK: locghe %r2, 0(%r3) ; CHECK: br %r14 %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %easy, i64 %other ret i64 %res } @@ -23,7 +23,7 @@ define i64 @f2(i64 %easy, i64 *%ptr, i64 %limit) { ; CHECK: locgl %r2, 0(%r3) ; CHECK: br %r14 %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %other, i64 %easy ret i64 %res } @@ -34,9 +34,9 @@ define i64 @f3(i64 %easy, i64 *%base, i64 %limit) { ; CHECK: clgfi %r4, 42 ; CHECK: locghe %r2, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65535 + %ptr = getelementptr i64, i64 *%base, i64 65535 %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %easy, i64 %other ret i64 %res } @@ -48,9 +48,9 @@ define i64 @f4(i64 %easy, i64 *%base, i64 %limit) { ; CHECK: clgfi %r4, 42 ; CHECK: locghe %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65536 + %ptr = getelementptr i64, i64 *%base, i64 65536 %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %easy, i64 %other ret i64 %res } @@ -61,9 +61,9 @@ define i64 @f5(i64 %easy, i64 *%base, i64 %limit) { ; CHECK: clgfi %r4, 42 ; CHECK: locghe %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65536 + %ptr = getelementptr i64, i64 *%base, i64 -65536 %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %easy, i64 %other ret i64 %res } @@ -75,9 +75,9 @@ define i64 @f6(i64 %easy, i64 *%base, i64 %limit) { ; CHECK: clgfi %r4, 42 ; CHECK: locghe %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65537 + %ptr = getelementptr i64, i64 *%base, i64 -65537 %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %easy, i64 %other ret i64 %res } @@ -91,7 +91,7 @@ define i64 @f7(i64 %alt, i64 %limit) { %ptr = alloca i64 %easy = call i64 @foo(i64 *%ptr) %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %easy, i64 %other ret i64 %res } @@ -105,7 +105,7 @@ define i64 @f8(i64 %easy, i64 %limit, i64 %base, i64 %index) { %add = add i64 %base, %index %ptr = inttoptr i64 %add to i64 * %cond = icmp ult i64 %limit, 42 - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr %res = select i1 %cond, i64 %easy, i64 %other ret i64 %res } @@ -121,7 +121,7 @@ entry: br i1 %cmp, label %load, label %exit load: - %other = load i64 *%ptr + %other = load i64 , i64 *%ptr br label %exit exit: diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll index 62e9796fa21b..ec7fc4a31fcd 100644 --- a/test/CodeGen/SystemZ/cond-store-01.ll +++ b/test/CodeGen/SystemZ/cond-store-01.ll @@ -15,7 +15,7 @@ define void @f1(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -31,7 +31,7 @@ define void @f2(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %alt, i8 %orig store i8 %res, i8 *%ptr ret void @@ -48,7 +48,7 @@ define void @f3(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = sext i8 %orig to i32 %res = select i1 %cond, i32 %ext, i32 %alt %trunc = trunc i32 %res to i8 @@ -66,7 +66,7 @@ define void @f4(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = sext i8 %orig to i32 %res = select i1 %cond, i32 %alt, i32 %ext %trunc = trunc i32 %res to i8 @@ -85,7 +85,7 @@ define void @f5(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = zext i8 %orig to i32 %res = select i1 %cond, i32 %ext, i32 %alt %trunc = trunc i32 %res to i8 @@ -103,7 +103,7 @@ define void @f6(i8 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = zext i8 %orig to i32 %res = select i1 %cond, i32 %alt, i32 %ext %trunc = trunc i32 %res to i8 @@ -122,7 +122,7 @@ define void @f7(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = sext i8 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i8 @@ -140,7 +140,7 @@ define void @f8(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = sext i8 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i8 @@ -159,7 +159,7 @@ define void @f9(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = zext i8 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i8 @@ -177,7 +177,7 @@ define void @f10(i8 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %ext = zext i8 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i8 @@ -194,9 +194,9 @@ define void @f11(i8 *%base, i8 %alt, i32 %limit) { ; CHECK: stc %r3, 4095(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i8 *%base, i64 4095 + %ptr = getelementptr i8, i8 *%base, i64 4095 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -211,9 +211,9 @@ define void @f12(i8 *%base, i8 %alt, i32 %limit) { ; CHECK: stcy %r3, 4096(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i8 *%base, i64 4096 + %ptr = getelementptr i8, i8 *%base, i64 4096 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -228,9 +228,9 @@ define void @f13(i8 *%base, i8 %alt, i32 %limit) { ; CHECK: stcy %r3, 524287(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i8 *%base, i64 524287 + %ptr = getelementptr i8, i8 *%base, i64 524287 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -247,9 +247,9 @@ define void @f14(i8 *%base, i8 %alt, i32 %limit) { ; CHECK: stc %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i8 *%base, i64 524288 + %ptr = getelementptr i8, i8 *%base, i64 524288 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -264,9 +264,9 @@ define void @f15(i8 *%base, i8 %alt, i32 %limit) { ; CHECK: stcy %r3, -524288(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i8 *%base, i64 -524288 + %ptr = getelementptr i8, i8 *%base, i64 -524288 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -283,9 +283,9 @@ define void @f16(i8 *%base, i8 %alt, i32 %limit) { ; CHECK: stc %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i8 *%base, i64 -524289 + %ptr = getelementptr i8, i8 *%base, i64 -524289 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -304,7 +304,7 @@ define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) { %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i8 * %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -319,7 +319,7 @@ define void @f18(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK: stc {{%r[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load volatile i8 *%ptr + %orig = load volatile i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -334,7 +334,7 @@ define void @f19(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK: stc %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store volatile i8 %res, i8 *%ptr ret void @@ -353,7 +353,7 @@ define void @f20(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK: stc {{%r[0-9]+}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load atomic i8 *%ptr unordered, align 1 + %orig = load atomic i8 , i8 *%ptr unordered, align 1 %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr ret void @@ -369,7 +369,7 @@ define void @f21(i8 *%ptr, i8 %alt, i32 %limit) { ; CHECK: stc %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store atomic i8 %res, i8 *%ptr unordered, align 1 ret void @@ -389,7 +389,7 @@ define void @f22(i8 %alt, i32 %limit) { %ptr = alloca i8 call void @foo(i8 *%ptr) %cond = icmp ult i32 %limit, 420 - %orig = load i8 *%ptr + %orig = load i8 , i8 *%ptr %res = select i1 %cond, i8 %orig, i8 %alt store i8 %res, i8 *%ptr call void @foo(i8 *%ptr) diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll index 4fbcdaba5103..22bdfa3c27dc 100644 --- a/test/CodeGen/SystemZ/cond-store-02.ll +++ b/test/CodeGen/SystemZ/cond-store-02.ll @@ -15,7 +15,7 @@ define void @f1(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -31,7 +31,7 @@ define void @f2(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %alt, i16 %orig store i16 %res, i16 *%ptr ret void @@ -48,7 +48,7 @@ define void @f3(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = sext i16 %orig to i32 %res = select i1 %cond, i32 %ext, i32 %alt %trunc = trunc i32 %res to i16 @@ -66,7 +66,7 @@ define void @f4(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = sext i16 %orig to i32 %res = select i1 %cond, i32 %alt, i32 %ext %trunc = trunc i32 %res to i16 @@ -85,7 +85,7 @@ define void @f5(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = zext i16 %orig to i32 %res = select i1 %cond, i32 %ext, i32 %alt %trunc = trunc i32 %res to i16 @@ -103,7 +103,7 @@ define void @f6(i16 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = zext i16 %orig to i32 %res = select i1 %cond, i32 %alt, i32 %ext %trunc = trunc i32 %res to i16 @@ -122,7 +122,7 @@ define void @f7(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = sext i16 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i16 @@ -140,7 +140,7 @@ define void @f8(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = sext i16 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i16 @@ -159,7 +159,7 @@ define void @f9(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = zext i16 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i16 @@ -177,7 +177,7 @@ define void @f10(i16 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %ext = zext i16 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i16 @@ -194,9 +194,9 @@ define void @f11(i16 *%base, i16 %alt, i32 %limit) { ; CHECK: sth %r3, 4094(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 2047 + %ptr = getelementptr i16, i16 *%base, i64 2047 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -211,9 +211,9 @@ define void @f12(i16 *%base, i16 %alt, i32 %limit) { ; CHECK: sthy %r3, 4096(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 2048 + %ptr = getelementptr i16, i16 *%base, i64 2048 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -228,9 +228,9 @@ define void @f13(i16 *%base, i16 %alt, i32 %limit) { ; CHECK: sthy %r3, 524286(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 262143 + %ptr = getelementptr i16, i16 *%base, i64 262143 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -247,9 +247,9 @@ define void @f14(i16 *%base, i16 %alt, i32 %limit) { ; CHECK: sth %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 262144 + %ptr = getelementptr i16, i16 *%base, i64 262144 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -264,9 +264,9 @@ define void @f15(i16 *%base, i16 %alt, i32 %limit) { ; CHECK: sthy %r3, -524288(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 -262144 + %ptr = getelementptr i16, i16 *%base, i64 -262144 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -283,9 +283,9 @@ define void @f16(i16 *%base, i16 %alt, i32 %limit) { ; CHECK: sth %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 -262145 + %ptr = getelementptr i16, i16 *%base, i64 -262145 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -304,7 +304,7 @@ define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) { %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i16 * %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -319,7 +319,7 @@ define void @f18(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK: sth {{%r[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load volatile i16 *%ptr + %orig = load volatile i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -334,7 +334,7 @@ define void @f19(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK: sth %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store volatile i16 %res, i16 *%ptr ret void @@ -353,7 +353,7 @@ define void @f20(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK: sth {{%r[0-9]+}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load atomic i16 *%ptr unordered, align 2 + %orig = load atomic i16 , i16 *%ptr unordered, align 2 %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr ret void @@ -369,7 +369,7 @@ define void @f21(i16 *%ptr, i16 %alt, i32 %limit) { ; CHECK: sth %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store atomic i16 %res, i16 *%ptr unordered, align 2 ret void @@ -389,7 +389,7 @@ define void @f22(i16 %alt, i32 %limit) { %ptr = alloca i16 call void @foo(i16 *%ptr) %cond = icmp ult i32 %limit, 420 - %orig = load i16 *%ptr + %orig = load i16 , i16 *%ptr %res = select i1 %cond, i16 %orig, i16 %alt store i16 %res, i16 *%ptr call void @foo(i16 *%ptr) diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll index 4b22555d0d60..7207164a6314 100644 --- a/test/CodeGen/SystemZ/cond-store-03.ll +++ b/test/CodeGen/SystemZ/cond-store-03.ll @@ -14,7 +14,7 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -30,7 +30,7 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %alt, i32 %orig store i32 %res, i32 *%ptr ret void @@ -47,7 +47,7 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = sext i32 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i32 @@ -65,7 +65,7 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = sext i32 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i32 @@ -84,7 +84,7 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = zext i32 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i32 @@ -102,7 +102,7 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = zext i32 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i32 @@ -119,9 +119,9 @@ define void @f7(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: st %r3, 4092(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1023 + %ptr = getelementptr i32, i32 *%base, i64 1023 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -136,9 +136,9 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: sty %r3, 4096(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1024 + %ptr = getelementptr i32, i32 *%base, i64 1024 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -153,9 +153,9 @@ define void @f9(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: sty %r3, 524284(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 + %ptr = getelementptr i32, i32 *%base, i64 131071 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -172,9 +172,9 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: st %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 + %ptr = getelementptr i32, i32 *%base, i64 131072 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -189,9 +189,9 @@ define void @f11(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: sty %r3, -524288(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 + %ptr = getelementptr i32, i32 *%base, i64 -131072 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -208,9 +208,9 @@ define void @f12(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: st %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 + %ptr = getelementptr i32, i32 *%base, i64 -131073 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -229,7 +229,7 @@ define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) { %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -244,7 +244,7 @@ define void @f14(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: st {{%r[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load volatile i32 *%ptr + %orig = load volatile i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -259,7 +259,7 @@ define void @f15(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: st %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store volatile i32 %res, i32 *%ptr ret void @@ -278,7 +278,7 @@ define void @f16(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: st {{%r[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load atomic i32 *%ptr unordered, align 4 + %orig = load atomic i32 , i32 *%ptr unordered, align 4 %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -294,7 +294,7 @@ define void @f17(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: st %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store atomic i32 %res, i32 *%ptr unordered, align 4 ret void @@ -314,7 +314,7 @@ define void @f18(i32 %alt, i32 %limit) { %ptr = alloca i32 call void @foo(i32 *%ptr) %cond = icmp ult i32 %limit, 420 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr call void @foo(i32 *%ptr) diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll index 346b51a17d78..7e25bb5c14a0 100644 --- a/test/CodeGen/SystemZ/cond-store-04.ll +++ b/test/CodeGen/SystemZ/cond-store-04.ll @@ -14,7 +14,7 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -30,7 +30,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %alt, i64 %orig store i64 %res, i64 *%ptr ret void @@ -45,9 +45,9 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: stg %r3, 524280(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65535 + %ptr = getelementptr i64, i64 *%base, i64 65535 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -64,9 +64,9 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: stg %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65536 + %ptr = getelementptr i64, i64 *%base, i64 65536 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -81,9 +81,9 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: stg %r3, -524288(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65536 + %ptr = getelementptr i64, i64 *%base, i64 -65536 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -100,9 +100,9 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: stg %r3, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65537 + %ptr = getelementptr i64, i64 *%base, i64 -65537 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -121,7 +121,7 @@ define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) { %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i64 * %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -136,7 +136,7 @@ define void @f8(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stg {{%r[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load volatile i64 *%ptr + %orig = load volatile i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -151,7 +151,7 @@ define void @f9(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stg %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store volatile i64 %res, i64 *%ptr ret void @@ -170,7 +170,7 @@ define void @f10(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stg {{%r[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load atomic i64 *%ptr unordered, align 8 + %orig = load atomic i64 , i64 *%ptr unordered, align 8 %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -186,7 +186,7 @@ define void @f11(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stg %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store atomic i64 %res, i64 *%ptr unordered, align 8 ret void @@ -206,7 +206,7 @@ define void @f12(i64 %alt, i32 %limit) { %ptr = alloca i64 call void @foo(i64 *%ptr) %cond = icmp ult i32 %limit, 420 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr call void @foo(i64 *%ptr) diff --git a/test/CodeGen/SystemZ/cond-store-05.ll b/test/CodeGen/SystemZ/cond-store-05.ll index f8056f73c928..0cc068380e07 100644 --- a/test/CodeGen/SystemZ/cond-store-05.ll +++ b/test/CodeGen/SystemZ/cond-store-05.ll @@ -14,7 +14,7 @@ define void @f1(float *%ptr, float %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -30,7 +30,7 @@ define void @f2(float *%ptr, float %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %alt, float %orig store float %res, float *%ptr ret void @@ -45,9 +45,9 @@ define void @f3(float *%base, float %alt, i32 %limit) { ; CHECK: ste %f0, 4092(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 + %ptr = getelementptr float, float *%base, i64 1023 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -62,9 +62,9 @@ define void @f4(float *%base, float %alt, i32 %limit) { ; CHECK: stey %f0, 4096(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 + %ptr = getelementptr float, float *%base, i64 1024 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -79,9 +79,9 @@ define void @f5(float *%base, float %alt, i32 %limit) { ; CHECK: stey %f0, 524284(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 131071 + %ptr = getelementptr float, float *%base, i64 131071 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -98,9 +98,9 @@ define void @f6(float *%base, float %alt, i32 %limit) { ; CHECK: ste %f0, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 131072 + %ptr = getelementptr float, float *%base, i64 131072 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -115,9 +115,9 @@ define void @f7(float *%base, float %alt, i32 %limit) { ; CHECK: stey %f0, -524288(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -131072 + %ptr = getelementptr float, float *%base, i64 -131072 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -134,9 +134,9 @@ define void @f8(float *%base, float %alt, i32 %limit) { ; CHECK: ste %f0, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -131073 + %ptr = getelementptr float, float *%base, i64 -131073 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -155,7 +155,7 @@ define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) { %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to float * %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -170,7 +170,7 @@ define void @f10(float *%ptr, float %alt, i32 %limit) { ; CHECK: ste {{%f[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load volatile float *%ptr + %orig = load volatile float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr ret void @@ -185,7 +185,7 @@ define void @f11(float *%ptr, float %alt, i32 %limit) { ; CHECK: ste %f0, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store volatile float %res, float *%ptr ret void @@ -205,7 +205,7 @@ define void @f12(float %alt, i32 %limit) { %ptr = alloca float call void @foo(float *%ptr) %cond = icmp ult i32 %limit, 420 - %orig = load float *%ptr + %orig = load float , float *%ptr %res = select i1 %cond, float %orig, float %alt store float %res, float *%ptr call void @foo(float *%ptr) diff --git a/test/CodeGen/SystemZ/cond-store-06.ll b/test/CodeGen/SystemZ/cond-store-06.ll index 66681958d474..01948b811504 100644 --- a/test/CodeGen/SystemZ/cond-store-06.ll +++ b/test/CodeGen/SystemZ/cond-store-06.ll @@ -14,7 +14,7 @@ define void @f1(double *%ptr, double %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -30,7 +30,7 @@ define void @f2(double *%ptr, double %alt, i32 %limit) { ; CHECK: [[LABEL]]: ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %alt, double %orig store double %res, double *%ptr ret void @@ -45,9 +45,9 @@ define void @f3(double *%base, double %alt, i32 %limit) { ; CHECK: std %f0, 4088(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 + %ptr = getelementptr double, double *%base, i64 511 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -62,9 +62,9 @@ define void @f4(double *%base, double %alt, i32 %limit) { ; CHECK: stdy %f0, 4096(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 + %ptr = getelementptr double, double *%base, i64 512 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -79,9 +79,9 @@ define void @f5(double *%base, double %alt, i32 %limit) { ; CHECK: stdy %f0, 524280(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 65535 + %ptr = getelementptr double, double *%base, i64 65535 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -98,9 +98,9 @@ define void @f6(double *%base, double %alt, i32 %limit) { ; CHECK: std %f0, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 65536 + %ptr = getelementptr double, double *%base, i64 65536 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -115,9 +115,9 @@ define void @f7(double *%base, double %alt, i32 %limit) { ; CHECK: stdy %f0, -524288(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -65536 + %ptr = getelementptr double, double *%base, i64 -65536 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -134,9 +134,9 @@ define void @f8(double *%base, double %alt, i32 %limit) { ; CHECK: std %f0, 0(%r2) ; CHECK: [[LABEL]]: ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -65537 + %ptr = getelementptr double, double *%base, i64 -65537 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -155,7 +155,7 @@ define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) { %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to double * %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -170,7 +170,7 @@ define void @f10(double *%ptr, double %alt, i32 %limit) { ; CHECK: std {{%f[0-5]}}, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load volatile double *%ptr + %orig = load volatile double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr ret void @@ -185,7 +185,7 @@ define void @f11(double *%ptr, double %alt, i32 %limit) { ; CHECK: std %f0, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store volatile double %res, double *%ptr ret void @@ -205,7 +205,7 @@ define void @f12(double %alt, i32 %limit) { %ptr = alloca double call void @foo(double *%ptr) %cond = icmp ult i32 %limit, 420 - %orig = load double *%ptr + %orig = load double , double *%ptr %res = select i1 %cond, double %orig, double %alt store double %res, double *%ptr call void @foo(double *%ptr) diff --git a/test/CodeGen/SystemZ/cond-store-07.ll b/test/CodeGen/SystemZ/cond-store-07.ll index b1df525566a3..35b1303f4024 100644 --- a/test/CodeGen/SystemZ/cond-store-07.ll +++ b/test/CodeGen/SystemZ/cond-store-07.ll @@ -11,7 +11,7 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: stoche %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -24,7 +24,7 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) { ; CHECK: stocl %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %alt, i32 %orig store i32 %res, i32 *%ptr ret void @@ -38,7 +38,7 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stoche %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = sext i32 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i32 @@ -53,7 +53,7 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stocl %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = sext i32 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i32 @@ -69,7 +69,7 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stoche %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = zext i32 %orig to i64 %res = select i1 %cond, i64 %ext, i64 %alt %trunc = trunc i64 %res to i32 @@ -84,7 +84,7 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stocl %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %ext = zext i32 %orig to i64 %res = select i1 %cond, i64 %alt, i64 %ext %trunc = trunc i64 %res to i32 @@ -98,9 +98,9 @@ define void @f7(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stoche %r3, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 + %ptr = getelementptr i32, i32 *%base, i64 131071 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -113,9 +113,9 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stoche %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 + %ptr = getelementptr i32, i32 *%base, i64 131072 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -127,9 +127,9 @@ define void @f9(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stoche %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 + %ptr = getelementptr i32, i32 *%base, i64 -131072 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -142,9 +142,9 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stoche %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 + %ptr = getelementptr i32, i32 *%base, i64 -131073 %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr ret void @@ -160,7 +160,7 @@ define void @f11(i32 %alt, i32 %limit) { %ptr = alloca i32 call void @foo(i32 *%ptr) %cond = icmp ult i32 %limit, 42 - %orig = load i32 *%ptr + %orig = load i32 , i32 *%ptr %res = select i1 %cond, i32 %orig, i32 %alt store i32 %res, i32 *%ptr call void @foo(i32 *%ptr) diff --git a/test/CodeGen/SystemZ/cond-store-08.ll b/test/CodeGen/SystemZ/cond-store-08.ll index 56dc7ee7777c..4c2b005968e8 100644 --- a/test/CodeGen/SystemZ/cond-store-08.ll +++ b/test/CodeGen/SystemZ/cond-store-08.ll @@ -11,7 +11,7 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stocghe %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -24,7 +24,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) { ; CHECK: stocgl %r3, 0(%r2) ; CHECK: br %r14 %cond = icmp ult i32 %limit, 42 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %alt, i64 %orig store i64 %res, i64 *%ptr ret void @@ -36,9 +36,9 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stocghe %r3, 524280(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65535 + %ptr = getelementptr i64, i64 *%base, i64 65535 %cond = icmp ult i32 %limit, 42 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -51,9 +51,9 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stocghe %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65536 + %ptr = getelementptr i64, i64 *%base, i64 65536 %cond = icmp ult i32 %limit, 42 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -65,9 +65,9 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stocghe %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65536 + %ptr = getelementptr i64, i64 *%base, i64 -65536 %cond = icmp ult i32 %limit, 42 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -80,9 +80,9 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) { ; CHECK: clfi %r4, 42 ; CHECK: stocghe %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65537 + %ptr = getelementptr i64, i64 *%base, i64 -65537 %cond = icmp ult i32 %limit, 42 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr ret void @@ -98,7 +98,7 @@ define void @f7(i64 %alt, i32 %limit) { %ptr = alloca i64 call void @foo(i64 *%ptr) %cond = icmp ult i32 %limit, 42 - %orig = load i64 *%ptr + %orig = load i64 , i64 *%ptr %res = select i1 %cond, i64 %orig, i64 %alt store i64 %res, i64 *%ptr call void @foo(i64 *%ptr) diff --git a/test/CodeGen/SystemZ/ctpop-01.ll b/test/CodeGen/SystemZ/ctpop-01.ll new file mode 100644 index 000000000000..ad80f9f21515 --- /dev/null +++ b/test/CodeGen/SystemZ/ctpop-01.ll @@ -0,0 +1,96 @@ +; Test population-count instruction +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +declare i32 @llvm.ctpop.i32(i32 %a) +declare i64 @llvm.ctpop.i64(i64 %a) + +define i32 @f1(i32 %a) { +; CHECK-LABEL: f1: +; CHECK: popcnt %r0, %r2 +; CHECK: sllk %r1, %r0, 16 +; CHECK: ar %r1, %r0 +; CHECK: sllk %r2, %r1, 8 +; CHECK: ar %r2, %r1 +; CHECK: srl %r2, 24 +; CHECK: br %r14 + + %popcnt = call i32 @llvm.ctpop.i32(i32 %a) + ret i32 %popcnt +} + +define i32 @f2(i32 %a) { +; CHECK-LABEL: f2: +; CHECK: llhr %r0, %r2 +; CHECK: popcnt %r0, %r0 +; CHECK: risblg %r2, %r0, 16, 151, 8 +; CHECK: ar %r2, %r0 +; CHECK: srl %r2, 8 +; CHECK: br %r14 + %and = and i32 %a, 65535 + %popcnt = call i32 @llvm.ctpop.i32(i32 %and) + ret i32 %popcnt +} + +define i32 @f3(i32 %a) { +; CHECK-LABEL: f3: +; CHECK: llcr %r0, %r2 +; CHECK: popcnt %r2, %r0 +; CHECK: br %r14 + %and = and i32 %a, 255 + %popcnt = call i32 @llvm.ctpop.i32(i32 %and) + ret i32 %popcnt +} + +define i64 @f4(i64 %a) { +; CHECK-LABEL: f4: +; CHECK: popcnt %r0, %r2 +; CHECK: sllg %r1, %r0, 32 +; CHECK: agr %r1, %r0 +; CHECK: sllg %r0, %r1, 16 +; CHECK: agr %r0, %r1 +; CHECK: sllg %r1, %r0, 8 +; CHECK: agr %r1, %r0 +; CHECK: srlg %r2, %r1, 56 +; CHECK: br %r14 + %popcnt = call i64 @llvm.ctpop.i64(i64 %a) + ret i64 %popcnt +} + +define i64 @f5(i64 %a) { +; CHECK-LABEL: f5: +; CHECK: llgfr %r0, %r2 +; CHECK: popcnt %r0, %r0 +; CHECK: sllg %r1, %r0, 16 +; CHECK: algfr %r0, %r1 +; CHECK: sllg %r1, %r0, 8 +; CHECK: algfr %r0, %r1 +; CHECK: srlg %r2, %r0, 24 + %and = and i64 %a, 4294967295 + %popcnt = call i64 @llvm.ctpop.i64(i64 %and) + ret i64 %popcnt +} + +define i64 @f6(i64 %a) { +; CHECK-LABEL: f6: +; CHECK: llghr %r0, %r2 +; CHECK: popcnt %r0, %r0 +; CHECK: risbg %r1, %r0, 48, 183, 8 +; CHECK: agr %r1, %r0 +; CHECK: srlg %r2, %r1, 8 +; CHECK: br %r14 + %and = and i64 %a, 65535 + %popcnt = call i64 @llvm.ctpop.i64(i64 %and) + ret i64 %popcnt +} + +define i64 @f7(i64 %a) { +; CHECK-LABEL: f7: +; CHECK: llgcr %r0, %r2 +; CHECK: popcnt %r2, %r0 +; CHECK: br %r14 + %and = and i64 %a, 255 + %popcnt = call i64 @llvm.ctpop.i64(i64 %and) + ret i64 %popcnt +} + diff --git a/test/CodeGen/SystemZ/fp-abs-01.ll b/test/CodeGen/SystemZ/fp-abs-01.ll index 0b4067da3d14..3b143d93315b 100644 --- a/test/CodeGen/SystemZ/fp-abs-01.ll +++ b/test/CodeGen/SystemZ/fp-abs-01.ll @@ -1,6 +1,7 @@ ; Test floating-point absolute. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test f32. declare float @llvm.fabs.f32(float %f) @@ -31,9 +32,9 @@ define void @f3(fp128 *%ptr, fp128 *%ptr2) { ; CHECK: lpxbr ; CHECK: dxbr ; CHECK: br %r14 - %orig = load fp128 *%ptr + %orig = load fp128 , fp128 *%ptr %abs = call fp128 @llvm.fabs.f128(fp128 %orig) - %op2 = load fp128 *%ptr2 + %op2 = load fp128 , fp128 *%ptr2 %res = fdiv fp128 %abs, %op2 store fp128 %res, fp128 *%ptr ret void diff --git a/test/CodeGen/SystemZ/fp-abs-02.ll b/test/CodeGen/SystemZ/fp-abs-02.ll index 909c48a06377..e831ddb86fea 100644 --- a/test/CodeGen/SystemZ/fp-abs-02.ll +++ b/test/CodeGen/SystemZ/fp-abs-02.ll @@ -1,6 +1,7 @@ ; Test negated floating-point absolute. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test f32. declare float @llvm.fabs.f32(float %f) @@ -33,10 +34,10 @@ define void @f3(fp128 *%ptr, fp128 *%ptr2) { ; CHECK: lnxbr ; CHECK: dxbr ; CHECK: br %r14 - %orig = load fp128 *%ptr + %orig = load fp128 , fp128 *%ptr %abs = call fp128 @llvm.fabs.f128(fp128 %orig) %negabs = fsub fp128 0xL00000000000000008000000000000000, %abs - %op2 = load fp128 *%ptr2 + %op2 = load fp128 , fp128 *%ptr2 %res = fdiv fp128 %negabs, %op2 store fp128 %res, fp128 *%ptr ret void diff --git a/test/CodeGen/SystemZ/fp-add-01.ll b/test/CodeGen/SystemZ/fp-add-01.ll index 28a212801a63..5b0ed0513a37 100644 --- a/test/CodeGen/SystemZ/fp-add-01.ll +++ b/test/CodeGen/SystemZ/fp-add-01.ll @@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: aeb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %res = fadd float %f1, %f2 ret float %res } @@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) { ; CHECK-LABEL: f3: ; CHECK: aeb %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %res = fadd float %f1, %f2 ret float %res } @@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: aeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %res = fadd float %f1, %f2 ret float %res } @@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) { ; CHECK: aghi %r2, -4 ; CHECK: aeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %res = fadd float %f1, %f2 ret float %res } @@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 2 ; CHECK: aeb %f0, 400(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %f2 = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %f2 = load float , float *%ptr2 %res = fadd float %f1, %f2 ret float %res } @@ -78,28 +78,28 @@ define float @f7(float *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: aeb %f0, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr float *%ptr0, i64 2 - %ptr2 = getelementptr float *%ptr0, i64 4 - %ptr3 = getelementptr float *%ptr0, i64 6 - %ptr4 = getelementptr float *%ptr0, i64 8 - %ptr5 = getelementptr float *%ptr0, i64 10 - %ptr6 = getelementptr float *%ptr0, i64 12 - %ptr7 = getelementptr float *%ptr0, i64 14 - %ptr8 = getelementptr float *%ptr0, i64 16 - %ptr9 = getelementptr float *%ptr0, i64 18 - %ptr10 = getelementptr float *%ptr0, i64 20 + %ptr1 = getelementptr float, float *%ptr0, i64 2 + %ptr2 = getelementptr float, float *%ptr0, i64 4 + %ptr3 = getelementptr float, float *%ptr0, i64 6 + %ptr4 = getelementptr float, float *%ptr0, i64 8 + %ptr5 = getelementptr float, float *%ptr0, i64 10 + %ptr6 = getelementptr float, float *%ptr0, i64 12 + %ptr7 = getelementptr float, float *%ptr0, i64 14 + %ptr8 = getelementptr float, float *%ptr0, i64 16 + %ptr9 = getelementptr float, float *%ptr0, i64 18 + %ptr10 = getelementptr float, float *%ptr0, i64 20 - %val0 = load float *%ptr0 - %val1 = load float *%ptr1 - %val2 = load float *%ptr2 - %val3 = load float *%ptr3 - %val4 = load float *%ptr4 - %val5 = load float *%ptr5 - %val6 = load float *%ptr6 - %val7 = load float *%ptr7 - %val8 = load float *%ptr8 - %val9 = load float *%ptr9 - %val10 = load float *%ptr10 + %val0 = load float , float *%ptr0 + %val1 = load float , float *%ptr1 + %val2 = load float , float *%ptr2 + %val3 = load float , float *%ptr3 + %val4 = load float , float *%ptr4 + %val5 = load float , float *%ptr5 + %val6 = load float , float *%ptr6 + %val7 = load float , float *%ptr7 + %val8 = load float , float *%ptr8 + %val9 = load float , float *%ptr9 + %val10 = load float , float *%ptr10 %ret = call float @foo() diff --git a/test/CodeGen/SystemZ/fp-add-02.ll b/test/CodeGen/SystemZ/fp-add-02.ll index 067c7474fb43..5be1ad79d453 100644 --- a/test/CodeGen/SystemZ/fp-add-02.ll +++ b/test/CodeGen/SystemZ/fp-add-02.ll @@ -1,7 +1,8 @@ ; Test 64-bit floating-point addition. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s - +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s declare double @foo() ; Check register addition. @@ -18,7 +19,7 @@ define double @f2(double %f1, double *%ptr) { ; CHECK-LABEL: f2: ; CHECK: adb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %res = fadd double %f1, %f2 ret double %res } @@ -28,8 +29,8 @@ define double @f3(double %f1, double *%base) { ; CHECK-LABEL: f3: ; CHECK: adb %f0, 4088(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %res = fadd double %f1, %f2 ret double %res } @@ -41,8 +42,8 @@ define double @f4(double %f1, double *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: adb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %res = fadd double %f1, %f2 ret double %res } @@ -53,8 +54,8 @@ define double @f5(double %f1, double *%base) { ; CHECK: aghi %r2, -8 ; CHECK: adb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %res = fadd double %f1, %f2 ret double %res } @@ -65,9 +66,9 @@ define double @f6(double %f1, double *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 3 ; CHECK: adb %f0, 800(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %f2 = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %f2 = load double , double *%ptr2 %res = fadd double %f1, %f2 ret double %res } @@ -76,30 +77,30 @@ define double @f6(double %f1, double *%base, i64 %index) { define double @f7(double *%ptr0) { ; CHECK-LABEL: f7: ; CHECK: brasl %r14, foo@PLT -; CHECK: adb %f0, 160(%r15) +; CHECK-SCALAR: adb %f0, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr double *%ptr0, i64 2 - %ptr2 = getelementptr double *%ptr0, i64 4 - %ptr3 = getelementptr double *%ptr0, i64 6 - %ptr4 = getelementptr double *%ptr0, i64 8 - %ptr5 = getelementptr double *%ptr0, i64 10 - %ptr6 = getelementptr double *%ptr0, i64 12 - %ptr7 = getelementptr double *%ptr0, i64 14 - %ptr8 = getelementptr double *%ptr0, i64 16 - %ptr9 = getelementptr double *%ptr0, i64 18 - %ptr10 = getelementptr double *%ptr0, i64 20 + %ptr1 = getelementptr double, double *%ptr0, i64 2 + %ptr2 = getelementptr double, double *%ptr0, i64 4 + %ptr3 = getelementptr double, double *%ptr0, i64 6 + %ptr4 = getelementptr double, double *%ptr0, i64 8 + %ptr5 = getelementptr double, double *%ptr0, i64 10 + %ptr6 = getelementptr double, double *%ptr0, i64 12 + %ptr7 = getelementptr double, double *%ptr0, i64 14 + %ptr8 = getelementptr double, double *%ptr0, i64 16 + %ptr9 = getelementptr double, double *%ptr0, i64 18 + %ptr10 = getelementptr double, double *%ptr0, i64 20 - %val0 = load double *%ptr0 - %val1 = load double *%ptr1 - %val2 = load double *%ptr2 - %val3 = load double *%ptr3 - %val4 = load double *%ptr4 - %val5 = load double *%ptr5 - %val6 = load double *%ptr6 - %val7 = load double *%ptr7 - %val8 = load double *%ptr8 - %val9 = load double *%ptr9 - %val10 = load double *%ptr10 + %val0 = load double , double *%ptr0 + %val1 = load double , double *%ptr1 + %val2 = load double , double *%ptr2 + %val3 = load double , double *%ptr3 + %val4 = load double , double *%ptr4 + %val5 = load double , double *%ptr5 + %val6 = load double , double *%ptr6 + %val7 = load double , double *%ptr7 + %val8 = load double , double *%ptr8 + %val9 = load double , double *%ptr9 + %val10 = load double , double *%ptr10 %ret = call double @foo() diff --git a/test/CodeGen/SystemZ/fp-add-03.ll b/test/CodeGen/SystemZ/fp-add-03.ll index cb4042eee472..53342e194edf 100644 --- a/test/CodeGen/SystemZ/fp-add-03.ll +++ b/test/CodeGen/SystemZ/fp-add-03.ll @@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) { ; CHECK: std %f1, 0(%r2) ; CHECK: std %f3, 8(%r2) ; CHECK: br %r14 - %f1 = load fp128 *%ptr + %f1 = load fp128 , fp128 *%ptr %f2x = fpext float %f2 to fp128 %sum = fadd fp128 %f1, %f2x store fp128 %sum, fp128 *%ptr diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll index d7c0cce9c2a5..ed58103e59a5 100644 --- a/test/CodeGen/SystemZ/fp-cmp-01.ll +++ b/test/CodeGen/SystemZ/fp-cmp-01.ll @@ -24,7 +24,7 @@ define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) { ; CHECK-NEXT: je ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %cond = fcmp oeq float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -37,8 +37,8 @@ define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) { ; CHECK-NEXT: je ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %cond = fcmp oeq float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -53,8 +53,8 @@ define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) { ; CHECK-NEXT: je ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %cond = fcmp oeq float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -68,8 +68,8 @@ define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) { ; CHECK-NEXT: je ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %cond = fcmp oeq float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -83,9 +83,9 @@ define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) { ; CHECK-NEXT: je ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %f2 = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %f2 = load float , float *%ptr2 %cond = fcmp oeq float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -97,28 +97,28 @@ define float @f7(float *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: ceb {{%f[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr float *%ptr0, i64 2 - %ptr2 = getelementptr float *%ptr0, i64 4 - %ptr3 = getelementptr float *%ptr0, i64 6 - %ptr4 = getelementptr float *%ptr0, i64 8 - %ptr5 = getelementptr float *%ptr0, i64 10 - %ptr6 = getelementptr float *%ptr0, i64 12 - %ptr7 = getelementptr float *%ptr0, i64 14 - %ptr8 = getelementptr float *%ptr0, i64 16 - %ptr9 = getelementptr float *%ptr0, i64 18 - %ptr10 = getelementptr float *%ptr0, i64 20 + %ptr1 = getelementptr float, float *%ptr0, i64 2 + %ptr2 = getelementptr float, float *%ptr0, i64 4 + %ptr3 = getelementptr float, float *%ptr0, i64 6 + %ptr4 = getelementptr float, float *%ptr0, i64 8 + %ptr5 = getelementptr float, float *%ptr0, i64 10 + %ptr6 = getelementptr float, float *%ptr0, i64 12 + %ptr7 = getelementptr float, float *%ptr0, i64 14 + %ptr8 = getelementptr float, float *%ptr0, i64 16 + %ptr9 = getelementptr float, float *%ptr0, i64 18 + %ptr10 = getelementptr float, float *%ptr0, i64 20 - %val0 = load float *%ptr0 - %val1 = load float *%ptr1 - %val2 = load float *%ptr2 - %val3 = load float *%ptr3 - %val4 = load float *%ptr4 - %val5 = load float *%ptr5 - %val6 = load float *%ptr6 - %val7 = load float *%ptr7 - %val8 = load float *%ptr8 - %val9 = load float *%ptr9 - %val10 = load float *%ptr10 + %val0 = load float , float *%ptr0 + %val1 = load float , float *%ptr1 + %val2 = load float , float *%ptr2 + %val3 = load float , float *%ptr3 + %val4 = load float , float *%ptr4 + %val5 = load float , float *%ptr5 + %val6 = load float , float *%ptr6 + %val7 = load float , float *%ptr7 + %val8 = load float , float *%ptr8 + %val9 = load float , float *%ptr9 + %val10 = load float , float *%ptr10 %ret = call float @foo() @@ -169,7 +169,7 @@ define i64 @f9(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: je {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp oeq float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -182,7 +182,7 @@ define i64 @f10(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jlh {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp one float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -195,7 +195,7 @@ define i64 @f11(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp olt float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -208,7 +208,7 @@ define i64 @f12(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jhe {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp ole float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -221,7 +221,7 @@ define i64 @f13(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jle {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp oge float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -234,7 +234,7 @@ define i64 @f14(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jl {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp ogt float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -247,7 +247,7 @@ define i64 @f15(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jnlh {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp ueq float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -260,7 +260,7 @@ define i64 @f16(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jne {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp une float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -273,7 +273,7 @@ define i64 @f17(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jnle {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp ult float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -286,7 +286,7 @@ define i64 @f18(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jnl {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp ule float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -299,7 +299,7 @@ define i64 @f19(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jnh {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp uge float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -312,7 +312,7 @@ define i64 @f20(i64 %a, i64 %b, float %f2, float *%ptr) { ; CHECK-NEXT: jnhe {{\.L.*}} ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f1 = load float *%ptr + %f1 = load float , float *%ptr %cond = fcmp ugt float %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll index c61f04ed244e..94a256777c75 100644 --- a/test/CodeGen/SystemZ/fp-cmp-02.ll +++ b/test/CodeGen/SystemZ/fp-cmp-02.ll @@ -1,7 +1,10 @@ ; Test 64-bit floating-point comparison. The tests assume a z10 implementation ; of select, using conditional branches rather than LOCGR. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s declare double @foo() @@ -9,8 +12,9 @@ declare double @foo() define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) { ; CHECK-LABEL: f1: ; CHECK: cdbr %f0, %f2 -; CHECK-NEXT: je -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 %cond = fcmp oeq double %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b @@ -21,10 +25,11 @@ define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) { define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) { ; CHECK-LABEL: f2: ; CHECK: cdb %f0, 0(%r4) -; CHECK-NEXT: je -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %cond = fcmp oeq double %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -34,11 +39,12 @@ define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) { define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) { ; CHECK-LABEL: f3: ; CHECK: cdb %f0, 4088(%r4) -; CHECK-NEXT: je -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %cond = fcmp oeq double %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -50,11 +56,12 @@ define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) { ; CHECK-LABEL: f4: ; CHECK: aghi %r4, 4096 ; CHECK: cdb %f0, 0(%r4) -; CHECK-NEXT: je -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %cond = fcmp oeq double %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -65,11 +72,12 @@ define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) { ; CHECK-LABEL: f5: ; CHECK: aghi %r4, -8 ; CHECK: cdb %f0, 0(%r4) -; CHECK-NEXT: je -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %cond = fcmp oeq double %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -80,12 +88,13 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) { ; CHECK-LABEL: f6: ; CHECK: sllg %r1, %r5, 3 ; CHECK: cdb %f0, 800(%r1,%r4) -; CHECK-NEXT: je -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %f2 = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %f2 = load double , double *%ptr2 %cond = fcmp oeq double %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -95,30 +104,30 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) { define double @f7(double *%ptr0) { ; CHECK-LABEL: f7: ; CHECK: brasl %r14, foo@PLT -; CHECK: cdb {{%f[0-9]+}}, 160(%r15) +; CHECK-SCALAR: cdb {{%f[0-9]+}}, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr double *%ptr0, i64 2 - %ptr2 = getelementptr double *%ptr0, i64 4 - %ptr3 = getelementptr double *%ptr0, i64 6 - %ptr4 = getelementptr double *%ptr0, i64 8 - %ptr5 = getelementptr double *%ptr0, i64 10 - %ptr6 = getelementptr double *%ptr0, i64 12 - %ptr7 = getelementptr double *%ptr0, i64 14 - %ptr8 = getelementptr double *%ptr0, i64 16 - %ptr9 = getelementptr double *%ptr0, i64 18 - %ptr10 = getelementptr double *%ptr0, i64 20 + %ptr1 = getelementptr double, double *%ptr0, i64 2 + %ptr2 = getelementptr double, double *%ptr0, i64 4 + %ptr3 = getelementptr double, double *%ptr0, i64 6 + %ptr4 = getelementptr double, double *%ptr0, i64 8 + %ptr5 = getelementptr double, double *%ptr0, i64 10 + %ptr6 = getelementptr double, double *%ptr0, i64 12 + %ptr7 = getelementptr double, double *%ptr0, i64 14 + %ptr8 = getelementptr double, double *%ptr0, i64 16 + %ptr9 = getelementptr double, double *%ptr0, i64 18 + %ptr10 = getelementptr double, double *%ptr0, i64 20 - %val0 = load double *%ptr0 - %val1 = load double *%ptr1 - %val2 = load double *%ptr2 - %val3 = load double *%ptr3 - %val4 = load double *%ptr4 - %val5 = load double *%ptr5 - %val6 = load double *%ptr6 - %val7 = load double *%ptr7 - %val8 = load double *%ptr8 - %val9 = load double *%ptr9 - %val10 = load double *%ptr10 + %val0 = load double , double *%ptr0 + %val1 = load double , double *%ptr1 + %val2 = load double , double *%ptr2 + %val3 = load double , double *%ptr3 + %val4 = load double , double *%ptr4 + %val5 = load double , double *%ptr5 + %val6 = load double , double *%ptr6 + %val7 = load double , double *%ptr7 + %val8 = load double , double *%ptr8 + %val9 = load double , double *%ptr9 + %val10 = load double , double *%ptr10 %ret = call double @foo() @@ -152,9 +161,12 @@ define double @f7(double *%ptr0) { ; Check comparison with zero. define i64 @f8(i64 %a, i64 %b, double %f) { ; CHECK-LABEL: f8: -; CHECK: ltdbr %f0, %f0 -; CHECK-NEXT: je -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR: ltdbr %f0, %f0 +; CHECK-SCALAR-NEXT: je +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR: lzdr %f1 +; CHECK-VECTOR-NEXT: cdbr %f0, %f1 +; CHECK-VECTOR-NEXT: locgrne %r2, %r3 ; CHECK: br %r14 %cond = fcmp oeq double %f, 0.0 %res = select i1 %cond, i64 %a, i64 %b @@ -165,10 +177,11 @@ define i64 @f8(i64 %a, i64 %b, double %f) { define i64 @f9(i64 %a, i64 %b, double %f2, double *%ptr) { ; CHECK-LABEL: f9: ; CHECK: cdb %f0, 0(%r4) -; CHECK-NEXT: jl {{\.L.*}} -; CHECK: lgr %r2, %r3 +; CHECK-SCALAR-NEXT: jl +; CHECK-SCALAR: lgr %r2, %r3 +; CHECK-VECTOR-NEXT: locgrnl %r2, %r3 ; CHECK: br %r14 - %f1 = load double *%ptr + %f1 = load double , double *%ptr %cond = fcmp ogt double %f1, %f2 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll index e777d00c9687..862c5e9b65b8 100644 --- a/test/CodeGen/SystemZ/fp-cmp-03.ll +++ b/test/CodeGen/SystemZ/fp-cmp-03.ll @@ -14,7 +14,7 @@ define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) { ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 %f2x = fpext float %f2 to fp128 - %f1 = load fp128 *%ptr + %f1 = load fp128 , fp128 *%ptr %cond = fcmp oeq fp128 %f1, %f2x %res = select i1 %cond, i64 %a, i64 %b ret i64 %res @@ -29,7 +29,7 @@ define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) { ; CHECK-NEXT: je ; CHECK: lgr %r2, %r3 ; CHECK: br %r14 - %f = load fp128 *%ptr + %f = load fp128 , fp128 *%ptr %cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000 %res = select i1 %cond, i64 %a, i64 %b ret i64 %res diff --git a/test/CodeGen/SystemZ/fp-cmp-04.ll b/test/CodeGen/SystemZ/fp-cmp-04.ll index 1637ccb0791b..05c6dfe7e8e4 100644 --- a/test/CodeGen/SystemZ/fp-cmp-04.ll +++ b/test/CodeGen/SystemZ/fp-cmp-04.ll @@ -88,7 +88,7 @@ define float @f5(float %a, float %b, float *%dest) { ; CHECK-NEXT: jnhe .L{{.*}} ; CHECK: br %r14 entry: - %cur = load float *%dest + %cur = load float , float *%dest %res = fsub float %a, %cur %cmp = fcmp ult float %res, 0.0 br i1 %cmp, label %exit, label %store @@ -284,8 +284,8 @@ define void @f14(fp128 *%ptr1, fp128 *%ptr2) { ; CHECK-NEXT: jl .L{{.*}} ; CHECK: br %r14 entry: - %val1 = load fp128 *%ptr1 - %val2 = load fp128 *%ptr2 + %val1 = load fp128 , fp128 *%ptr1 + %val2 = load fp128 , fp128 *%ptr2 %div = fdiv fp128 %val1, %val2 store fp128 %div, fp128 *%ptr1 %mul = fmul fp128 %val1, %val2 diff --git a/test/CodeGen/SystemZ/fp-conv-01.ll b/test/CodeGen/SystemZ/fp-conv-01.ll index 49ed43bce51c..06740ed4b4a6 100644 --- a/test/CodeGen/SystemZ/fp-conv-01.ll +++ b/test/CodeGen/SystemZ/fp-conv-01.ll @@ -1,11 +1,15 @@ ; Test floating-point truncations. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s ; Test f64->f32. define float @f1(double %d1, double %d2) { ; CHECK-LABEL: f1: -; CHECK: ledbr %f0, %f2 +; CHECK-SCALAR: ledbr %f0, %f2 +; CHECK-VECTOR: ledbra %f0, 0, %f2, 0 ; CHECK: br %r14 %res = fptrunc double %d2 to float ret float %res @@ -16,7 +20,7 @@ define float @f2(fp128 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: lexbr %f0, %f0 ; CHECK: br %r14 - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %res = fptrunc fp128 %val to float ret float %res } @@ -29,7 +33,7 @@ define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) { ; CHECK: aebr %f1, %f2 ; CHECK: ste %f1, 0(%r2) ; CHECK: br %r14 - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %conv = fptrunc fp128 %val to float %res = fadd float %conv, %d2 store float %res, float *%dst @@ -41,7 +45,7 @@ define double @f4(fp128 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: ldxbr %f0, %f0 ; CHECK: br %r14 - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %res = fptrunc fp128 %val to double ret double %res } @@ -50,10 +54,12 @@ define double @f4(fp128 *%ptr) { define void @f5(double *%dst, fp128 *%ptr, double %d1, double %d2) { ; CHECK-LABEL: f5: ; CHECK: ldxbr %f1, %f1 -; CHECK: adbr %f1, %f2 -; CHECK: std %f1, 0(%r2) +; CHECK-SCALAR: adbr %f1, %f2 +; CHECK-SCALAR: std %f1, 0(%r2) +; CHECK-VECTOR: wfadb [[REG:%f[0-9]+]], %f1, %f2 +; CHECK-VECTOR: std [[REG]], 0(%r2) ; CHECK: br %r14 - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %conv = fptrunc fp128 %val to double %res = fadd double %conv, %d2 store double %res, double *%dst diff --git a/test/CodeGen/SystemZ/fp-conv-02.ll b/test/CodeGen/SystemZ/fp-conv-02.ll index 93fb7c8d4d92..be32bfe7ba9a 100644 --- a/test/CodeGen/SystemZ/fp-conv-02.ll +++ b/test/CodeGen/SystemZ/fp-conv-02.ll @@ -1,6 +1,8 @@ ; Test extensions of f32 to f64. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Check register extension. define double @f1(float %val) { @@ -16,7 +18,7 @@ define double @f2(float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: ldeb %f0, 0(%r2) ; CHECK: br %r14 - %val = load float *%ptr + %val = load float , float *%ptr %res = fpext float %val to double ret double %res } @@ -26,8 +28,8 @@ define double @f3(float *%base) { ; CHECK-LABEL: f3: ; CHECK: ldeb %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %val = load float , float *%ptr %res = fpext float %val to double ret double %res } @@ -39,8 +41,8 @@ define double @f4(float *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: ldeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %val = load float , float *%ptr %res = fpext float %val to double ret double %res } @@ -51,8 +53,8 @@ define double @f5(float *%base) { ; CHECK: aghi %r2, -4 ; CHECK: ldeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %val = load float , float *%ptr %res = fpext float %val to double ret double %res } @@ -63,9 +65,9 @@ define double @f6(float *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 2 ; CHECK: ldeb %f0, 400(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %val = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %val = load float , float *%ptr2 %res = fpext float %val to double ret double %res } @@ -74,25 +76,25 @@ define double @f6(float *%base, i64 %index) { ; to use LDEB if possible. define void @f7(double *%ptr1, float *%ptr2) { ; CHECK-LABEL: f7: -; CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15) +; CHECK-SCALAR: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile float *%ptr2 - %val1 = load volatile float *%ptr2 - %val2 = load volatile float *%ptr2 - %val3 = load volatile float *%ptr2 - %val4 = load volatile float *%ptr2 - %val5 = load volatile float *%ptr2 - %val6 = load volatile float *%ptr2 - %val7 = load volatile float *%ptr2 - %val8 = load volatile float *%ptr2 - %val9 = load volatile float *%ptr2 - %val10 = load volatile float *%ptr2 - %val11 = load volatile float *%ptr2 - %val12 = load volatile float *%ptr2 - %val13 = load volatile float *%ptr2 - %val14 = load volatile float *%ptr2 - %val15 = load volatile float *%ptr2 - %val16 = load volatile float *%ptr2 + %val0 = load volatile float , float *%ptr2 + %val1 = load volatile float , float *%ptr2 + %val2 = load volatile float , float *%ptr2 + %val3 = load volatile float , float *%ptr2 + %val4 = load volatile float , float *%ptr2 + %val5 = load volatile float , float *%ptr2 + %val6 = load volatile float , float *%ptr2 + %val7 = load volatile float , float *%ptr2 + %val8 = load volatile float , float *%ptr2 + %val9 = load volatile float , float *%ptr2 + %val10 = load volatile float , float *%ptr2 + %val11 = load volatile float , float *%ptr2 + %val12 = load volatile float , float *%ptr2 + %val13 = load volatile float , float *%ptr2 + %val14 = load volatile float , float *%ptr2 + %val15 = load volatile float , float *%ptr2 + %val16 = load volatile float , float *%ptr2 %ext0 = fpext float %val0 to double %ext1 = fpext float %val1 to double diff --git a/test/CodeGen/SystemZ/fp-conv-03.ll b/test/CodeGen/SystemZ/fp-conv-03.ll index d42ce6650aaf..bb14e610f720 100644 --- a/test/CodeGen/SystemZ/fp-conv-03.ll +++ b/test/CodeGen/SystemZ/fp-conv-03.ll @@ -21,7 +21,7 @@ define void @f2(fp128 *%dst, float *%ptr) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %val = load float *%ptr + %val = load float , float *%ptr %res = fpext float %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -34,8 +34,8 @@ define void @f3(fp128 *%dst, float *%base) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %val = load float , float *%ptr %res = fpext float %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -50,8 +50,8 @@ define void @f4(fp128 *%dst, float *%base) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %val = load float , float *%ptr %res = fpext float %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -65,8 +65,8 @@ define void @f5(fp128 *%dst, float *%base) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %val = load float , float *%ptr %res = fpext float %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -80,9 +80,9 @@ define void @f6(fp128 *%dst, float *%base, i64 %index) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %val = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %val = load float , float *%ptr2 %res = fpext float %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -94,23 +94,23 @@ define void @f7(fp128 *%ptr1, float *%ptr2) { ; CHECK-LABEL: f7: ; CHECK: lxeb {{%f[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile float *%ptr2 - %val1 = load volatile float *%ptr2 - %val2 = load volatile float *%ptr2 - %val3 = load volatile float *%ptr2 - %val4 = load volatile float *%ptr2 - %val5 = load volatile float *%ptr2 - %val6 = load volatile float *%ptr2 - %val7 = load volatile float *%ptr2 - %val8 = load volatile float *%ptr2 - %val9 = load volatile float *%ptr2 - %val10 = load volatile float *%ptr2 - %val11 = load volatile float *%ptr2 - %val12 = load volatile float *%ptr2 - %val13 = load volatile float *%ptr2 - %val14 = load volatile float *%ptr2 - %val15 = load volatile float *%ptr2 - %val16 = load volatile float *%ptr2 + %val0 = load volatile float , float *%ptr2 + %val1 = load volatile float , float *%ptr2 + %val2 = load volatile float , float *%ptr2 + %val3 = load volatile float , float *%ptr2 + %val4 = load volatile float , float *%ptr2 + %val5 = load volatile float , float *%ptr2 + %val6 = load volatile float , float *%ptr2 + %val7 = load volatile float , float *%ptr2 + %val8 = load volatile float , float *%ptr2 + %val9 = load volatile float , float *%ptr2 + %val10 = load volatile float , float *%ptr2 + %val11 = load volatile float , float *%ptr2 + %val12 = load volatile float , float *%ptr2 + %val13 = load volatile float , float *%ptr2 + %val14 = load volatile float , float *%ptr2 + %val15 = load volatile float , float *%ptr2 + %val16 = load volatile float , float *%ptr2 %ext0 = fpext float %val0 to fp128 %ext1 = fpext float %val1 to fp128 diff --git a/test/CodeGen/SystemZ/fp-conv-04.ll b/test/CodeGen/SystemZ/fp-conv-04.ll index 518d6c28d867..cfcb98aaa70a 100644 --- a/test/CodeGen/SystemZ/fp-conv-04.ll +++ b/test/CodeGen/SystemZ/fp-conv-04.ll @@ -21,7 +21,7 @@ define void @f2(fp128 *%dst, double *%ptr) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %val = load double *%ptr + %val = load double , double *%ptr %res = fpext double %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -34,8 +34,8 @@ define void @f3(fp128 *%dst, double *%base) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %val = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %val = load double , double *%ptr %res = fpext double %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -50,8 +50,8 @@ define void @f4(fp128 *%dst, double *%base) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %val = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %val = load double , double *%ptr %res = fpext double %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -65,8 +65,8 @@ define void @f5(fp128 *%dst, double *%base) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %val = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %val = load double , double *%ptr %res = fpext double %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -80,9 +80,9 @@ define void @f6(fp128 *%dst, double *%base, i64 %index) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %val = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %val = load double , double *%ptr2 %res = fpext double %val to fp128 store fp128 %res, fp128 *%dst ret void @@ -94,23 +94,23 @@ define void @f7(fp128 *%ptr1, double *%ptr2) { ; CHECK-LABEL: f7: ; CHECK: lxdb {{%f[0-9]+}}, 160(%r15) ; CHECK: br %r14 - %val0 = load volatile double *%ptr2 - %val1 = load volatile double *%ptr2 - %val2 = load volatile double *%ptr2 - %val3 = load volatile double *%ptr2 - %val4 = load volatile double *%ptr2 - %val5 = load volatile double *%ptr2 - %val6 = load volatile double *%ptr2 - %val7 = load volatile double *%ptr2 - %val8 = load volatile double *%ptr2 - %val9 = load volatile double *%ptr2 - %val10 = load volatile double *%ptr2 - %val11 = load volatile double *%ptr2 - %val12 = load volatile double *%ptr2 - %val13 = load volatile double *%ptr2 - %val14 = load volatile double *%ptr2 - %val15 = load volatile double *%ptr2 - %val16 = load volatile double *%ptr2 + %val0 = load volatile double , double *%ptr2 + %val1 = load volatile double , double *%ptr2 + %val2 = load volatile double , double *%ptr2 + %val3 = load volatile double , double *%ptr2 + %val4 = load volatile double , double *%ptr2 + %val5 = load volatile double , double *%ptr2 + %val6 = load volatile double , double *%ptr2 + %val7 = load volatile double , double *%ptr2 + %val8 = load volatile double , double *%ptr2 + %val9 = load volatile double , double *%ptr2 + %val10 = load volatile double , double *%ptr2 + %val11 = load volatile double , double *%ptr2 + %val12 = load volatile double , double *%ptr2 + %val13 = load volatile double , double *%ptr2 + %val14 = load volatile double , double *%ptr2 + %val15 = load volatile double , double *%ptr2 + %val16 = load volatile double , double *%ptr2 %ext0 = fpext double %val0 to fp128 %ext1 = fpext double %val1 to fp128 diff --git a/test/CodeGen/SystemZ/fp-conv-09.ll b/test/CodeGen/SystemZ/fp-conv-09.ll index 6aee73644a16..21b809d40e29 100644 --- a/test/CodeGen/SystemZ/fp-conv-09.ll +++ b/test/CodeGen/SystemZ/fp-conv-09.ll @@ -27,7 +27,7 @@ define i32 @f3(fp128 *%src) { ; CHECK: ld %f2, 8(%r2) ; CHECK: cfxbr %r2, 5, %f0 ; CHECK: br %r14 - %f = load fp128 *%src + %f = load fp128 , fp128 *%src %conv = fptosi fp128 %f to i32 ret i32 %conv } diff --git a/test/CodeGen/SystemZ/fp-conv-10.ll b/test/CodeGen/SystemZ/fp-conv-10.ll index b8155ed067da..cfbe0b939747 100644 --- a/test/CodeGen/SystemZ/fp-conv-10.ll +++ b/test/CodeGen/SystemZ/fp-conv-10.ll @@ -39,7 +39,7 @@ define i32 @f3(fp128 *%src) { ; CHECK: cfxbr ; CHECK: xilf ; CHECK: br %r14 - %f = load fp128 *%src + %f = load fp128 , fp128 *%src %conv = fptoui fp128 %f to i32 ret i32 %conv } diff --git a/test/CodeGen/SystemZ/fp-conv-11.ll b/test/CodeGen/SystemZ/fp-conv-11.ll index 46f4cb3a6d89..eb996cb3bb1b 100644 --- a/test/CodeGen/SystemZ/fp-conv-11.ll +++ b/test/CodeGen/SystemZ/fp-conv-11.ll @@ -27,7 +27,7 @@ define i64 @f3(fp128 *%src) { ; CHECK: ld %f2, 8(%r2) ; CHECK: cgxbr %r2, 5, %f0 ; CHECK: br %r14 - %f = load fp128 *%src + %f = load fp128 , fp128 *%src %conv = fptosi fp128 %f to i64 ret i64 %conv } diff --git a/test/CodeGen/SystemZ/fp-conv-12.ll b/test/CodeGen/SystemZ/fp-conv-12.ll index 770c9407a0af..28a521605a95 100644 --- a/test/CodeGen/SystemZ/fp-conv-12.ll +++ b/test/CodeGen/SystemZ/fp-conv-12.ll @@ -38,7 +38,7 @@ define i64 @f3(fp128 *%src) { ; CHECK: cgxbr ; CHECK: xihf ; CHECK: br %r14 - %f = load fp128 *%src + %f = load fp128 , fp128 *%src %conv = fptoui fp128 %f to i64 ret i64 %conv } diff --git a/test/CodeGen/SystemZ/fp-conv-14.ll b/test/CodeGen/SystemZ/fp-conv-14.ll index e926e9bb31f5..e4f0a27022e8 100644 --- a/test/CodeGen/SystemZ/fp-conv-14.ll +++ b/test/CodeGen/SystemZ/fp-conv-14.ll @@ -27,7 +27,7 @@ define i32 @f3(fp128 *%src) { ; CHECK-DAG: ld %f2, 8(%r2) ; CHECK: clfxbr %r2, 5, %f0, 0 ; CHECK: br %r14 - %f = load fp128 *%src + %f = load fp128 , fp128 *%src %conv = fptoui fp128 %f to i32 ret i32 %conv } @@ -57,7 +57,7 @@ define i64 @f6(fp128 *%src) { ; CHECK-DAG: ld %f2, 8(%r2) ; CHECK: clgxbr %r2, 5, %f0, 0 ; CHECK: br %r14 - %f = load fp128 *%src + %f = load fp128 , fp128 *%src %conv = fptoui fp128 %f to i64 ret i64 %conv } diff --git a/test/CodeGen/SystemZ/fp-copysign-01.ll b/test/CodeGen/SystemZ/fp-copysign-01.ll index 50177e5f41bf..57ad76fcbb2a 100644 --- a/test/CodeGen/SystemZ/fp-copysign-01.ll +++ b/test/CodeGen/SystemZ/fp-copysign-01.ll @@ -35,7 +35,7 @@ define float @f3(float %a, fp128 *%bptr) { ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2) ; CHECK: cpsdr %f0, %f0, [[BHIGH]] ; CHECK: br %r14 - %bl = load volatile fp128 *%bptr + %bl = load volatile fp128 , fp128 *%bptr %b = fptrunc fp128 %bl to float %res = call float @copysignf(float %a, float %b) readnone ret float %res @@ -69,7 +69,7 @@ define double @f6(double %a, fp128 *%bptr) { ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2) ; CHECK: cpsdr %f0, %f0, [[BHIGH]] ; CHECK: br %r14 - %bl = load volatile fp128 *%bptr + %bl = load volatile fp128 , fp128 *%bptr %b = fptrunc fp128 %bl to double %res = call double @copysign(double %a, double %b) readnone ret double %res @@ -86,7 +86,7 @@ define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) { ; CHECK: std [[AHIGH]], 0(%r2) ; CHECK: std [[ALOW]], 8(%r2) ; CHECK: br %r14 - %a = load volatile fp128 *%aptr + %a = load volatile fp128 , fp128 *%aptr %b = fpext float %bf to fp128 %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone store fp128 %c, fp128 *%cptr @@ -102,7 +102,7 @@ define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) { ; CHECK: std [[AHIGH]], 0(%r2) ; CHECK: std [[ALOW]], 8(%r2) ; CHECK: br %r14 - %a = load volatile fp128 *%aptr + %a = load volatile fp128 , fp128 *%aptr %b = fpext double %bd to fp128 %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone store fp128 %c, fp128 *%cptr @@ -120,8 +120,8 @@ define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) { ; CHECK: std [[AHIGH]], 0(%r2) ; CHECK: std [[ALOW]], 8(%r2) ; CHECK: br %r14 - %a = load volatile fp128 *%aptr - %b = load volatile fp128 *%bptr + %a = load volatile fp128 , fp128 *%aptr + %b = load volatile fp128 , fp128 *%bptr %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone store fp128 %c, fp128 *%cptr ret void diff --git a/test/CodeGen/SystemZ/fp-div-01.ll b/test/CodeGen/SystemZ/fp-div-01.ll index 1b99463327b4..0791e8db93f8 100644 --- a/test/CodeGen/SystemZ/fp-div-01.ll +++ b/test/CodeGen/SystemZ/fp-div-01.ll @@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: deb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %res = fdiv float %f1, %f2 ret float %res } @@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) { ; CHECK-LABEL: f3: ; CHECK: deb %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %res = fdiv float %f1, %f2 ret float %res } @@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: deb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %res = fdiv float %f1, %f2 ret float %res } @@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) { ; CHECK: aghi %r2, -4 ; CHECK: deb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %res = fdiv float %f1, %f2 ret float %res } @@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 2 ; CHECK: deb %f0, 400(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %f2 = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %f2 = load float , float *%ptr2 %res = fdiv float %f1, %f2 ret float %res } @@ -78,28 +78,28 @@ define float @f7(float *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: deb %f0, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr float *%ptr0, i64 2 - %ptr2 = getelementptr float *%ptr0, i64 4 - %ptr3 = getelementptr float *%ptr0, i64 6 - %ptr4 = getelementptr float *%ptr0, i64 8 - %ptr5 = getelementptr float *%ptr0, i64 10 - %ptr6 = getelementptr float *%ptr0, i64 12 - %ptr7 = getelementptr float *%ptr0, i64 14 - %ptr8 = getelementptr float *%ptr0, i64 16 - %ptr9 = getelementptr float *%ptr0, i64 18 - %ptr10 = getelementptr float *%ptr0, i64 20 + %ptr1 = getelementptr float, float *%ptr0, i64 2 + %ptr2 = getelementptr float, float *%ptr0, i64 4 + %ptr3 = getelementptr float, float *%ptr0, i64 6 + %ptr4 = getelementptr float, float *%ptr0, i64 8 + %ptr5 = getelementptr float, float *%ptr0, i64 10 + %ptr6 = getelementptr float, float *%ptr0, i64 12 + %ptr7 = getelementptr float, float *%ptr0, i64 14 + %ptr8 = getelementptr float, float *%ptr0, i64 16 + %ptr9 = getelementptr float, float *%ptr0, i64 18 + %ptr10 = getelementptr float, float *%ptr0, i64 20 - %val0 = load float *%ptr0 - %val1 = load float *%ptr1 - %val2 = load float *%ptr2 - %val3 = load float *%ptr3 - %val4 = load float *%ptr4 - %val5 = load float *%ptr5 - %val6 = load float *%ptr6 - %val7 = load float *%ptr7 - %val8 = load float *%ptr8 - %val9 = load float *%ptr9 - %val10 = load float *%ptr10 + %val0 = load float , float *%ptr0 + %val1 = load float , float *%ptr1 + %val2 = load float , float *%ptr2 + %val3 = load float , float *%ptr3 + %val4 = load float , float *%ptr4 + %val5 = load float , float *%ptr5 + %val6 = load float , float *%ptr6 + %val7 = load float , float *%ptr7 + %val8 = load float , float *%ptr8 + %val9 = load float , float *%ptr9 + %val10 = load float , float *%ptr10 %ret = call float @foo() diff --git a/test/CodeGen/SystemZ/fp-div-02.ll b/test/CodeGen/SystemZ/fp-div-02.ll index 513664bd9496..f120e7c923dc 100644 --- a/test/CodeGen/SystemZ/fp-div-02.ll +++ b/test/CodeGen/SystemZ/fp-div-02.ll @@ -1,6 +1,8 @@ ; Test 64-bit floating-point division. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s declare double @foo() @@ -18,7 +20,7 @@ define double @f2(double %f1, double *%ptr) { ; CHECK-LABEL: f2: ; CHECK: ddb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %res = fdiv double %f1, %f2 ret double %res } @@ -28,8 +30,8 @@ define double @f3(double %f1, double *%base) { ; CHECK-LABEL: f3: ; CHECK: ddb %f0, 4088(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %res = fdiv double %f1, %f2 ret double %res } @@ -41,8 +43,8 @@ define double @f4(double %f1, double *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: ddb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %res = fdiv double %f1, %f2 ret double %res } @@ -53,8 +55,8 @@ define double @f5(double %f1, double *%base) { ; CHECK: aghi %r2, -8 ; CHECK: ddb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %res = fdiv double %f1, %f2 ret double %res } @@ -65,9 +67,9 @@ define double @f6(double %f1, double *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 3 ; CHECK: ddb %f0, 800(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %f2 = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %f2 = load double , double *%ptr2 %res = fdiv double %f1, %f2 ret double %res } @@ -76,30 +78,30 @@ define double @f6(double %f1, double *%base, i64 %index) { define double @f7(double *%ptr0) { ; CHECK-LABEL: f7: ; CHECK: brasl %r14, foo@PLT -; CHECK: ddb %f0, 160(%r15) +; CHECK-SCALAR: ddb %f0, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr double *%ptr0, i64 2 - %ptr2 = getelementptr double *%ptr0, i64 4 - %ptr3 = getelementptr double *%ptr0, i64 6 - %ptr4 = getelementptr double *%ptr0, i64 8 - %ptr5 = getelementptr double *%ptr0, i64 10 - %ptr6 = getelementptr double *%ptr0, i64 12 - %ptr7 = getelementptr double *%ptr0, i64 14 - %ptr8 = getelementptr double *%ptr0, i64 16 - %ptr9 = getelementptr double *%ptr0, i64 18 - %ptr10 = getelementptr double *%ptr0, i64 20 + %ptr1 = getelementptr double, double *%ptr0, i64 2 + %ptr2 = getelementptr double, double *%ptr0, i64 4 + %ptr3 = getelementptr double, double *%ptr0, i64 6 + %ptr4 = getelementptr double, double *%ptr0, i64 8 + %ptr5 = getelementptr double, double *%ptr0, i64 10 + %ptr6 = getelementptr double, double *%ptr0, i64 12 + %ptr7 = getelementptr double, double *%ptr0, i64 14 + %ptr8 = getelementptr double, double *%ptr0, i64 16 + %ptr9 = getelementptr double, double *%ptr0, i64 18 + %ptr10 = getelementptr double, double *%ptr0, i64 20 - %val0 = load double *%ptr0 - %val1 = load double *%ptr1 - %val2 = load double *%ptr2 - %val3 = load double *%ptr3 - %val4 = load double *%ptr4 - %val5 = load double *%ptr5 - %val6 = load double *%ptr6 - %val7 = load double *%ptr7 - %val8 = load double *%ptr8 - %val9 = load double *%ptr9 - %val10 = load double *%ptr10 + %val0 = load double , double *%ptr0 + %val1 = load double , double *%ptr1 + %val2 = load double , double *%ptr2 + %val3 = load double , double *%ptr3 + %val4 = load double , double *%ptr4 + %val5 = load double , double *%ptr5 + %val6 = load double , double *%ptr6 + %val7 = load double , double *%ptr7 + %val8 = load double , double *%ptr8 + %val9 = load double , double *%ptr9 + %val10 = load double , double *%ptr10 %ret = call double @foo() diff --git a/test/CodeGen/SystemZ/fp-div-03.ll b/test/CodeGen/SystemZ/fp-div-03.ll index 079b349b4084..f052635a483e 100644 --- a/test/CodeGen/SystemZ/fp-div-03.ll +++ b/test/CodeGen/SystemZ/fp-div-03.ll @@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) { ; CHECK: std %f1, 0(%r2) ; CHECK: std %f3, 8(%r2) ; CHECK: br %r14 - %f1 = load fp128 *%ptr + %f1 = load fp128 , fp128 *%ptr %f2x = fpext float %f2 to fp128 %sum = fdiv fp128 %f1, %f2x store fp128 %sum, fp128 *%ptr diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll index d16502f2f7c8..843b1b6a6e64 100644 --- a/test/CodeGen/SystemZ/fp-move-01.ll +++ b/test/CodeGen/SystemZ/fp-move-01.ll @@ -1,11 +1,13 @@ ; Test moves between FPRs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test f32 moves. define float @f1(float %a, float %b) { ; CHECK-LABEL: f1: ; CHECK: ler %f0, %f2 +; CHECK: br %r14 ret float %b } @@ -13,6 +15,7 @@ define float @f1(float %a, float %b) { define double @f2(double %a, double %b) { ; CHECK-LABEL: f2: ; CHECK: ldr %f0, %f2 +; CHECK: br %r14 ret double %b } @@ -22,7 +25,8 @@ define void @f3(fp128 *%x) { ; CHECK-LABEL: f3: ; CHECK: lxr ; CHECK: axbr - %val = load volatile fp128 *%x +; CHECK: br %r14 + %val = load volatile fp128 , fp128 *%x %sum = fadd fp128 %val, %val store volatile fp128 %sum, fp128 *%x store volatile fp128 %val, fp128 *%x diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll index 505ee8d37a4e..2bd63f4674d9 100644 --- a/test/CodeGen/SystemZ/fp-move-02.ll +++ b/test/CodeGen/SystemZ/fp-move-02.ll @@ -71,7 +71,7 @@ define void @f6(fp128 *%a, i128 *%b) { ; CHECK: stg ; CHECK: stg ; CHECK: br %r14 - %val = load i128 *%b + %val = load i128 , i128 *%b %res = bitcast i128 %val to fp128 store fp128 %res, fp128 *%a ret void @@ -102,7 +102,7 @@ define void @f9(fp128 *%a, i128 *%b) { ; CHECK: ld ; CHECK: std ; CHECK: std - %val = load fp128 *%a + %val = load fp128 , fp128 *%a %res = bitcast fp128 %val to i128 store i128 %res, i128 *%b ret void @@ -119,34 +119,34 @@ define void @f10(double %extra) { ; CHECK: %exit ; CHECK: br %r14 entry: - %double0 = load volatile double *@dptr + %double0 = load volatile double , double *@dptr %biased0 = fadd double %double0, %extra %int0 = bitcast double %biased0 to i64 - %double1 = load volatile double *@dptr + %double1 = load volatile double , double *@dptr %biased1 = fadd double %double1, %extra %int1 = bitcast double %biased1 to i64 - %double2 = load volatile double *@dptr + %double2 = load volatile double , double *@dptr %biased2 = fadd double %double2, %extra %int2 = bitcast double %biased2 to i64 - %double3 = load volatile double *@dptr + %double3 = load volatile double , double *@dptr %biased3 = fadd double %double3, %extra %int3 = bitcast double %biased3 to i64 - %double4 = load volatile double *@dptr + %double4 = load volatile double , double *@dptr %biased4 = fadd double %double4, %extra %int4 = bitcast double %biased4 to i64 - %double5 = load volatile double *@dptr + %double5 = load volatile double , double *@dptr %biased5 = fadd double %double5, %extra %int5 = bitcast double %biased5 to i64 - %double6 = load volatile double *@dptr + %double6 = load volatile double , double *@dptr %biased6 = fadd double %double6, %extra %int6 = bitcast double %biased6 to i64 - %double7 = load volatile double *@dptr + %double7 = load volatile double , double *@dptr %biased7 = fadd double %double7, %extra %int7 = bitcast double %biased7 to i64 - %double8 = load volatile double *@dptr + %double8 = load volatile double , double *@dptr %biased8 = fadd double %double8, %extra %int8 = bitcast double %biased8 to i64 - %double9 = load volatile double *@dptr + %double9 = load volatile double , double *@dptr %biased9 = fadd double %double9, %extra %int9 = bitcast double %biased9 to i64 br label %loop @@ -181,34 +181,34 @@ define void @f11(i64 %mask) { ; CHECK: %exit ; CHECK: br %r14 entry: - %int0 = load volatile i64 *@iptr + %int0 = load volatile i64 , i64 *@iptr %masked0 = and i64 %int0, %mask %double0 = bitcast i64 %masked0 to double - %int1 = load volatile i64 *@iptr + %int1 = load volatile i64 , i64 *@iptr %masked1 = and i64 %int1, %mask %double1 = bitcast i64 %masked1 to double - %int2 = load volatile i64 *@iptr + %int2 = load volatile i64 , i64 *@iptr %masked2 = and i64 %int2, %mask %double2 = bitcast i64 %masked2 to double - %int3 = load volatile i64 *@iptr + %int3 = load volatile i64 , i64 *@iptr %masked3 = and i64 %int3, %mask %double3 = bitcast i64 %masked3 to double - %int4 = load volatile i64 *@iptr + %int4 = load volatile i64 , i64 *@iptr %masked4 = and i64 %int4, %mask %double4 = bitcast i64 %masked4 to double - %int5 = load volatile i64 *@iptr + %int5 = load volatile i64 , i64 *@iptr %masked5 = and i64 %int5, %mask %double5 = bitcast i64 %masked5 to double - %int6 = load volatile i64 *@iptr + %int6 = load volatile i64 , i64 *@iptr %masked6 = and i64 %int6, %mask %double6 = bitcast i64 %masked6 to double - %int7 = load volatile i64 *@iptr + %int7 = load volatile i64 , i64 *@iptr %masked7 = and i64 %int7, %mask %double7 = bitcast i64 %masked7 to double - %int8 = load volatile i64 *@iptr + %int8 = load volatile i64 , i64 *@iptr %masked8 = and i64 %int8, %mask %double8 = bitcast i64 %masked8 to double - %int9 = load volatile i64 *@iptr + %int9 = load volatile i64 , i64 *@iptr %masked9 = and i64 %int9, %mask %double9 = bitcast i64 %masked9 to double br label %loop @@ -275,7 +275,7 @@ loop: exit: %unused1 = call i64 @foo() - %factor = load volatile double *@dptr + %factor = load volatile double , double *@dptr %conv0 = bitcast i64 %add0 to double %mul0 = fmul double %conv0, %factor @@ -354,7 +354,7 @@ loop: exit: %unused1 = call i64 @foo() - %bias = load volatile i64 *@iptr + %bias = load volatile i64 , i64 *@iptr %conv0 = bitcast double %mul0 to i64 %add0 = add i64 %conv0, %bias diff --git a/test/CodeGen/SystemZ/fp-move-03.ll b/test/CodeGen/SystemZ/fp-move-03.ll index 1273358f65ad..f50e097bef69 100644 --- a/test/CodeGen/SystemZ/fp-move-03.ll +++ b/test/CodeGen/SystemZ/fp-move-03.ll @@ -7,7 +7,7 @@ define float @f1(float *%src) { ; CHECK-LABEL: f1: ; CHECK: le %f0, 0(%r2) ; CHECK: br %r14 - %val = load float *%src + %val = load float , float *%src ret float %val } @@ -16,8 +16,8 @@ define float @f2(float *%src) { ; CHECK-LABEL: f2: ; CHECK: le %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 1023 - %val = load float *%ptr + %ptr = getelementptr float, float *%src, i64 1023 + %val = load float , float *%ptr ret float %val } @@ -26,8 +26,8 @@ define float @f3(float *%src) { ; CHECK-LABEL: f3: ; CHECK: ley %f0, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 1024 - %val = load float *%ptr + %ptr = getelementptr float, float *%src, i64 1024 + %val = load float , float *%ptr ret float %val } @@ -36,8 +36,8 @@ define float @f4(float *%src) { ; CHECK-LABEL: f4: ; CHECK: ley %f0, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 131071 - %val = load float *%ptr + %ptr = getelementptr float, float *%src, i64 131071 + %val = load float , float *%ptr ret float %val } @@ -48,8 +48,8 @@ define float @f5(float *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: le %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 131072 - %val = load float *%ptr + %ptr = getelementptr float, float *%src, i64 131072 + %val = load float , float *%ptr ret float %val } @@ -58,8 +58,8 @@ define float @f6(float *%src) { ; CHECK-LABEL: f6: ; CHECK: ley %f0, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 -1 - %val = load float *%ptr + %ptr = getelementptr float, float *%src, i64 -1 + %val = load float , float *%ptr ret float %val } @@ -68,8 +68,8 @@ define float @f7(float *%src) { ; CHECK-LABEL: f7: ; CHECK: ley %f0, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 -131072 - %val = load float *%ptr + %ptr = getelementptr float, float *%src, i64 -131072 + %val = load float , float *%ptr ret float %val } @@ -80,8 +80,8 @@ define float @f8(float *%src) { ; CHECK: agfi %r2, -524292 ; CHECK: le %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 -131073 - %val = load float *%ptr + %ptr = getelementptr float, float *%src, i64 -131073 + %val = load float , float *%ptr ret float %val } @@ -93,7 +93,7 @@ define float @f9(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to float * - %val = load float *%ptr + %val = load float , float *%ptr ret float %val } @@ -105,6 +105,6 @@ define float @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to float * - %val = load float *%ptr + %val = load float , float *%ptr ret float %val } diff --git a/test/CodeGen/SystemZ/fp-move-04.ll b/test/CodeGen/SystemZ/fp-move-04.ll index 1b0278fdee0f..6650419b2c38 100644 --- a/test/CodeGen/SystemZ/fp-move-04.ll +++ b/test/CodeGen/SystemZ/fp-move-04.ll @@ -1,13 +1,14 @@ ; Test 64-bit floating-point loads. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test the low end of the LD range. define double @f1(double *%src) { ; CHECK-LABEL: f1: ; CHECK: ld %f0, 0(%r2) ; CHECK: br %r14 - %val = load double *%src + %val = load double , double *%src ret double %val } @@ -16,8 +17,8 @@ define double @f2(double *%src) { ; CHECK-LABEL: f2: ; CHECK: ld %f0, 4088(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 511 - %val = load double *%ptr + %ptr = getelementptr double, double *%src, i64 511 + %val = load double , double *%ptr ret double %val } @@ -26,8 +27,8 @@ define double @f3(double *%src) { ; CHECK-LABEL: f3: ; CHECK: ldy %f0, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 512 - %val = load double *%ptr + %ptr = getelementptr double, double *%src, i64 512 + %val = load double , double *%ptr ret double %val } @@ -36,8 +37,8 @@ define double @f4(double *%src) { ; CHECK-LABEL: f4: ; CHECK: ldy %f0, 524280(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 65535 - %val = load double *%ptr + %ptr = getelementptr double, double *%src, i64 65535 + %val = load double , double *%ptr ret double %val } @@ -48,8 +49,8 @@ define double @f5(double *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: ld %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 65536 - %val = load double *%ptr + %ptr = getelementptr double, double *%src, i64 65536 + %val = load double , double *%ptr ret double %val } @@ -58,8 +59,8 @@ define double @f6(double *%src) { ; CHECK-LABEL: f6: ; CHECK: ldy %f0, -8(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 -1 - %val = load double *%ptr + %ptr = getelementptr double, double *%src, i64 -1 + %val = load double , double *%ptr ret double %val } @@ -68,8 +69,8 @@ define double @f7(double *%src) { ; CHECK-LABEL: f7: ; CHECK: ldy %f0, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 -65536 - %val = load double *%ptr + %ptr = getelementptr double, double *%src, i64 -65536 + %val = load double , double *%ptr ret double %val } @@ -80,8 +81,8 @@ define double @f8(double *%src) { ; CHECK: agfi %r2, -524296 ; CHECK: ld %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 -65537 - %val = load double *%ptr + %ptr = getelementptr double, double *%src, i64 -65537 + %val = load double , double *%ptr ret double %val } @@ -93,7 +94,7 @@ define double @f9(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4095 %ptr = inttoptr i64 %add2 to double * - %val = load double *%ptr + %val = load double , double *%ptr ret double %val } @@ -105,6 +106,6 @@ define double @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to double * - %val = load double *%ptr + %val = load double , double *%ptr ret double %val } diff --git a/test/CodeGen/SystemZ/fp-move-05.ll b/test/CodeGen/SystemZ/fp-move-05.ll index d302a0f9c633..da12af6d68c1 100644 --- a/test/CodeGen/SystemZ/fp-move-05.ll +++ b/test/CodeGen/SystemZ/fp-move-05.ll @@ -9,7 +9,7 @@ define double @f1(i64 %src) { ; CHECK: ld %f2, 8(%r2) ; CHECK: br %r14 %ptr = inttoptr i64 %src to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -22,7 +22,7 @@ define double @f2(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, 4080 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -35,7 +35,7 @@ define double @f3(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, 4088 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -48,7 +48,7 @@ define double @f4(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, 4096 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -61,7 +61,7 @@ define double @f5(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, 524272 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -76,7 +76,7 @@ define double @f6(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, 524280 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -90,7 +90,7 @@ define double @f7(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, -8 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -103,7 +103,7 @@ define double @f8(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, -16 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -116,7 +116,7 @@ define double @f9(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, -524288 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -131,7 +131,7 @@ define double @f10(i64 %src) { ; CHECK: br %r14 %add = add i64 %src, -524296 %ptr = inttoptr i64 %add to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } @@ -145,7 +145,7 @@ define double @f11(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4088 %ptr = inttoptr i64 %add2 to fp128 * - %val = load fp128 *%ptr + %val = load fp128 , fp128 *%ptr %trunc = fptrunc fp128 %val to double ret double %trunc } diff --git a/test/CodeGen/SystemZ/fp-move-06.ll b/test/CodeGen/SystemZ/fp-move-06.ll index da67691729e3..eb0f87f1c572 100644 --- a/test/CodeGen/SystemZ/fp-move-06.ll +++ b/test/CodeGen/SystemZ/fp-move-06.ll @@ -16,7 +16,7 @@ define void @f2(float *%src, float %val) { ; CHECK-LABEL: f2: ; CHECK: ste %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 1023 + %ptr = getelementptr float, float *%src, i64 1023 store float %val, float *%ptr ret void } @@ -26,7 +26,7 @@ define void @f3(float *%src, float %val) { ; CHECK-LABEL: f3: ; CHECK: stey %f0, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 1024 + %ptr = getelementptr float, float *%src, i64 1024 store float %val, float *%ptr ret void } @@ -36,7 +36,7 @@ define void @f4(float *%src, float %val) { ; CHECK-LABEL: f4: ; CHECK: stey %f0, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 131071 + %ptr = getelementptr float, float *%src, i64 131071 store float %val, float *%ptr ret void } @@ -48,7 +48,7 @@ define void @f5(float *%src, float %val) { ; CHECK: agfi %r2, 524288 ; CHECK: ste %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 131072 + %ptr = getelementptr float, float *%src, i64 131072 store float %val, float *%ptr ret void } @@ -58,7 +58,7 @@ define void @f6(float *%src, float %val) { ; CHECK-LABEL: f6: ; CHECK: stey %f0, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 -1 + %ptr = getelementptr float, float *%src, i64 -1 store float %val, float *%ptr ret void } @@ -68,7 +68,7 @@ define void @f7(float *%src, float %val) { ; CHECK-LABEL: f7: ; CHECK: stey %f0, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 -131072 + %ptr = getelementptr float, float *%src, i64 -131072 store float %val, float *%ptr ret void } @@ -80,7 +80,7 @@ define void @f8(float *%src, float %val) { ; CHECK: agfi %r2, -524292 ; CHECK: ste %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%src, i64 -131073 + %ptr = getelementptr float, float *%src, i64 -131073 store float %val, float *%ptr ret void } diff --git a/test/CodeGen/SystemZ/fp-move-07.ll b/test/CodeGen/SystemZ/fp-move-07.ll index a4f1820d1204..5361002a97e0 100644 --- a/test/CodeGen/SystemZ/fp-move-07.ll +++ b/test/CodeGen/SystemZ/fp-move-07.ll @@ -1,6 +1,7 @@ ; Test 64-bit floating-point stores. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test the low end of the STD range. define void @f1(double *%src, double %val) { @@ -16,7 +17,7 @@ define void @f2(double *%src, double %val) { ; CHECK-LABEL: f2: ; CHECK: std %f0, 4088(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 511 + %ptr = getelementptr double, double *%src, i64 511 store double %val, double *%ptr ret void } @@ -26,7 +27,7 @@ define void @f3(double *%src, double %val) { ; CHECK-LABEL: f3: ; CHECK: stdy %f0, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 512 + %ptr = getelementptr double, double *%src, i64 512 store double %val, double *%ptr ret void } @@ -36,7 +37,7 @@ define void @f4(double *%src, double %val) { ; CHECK-LABEL: f4: ; CHECK: stdy %f0, 524280(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 65535 + %ptr = getelementptr double, double *%src, i64 65535 store double %val, double *%ptr ret void } @@ -48,7 +49,7 @@ define void @f5(double *%src, double %val) { ; CHECK: agfi %r2, 524288 ; CHECK: std %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 65536 + %ptr = getelementptr double, double *%src, i64 65536 store double %val, double *%ptr ret void } @@ -58,7 +59,7 @@ define void @f6(double *%src, double %val) { ; CHECK-LABEL: f6: ; CHECK: stdy %f0, -8(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 -1 + %ptr = getelementptr double, double *%src, i64 -1 store double %val, double *%ptr ret void } @@ -68,7 +69,7 @@ define void @f7(double *%src, double %val) { ; CHECK-LABEL: f7: ; CHECK: stdy %f0, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 -65536 + %ptr = getelementptr double, double *%src, i64 -65536 store double %val, double *%ptr ret void } @@ -80,7 +81,7 @@ define void @f8(double *%src, double %val) { ; CHECK: agfi %r2, -524296 ; CHECK: std %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%src, i64 -65537 + %ptr = getelementptr double, double *%src, i64 -65537 store double %val, double *%ptr ret void } diff --git a/test/CodeGen/SystemZ/fp-move-09.ll b/test/CodeGen/SystemZ/fp-move-09.ll index 52b2ee2e31ab..5e8dce272c23 100644 --- a/test/CodeGen/SystemZ/fp-move-09.ll +++ b/test/CodeGen/SystemZ/fp-move-09.ll @@ -1,4 +1,4 @@ -; Test moves between FPRs and GPRs for z196 and above. +; Test moves between FPRs and GPRs for z196 and zEC12. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s @@ -9,7 +9,7 @@ define float @f1(i16 *%ptr) { ; CHECK: oihh [[REG]], 16256 ; CHECK: ldgr %f0, [[REG]] ; CHECK: br %r14 - %base = load i16 *%ptr + %base = load i16 , i16 *%ptr %ext = zext i16 %base to i32 %full = or i32 %ext, 1065353216 %res = bitcast i32 %full to float @@ -38,7 +38,7 @@ define void @f3(float %val, i8 *%ptr, i32 %which) { ; CHECK: br %r14 %int = bitcast float %val to i32 %trunc = trunc i32 %int to i8 - %old = load i8 *%ptr + %old = load i8 , i8 *%ptr %cmp = icmp eq i32 %which, 0 %res = select i1 %cmp, i8 %trunc, i8 %old store i8 %res, i8 *%ptr @@ -54,7 +54,7 @@ define void @f4(float %val, i16 *%ptr, i32 %which) { ; CHECK: br %r14 %int = bitcast float %val to i32 %trunc = trunc i32 %int to i16 - %old = load i16 *%ptr + %old = load i16 , i16 *%ptr %cmp = icmp eq i32 %which, 0 %res = select i1 %cmp, i16 %trunc, i16 %old store i16 %res, i16 *%ptr diff --git a/test/CodeGen/SystemZ/fp-move-10.ll b/test/CodeGen/SystemZ/fp-move-10.ll new file mode 100644 index 000000000000..602397d58a8d --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-10.ll @@ -0,0 +1,61 @@ +; Test moves between FPRs and GPRs for z13 and above. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Check that moves from i32s to floats use a low GR32 and vector operation. +define float @f1(i16 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: llh [[REG:%r[0-5]]], 0(%r2) +; CHECK: oilh [[REG]], 16256 +; CHECK: vlvgf %v0, [[REG]], 0 +; CHECK: br %r14 + %base = load i16, i16 *%ptr + %ext = zext i16 %base to i32 + %full = or i32 %ext, 1065353216 + %res = bitcast i32 %full to float + ret float %res +} + +; Check that moves from floats to i32s use a low GR32 and vector operation. +define void @f2(float %val, i8 *%ptr) { +; CHECK-LABEL: f2: +; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0 +; CHECK: stc [[REG]], 0(%r2) +; CHECK: br %r14 + %res = bitcast float %val to i32 + %trunc = trunc i32 %res to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Like f2, but with a conditional store. +define void @f3(float %val, i8 *%ptr, i32 %which) { +; CHECK-LABEL: f3: +; CHECK-DAG: cijlh %r3, 0, +; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0 +; CHECK: stc [[REG]], 0(%r2) +; CHECK: br %r14 + %int = bitcast float %val to i32 + %trunc = trunc i32 %int to i8 + %old = load i8, i8 *%ptr + %cmp = icmp eq i32 %which, 0 + %res = select i1 %cmp, i8 %trunc, i8 %old + store i8 %res, i8 *%ptr + ret void +} + +; ...and again with 16-bit memory. +define void @f4(float %val, i16 *%ptr, i32 %which) { +; CHECK-LABEL: f4: +; CHECK-DAG: cijlh %r3, 0, +; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0 +; CHECK: sth [[REG]], 0(%r2) +; CHECK: br %r14 + %int = bitcast float %val to i32 + %trunc = trunc i32 %int to i16 + %old = load i16, i16 *%ptr + %cmp = icmp eq i32 %which, 0 + %res = select i1 %cmp, i16 %trunc, i16 %old + store i16 %res, i16 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-move-11.ll b/test/CodeGen/SystemZ/fp-move-11.ll new file mode 100644 index 000000000000..ce45019425cb --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-11.ll @@ -0,0 +1,110 @@ +; Test 32-bit floating-point loads for z13. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test that we use LDE instead of LE - low end of the LE range. +define float @f1(float *%src) { +; CHECK-LABEL: f1: +; CHECK: lde %f0, 0(%r2) +; CHECK: br %r14 + %val = load float, float *%src + ret float %val +} + +; Test that we use LDE instead of LE - high end of the LE range. +define float @f2(float *%src) { +; CHECK-LABEL: f2: +; CHECK: lde %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%src, i64 1023 + %val = load float, float *%ptr + ret float %val +} + +; Check the next word up, which should use LEY instead of LDE. +define float @f3(float *%src) { +; CHECK-LABEL: f3: +; CHECK: ley %f0, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%src, i64 1024 + %val = load float, float *%ptr + ret float %val +} + +; Check the high end of the aligned LEY range. +define float @f4(float *%src) { +; CHECK-LABEL: f4: +; CHECK: ley %f0, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%src, i64 131071 + %val = load float, float *%ptr + ret float %val +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f5(float *%src) { +; CHECK-LABEL: f5: +; CHECK: agfi %r2, 524288 +; CHECK: lde %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%src, i64 131072 + %val = load float, float *%ptr + ret float %val +} + +; Check the high end of the negative aligned LEY range. +define float @f6(float *%src) { +; CHECK-LABEL: f6: +; CHECK: ley %f0, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%src, i64 -1 + %val = load float, float *%ptr + ret float %val +} + +; Check the low end of the LEY range. +define float @f7(float *%src) { +; CHECK-LABEL: f7: +; CHECK: ley %f0, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%src, i64 -131072 + %val = load float, float *%ptr + ret float %val +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f8(float *%src) { +; CHECK-LABEL: f8: +; CHECK: agfi %r2, -524292 +; CHECK: lde %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%src, i64 -131073 + %val = load float, float *%ptr + ret float %val +} + +; Check that LDE allows an index. +define float @f9(i64 %src, i64 %index) { +; CHECK-LABEL: f9: +; CHECK: lde %f0, 4092({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to float * + %val = load float, float *%ptr + ret float %val +} + +; Check that LEY allows an index. +define float @f10(i64 %src, i64 %index) { +; CHECK-LABEL: f10: +; CHECK: ley %f0, 4096({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to float * + %val = load float, float *%ptr + ret float %val +} diff --git a/test/CodeGen/SystemZ/fp-mul-01.ll b/test/CodeGen/SystemZ/fp-mul-01.ll index 7562d6bf071b..3b72d25e0b5c 100644 --- a/test/CodeGen/SystemZ/fp-mul-01.ll +++ b/test/CodeGen/SystemZ/fp-mul-01.ll @@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: meeb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %res = fmul float %f1, %f2 ret float %res } @@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) { ; CHECK-LABEL: f3: ; CHECK: meeb %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %res = fmul float %f1, %f2 ret float %res } @@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: meeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %res = fmul float %f1, %f2 ret float %res } @@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) { ; CHECK: aghi %r2, -4 ; CHECK: meeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %res = fmul float %f1, %f2 ret float %res } @@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 2 ; CHECK: meeb %f0, 400(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %f2 = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %f2 = load float , float *%ptr2 %res = fmul float %f1, %f2 ret float %res } @@ -78,28 +78,28 @@ define float @f7(float *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: meeb %f0, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr float *%ptr0, i64 2 - %ptr2 = getelementptr float *%ptr0, i64 4 - %ptr3 = getelementptr float *%ptr0, i64 6 - %ptr4 = getelementptr float *%ptr0, i64 8 - %ptr5 = getelementptr float *%ptr0, i64 10 - %ptr6 = getelementptr float *%ptr0, i64 12 - %ptr7 = getelementptr float *%ptr0, i64 14 - %ptr8 = getelementptr float *%ptr0, i64 16 - %ptr9 = getelementptr float *%ptr0, i64 18 - %ptr10 = getelementptr float *%ptr0, i64 20 + %ptr1 = getelementptr float, float *%ptr0, i64 2 + %ptr2 = getelementptr float, float *%ptr0, i64 4 + %ptr3 = getelementptr float, float *%ptr0, i64 6 + %ptr4 = getelementptr float, float *%ptr0, i64 8 + %ptr5 = getelementptr float, float *%ptr0, i64 10 + %ptr6 = getelementptr float, float *%ptr0, i64 12 + %ptr7 = getelementptr float, float *%ptr0, i64 14 + %ptr8 = getelementptr float, float *%ptr0, i64 16 + %ptr9 = getelementptr float, float *%ptr0, i64 18 + %ptr10 = getelementptr float, float *%ptr0, i64 20 - %val0 = load float *%ptr0 - %val1 = load float *%ptr1 - %val2 = load float *%ptr2 - %val3 = load float *%ptr3 - %val4 = load float *%ptr4 - %val5 = load float *%ptr5 - %val6 = load float *%ptr6 - %val7 = load float *%ptr7 - %val8 = load float *%ptr8 - %val9 = load float *%ptr9 - %val10 = load float *%ptr10 + %val0 = load float , float *%ptr0 + %val1 = load float , float *%ptr1 + %val2 = load float , float *%ptr2 + %val3 = load float , float *%ptr3 + %val4 = load float , float *%ptr4 + %val5 = load float , float *%ptr5 + %val6 = load float , float *%ptr6 + %val7 = load float , float *%ptr7 + %val8 = load float , float *%ptr8 + %val9 = load float , float *%ptr9 + %val10 = load float , float *%ptr10 %ret = call float @foo() diff --git a/test/CodeGen/SystemZ/fp-mul-02.ll b/test/CodeGen/SystemZ/fp-mul-02.ll index cf4448fd7dd1..8435c3f5d3a1 100644 --- a/test/CodeGen/SystemZ/fp-mul-02.ll +++ b/test/CodeGen/SystemZ/fp-mul-02.ll @@ -20,7 +20,7 @@ define double @f2(float %f1, float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: mdeb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %f1x = fpext float %f1 to double %f2x = fpext float %f2 to double %res = fmul double %f1x, %f2x @@ -32,8 +32,8 @@ define double @f3(float %f1, float *%base) { ; CHECK-LABEL: f3: ; CHECK: mdeb %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %f1x = fpext float %f1 to double %f2x = fpext float %f2 to double %res = fmul double %f1x, %f2x @@ -47,8 +47,8 @@ define double @f4(float %f1, float *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: mdeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %f1x = fpext float %f1 to double %f2x = fpext float %f2 to double %res = fmul double %f1x, %f2x @@ -61,8 +61,8 @@ define double @f5(float %f1, float *%base) { ; CHECK: aghi %r2, -4 ; CHECK: mdeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %f1x = fpext float %f1 to double %f2x = fpext float %f2 to double %res = fmul double %f1x, %f2x @@ -75,9 +75,9 @@ define double @f6(float %f1, float *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 2 ; CHECK: mdeb %f0, 400(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %f2 = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %f2 = load float , float *%ptr2 %f1x = fpext float %f1 to double %f2x = fpext float %f2 to double %res = fmul double %f1x, %f2x @@ -90,28 +90,28 @@ define float @f7(float *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: mdeb %f0, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr float *%ptr0, i64 2 - %ptr2 = getelementptr float *%ptr0, i64 4 - %ptr3 = getelementptr float *%ptr0, i64 6 - %ptr4 = getelementptr float *%ptr0, i64 8 - %ptr5 = getelementptr float *%ptr0, i64 10 - %ptr6 = getelementptr float *%ptr0, i64 12 - %ptr7 = getelementptr float *%ptr0, i64 14 - %ptr8 = getelementptr float *%ptr0, i64 16 - %ptr9 = getelementptr float *%ptr0, i64 18 - %ptr10 = getelementptr float *%ptr0, i64 20 - - %val0 = load float *%ptr0 - %val1 = load float *%ptr1 - %val2 = load float *%ptr2 - %val3 = load float *%ptr3 - %val4 = load float *%ptr4 - %val5 = load float *%ptr5 - %val6 = load float *%ptr6 - %val7 = load float *%ptr7 - %val8 = load float *%ptr8 - %val9 = load float *%ptr9 - %val10 = load float *%ptr10 + %ptr1 = getelementptr float, float *%ptr0, i64 2 + %ptr2 = getelementptr float, float *%ptr0, i64 4 + %ptr3 = getelementptr float, float *%ptr0, i64 6 + %ptr4 = getelementptr float, float *%ptr0, i64 8 + %ptr5 = getelementptr float, float *%ptr0, i64 10 + %ptr6 = getelementptr float, float *%ptr0, i64 12 + %ptr7 = getelementptr float, float *%ptr0, i64 14 + %ptr8 = getelementptr float, float *%ptr0, i64 16 + %ptr9 = getelementptr float, float *%ptr0, i64 18 + %ptr10 = getelementptr float, float *%ptr0, i64 20 + + %val0 = load float , float *%ptr0 + %val1 = load float , float *%ptr1 + %val2 = load float , float *%ptr2 + %val3 = load float , float *%ptr3 + %val4 = load float , float *%ptr4 + %val5 = load float , float *%ptr5 + %val6 = load float , float *%ptr6 + %val7 = load float , float *%ptr7 + %val8 = load float , float *%ptr8 + %val9 = load float , float *%ptr9 + %val10 = load float , float *%ptr10 %frob0 = fadd float %val0, %val0 %frob1 = fadd float %val1, %val1 diff --git a/test/CodeGen/SystemZ/fp-mul-03.ll b/test/CodeGen/SystemZ/fp-mul-03.ll index 6d296f07d1f2..0d52121f41c6 100644 --- a/test/CodeGen/SystemZ/fp-mul-03.ll +++ b/test/CodeGen/SystemZ/fp-mul-03.ll @@ -1,6 +1,8 @@ ; Test multiplication of two f64s, producing an f64 result. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s declare double @foo() @@ -18,7 +20,7 @@ define double @f2(double %f1, double *%ptr) { ; CHECK-LABEL: f2: ; CHECK: mdb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %res = fmul double %f1, %f2 ret double %res } @@ -28,8 +30,8 @@ define double @f3(double %f1, double *%base) { ; CHECK-LABEL: f3: ; CHECK: mdb %f0, 4088(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %res = fmul double %f1, %f2 ret double %res } @@ -41,8 +43,8 @@ define double @f4(double %f1, double *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: mdb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %res = fmul double %f1, %f2 ret double %res } @@ -53,8 +55,8 @@ define double @f5(double %f1, double *%base) { ; CHECK: aghi %r2, -8 ; CHECK: mdb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %res = fmul double %f1, %f2 ret double %res } @@ -65,9 +67,9 @@ define double @f6(double %f1, double *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 3 ; CHECK: mdb %f0, 800(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %f2 = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %f2 = load double , double *%ptr2 %res = fmul double %f1, %f2 ret double %res } @@ -76,30 +78,30 @@ define double @f6(double %f1, double *%base, i64 %index) { define double @f7(double *%ptr0) { ; CHECK-LABEL: f7: ; CHECK: brasl %r14, foo@PLT -; CHECK: mdb %f0, 160(%r15) +; CHECK-SCALAR: mdb %f0, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr double *%ptr0, i64 2 - %ptr2 = getelementptr double *%ptr0, i64 4 - %ptr3 = getelementptr double *%ptr0, i64 6 - %ptr4 = getelementptr double *%ptr0, i64 8 - %ptr5 = getelementptr double *%ptr0, i64 10 - %ptr6 = getelementptr double *%ptr0, i64 12 - %ptr7 = getelementptr double *%ptr0, i64 14 - %ptr8 = getelementptr double *%ptr0, i64 16 - %ptr9 = getelementptr double *%ptr0, i64 18 - %ptr10 = getelementptr double *%ptr0, i64 20 + %ptr1 = getelementptr double, double *%ptr0, i64 2 + %ptr2 = getelementptr double, double *%ptr0, i64 4 + %ptr3 = getelementptr double, double *%ptr0, i64 6 + %ptr4 = getelementptr double, double *%ptr0, i64 8 + %ptr5 = getelementptr double, double *%ptr0, i64 10 + %ptr6 = getelementptr double, double *%ptr0, i64 12 + %ptr7 = getelementptr double, double *%ptr0, i64 14 + %ptr8 = getelementptr double, double *%ptr0, i64 16 + %ptr9 = getelementptr double, double *%ptr0, i64 18 + %ptr10 = getelementptr double, double *%ptr0, i64 20 - %val0 = load double *%ptr0 - %val1 = load double *%ptr1 - %val2 = load double *%ptr2 - %val3 = load double *%ptr3 - %val4 = load double *%ptr4 - %val5 = load double *%ptr5 - %val6 = load double *%ptr6 - %val7 = load double *%ptr7 - %val8 = load double *%ptr8 - %val9 = load double *%ptr9 - %val10 = load double *%ptr10 + %val0 = load double , double *%ptr0 + %val1 = load double , double *%ptr1 + %val2 = load double , double *%ptr2 + %val3 = load double , double *%ptr3 + %val4 = load double , double *%ptr4 + %val5 = load double , double *%ptr5 + %val6 = load double , double *%ptr6 + %val7 = load double , double *%ptr7 + %val8 = load double , double *%ptr8 + %val9 = load double , double *%ptr9 + %val10 = load double , double *%ptr10 %ret = call double @foo() diff --git a/test/CodeGen/SystemZ/fp-mul-04.ll b/test/CodeGen/SystemZ/fp-mul-04.ll index 3c4325e6cbbb..4226a3f61dff 100644 --- a/test/CodeGen/SystemZ/fp-mul-04.ll +++ b/test/CodeGen/SystemZ/fp-mul-04.ll @@ -27,7 +27,7 @@ define void @f2(double %f1, double *%ptr, fp128 *%dst) { ; CHECK: std %f0, 0(%r3) ; CHECK: std %f2, 8(%r3) ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %f1x = fpext double %f1 to fp128 %f2x = fpext double %f2 to fp128 %res = fmul fp128 %f1x, %f2x @@ -42,8 +42,8 @@ define void @f3(double %f1, double *%base, fp128 *%dst) { ; CHECK: std %f0, 0(%r3) ; CHECK: std %f2, 8(%r3) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %f1x = fpext double %f1 to fp128 %f2x = fpext double %f2 to fp128 %res = fmul fp128 %f1x, %f2x @@ -60,8 +60,8 @@ define void @f4(double %f1, double *%base, fp128 *%dst) { ; CHECK: std %f0, 0(%r3) ; CHECK: std %f2, 8(%r3) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %f1x = fpext double %f1 to fp128 %f2x = fpext double %f2 to fp128 %res = fmul fp128 %f1x, %f2x @@ -77,8 +77,8 @@ define void @f5(double %f1, double *%base, fp128 *%dst) { ; CHECK: std %f0, 0(%r3) ; CHECK: std %f2, 8(%r3) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %f1x = fpext double %f1 to fp128 %f2x = fpext double %f2 to fp128 %res = fmul fp128 %f1x, %f2x @@ -94,9 +94,9 @@ define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) { ; CHECK: std %f0, 0(%r4) ; CHECK: std %f2, 8(%r4) ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %f2 = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %f2 = load double , double *%ptr2 %f1x = fpext double %f1 to fp128 %f2x = fpext double %f2 to fp128 %res = fmul fp128 %f1x, %f2x @@ -110,28 +110,28 @@ define double @f7(double *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: mxdb %f0, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr double *%ptr0, i64 2 - %ptr2 = getelementptr double *%ptr0, i64 4 - %ptr3 = getelementptr double *%ptr0, i64 6 - %ptr4 = getelementptr double *%ptr0, i64 8 - %ptr5 = getelementptr double *%ptr0, i64 10 - %ptr6 = getelementptr double *%ptr0, i64 12 - %ptr7 = getelementptr double *%ptr0, i64 14 - %ptr8 = getelementptr double *%ptr0, i64 16 - %ptr9 = getelementptr double *%ptr0, i64 18 - %ptr10 = getelementptr double *%ptr0, i64 20 - - %val0 = load double *%ptr0 - %val1 = load double *%ptr1 - %val2 = load double *%ptr2 - %val3 = load double *%ptr3 - %val4 = load double *%ptr4 - %val5 = load double *%ptr5 - %val6 = load double *%ptr6 - %val7 = load double *%ptr7 - %val8 = load double *%ptr8 - %val9 = load double *%ptr9 - %val10 = load double *%ptr10 + %ptr1 = getelementptr double, double *%ptr0, i64 2 + %ptr2 = getelementptr double, double *%ptr0, i64 4 + %ptr3 = getelementptr double, double *%ptr0, i64 6 + %ptr4 = getelementptr double, double *%ptr0, i64 8 + %ptr5 = getelementptr double, double *%ptr0, i64 10 + %ptr6 = getelementptr double, double *%ptr0, i64 12 + %ptr7 = getelementptr double, double *%ptr0, i64 14 + %ptr8 = getelementptr double, double *%ptr0, i64 16 + %ptr9 = getelementptr double, double *%ptr0, i64 18 + %ptr10 = getelementptr double, double *%ptr0, i64 20 + + %val0 = load double , double *%ptr0 + %val1 = load double , double *%ptr1 + %val2 = load double , double *%ptr2 + %val3 = load double , double *%ptr3 + %val4 = load double , double *%ptr4 + %val5 = load double , double *%ptr5 + %val6 = load double , double *%ptr6 + %val7 = load double , double *%ptr7 + %val8 = load double , double *%ptr8 + %val9 = load double , double *%ptr9 + %val10 = load double , double *%ptr10 %frob0 = fadd double %val0, %val0 %frob1 = fadd double %val1, %val1 diff --git a/test/CodeGen/SystemZ/fp-mul-05.ll b/test/CodeGen/SystemZ/fp-mul-05.ll index 0be1fe8b41a0..48d0dcdcaff4 100644 --- a/test/CodeGen/SystemZ/fp-mul-05.ll +++ b/test/CodeGen/SystemZ/fp-mul-05.ll @@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) { ; CHECK: std %f1, 0(%r2) ; CHECK: std %f3, 8(%r2) ; CHECK: br %r14 - %f1 = load fp128 *%ptr + %f1 = load fp128 , fp128 *%ptr %f2x = fpext float %f2 to fp128 %diff = fmul fp128 %f1, %f2x store fp128 %diff, fp128 *%ptr diff --git a/test/CodeGen/SystemZ/fp-mul-06.ll b/test/CodeGen/SystemZ/fp-mul-06.ll index 3f631a68b575..896fafecbdaf 100644 --- a/test/CodeGen/SystemZ/fp-mul-06.ll +++ b/test/CodeGen/SystemZ/fp-mul-06.ll @@ -16,7 +16,7 @@ define float @f2(float %f1, float *%ptr, float %acc) { ; CHECK: maeb %f2, %f0, 0(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) ret float %res } @@ -26,8 +26,8 @@ define float @f3(float %f1, float *%base, float %acc) { ; CHECK: maeb %f2, %f0, 4092(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) ret float %res } @@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base, float %acc) { ; CHECK: maeb %f2, %f0, 0(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) ret float %res } @@ -56,8 +56,8 @@ define float @f5(float %f1, float *%base, float %acc) { ; CHECK: maeb %f2, %f0, 0(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) ret float %res } @@ -68,8 +68,8 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) { ; CHECK: maeb %f2, %f0, 0(%r1,%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 %index - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 %index + %f2 = load float , float *%ptr %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) ret float %res } @@ -81,8 +81,8 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) { ; CHECK: ler %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 1023 - %ptr = getelementptr float *%base, i64 %index2 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 %index2 + %f2 = load float , float *%ptr %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) ret float %res } @@ -95,8 +95,8 @@ define float @f8(float %f1, float *%base, i64 %index, float %acc) { ; CHECK: ler %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 1024 - %ptr = getelementptr float *%base, i64 %index2 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 %index2 + %f2 = load float , float *%ptr %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) ret float %res } diff --git a/test/CodeGen/SystemZ/fp-mul-07.ll b/test/CodeGen/SystemZ/fp-mul-07.ll index e4f590447215..e0b4a5c5d780 100644 --- a/test/CodeGen/SystemZ/fp-mul-07.ll +++ b/test/CodeGen/SystemZ/fp-mul-07.ll @@ -1,11 +1,15 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s declare double @llvm.fma.f64(double %f1, double %f2, double %f3) define double @f1(double %f1, double %f2, double %acc) { ; CHECK-LABEL: f1: -; CHECK: madbr %f4, %f0, %f2 -; CHECK: ldr %f0, %f4 +; CHECK-SCALAR: madbr %f4, %f0, %f2 +; CHECK-SCALAR: ldr %f0, %f4 +; CHECK-VECTOR: wfmadb %f0, %f0, %f2, %f4 ; CHECK: br %r14 %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res @@ -16,7 +20,7 @@ define double @f2(double %f1, double *%ptr, double %acc) { ; CHECK: madb %f2, %f0, 0(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res } @@ -26,8 +30,8 @@ define double @f3(double %f1, double *%base, double %acc) { ; CHECK: madb %f2, %f0, 4088(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res } @@ -41,8 +45,8 @@ define double @f4(double %f1, double *%base, double %acc) { ; CHECK: madb %f2, %f0, 0(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res } @@ -56,8 +60,8 @@ define double @f5(double %f1, double *%base, double %acc) { ; CHECK: madb %f2, %f0, 0(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res } @@ -68,8 +72,8 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) { ; CHECK: madb %f2, %f0, 0(%r1,%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 %index - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 %index + %f2 = load double , double *%ptr %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res } @@ -81,8 +85,8 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 511 - %ptr = getelementptr double *%base, i64 %index2 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 %index2 + %f2 = load double , double *%ptr %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res } @@ -95,8 +99,8 @@ define double @f8(double %f1, double *%base, i64 %index, double %acc) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 512 - %ptr = getelementptr double *%base, i64 %index2 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 %index2 + %f2 = load double , double *%ptr %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) ret double %res } diff --git a/test/CodeGen/SystemZ/fp-mul-08.ll b/test/CodeGen/SystemZ/fp-mul-08.ll index ab5fcb2cbefd..5e5538bfacc9 100644 --- a/test/CodeGen/SystemZ/fp-mul-08.ll +++ b/test/CodeGen/SystemZ/fp-mul-08.ll @@ -17,7 +17,7 @@ define float @f2(float %f1, float *%ptr, float %acc) { ; CHECK: mseb %f2, %f0, 0(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %negacc = fsub float -0.0, %acc %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) ret float %res @@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base, float %acc) { ; CHECK: mseb %f2, %f0, 4092(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %negacc = fsub float -0.0, %acc %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) ret float %res @@ -44,8 +44,8 @@ define float @f4(float %f1, float *%base, float %acc) { ; CHECK: mseb %f2, %f0, 0(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %negacc = fsub float -0.0, %acc %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) ret float %res @@ -60,8 +60,8 @@ define float @f5(float %f1, float *%base, float %acc) { ; CHECK: mseb %f2, %f0, 0(%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %negacc = fsub float -0.0, %acc %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) ret float %res @@ -73,8 +73,8 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) { ; CHECK: mseb %f2, %f0, 0(%r1,%r2) ; CHECK: ler %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 %index - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 %index + %f2 = load float , float *%ptr %negacc = fsub float -0.0, %acc %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) ret float %res @@ -87,8 +87,8 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) { ; CHECK: ler %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 1023 - %ptr = getelementptr float *%base, i64 %index2 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 %index2 + %f2 = load float , float *%ptr %negacc = fsub float -0.0, %acc %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) ret float %res @@ -102,8 +102,8 @@ define float @f8(float %f1, float *%base, i64 %index, float %acc) { ; CHECK: ler %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 1024 - %ptr = getelementptr float *%base, i64 %index2 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 %index2 + %f2 = load float , float *%ptr %negacc = fsub float -0.0, %acc %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) ret float %res diff --git a/test/CodeGen/SystemZ/fp-mul-09.ll b/test/CodeGen/SystemZ/fp-mul-09.ll index 7e740968a8c7..927a8064823c 100644 --- a/test/CodeGen/SystemZ/fp-mul-09.ll +++ b/test/CodeGen/SystemZ/fp-mul-09.ll @@ -1,11 +1,15 @@ -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s declare double @llvm.fma.f64(double %f1, double %f2, double %f3) define double @f1(double %f1, double %f2, double %acc) { ; CHECK-LABEL: f1: -; CHECK: msdbr %f4, %f0, %f2 -; CHECK: ldr %f0, %f4 +; CHECK-SCALAR: msdbr %f4, %f0, %f2 +; CHECK-SCALAR: ldr %f0, %f4 +; CHECK-VECTOR: wfmsdb %f0, %f0, %f2, %f4 ; CHECK: br %r14 %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) @@ -17,7 +21,7 @@ define double @f2(double %f1, double *%ptr, double %acc) { ; CHECK: msdb %f2, %f0, 0(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) ret double %res @@ -28,8 +32,8 @@ define double @f3(double %f1, double *%base, double %acc) { ; CHECK: msdb %f2, %f0, 4088(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) ret double %res @@ -44,8 +48,8 @@ define double @f4(double %f1, double *%base, double %acc) { ; CHECK: msdb %f2, %f0, 0(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) ret double %res @@ -60,8 +64,8 @@ define double @f5(double %f1, double *%base, double %acc) { ; CHECK: msdb %f2, %f0, 0(%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) ret double %res @@ -73,8 +77,8 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) { ; CHECK: msdb %f2, %f0, 0(%r1,%r2) ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 %index - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 %index + %f2 = load double , double *%ptr %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) ret double %res @@ -87,8 +91,8 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 511 - %ptr = getelementptr double *%base, i64 %index2 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 %index2 + %f2 = load double , double *%ptr %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) ret double %res @@ -102,8 +106,8 @@ define double @f8(double %f1, double *%base, i64 %index, double %acc) { ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %index2 = add i64 %index, 512 - %ptr = getelementptr double *%base, i64 %index2 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 %index2 + %f2 = load double , double *%ptr %negacc = fsub double -0.0, %acc %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) ret double %res diff --git a/test/CodeGen/SystemZ/fp-neg-01.ll b/test/CodeGen/SystemZ/fp-neg-01.ll index 1cc6d816fee3..fe2e5f67cf5b 100644 --- a/test/CodeGen/SystemZ/fp-neg-01.ll +++ b/test/CodeGen/SystemZ/fp-neg-01.ll @@ -1,6 +1,7 @@ ; Test floating-point negation. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test f32. define float @f1(float %f) { @@ -28,10 +29,10 @@ define void @f3(fp128 *%ptr, fp128 *%ptr2) { ; CHECK: lcxbr ; CHECK: dxbr ; CHECK: br %r14 - %orig = load fp128 *%ptr + %orig = load fp128 , fp128 *%ptr %negzero = fpext float -0.0 to fp128 %neg = fsub fp128 0xL00000000000000008000000000000000, %orig - %op2 = load fp128 *%ptr2 + %op2 = load fp128 , fp128 *%ptr2 %res = fdiv fp128 %neg, %op2 store fp128 %res, fp128 *%ptr ret void diff --git a/test/CodeGen/SystemZ/fp-round-01.ll b/test/CodeGen/SystemZ/fp-round-01.ll index 565db5ad4f51..bdec02f19c83 100644 --- a/test/CodeGen/SystemZ/fp-round-01.ll +++ b/test/CodeGen/SystemZ/fp-round-01.ll @@ -28,7 +28,7 @@ define void @f3(fp128 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: fixbr %f0, 0, %f0 ; CHECK: br %r14 - %src = load fp128 *%ptr + %src = load fp128 , fp128 *%ptr %res = call fp128 @llvm.rint.f128(fp128 %src) store fp128 %res, fp128 *%ptr ret void diff --git a/test/CodeGen/SystemZ/fp-round-02.ll b/test/CodeGen/SystemZ/fp-round-02.ll index d79c9c47050a..428261478dc8 100644 --- a/test/CodeGen/SystemZ/fp-round-02.ll +++ b/test/CodeGen/SystemZ/fp-round-02.ll @@ -1,6 +1,9 @@ ; Test rounding functions for z196 and above. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s ; Test rint for f32. declare float @llvm.rint.f32(float %f) @@ -16,7 +19,8 @@ define float @f1(float %f) { declare double @llvm.rint.f64(double %f) define double @f2(double %f) { ; CHECK-LABEL: f2: -; CHECK: fidbr %f0, 0, %f0 +; CHECK-SCALAR: fidbr %f0, 0, %f0 +; CHECK-VECTOR: fidbra %f0, 0, %f0, 0 ; CHECK: br %r14 %res = call double @llvm.rint.f64(double %f) ret double %res @@ -28,7 +32,7 @@ define void @f3(fp128 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: fixbr %f0, 0, %f0 ; CHECK: br %r14 - %src = load fp128 *%ptr + %src = load fp128 , fp128 *%ptr %res = call fp128 @llvm.rint.f128(fp128 %src) store fp128 %res, fp128 *%ptr ret void @@ -60,7 +64,7 @@ define void @f6(fp128 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: fixbra %f0, 0, %f0, 4 ; CHECK: br %r14 - %src = load fp128 *%ptr + %src = load fp128 , fp128 *%ptr %res = call fp128 @llvm.nearbyint.f128(fp128 %src) store fp128 %res, fp128 *%ptr ret void @@ -92,7 +96,7 @@ define void @f9(fp128 *%ptr) { ; CHECK-LABEL: f9: ; CHECK: fixbra %f0, 7, %f0, 4 ; CHECK: br %r14 - %src = load fp128 *%ptr + %src = load fp128 , fp128 *%ptr %res = call fp128 @llvm.floor.f128(fp128 %src) store fp128 %res, fp128 *%ptr ret void @@ -124,7 +128,7 @@ define void @f12(fp128 *%ptr) { ; CHECK-LABEL: f12: ; CHECK: fixbra %f0, 6, %f0, 4 ; CHECK: br %r14 - %src = load fp128 *%ptr + %src = load fp128 , fp128 *%ptr %res = call fp128 @llvm.ceil.f128(fp128 %src) store fp128 %res, fp128 *%ptr ret void @@ -156,7 +160,7 @@ define void @f15(fp128 *%ptr) { ; CHECK-LABEL: f15: ; CHECK: fixbra %f0, 5, %f0, 4 ; CHECK: br %r14 - %src = load fp128 *%ptr + %src = load fp128 , fp128 *%ptr %res = call fp128 @llvm.trunc.f128(fp128 %src) store fp128 %res, fp128 *%ptr ret void @@ -188,7 +192,7 @@ define void @f18(fp128 *%ptr) { ; CHECK-LABEL: f18: ; CHECK: fixbra %f0, 1, %f0, 4 ; CHECK: br %r14 - %src = load fp128 *%ptr + %src = load fp128 , fp128 *%ptr %res = call fp128 @llvm.round.f128(fp128 %src) store fp128 %res, fp128 *%ptr ret void diff --git a/test/CodeGen/SystemZ/fp-sqrt-01.ll b/test/CodeGen/SystemZ/fp-sqrt-01.ll index 7465af456b83..e8bf65bdc981 100644 --- a/test/CodeGen/SystemZ/fp-sqrt-01.ll +++ b/test/CodeGen/SystemZ/fp-sqrt-01.ll @@ -19,7 +19,7 @@ define float @f2(float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: sqeb %f0, 0(%r2) ; CHECK: br %r14 - %val = load float *%ptr + %val = load float , float *%ptr %res = call float @llvm.sqrt.f32(float %val) ret float %res } @@ -29,8 +29,8 @@ define float @f3(float *%base) { ; CHECK-LABEL: f3: ; CHECK: sqeb %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %val = load float , float *%ptr %res = call float @llvm.sqrt.f32(float %val) ret float %res } @@ -42,8 +42,8 @@ define float @f4(float *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: sqeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %val = load float , float *%ptr %res = call float @llvm.sqrt.f32(float %val) ret float %res } @@ -54,8 +54,8 @@ define float @f5(float *%base) { ; CHECK: aghi %r2, -4 ; CHECK: sqeb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %val = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %val = load float , float *%ptr %res = call float @llvm.sqrt.f32(float %val) ret float %res } @@ -66,9 +66,9 @@ define float @f6(float *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 2 ; CHECK: sqeb %f0, 400(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %val = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %val = load float , float *%ptr2 %res = call float @llvm.sqrt.f32(float %val) ret float %res } @@ -79,23 +79,23 @@ define void @f7(float *%ptr) { ; CHECK-LABEL: f7: ; CHECK: sqeb {{%f[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile float *%ptr - %val1 = load volatile float *%ptr - %val2 = load volatile float *%ptr - %val3 = load volatile float *%ptr - %val4 = load volatile float *%ptr - %val5 = load volatile float *%ptr - %val6 = load volatile float *%ptr - %val7 = load volatile float *%ptr - %val8 = load volatile float *%ptr - %val9 = load volatile float *%ptr - %val10 = load volatile float *%ptr - %val11 = load volatile float *%ptr - %val12 = load volatile float *%ptr - %val13 = load volatile float *%ptr - %val14 = load volatile float *%ptr - %val15 = load volatile float *%ptr - %val16 = load volatile float *%ptr + %val0 = load volatile float , float *%ptr + %val1 = load volatile float , float *%ptr + %val2 = load volatile float , float *%ptr + %val3 = load volatile float , float *%ptr + %val4 = load volatile float , float *%ptr + %val5 = load volatile float , float *%ptr + %val6 = load volatile float , float *%ptr + %val7 = load volatile float , float *%ptr + %val8 = load volatile float , float *%ptr + %val9 = load volatile float , float *%ptr + %val10 = load volatile float , float *%ptr + %val11 = load volatile float , float *%ptr + %val12 = load volatile float , float *%ptr + %val13 = load volatile float , float *%ptr + %val14 = load volatile float , float *%ptr + %val15 = load volatile float , float *%ptr + %val16 = load volatile float , float *%ptr %sqrt0 = call float @llvm.sqrt.f32(float %val0) %sqrt1 = call float @llvm.sqrt.f32(float %val1) diff --git a/test/CodeGen/SystemZ/fp-sqrt-02.ll b/test/CodeGen/SystemZ/fp-sqrt-02.ll index 66ffd19d6c31..a162466064e8 100644 --- a/test/CodeGen/SystemZ/fp-sqrt-02.ll +++ b/test/CodeGen/SystemZ/fp-sqrt-02.ll @@ -1,6 +1,8 @@ ; Test 64-bit square root. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s declare double @llvm.sqrt.f64(double %f) declare double @sqrt(double) @@ -19,7 +21,7 @@ define double @f2(double *%ptr) { ; CHECK-LABEL: f2: ; CHECK: sqdb %f0, 0(%r2) ; CHECK: br %r14 - %val = load double *%ptr + %val = load double , double *%ptr %res = call double @llvm.sqrt.f64(double %val) ret double %res } @@ -29,8 +31,8 @@ define double @f3(double *%base) { ; CHECK-LABEL: f3: ; CHECK: sqdb %f0, 4088(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %val = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %val = load double , double *%ptr %res = call double @llvm.sqrt.f64(double %val) ret double %res } @@ -42,8 +44,8 @@ define double @f4(double *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: sqdb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %val = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %val = load double , double *%ptr %res = call double @llvm.sqrt.f64(double %val) ret double %res } @@ -54,8 +56,8 @@ define double @f5(double *%base) { ; CHECK: aghi %r2, -8 ; CHECK: sqdb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %val = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %val = load double , double *%ptr %res = call double @llvm.sqrt.f64(double %val) ret double %res } @@ -66,9 +68,9 @@ define double @f6(double *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 3 ; CHECK: sqdb %f0, 800(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %val = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %val = load double , double *%ptr2 %res = call double @llvm.sqrt.f64(double %val) ret double %res } @@ -77,25 +79,25 @@ define double @f6(double *%base, i64 %index) { ; to use SQDB if possible. define void @f7(double *%ptr) { ; CHECK-LABEL: f7: -; CHECK: sqdb {{%f[0-9]+}}, 160(%r15) +; CHECK-SCALAR: sqdb {{%f[0-9]+}}, 160(%r15) ; CHECK: br %r14 - %val0 = load volatile double *%ptr - %val1 = load volatile double *%ptr - %val2 = load volatile double *%ptr - %val3 = load volatile double *%ptr - %val4 = load volatile double *%ptr - %val5 = load volatile double *%ptr - %val6 = load volatile double *%ptr - %val7 = load volatile double *%ptr - %val8 = load volatile double *%ptr - %val9 = load volatile double *%ptr - %val10 = load volatile double *%ptr - %val11 = load volatile double *%ptr - %val12 = load volatile double *%ptr - %val13 = load volatile double *%ptr - %val14 = load volatile double *%ptr - %val15 = load volatile double *%ptr - %val16 = load volatile double *%ptr + %val0 = load volatile double , double *%ptr + %val1 = load volatile double , double *%ptr + %val2 = load volatile double , double *%ptr + %val3 = load volatile double , double *%ptr + %val4 = load volatile double , double *%ptr + %val5 = load volatile double , double *%ptr + %val6 = load volatile double , double *%ptr + %val7 = load volatile double , double *%ptr + %val8 = load volatile double , double *%ptr + %val9 = load volatile double , double *%ptr + %val10 = load volatile double , double *%ptr + %val11 = load volatile double , double *%ptr + %val12 = load volatile double , double *%ptr + %val13 = load volatile double , double *%ptr + %val14 = load volatile double , double *%ptr + %val15 = load volatile double , double *%ptr + %val16 = load volatile double , double *%ptr %sqrt0 = call double @llvm.sqrt.f64(double %val0) %sqrt1 = call double @llvm.sqrt.f64(double %val1) diff --git a/test/CodeGen/SystemZ/fp-sqrt-03.ll b/test/CodeGen/SystemZ/fp-sqrt-03.ll index 71426440aca3..4bc05f100a0a 100644 --- a/test/CodeGen/SystemZ/fp-sqrt-03.ll +++ b/test/CodeGen/SystemZ/fp-sqrt-03.ll @@ -13,7 +13,7 @@ define void @f1(fp128 *%ptr) { ; CHECK: std %f0, 0(%r2) ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 - %orig = load fp128 *%ptr + %orig = load fp128 , fp128 *%ptr %sqrt = call fp128 @llvm.sqrt.f128(fp128 %orig) store fp128 %sqrt, fp128 *%ptr ret void diff --git a/test/CodeGen/SystemZ/fp-sub-01.ll b/test/CodeGen/SystemZ/fp-sub-01.ll index 76f46f626705..f4185ca3108d 100644 --- a/test/CodeGen/SystemZ/fp-sub-01.ll +++ b/test/CodeGen/SystemZ/fp-sub-01.ll @@ -18,7 +18,7 @@ define float @f2(float %f1, float *%ptr) { ; CHECK-LABEL: f2: ; CHECK: seb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load float *%ptr + %f2 = load float , float *%ptr %res = fsub float %f1, %f2 ret float %res } @@ -28,8 +28,8 @@ define float @f3(float %f1, float *%base) { ; CHECK-LABEL: f3: ; CHECK: seb %f0, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1023 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1023 + %f2 = load float , float *%ptr %res = fsub float %f1, %f2 ret float %res } @@ -41,8 +41,8 @@ define float @f4(float %f1, float *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: seb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 1024 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 1024 + %f2 = load float , float *%ptr %res = fsub float %f1, %f2 ret float %res } @@ -53,8 +53,8 @@ define float @f5(float %f1, float *%base) { ; CHECK: aghi %r2, -4 ; CHECK: seb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr float *%base, i64 -1 - %f2 = load float *%ptr + %ptr = getelementptr float, float *%base, i64 -1 + %f2 = load float , float *%ptr %res = fsub float %f1, %f2 ret float %res } @@ -65,9 +65,9 @@ define float @f6(float %f1, float *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 2 ; CHECK: seb %f0, 400(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr float *%base, i64 %index - %ptr2 = getelementptr float *%ptr1, i64 100 - %f2 = load float *%ptr2 + %ptr1 = getelementptr float, float *%base, i64 %index + %ptr2 = getelementptr float, float *%ptr1, i64 100 + %f2 = load float , float *%ptr2 %res = fsub float %f1, %f2 ret float %res } @@ -78,28 +78,28 @@ define float @f7(float *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: seb %f0, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr float *%ptr0, i64 2 - %ptr2 = getelementptr float *%ptr0, i64 4 - %ptr3 = getelementptr float *%ptr0, i64 6 - %ptr4 = getelementptr float *%ptr0, i64 8 - %ptr5 = getelementptr float *%ptr0, i64 10 - %ptr6 = getelementptr float *%ptr0, i64 12 - %ptr7 = getelementptr float *%ptr0, i64 14 - %ptr8 = getelementptr float *%ptr0, i64 16 - %ptr9 = getelementptr float *%ptr0, i64 18 - %ptr10 = getelementptr float *%ptr0, i64 20 + %ptr1 = getelementptr float, float *%ptr0, i64 2 + %ptr2 = getelementptr float, float *%ptr0, i64 4 + %ptr3 = getelementptr float, float *%ptr0, i64 6 + %ptr4 = getelementptr float, float *%ptr0, i64 8 + %ptr5 = getelementptr float, float *%ptr0, i64 10 + %ptr6 = getelementptr float, float *%ptr0, i64 12 + %ptr7 = getelementptr float, float *%ptr0, i64 14 + %ptr8 = getelementptr float, float *%ptr0, i64 16 + %ptr9 = getelementptr float, float *%ptr0, i64 18 + %ptr10 = getelementptr float, float *%ptr0, i64 20 - %val0 = load float *%ptr0 - %val1 = load float *%ptr1 - %val2 = load float *%ptr2 - %val3 = load float *%ptr3 - %val4 = load float *%ptr4 - %val5 = load float *%ptr5 - %val6 = load float *%ptr6 - %val7 = load float *%ptr7 - %val8 = load float *%ptr8 - %val9 = load float *%ptr9 - %val10 = load float *%ptr10 + %val0 = load float , float *%ptr0 + %val1 = load float , float *%ptr1 + %val2 = load float , float *%ptr2 + %val3 = load float , float *%ptr3 + %val4 = load float , float *%ptr4 + %val5 = load float , float *%ptr5 + %val6 = load float , float *%ptr6 + %val7 = load float , float *%ptr7 + %val8 = load float , float *%ptr8 + %val9 = load float , float *%ptr9 + %val10 = load float , float *%ptr10 %ret = call float @foo() diff --git a/test/CodeGen/SystemZ/fp-sub-02.ll b/test/CodeGen/SystemZ/fp-sub-02.ll index 99cafed8d08b..143baac23e19 100644 --- a/test/CodeGen/SystemZ/fp-sub-02.ll +++ b/test/CodeGen/SystemZ/fp-sub-02.ll @@ -1,6 +1,8 @@ ; Test 64-bit floating-point subtraction. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ +; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s declare double @foo() @@ -18,7 +20,7 @@ define double @f2(double %f1, double *%ptr) { ; CHECK-LABEL: f2: ; CHECK: sdb %f0, 0(%r2) ; CHECK: br %r14 - %f2 = load double *%ptr + %f2 = load double , double *%ptr %res = fsub double %f1, %f2 ret double %res } @@ -28,8 +30,8 @@ define double @f3(double %f1, double *%base) { ; CHECK-LABEL: f3: ; CHECK: sdb %f0, 4088(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 511 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 511 + %f2 = load double , double *%ptr %res = fsub double %f1, %f2 ret double %res } @@ -41,8 +43,8 @@ define double @f4(double %f1, double *%base) { ; CHECK: aghi %r2, 4096 ; CHECK: sdb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 512 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 512 + %f2 = load double , double *%ptr %res = fsub double %f1, %f2 ret double %res } @@ -53,8 +55,8 @@ define double @f5(double %f1, double *%base) { ; CHECK: aghi %r2, -8 ; CHECK: sdb %f0, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr double *%base, i64 -1 - %f2 = load double *%ptr + %ptr = getelementptr double, double *%base, i64 -1 + %f2 = load double , double *%ptr %res = fsub double %f1, %f2 ret double %res } @@ -65,9 +67,9 @@ define double @f6(double %f1, double *%base, i64 %index) { ; CHECK: sllg %r1, %r3, 3 ; CHECK: sdb %f0, 800(%r1,%r2) ; CHECK: br %r14 - %ptr1 = getelementptr double *%base, i64 %index - %ptr2 = getelementptr double *%ptr1, i64 100 - %f2 = load double *%ptr2 + %ptr1 = getelementptr double, double *%base, i64 %index + %ptr2 = getelementptr double, double *%ptr1, i64 100 + %f2 = load double , double *%ptr2 %res = fsub double %f1, %f2 ret double %res } @@ -76,30 +78,30 @@ define double @f6(double %f1, double *%base, i64 %index) { define double @f7(double *%ptr0) { ; CHECK-LABEL: f7: ; CHECK: brasl %r14, foo@PLT -; CHECK: sdb %f0, 16{{[04]}}(%r15) +; CHECK-SCALAR: sdb %f0, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr double *%ptr0, i64 2 - %ptr2 = getelementptr double *%ptr0, i64 4 - %ptr3 = getelementptr double *%ptr0, i64 6 - %ptr4 = getelementptr double *%ptr0, i64 8 - %ptr5 = getelementptr double *%ptr0, i64 10 - %ptr6 = getelementptr double *%ptr0, i64 12 - %ptr7 = getelementptr double *%ptr0, i64 14 - %ptr8 = getelementptr double *%ptr0, i64 16 - %ptr9 = getelementptr double *%ptr0, i64 18 - %ptr10 = getelementptr double *%ptr0, i64 20 + %ptr1 = getelementptr double, double *%ptr0, i64 2 + %ptr2 = getelementptr double, double *%ptr0, i64 4 + %ptr3 = getelementptr double, double *%ptr0, i64 6 + %ptr4 = getelementptr double, double *%ptr0, i64 8 + %ptr5 = getelementptr double, double *%ptr0, i64 10 + %ptr6 = getelementptr double, double *%ptr0, i64 12 + %ptr7 = getelementptr double, double *%ptr0, i64 14 + %ptr8 = getelementptr double, double *%ptr0, i64 16 + %ptr9 = getelementptr double, double *%ptr0, i64 18 + %ptr10 = getelementptr double, double *%ptr0, i64 20 - %val0 = load double *%ptr0 - %val1 = load double *%ptr1 - %val2 = load double *%ptr2 - %val3 = load double *%ptr3 - %val4 = load double *%ptr4 - %val5 = load double *%ptr5 - %val6 = load double *%ptr6 - %val7 = load double *%ptr7 - %val8 = load double *%ptr8 - %val9 = load double *%ptr9 - %val10 = load double *%ptr10 + %val0 = load double , double *%ptr0 + %val1 = load double , double *%ptr1 + %val2 = load double , double *%ptr2 + %val3 = load double , double *%ptr3 + %val4 = load double , double *%ptr4 + %val5 = load double , double *%ptr5 + %val6 = load double , double *%ptr6 + %val7 = load double , double *%ptr7 + %val8 = load double , double *%ptr8 + %val9 = load double , double *%ptr9 + %val10 = load double , double *%ptr10 %ret = call double @foo() diff --git a/test/CodeGen/SystemZ/fp-sub-03.ll b/test/CodeGen/SystemZ/fp-sub-03.ll index a1404c4ff0e7..86faafeaaca2 100644 --- a/test/CodeGen/SystemZ/fp-sub-03.ll +++ b/test/CodeGen/SystemZ/fp-sub-03.ll @@ -12,7 +12,7 @@ define void @f1(fp128 *%ptr, float %f2) { ; CHECK: std %f1, 0(%r2) ; CHECK: std %f3, 8(%r2) ; CHECK: br %r14 - %f1 = load fp128 *%ptr + %f1 = load fp128 , fp128 *%ptr %f2x = fpext float %f2 to fp128 %sum = fsub fp128 %f1, %f2x store fp128 %sum, fp128 *%ptr diff --git a/test/CodeGen/SystemZ/frame-01.ll b/test/CodeGen/SystemZ/frame-01.ll index f61836ca8552..5afc4f1cef34 100644 --- a/test/CodeGen/SystemZ/frame-01.ll +++ b/test/CodeGen/SystemZ/frame-01.ll @@ -31,7 +31,7 @@ define void @f2(i64 %x) { ; CHECK: aghi %r15, 32760 ; CHECK: br %r14 %y = alloca [4073 x i64], align 8 - %ptr = getelementptr inbounds [4073 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [4073 x i64], [4073 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } @@ -46,7 +46,7 @@ define void @f3(i64 %x) { ; CHECK: agfi %r15, 32768 ; CHECK: br %r14 %y = alloca [4074 x i64], align 8 - %ptr = getelementptr inbounds [4074 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [4074 x i64], [4074 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } @@ -61,7 +61,7 @@ define void @f4(i64 %x) { ; CHECK: agfi %r15, 32776 ; CHECK: br %r14 %y = alloca [4075 x i64], align 8 - %ptr = getelementptr inbounds [4075 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [4075 x i64], [4075 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } @@ -75,7 +75,7 @@ define void @f5(i64 %x) { ; CHECK: agfi %r15, 2147483640 ; CHECK: br %r14 %y = alloca [268435433 x i64], align 8 - %ptr = getelementptr inbounds [268435433 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [268435433 x i64], [268435433 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } @@ -90,7 +90,7 @@ define void @f6(i64 %x) { ; CHECK: aghi %r15, 8 ; CHECK: br %r14 %y = alloca [268435434 x i64], align 8 - %ptr = getelementptr inbounds [268435434 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [268435434 x i64], [268435434 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } @@ -106,7 +106,7 @@ define void @f7(i64 %x) { ; CHECK: aghi %r15, 16 ; CHECK: br %r14 %y = alloca [268435435 x i64], align 8 - %ptr = getelementptr inbounds [268435435 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [268435435 x i64], [268435435 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } diff --git a/test/CodeGen/SystemZ/frame-02.ll b/test/CodeGen/SystemZ/frame-02.ll index 9a7f8eac9eba..a41db77e851a 100644 --- a/test/CodeGen/SystemZ/frame-02.ll +++ b/test/CodeGen/SystemZ/frame-02.ll @@ -37,22 +37,22 @@ define void @f1(float *%ptr) { ; CHECK: ld %f15, 160(%r15) ; CHECK: aghi %r15, 224 ; CHECK: br %r14 - %l0 = load volatile float *%ptr - %l1 = load volatile float *%ptr - %l2 = load volatile float *%ptr - %l3 = load volatile float *%ptr - %l4 = load volatile float *%ptr - %l5 = load volatile float *%ptr - %l6 = load volatile float *%ptr - %l7 = load volatile float *%ptr - %l8 = load volatile float *%ptr - %l9 = load volatile float *%ptr - %l10 = load volatile float *%ptr - %l11 = load volatile float *%ptr - %l12 = load volatile float *%ptr - %l13 = load volatile float *%ptr - %l14 = load volatile float *%ptr - %l15 = load volatile float *%ptr + %l0 = load volatile float , float *%ptr + %l1 = load volatile float , float *%ptr + %l2 = load volatile float , float *%ptr + %l3 = load volatile float , float *%ptr + %l4 = load volatile float , float *%ptr + %l5 = load volatile float , float *%ptr + %l6 = load volatile float , float *%ptr + %l7 = load volatile float , float *%ptr + %l8 = load volatile float , float *%ptr + %l9 = load volatile float , float *%ptr + %l10 = load volatile float , float *%ptr + %l11 = load volatile float , float *%ptr + %l12 = load volatile float , float *%ptr + %l13 = load volatile float , float *%ptr + %l14 = load volatile float , float *%ptr + %l15 = load volatile float , float *%ptr %add0 = fadd float %l0, %l0 %add1 = fadd float %l1, %add0 %add2 = fadd float %l2, %add1 @@ -119,21 +119,21 @@ define void @f2(float *%ptr) { ; CHECK: ld %f14, 160(%r15) ; CHECK: aghi %r15, 216 ; CHECK: br %r14 - %l0 = load volatile float *%ptr - %l1 = load volatile float *%ptr - %l2 = load volatile float *%ptr - %l3 = load volatile float *%ptr - %l4 = load volatile float *%ptr - %l5 = load volatile float *%ptr - %l6 = load volatile float *%ptr - %l7 = load volatile float *%ptr - %l8 = load volatile float *%ptr - %l9 = load volatile float *%ptr - %l10 = load volatile float *%ptr - %l11 = load volatile float *%ptr - %l12 = load volatile float *%ptr - %l13 = load volatile float *%ptr - %l14 = load volatile float *%ptr + %l0 = load volatile float , float *%ptr + %l1 = load volatile float , float *%ptr + %l2 = load volatile float , float *%ptr + %l3 = load volatile float , float *%ptr + %l4 = load volatile float , float *%ptr + %l5 = load volatile float , float *%ptr + %l6 = load volatile float , float *%ptr + %l7 = load volatile float , float *%ptr + %l8 = load volatile float , float *%ptr + %l9 = load volatile float , float *%ptr + %l10 = load volatile float , float *%ptr + %l11 = load volatile float , float *%ptr + %l12 = load volatile float , float *%ptr + %l13 = load volatile float , float *%ptr + %l14 = load volatile float , float *%ptr %add0 = fadd float %l0, %l0 %add1 = fadd float %l1, %add0 %add2 = fadd float %l2, %add1 @@ -185,15 +185,15 @@ define void @f3(float *%ptr) { ; CHECK: ld %f8, 160(%r15) ; CHECK: aghi %r15, 168 ; CHECK: br %r14 - %l0 = load volatile float *%ptr - %l1 = load volatile float *%ptr - %l2 = load volatile float *%ptr - %l3 = load volatile float *%ptr - %l4 = load volatile float *%ptr - %l5 = load volatile float *%ptr - %l6 = load volatile float *%ptr - %l7 = load volatile float *%ptr - %l8 = load volatile float *%ptr + %l0 = load volatile float , float *%ptr + %l1 = load volatile float , float *%ptr + %l2 = load volatile float , float *%ptr + %l3 = load volatile float , float *%ptr + %l4 = load volatile float , float *%ptr + %l5 = load volatile float , float *%ptr + %l6 = load volatile float , float *%ptr + %l7 = load volatile float , float *%ptr + %l8 = load volatile float , float *%ptr %add0 = fadd float %l0, %l0 %add1 = fadd float %l1, %add0 %add2 = fadd float %l2, %add1 @@ -229,14 +229,14 @@ define void @f4(float *%ptr) { ; CHECK-NOT: %f14 ; CHECK-NOT: %f15 ; CHECK: br %r14 - %l0 = load volatile float *%ptr - %l1 = load volatile float *%ptr - %l2 = load volatile float *%ptr - %l3 = load volatile float *%ptr - %l4 = load volatile float *%ptr - %l5 = load volatile float *%ptr - %l6 = load volatile float *%ptr - %l7 = load volatile float *%ptr + %l0 = load volatile float , float *%ptr + %l1 = load volatile float , float *%ptr + %l2 = load volatile float , float *%ptr + %l3 = load volatile float , float *%ptr + %l4 = load volatile float , float *%ptr + %l5 = load volatile float , float *%ptr + %l6 = load volatile float , float *%ptr + %l7 = load volatile float , float *%ptr %add0 = fadd float %l0, %l0 %add1 = fadd float %l1, %add0 %add2 = fadd float %l2, %add1 diff --git a/test/CodeGen/SystemZ/frame-03.ll b/test/CodeGen/SystemZ/frame-03.ll index db146c7c985d..21b8fdb0d672 100644 --- a/test/CodeGen/SystemZ/frame-03.ll +++ b/test/CodeGen/SystemZ/frame-03.ll @@ -2,7 +2,7 @@ ; uses a different register class, but the set of saved and restored ; registers should be the same. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; This function should require all FPRs, but no other spill slots. ; We need to save and restore 8 of the 16 FPRs, so the frame size @@ -39,22 +39,22 @@ define void @f1(double *%ptr) { ; CHECK: ld %f15, 160(%r15) ; CHECK: aghi %r15, 224 ; CHECK: br %r14 - %l0 = load volatile double *%ptr - %l1 = load volatile double *%ptr - %l2 = load volatile double *%ptr - %l3 = load volatile double *%ptr - %l4 = load volatile double *%ptr - %l5 = load volatile double *%ptr - %l6 = load volatile double *%ptr - %l7 = load volatile double *%ptr - %l8 = load volatile double *%ptr - %l9 = load volatile double *%ptr - %l10 = load volatile double *%ptr - %l11 = load volatile double *%ptr - %l12 = load volatile double *%ptr - %l13 = load volatile double *%ptr - %l14 = load volatile double *%ptr - %l15 = load volatile double *%ptr + %l0 = load volatile double , double *%ptr + %l1 = load volatile double , double *%ptr + %l2 = load volatile double , double *%ptr + %l3 = load volatile double , double *%ptr + %l4 = load volatile double , double *%ptr + %l5 = load volatile double , double *%ptr + %l6 = load volatile double , double *%ptr + %l7 = load volatile double , double *%ptr + %l8 = load volatile double , double *%ptr + %l9 = load volatile double , double *%ptr + %l10 = load volatile double , double *%ptr + %l11 = load volatile double , double *%ptr + %l12 = load volatile double , double *%ptr + %l13 = load volatile double , double *%ptr + %l14 = load volatile double , double *%ptr + %l15 = load volatile double , double *%ptr %add0 = fadd double %l0, %l0 %add1 = fadd double %l1, %add0 %add2 = fadd double %l2, %add1 @@ -121,21 +121,21 @@ define void @f2(double *%ptr) { ; CHECK: ld %f14, 160(%r15) ; CHECK: aghi %r15, 216 ; CHECK: br %r14 - %l0 = load volatile double *%ptr - %l1 = load volatile double *%ptr - %l2 = load volatile double *%ptr - %l3 = load volatile double *%ptr - %l4 = load volatile double *%ptr - %l5 = load volatile double *%ptr - %l6 = load volatile double *%ptr - %l7 = load volatile double *%ptr - %l8 = load volatile double *%ptr - %l9 = load volatile double *%ptr - %l10 = load volatile double *%ptr - %l11 = load volatile double *%ptr - %l12 = load volatile double *%ptr - %l13 = load volatile double *%ptr - %l14 = load volatile double *%ptr + %l0 = load volatile double , double *%ptr + %l1 = load volatile double , double *%ptr + %l2 = load volatile double , double *%ptr + %l3 = load volatile double , double *%ptr + %l4 = load volatile double , double *%ptr + %l5 = load volatile double , double *%ptr + %l6 = load volatile double , double *%ptr + %l7 = load volatile double , double *%ptr + %l8 = load volatile double , double *%ptr + %l9 = load volatile double , double *%ptr + %l10 = load volatile double , double *%ptr + %l11 = load volatile double , double *%ptr + %l12 = load volatile double , double *%ptr + %l13 = load volatile double , double *%ptr + %l14 = load volatile double , double *%ptr %add0 = fadd double %l0, %l0 %add1 = fadd double %l1, %add0 %add2 = fadd double %l2, %add1 @@ -187,15 +187,15 @@ define void @f3(double *%ptr) { ; CHECK: ld %f8, 160(%r15) ; CHECK: aghi %r15, 168 ; CHECK: br %r14 - %l0 = load volatile double *%ptr - %l1 = load volatile double *%ptr - %l2 = load volatile double *%ptr - %l3 = load volatile double *%ptr - %l4 = load volatile double *%ptr - %l5 = load volatile double *%ptr - %l6 = load volatile double *%ptr - %l7 = load volatile double *%ptr - %l8 = load volatile double *%ptr + %l0 = load volatile double , double *%ptr + %l1 = load volatile double , double *%ptr + %l2 = load volatile double , double *%ptr + %l3 = load volatile double , double *%ptr + %l4 = load volatile double , double *%ptr + %l5 = load volatile double , double *%ptr + %l6 = load volatile double , double *%ptr + %l7 = load volatile double , double *%ptr + %l8 = load volatile double , double *%ptr %add0 = fadd double %l0, %l0 %add1 = fadd double %l1, %add0 %add2 = fadd double %l2, %add1 @@ -231,14 +231,14 @@ define void @f4(double *%ptr) { ; CHECK-NOT: %f14 ; CHECK-NOT: %f15 ; CHECK: br %r14 - %l0 = load volatile double *%ptr - %l1 = load volatile double *%ptr - %l2 = load volatile double *%ptr - %l3 = load volatile double *%ptr - %l4 = load volatile double *%ptr - %l5 = load volatile double *%ptr - %l6 = load volatile double *%ptr - %l7 = load volatile double *%ptr + %l0 = load volatile double , double *%ptr + %l1 = load volatile double , double *%ptr + %l2 = load volatile double , double *%ptr + %l3 = load volatile double , double *%ptr + %l4 = load volatile double , double *%ptr + %l5 = load volatile double , double *%ptr + %l6 = load volatile double , double *%ptr + %l7 = load volatile double , double *%ptr %add0 = fadd double %l0, %l0 %add1 = fadd double %l1, %add0 %add2 = fadd double %l2, %add1 diff --git a/test/CodeGen/SystemZ/frame-04.ll b/test/CodeGen/SystemZ/frame-04.ll index 93c59a3bc15f..602050978d30 100644 --- a/test/CodeGen/SystemZ/frame-04.ll +++ b/test/CodeGen/SystemZ/frame-04.ll @@ -38,14 +38,14 @@ define void @f1(fp128 *%ptr) { ; CHECK: ld %f15, 160(%r15) ; CHECK: aghi %r15, 224 ; CHECK: br %r14 - %l0 = load volatile fp128 *%ptr - %l1 = load volatile fp128 *%ptr - %l4 = load volatile fp128 *%ptr - %l5 = load volatile fp128 *%ptr - %l8 = load volatile fp128 *%ptr - %l9 = load volatile fp128 *%ptr - %l12 = load volatile fp128 *%ptr - %l13 = load volatile fp128 *%ptr + %l0 = load volatile fp128 , fp128 *%ptr + %l1 = load volatile fp128 , fp128 *%ptr + %l4 = load volatile fp128 , fp128 *%ptr + %l5 = load volatile fp128 , fp128 *%ptr + %l8 = load volatile fp128 , fp128 *%ptr + %l9 = load volatile fp128 , fp128 *%ptr + %l12 = load volatile fp128 , fp128 *%ptr + %l13 = load volatile fp128 , fp128 *%ptr %add0 = fadd fp128 %l0, %l0 %add1 = fadd fp128 %l1, %add0 %add4 = fadd fp128 %l4, %add1 @@ -94,13 +94,13 @@ define void @f2(fp128 *%ptr) { ; CHECK: ld %f14, 160(%r15) ; CHECK: aghi %r15, 208 ; CHECK: br %r14 - %l0 = load volatile fp128 *%ptr - %l1 = load volatile fp128 *%ptr - %l4 = load volatile fp128 *%ptr - %l5 = load volatile fp128 *%ptr - %l8 = load volatile fp128 *%ptr - %l9 = load volatile fp128 *%ptr - %l12 = load volatile fp128 *%ptr + %l0 = load volatile fp128 , fp128 *%ptr + %l1 = load volatile fp128 , fp128 *%ptr + %l4 = load volatile fp128 , fp128 *%ptr + %l5 = load volatile fp128 , fp128 *%ptr + %l8 = load volatile fp128 , fp128 *%ptr + %l9 = load volatile fp128 , fp128 *%ptr + %l12 = load volatile fp128 , fp128 *%ptr %add0 = fadd fp128 %l0, %l0 %add1 = fadd fp128 %l1, %add0 %add4 = fadd fp128 %l4, %add1 @@ -139,11 +139,11 @@ define void @f3(fp128 *%ptr) { ; CHECK: ld %f10, 160(%r15) ; CHECK: aghi %r15, 176 ; CHECK: br %r14 - %l0 = load volatile fp128 *%ptr - %l1 = load volatile fp128 *%ptr - %l4 = load volatile fp128 *%ptr - %l5 = load volatile fp128 *%ptr - %l8 = load volatile fp128 *%ptr + %l0 = load volatile fp128 , fp128 *%ptr + %l1 = load volatile fp128 , fp128 *%ptr + %l4 = load volatile fp128 , fp128 *%ptr + %l5 = load volatile fp128 , fp128 *%ptr + %l8 = load volatile fp128 , fp128 *%ptr %add0 = fadd fp128 %l0, %l0 %add1 = fadd fp128 %l1, %add0 %add4 = fadd fp128 %l4, %add1 @@ -171,10 +171,10 @@ define void @f4(fp128 *%ptr) { ; CHECK-NOT: %f14 ; CHECK-NOT: %f15 ; CHECK: br %r14 - %l0 = load volatile fp128 *%ptr - %l1 = load volatile fp128 *%ptr - %l4 = load volatile fp128 *%ptr - %l5 = load volatile fp128 *%ptr + %l0 = load volatile fp128 , fp128 *%ptr + %l1 = load volatile fp128 , fp128 *%ptr + %l4 = load volatile fp128 , fp128 *%ptr + %l5 = load volatile fp128 , fp128 *%ptr %add0 = fadd fp128 %l0, %l0 %add1 = fadd fp128 %l1, %add0 %add4 = fadd fp128 %l4, %add1 diff --git a/test/CodeGen/SystemZ/frame-05.ll b/test/CodeGen/SystemZ/frame-05.ll index f95284deeb79..93130dcbfbbc 100644 --- a/test/CodeGen/SystemZ/frame-05.ll +++ b/test/CodeGen/SystemZ/frame-05.ll @@ -32,20 +32,20 @@ define void @f1(i32 *%ptr) { ; CHECK: st {{.*}}, 4(%r2) ; CHECK: lmg %r6, %r15, 48(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l3 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l6 = load volatile i32 *%ptr - %l7 = load volatile i32 *%ptr - %l8 = load volatile i32 *%ptr - %l9 = load volatile i32 *%ptr - %l10 = load volatile i32 *%ptr - %l11 = load volatile i32 *%ptr - %l12 = load volatile i32 *%ptr - %l13 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l3 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l6 = load volatile i32 , i32 *%ptr + %l7 = load volatile i32 , i32 *%ptr + %l8 = load volatile i32 , i32 *%ptr + %l9 = load volatile i32 , i32 *%ptr + %l10 = load volatile i32 , i32 *%ptr + %l11 = load volatile i32 , i32 *%ptr + %l12 = load volatile i32 , i32 *%ptr + %l13 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add3 = add i32 %l3, %add1 @@ -73,7 +73,7 @@ define void @f1(i32 *%ptr) { store volatile i32 %add11, i32 *%ptr store volatile i32 %add12, i32 *%ptr store volatile i32 %add13, i32 *%ptr - %final = getelementptr i32 *%ptr, i32 1 + %final = getelementptr i32, i32 *%ptr, i32 1 store volatile i32 %add14, i32 *%final ret void } @@ -100,19 +100,19 @@ define void @f2(i32 *%ptr) { ; CHECK: st {{.*}}, 4(%r2) ; CHECK: lmg %r7, %r15, 56(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l3 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l7 = load volatile i32 *%ptr - %l8 = load volatile i32 *%ptr - %l9 = load volatile i32 *%ptr - %l10 = load volatile i32 *%ptr - %l11 = load volatile i32 *%ptr - %l12 = load volatile i32 *%ptr - %l13 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l3 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l7 = load volatile i32 , i32 *%ptr + %l8 = load volatile i32 , i32 *%ptr + %l9 = load volatile i32 , i32 *%ptr + %l10 = load volatile i32 , i32 *%ptr + %l11 = load volatile i32 , i32 *%ptr + %l12 = load volatile i32 , i32 *%ptr + %l13 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add3 = add i32 %l3, %add1 @@ -138,7 +138,7 @@ define void @f2(i32 *%ptr) { store volatile i32 %add11, i32 *%ptr store volatile i32 %add12, i32 *%ptr store volatile i32 %add13, i32 *%ptr - %final = getelementptr i32 *%ptr, i32 1 + %final = getelementptr i32, i32 *%ptr, i32 1 store volatile i32 %add14, i32 *%final ret void } @@ -163,12 +163,12 @@ define void @f3(i32 *%ptr) { ; CHECK: st {{.*}}, 4(%r2) ; CHECK: lmg %r14, %r15, 112(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l3 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l3 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add3 = add i32 %l3, %add1 @@ -180,7 +180,7 @@ define void @f3(i32 *%ptr) { store volatile i32 %add3, i32 *%ptr store volatile i32 %add4, i32 *%ptr store volatile i32 %add5, i32 *%ptr - %final = getelementptr i32 *%ptr, i32 1 + %final = getelementptr i32, i32 *%ptr, i32 1 store volatile i32 %add14, i32 *%final ret void } @@ -199,11 +199,11 @@ define void @f4(i32 *%ptr) { ; CHECK-NOT: %r12 ; CHECK-NOT: %r13 ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l3 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l3 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add3 = add i32 %l3, %add1 @@ -213,7 +213,7 @@ define void @f4(i32 *%ptr) { store volatile i32 %add1, i32 *%ptr store volatile i32 %add3, i32 *%ptr store volatile i32 %add4, i32 *%ptr - %final = getelementptr i32 *%ptr, i32 1 + %final = getelementptr i32, i32 *%ptr, i32 1 store volatile i32 %add5, i32 *%final ret void } diff --git a/test/CodeGen/SystemZ/frame-06.ll b/test/CodeGen/SystemZ/frame-06.ll index ad22f10903ad..c2aa8af336a0 100644 --- a/test/CodeGen/SystemZ/frame-06.ll +++ b/test/CodeGen/SystemZ/frame-06.ll @@ -29,20 +29,20 @@ define void @f1(i64 *%ptr) { ; CHECK: stg {{.*}}, 8(%r2) ; CHECK: lmg %r6, %r15, 48(%r15) ; CHECK: br %r14 - %l0 = load volatile i64 *%ptr - %l1 = load volatile i64 *%ptr - %l3 = load volatile i64 *%ptr - %l4 = load volatile i64 *%ptr - %l5 = load volatile i64 *%ptr - %l6 = load volatile i64 *%ptr - %l7 = load volatile i64 *%ptr - %l8 = load volatile i64 *%ptr - %l9 = load volatile i64 *%ptr - %l10 = load volatile i64 *%ptr - %l11 = load volatile i64 *%ptr - %l12 = load volatile i64 *%ptr - %l13 = load volatile i64 *%ptr - %l14 = load volatile i64 *%ptr + %l0 = load volatile i64 , i64 *%ptr + %l1 = load volatile i64 , i64 *%ptr + %l3 = load volatile i64 , i64 *%ptr + %l4 = load volatile i64 , i64 *%ptr + %l5 = load volatile i64 , i64 *%ptr + %l6 = load volatile i64 , i64 *%ptr + %l7 = load volatile i64 , i64 *%ptr + %l8 = load volatile i64 , i64 *%ptr + %l9 = load volatile i64 , i64 *%ptr + %l10 = load volatile i64 , i64 *%ptr + %l11 = load volatile i64 , i64 *%ptr + %l12 = load volatile i64 , i64 *%ptr + %l13 = load volatile i64 , i64 *%ptr + %l14 = load volatile i64 , i64 *%ptr %add0 = add i64 %l0, %l0 %add1 = add i64 %l1, %add0 %add3 = add i64 %l3, %add1 @@ -70,7 +70,7 @@ define void @f1(i64 *%ptr) { store volatile i64 %add11, i64 *%ptr store volatile i64 %add12, i64 *%ptr store volatile i64 %add13, i64 *%ptr - %final = getelementptr i64 *%ptr, i64 1 + %final = getelementptr i64, i64 *%ptr, i64 1 store volatile i64 %add14, i64 *%final ret void } @@ -97,19 +97,19 @@ define void @f2(i64 *%ptr) { ; CHECK: stg {{.*}}, 8(%r2) ; CHECK: lmg %r7, %r15, 56(%r15) ; CHECK: br %r14 - %l0 = load volatile i64 *%ptr - %l1 = load volatile i64 *%ptr - %l3 = load volatile i64 *%ptr - %l4 = load volatile i64 *%ptr - %l5 = load volatile i64 *%ptr - %l7 = load volatile i64 *%ptr - %l8 = load volatile i64 *%ptr - %l9 = load volatile i64 *%ptr - %l10 = load volatile i64 *%ptr - %l11 = load volatile i64 *%ptr - %l12 = load volatile i64 *%ptr - %l13 = load volatile i64 *%ptr - %l14 = load volatile i64 *%ptr + %l0 = load volatile i64 , i64 *%ptr + %l1 = load volatile i64 , i64 *%ptr + %l3 = load volatile i64 , i64 *%ptr + %l4 = load volatile i64 , i64 *%ptr + %l5 = load volatile i64 , i64 *%ptr + %l7 = load volatile i64 , i64 *%ptr + %l8 = load volatile i64 , i64 *%ptr + %l9 = load volatile i64 , i64 *%ptr + %l10 = load volatile i64 , i64 *%ptr + %l11 = load volatile i64 , i64 *%ptr + %l12 = load volatile i64 , i64 *%ptr + %l13 = load volatile i64 , i64 *%ptr + %l14 = load volatile i64 , i64 *%ptr %add0 = add i64 %l0, %l0 %add1 = add i64 %l1, %add0 %add3 = add i64 %l3, %add1 @@ -135,7 +135,7 @@ define void @f2(i64 *%ptr) { store volatile i64 %add11, i64 *%ptr store volatile i64 %add12, i64 *%ptr store volatile i64 %add13, i64 *%ptr - %final = getelementptr i64 *%ptr, i64 1 + %final = getelementptr i64, i64 *%ptr, i64 1 store volatile i64 %add14, i64 *%final ret void } @@ -160,12 +160,12 @@ define void @f3(i64 *%ptr) { ; CHECK: stg {{.*}}, 8(%r2) ; CHECK: lmg %r14, %r15, 112(%r15) ; CHECK: br %r14 - %l0 = load volatile i64 *%ptr - %l1 = load volatile i64 *%ptr - %l3 = load volatile i64 *%ptr - %l4 = load volatile i64 *%ptr - %l5 = load volatile i64 *%ptr - %l14 = load volatile i64 *%ptr + %l0 = load volatile i64 , i64 *%ptr + %l1 = load volatile i64 , i64 *%ptr + %l3 = load volatile i64 , i64 *%ptr + %l4 = load volatile i64 , i64 *%ptr + %l5 = load volatile i64 , i64 *%ptr + %l14 = load volatile i64 , i64 *%ptr %add0 = add i64 %l0, %l0 %add1 = add i64 %l1, %add0 %add3 = add i64 %l3, %add1 @@ -177,7 +177,7 @@ define void @f3(i64 *%ptr) { store volatile i64 %add3, i64 *%ptr store volatile i64 %add4, i64 *%ptr store volatile i64 %add5, i64 *%ptr - %final = getelementptr i64 *%ptr, i64 1 + %final = getelementptr i64, i64 *%ptr, i64 1 store volatile i64 %add14, i64 *%final ret void } @@ -196,11 +196,11 @@ define void @f4(i64 *%ptr) { ; CHECK-NOT: %r12 ; CHECK-NOT: %r13 ; CHECK: br %r14 - %l0 = load volatile i64 *%ptr - %l1 = load volatile i64 *%ptr - %l3 = load volatile i64 *%ptr - %l4 = load volatile i64 *%ptr - %l5 = load volatile i64 *%ptr + %l0 = load volatile i64 , i64 *%ptr + %l1 = load volatile i64 , i64 *%ptr + %l3 = load volatile i64 , i64 *%ptr + %l4 = load volatile i64 , i64 *%ptr + %l5 = load volatile i64 , i64 *%ptr %add0 = add i64 %l0, %l0 %add1 = add i64 %l1, %add0 %add3 = add i64 %l3, %add1 @@ -210,7 +210,7 @@ define void @f4(i64 *%ptr) { store volatile i64 %add1, i64 *%ptr store volatile i64 %add3, i64 *%ptr store volatile i64 %add4, i64 *%ptr - %final = getelementptr i64 *%ptr, i64 1 + %final = getelementptr i64, i64 *%ptr, i64 1 store volatile i64 %add5, i64 *%final ret void } diff --git a/test/CodeGen/SystemZ/frame-07.ll b/test/CodeGen/SystemZ/frame-07.ll index eab313744b94..dd8101429628 100644 --- a/test/CodeGen/SystemZ/frame-07.ll +++ b/test/CodeGen/SystemZ/frame-07.ll @@ -1,7 +1,7 @@ ; Test the saving and restoring of FPRs in large frames. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s ; Test a frame size that requires some FPRs to be saved and loaded using ; the 20-bit STDY and LDY while others can use the 12-bit STD and LD. @@ -66,24 +66,24 @@ define void @f1(double *%ptr, i64 %x) { ; CHECK-FP: lmg %r11, %r15, 4216(%r11) ; CHECK-FP: br %r14 %y = alloca [486 x i64], align 8 - %elem = getelementptr inbounds [486 x i64]* %y, i64 0, i64 0 + %elem = getelementptr inbounds [486 x i64], [486 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %elem - %l0 = load volatile double *%ptr - %l1 = load volatile double *%ptr - %l2 = load volatile double *%ptr - %l3 = load volatile double *%ptr - %l4 = load volatile double *%ptr - %l5 = load volatile double *%ptr - %l6 = load volatile double *%ptr - %l7 = load volatile double *%ptr - %l8 = load volatile double *%ptr - %l9 = load volatile double *%ptr - %l10 = load volatile double *%ptr - %l11 = load volatile double *%ptr - %l12 = load volatile double *%ptr - %l13 = load volatile double *%ptr - %l14 = load volatile double *%ptr - %l15 = load volatile double *%ptr + %l0 = load volatile double , double *%ptr + %l1 = load volatile double , double *%ptr + %l2 = load volatile double , double *%ptr + %l3 = load volatile double , double *%ptr + %l4 = load volatile double , double *%ptr + %l5 = load volatile double , double *%ptr + %l6 = load volatile double , double *%ptr + %l7 = load volatile double , double *%ptr + %l8 = load volatile double , double *%ptr + %l9 = load volatile double , double *%ptr + %l10 = load volatile double , double *%ptr + %l11 = load volatile double , double *%ptr + %l12 = load volatile double , double *%ptr + %l13 = load volatile double , double *%ptr + %l14 = load volatile double , double *%ptr + %l15 = load volatile double , double *%ptr %add0 = fadd double %l0, %l0 %add1 = fadd double %l1, %add0 %add2 = fadd double %l2, %add1 @@ -195,24 +195,24 @@ define void @f2(double *%ptr, i64 %x) { ; CHECK-FP: lmg %r11, %r15, 524280(%r11) ; CHECK-FP: br %r14 %y = alloca [65510 x i64], align 8 - %elem = getelementptr inbounds [65510 x i64]* %y, i64 0, i64 0 + %elem = getelementptr inbounds [65510 x i64], [65510 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %elem - %l0 = load volatile double *%ptr - %l1 = load volatile double *%ptr - %l2 = load volatile double *%ptr - %l3 = load volatile double *%ptr - %l4 = load volatile double *%ptr - %l5 = load volatile double *%ptr - %l6 = load volatile double *%ptr - %l7 = load volatile double *%ptr - %l8 = load volatile double *%ptr - %l9 = load volatile double *%ptr - %l10 = load volatile double *%ptr - %l11 = load volatile double *%ptr - %l12 = load volatile double *%ptr - %l13 = load volatile double *%ptr - %l14 = load volatile double *%ptr - %l15 = load volatile double *%ptr + %l0 = load volatile double , double *%ptr + %l1 = load volatile double , double *%ptr + %l2 = load volatile double , double *%ptr + %l3 = load volatile double , double *%ptr + %l4 = load volatile double , double *%ptr + %l5 = load volatile double , double *%ptr + %l6 = load volatile double , double *%ptr + %l7 = load volatile double , double *%ptr + %l8 = load volatile double , double *%ptr + %l9 = load volatile double , double *%ptr + %l10 = load volatile double , double *%ptr + %l11 = load volatile double , double *%ptr + %l12 = load volatile double , double *%ptr + %l13 = load volatile double , double *%ptr + %l14 = load volatile double , double *%ptr + %l15 = load volatile double , double *%ptr %add0 = fadd double %l0, %l0 %add1 = fadd double %l1, %add0 %add2 = fadd double %l2, %add1 diff --git a/test/CodeGen/SystemZ/frame-08.ll b/test/CodeGen/SystemZ/frame-08.ll index aa4e3f481da4..99e64108bca1 100644 --- a/test/CodeGen/SystemZ/frame-08.ll +++ b/test/CodeGen/SystemZ/frame-08.ll @@ -25,19 +25,19 @@ define void @f1(i32 *%ptr, i64 %x) { ; CHECK-NOT: ag ; CHECK: lmg %r6, %r15, 524280(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l6 = load volatile i32 *%ptr - %l7 = load volatile i32 *%ptr - %l8 = load volatile i32 *%ptr - %l9 = load volatile i32 *%ptr - %l10 = load volatile i32 *%ptr - %l11 = load volatile i32 *%ptr - %l12 = load volatile i32 *%ptr - %l13 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l6 = load volatile i32 , i32 *%ptr + %l7 = load volatile i32 , i32 *%ptr + %l8 = load volatile i32 , i32 *%ptr + %l9 = load volatile i32 , i32 *%ptr + %l10 = load volatile i32 , i32 *%ptr + %l11 = load volatile i32 , i32 *%ptr + %l12 = load volatile i32 , i32 *%ptr + %l13 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add4 = add i32 %l4, %add1 @@ -65,7 +65,7 @@ define void @f1(i32 *%ptr, i64 %x) { store volatile i32 %add13, i32 *%ptr store volatile i32 %add14, i32 *%ptr %y = alloca [65507 x i64], align 8 - %entry = getelementptr inbounds [65507 x i64]* %y, i64 0, i64 0 + %entry = getelementptr inbounds [65507 x i64], [65507 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %entry ret void } @@ -85,11 +85,11 @@ define void @f2(i32 *%ptr, i64 %x) { ; CHECK-NOT: ag ; CHECK: lmg %r14, %r15, 524280(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add4 = add i32 %l4, %add1 @@ -101,7 +101,7 @@ define void @f2(i32 *%ptr, i64 %x) { store volatile i32 %add5, i32 *%ptr store volatile i32 %add14, i32 *%ptr %y = alloca [65499 x i64], align 8 - %entry = getelementptr inbounds [65499 x i64]* %y, i64 0, i64 0 + %entry = getelementptr inbounds [65499 x i64], [65499 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %entry ret void } @@ -128,19 +128,19 @@ define void @f3(i32 *%ptr, i64 %x) { ; CHECK: aghi %r15, 8 ; CHECK: lmg %r6, %r15, 524280(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l6 = load volatile i32 *%ptr - %l7 = load volatile i32 *%ptr - %l8 = load volatile i32 *%ptr - %l9 = load volatile i32 *%ptr - %l10 = load volatile i32 *%ptr - %l11 = load volatile i32 *%ptr - %l12 = load volatile i32 *%ptr - %l13 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l6 = load volatile i32 , i32 *%ptr + %l7 = load volatile i32 , i32 *%ptr + %l8 = load volatile i32 , i32 *%ptr + %l9 = load volatile i32 , i32 *%ptr + %l10 = load volatile i32 , i32 *%ptr + %l11 = load volatile i32 , i32 *%ptr + %l12 = load volatile i32 , i32 *%ptr + %l13 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add4 = add i32 %l4, %add1 @@ -168,7 +168,7 @@ define void @f3(i32 *%ptr, i64 %x) { store volatile i32 %add13, i32 *%ptr store volatile i32 %add14, i32 *%ptr %y = alloca [65508 x i64], align 8 - %entry = getelementptr inbounds [65508 x i64]* %y, i64 0, i64 0 + %entry = getelementptr inbounds [65508 x i64], [65508 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %entry ret void } @@ -187,11 +187,11 @@ define void @f4(i32 *%ptr, i64 %x) { ; CHECK: aghi %r15, 8 ; CHECK: lmg %r14, %r15, 524280(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add4 = add i32 %l4, %add1 @@ -203,7 +203,7 @@ define void @f4(i32 *%ptr, i64 %x) { store volatile i32 %add5, i32 *%ptr store volatile i32 %add14, i32 *%ptr %y = alloca [65500 x i64], align 8 - %entry = getelementptr inbounds [65500 x i64]* %y, i64 0, i64 0 + %entry = getelementptr inbounds [65500 x i64], [65500 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %entry ret void } @@ -221,11 +221,11 @@ define void @f5(i32 *%ptr, i64 %x) { ; CHECK: aghi %r15, 32760 ; CHECK: lmg %r14, %r15, 524280(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add4 = add i32 %l4, %add1 @@ -237,7 +237,7 @@ define void @f5(i32 *%ptr, i64 %x) { store volatile i32 %add5, i32 *%ptr store volatile i32 %add14, i32 *%ptr %y = alloca [69594 x i64], align 8 - %entry = getelementptr inbounds [69594 x i64]* %y, i64 0, i64 0 + %entry = getelementptr inbounds [69594 x i64], [69594 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %entry ret void } @@ -255,11 +255,11 @@ define void @f6(i32 *%ptr, i64 %x) { ; CHECK: agfi %r15, 32768 ; CHECK: lmg %r14, %r15, 524280(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add4 = add i32 %l4, %add1 @@ -271,7 +271,7 @@ define void @f6(i32 *%ptr, i64 %x) { store volatile i32 %add5, i32 *%ptr store volatile i32 %add14, i32 *%ptr %y = alloca [69595 x i64], align 8 - %entry = getelementptr inbounds [69595 x i64]* %y, i64 0, i64 0 + %entry = getelementptr inbounds [69595 x i64], [69595 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %entry ret void } diff --git a/test/CodeGen/SystemZ/frame-09.ll b/test/CodeGen/SystemZ/frame-09.ll index 8a4f99c343a0..ead944e59f98 100644 --- a/test/CodeGen/SystemZ/frame-09.ll +++ b/test/CodeGen/SystemZ/frame-09.ll @@ -64,19 +64,19 @@ define void @f3(i32 *%ptr) { ; CHECK: st {{.*}}, 4(%r2) ; CHECK: lmg %r6, %r15, 48(%r11) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l3 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l6 = load volatile i32 *%ptr - %l7 = load volatile i32 *%ptr - %l8 = load volatile i32 *%ptr - %l9 = load volatile i32 *%ptr - %l10 = load volatile i32 *%ptr - %l12 = load volatile i32 *%ptr - %l13 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l3 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l6 = load volatile i32 , i32 *%ptr + %l7 = load volatile i32 , i32 *%ptr + %l8 = load volatile i32 , i32 *%ptr + %l9 = load volatile i32 , i32 *%ptr + %l10 = load volatile i32 , i32 *%ptr + %l12 = load volatile i32 , i32 *%ptr + %l13 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr %add0 = add i32 %l0, %l0 %add1 = add i32 %l1, %add0 %add3 = add i32 %l3, %add1 @@ -102,7 +102,7 @@ define void @f3(i32 *%ptr) { store volatile i32 %add10, i32 *%ptr store volatile i32 %add12, i32 *%ptr store volatile i32 %add13, i32 *%ptr - %final = getelementptr i32 *%ptr, i32 1 + %final = getelementptr i32, i32 *%ptr, i32 1 store volatile i32 %add14, i32 *%final ret void } @@ -124,7 +124,7 @@ define void @f4(i64 %x) { ; CHECK: lmg %r11, %r15, 524280(%r11) ; CHECK: br %r14 %y = alloca [65502 x i64], align 8 - %ptr = getelementptr inbounds [65502 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [65502 x i64], [65502 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } @@ -144,7 +144,7 @@ define void @f5(i64 %x) { ; CHECK: lmg %r11, %r15, 524280(%r11) ; CHECK: br %r14 %y = alloca [65503 x i64], align 8 - %ptr = getelementptr inbounds [65503 x i64]* %y, i64 0, i64 0 + %ptr = getelementptr inbounds [65503 x i64], [65503 x i64]* %y, i64 0, i64 0 store volatile i64 %x, i64* %ptr ret void } diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll index 58dee1da58b5..2afe6d74388b 100644 --- a/test/CodeGen/SystemZ/frame-13.ll +++ b/test/CodeGen/SystemZ/frame-13.ll @@ -34,8 +34,8 @@ define void @f1() { ; CHECK-FP: br %r14 %region1 = alloca [978 x i32], align 8 %region2 = alloca [978 x i32], align 8 - %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 1 - %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 1 + %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 1 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -54,8 +54,8 @@ define void @f2() { ; CHECK-FP: br %r14 %region1 = alloca [978 x i32], align 8 %region2 = alloca [978 x i32], align 8 - %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2 - %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2 + %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 2 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -74,8 +74,8 @@ define void @f3() { ; CHECK-FP: br %r14 %region1 = alloca [978 x i32], align 8 %region2 = alloca [978 x i32], align 8 - %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 3 - %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 3 + %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 3 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -94,8 +94,8 @@ define void @f4() { ; CHECK-FP: br %r14 %region1 = alloca [2002 x i32], align 8 %region2 = alloca [2002 x i32], align 8 - %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 1 - %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 1 + %ptr1 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region2, i64 0, i64 1 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -114,8 +114,8 @@ define void @f5() { ; CHECK-FP: br %r14 %region1 = alloca [2002 x i32], align 8 %region2 = alloca [2002 x i32], align 8 - %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 2 - %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 2 + %ptr1 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region2, i64 0, i64 2 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -134,8 +134,8 @@ define void @f6() { ; CHECK-FP: br %r14 %region1 = alloca [2002 x i32], align 8 %region2 = alloca [2002 x i32], align 8 - %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 3 - %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 3 + %ptr1 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [2002 x i32], [2002 x i32]* %region2, i64 0, i64 3 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -156,8 +156,8 @@ define void @f7() { ; CHECK-FP: br %r14 %region1 = alloca [2004 x i32], align 8 %region2 = alloca [2004 x i32], align 8 - %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 1023 - %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 1023 + %ptr1 = getelementptr inbounds [2004 x i32], [2004 x i32]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2004 x i32], [2004 x i32]* %region2, i64 0, i64 1023 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -177,8 +177,8 @@ define void @f8() { ; CHECK-FP: br %r14 %region1 = alloca [2006 x i32], align 8 %region2 = alloca [2006 x i32], align 8 - %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1023 - %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1023 + %ptr1 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region2, i64 0, i64 1023 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -198,8 +198,8 @@ define void @f9() { ; CHECK-FP: br %r14 %region1 = alloca [2006 x i32], align 8 %region2 = alloca [2006 x i32], align 8 - %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1024 - %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1024 + %ptr1 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region1, i64 0, i64 1024 + %ptr2 = getelementptr inbounds [2006 x i32], [2006 x i32]* %region2, i64 0, i64 1024 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 ret void @@ -222,15 +222,15 @@ define void @f10(i32 *%vptr) { ; CHECK-FP: mvhi 0([[REGISTER]]), 42 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11) ; CHECK-FP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i3 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i3 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr %region1 = alloca [978 x i32], align 8 %region2 = alloca [978 x i32], align 8 - %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2 - %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2 + %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 2 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 store volatile i32 %i0, i32 *%vptr @@ -254,24 +254,24 @@ define void @f11(i32 *%vptr) { ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15) ; CHECK-NOFP: lmg %r6, %r15, ; CHECK-NOFP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i3 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr - %i6 = load volatile i32 *%vptr - %i7 = load volatile i32 *%vptr - %i8 = load volatile i32 *%vptr - %i9 = load volatile i32 *%vptr - %i10 = load volatile i32 *%vptr - %i11 = load volatile i32 *%vptr - %i12 = load volatile i32 *%vptr - %i13 = load volatile i32 *%vptr - %i14 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i3 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr + %i6 = load volatile i32 , i32 *%vptr + %i7 = load volatile i32 , i32 *%vptr + %i8 = load volatile i32 , i32 *%vptr + %i9 = load volatile i32 , i32 *%vptr + %i10 = load volatile i32 , i32 *%vptr + %i11 = load volatile i32 , i32 *%vptr + %i12 = load volatile i32 , i32 *%vptr + %i13 = load volatile i32 , i32 *%vptr + %i14 = load volatile i32 , i32 *%vptr %region1 = alloca [978 x i32], align 8 %region2 = alloca [978 x i32], align 8 - %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2 - %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2 + %ptr1 = getelementptr inbounds [978 x i32], [978 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [978 x i32], [978 x i32]* %region2, i64 0, i64 2 store volatile i32 42, i32 *%ptr1 store volatile i32 42, i32 *%ptr2 store volatile i32 %i0, i32 *%vptr diff --git a/test/CodeGen/SystemZ/frame-14.ll b/test/CodeGen/SystemZ/frame-14.ll index 24169cf61f00..3c080a401648 100644 --- a/test/CodeGen/SystemZ/frame-14.ll +++ b/test/CodeGen/SystemZ/frame-14.ll @@ -33,8 +33,8 @@ define void @f1() { ; CHECK-FP: br %r14 %region1 = alloca [3912 x i8], align 8 %region2 = alloca [3912 x i8], align 8 - %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 7 - %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 7 + %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 7 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -51,8 +51,8 @@ define void @f2() { ; CHECK-FP: br %r14 %region1 = alloca [3912 x i8], align 8 %region2 = alloca [3912 x i8], align 8 - %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 8 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -72,8 +72,8 @@ define void @f3() { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 7 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 7 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 7 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -96,8 +96,8 @@ define void @f4() { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -119,8 +119,8 @@ define void @f5() { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4103 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4103 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4103 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4103 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -141,8 +141,8 @@ define void @f6() { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4104 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4104 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4104 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4104 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -166,8 +166,8 @@ define void @f7() { ; CHECK-FP: br %r14 %region1 = alloca [1048400 x i8], align 8 %region2 = alloca [1048400 x i8], align 8 - %ptr1 = getelementptr inbounds [1048400 x i8]* %region1, i64 0, i64 524287 - %ptr2 = getelementptr inbounds [1048400 x i8]* %region2, i64 0, i64 524287 + %ptr1 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region2, i64 0, i64 524287 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -189,8 +189,8 @@ define void @f8() { ; CHECK-FP: br %r14 %region1 = alloca [1048408 x i8], align 8 %region2 = alloca [1048408 x i8], align 8 - %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287 - %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287 + %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524287 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -219,8 +219,8 @@ define void @f9() { ; CHECK-FP: br %r14 %region1 = alloca [1048408 x i8], align 8 %region2 = alloca [1048408 x i8], align 8 - %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524288 - %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524288 + %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524288 + %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524288 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 ret void @@ -245,15 +245,15 @@ define void @f10(i32 *%vptr) { ; CHECK-FP: mvi 0([[REGISTER]]), 42 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11) ; CHECK-FP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i3 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i3 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 store volatile i32 %i0, i32 *%vptr @@ -278,24 +278,24 @@ define void @f11(i32 *%vptr) { ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15) ; CHECK-NOFP: lmg %r6, %r15, ; CHECK-NOFP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i3 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr - %i6 = load volatile i32 *%vptr - %i7 = load volatile i32 *%vptr - %i8 = load volatile i32 *%vptr - %i9 = load volatile i32 *%vptr - %i10 = load volatile i32 *%vptr - %i11 = load volatile i32 *%vptr - %i12 = load volatile i32 *%vptr - %i13 = load volatile i32 *%vptr - %i14 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i3 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr + %i6 = load volatile i32 , i32 *%vptr + %i7 = load volatile i32 , i32 *%vptr + %i8 = load volatile i32 , i32 *%vptr + %i9 = load volatile i32 , i32 *%vptr + %i10 = load volatile i32 , i32 *%vptr + %i11 = load volatile i32 , i32 *%vptr + %i12 = load volatile i32 , i32 *%vptr + %i13 = load volatile i32 , i32 *%vptr + %i14 = load volatile i32 , i32 *%vptr %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8 store volatile i8 42, i8 *%ptr1 store volatile i8 42, i8 *%ptr2 store volatile i32 %i0, i32 *%vptr diff --git a/test/CodeGen/SystemZ/frame-15.ll b/test/CodeGen/SystemZ/frame-15.ll index b3c95e73c1af..f81c9dc5c2c4 100644 --- a/test/CodeGen/SystemZ/frame-15.ll +++ b/test/CodeGen/SystemZ/frame-15.ll @@ -36,13 +36,13 @@ define void @f1(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [978 x float], align 8 %region2 = alloca [978 x float], align 8 - %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 1 - %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 1 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 1 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -63,13 +63,13 @@ define void @f2(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [978 x float], align 8 %region2 = alloca [978 x float], align 8 - %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2 - %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 2 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -90,13 +90,13 @@ define void @f3(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [978 x float], align 8 %region2 = alloca [978 x float], align 8 - %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 3 - %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 3 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 3 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -117,13 +117,13 @@ define void @f4(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [2002 x float], align 8 %region2 = alloca [2002 x float], align 8 - %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 1 - %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 1 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 1 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -144,13 +144,13 @@ define void @f5(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [2002 x float], align 8 %region2 = alloca [2002 x float], align 8 - %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 2 - %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 2 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 2 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -171,13 +171,13 @@ define void @f6(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [2002 x float], align 8 %region2 = alloca [2002 x float], align 8 - %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 3 - %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 3 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [2002 x float], [2002 x float]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [2002 x float], [2002 x float]* %region2, i64 0, i64 3 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -200,13 +200,13 @@ define void @f7(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [2004 x float], align 8 %region2 = alloca [2004 x float], align 8 - %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [2004 x float], [2004 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2004 x float], [2004 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 1023 - %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 1023 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [2004 x float], [2004 x float]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2004 x float], [2004 x float]* %region2, i64 0, i64 1023 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -228,13 +228,13 @@ define void @f8(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [2006 x float], align 8 %region2 = alloca [2006 x float], align 8 - %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1023 - %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1023 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 1023 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -257,13 +257,13 @@ define void @f9(double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [2006 x float], align 8 %region2 = alloca [2006 x float], align 8 - %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1024 - %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1024 - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [2006 x float], [2006 x float]* %region1, i64 0, i64 1024 + %ptr2 = getelementptr inbounds [2006 x float], [2006 x float]* %region2, i64 0, i64 1024 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -291,20 +291,20 @@ define void @f10(i32 *%vptr, double *%dst) { ; CHECK-FP: br %r14 %region1 = alloca [978 x float], align 8 %region2 = alloca [978 x float], align 8 - %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2 - %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i2 = load volatile i32 *%vptr - %i3 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr - %i14 = load volatile i32 *%vptr - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %ptr1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 2 + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i2 = load volatile i32 , i32 *%vptr + %i3 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr + %i14 = load volatile i32 , i32 *%vptr + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst @@ -334,19 +334,19 @@ define void @f11(double *%dst, i64 %index) { ; CHECK-FP: br %r14 %region1 = alloca [978 x float], align 8 %region2 = alloca [978 x float], align 8 - %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0 - %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0 + %start1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 0 call void @foo(float *%start1, float *%start2) - %elem1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2 - %elem2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2 + %elem1 = getelementptr inbounds [978 x float], [978 x float]* %region1, i64 0, i64 2 + %elem2 = getelementptr inbounds [978 x float], [978 x float]* %region2, i64 0, i64 2 %base1 = ptrtoint float *%elem1 to i64 %base2 = ptrtoint float *%elem2 to i64 %addr1 = add i64 %base1, %index %addr2 = add i64 %base2, %index %ptr1 = inttoptr i64 %addr1 to float * %ptr2 = inttoptr i64 %addr2 to float * - %float1 = load float *%ptr1 - %float2 = load float *%ptr2 + %float1 = load float , float *%ptr1 + %float2 = load float , float *%ptr2 %double1 = fpext float %float1 to double %double2 = fpext float %float2 to double store volatile double %double1, double *%dst diff --git a/test/CodeGen/SystemZ/frame-16.ll b/test/CodeGen/SystemZ/frame-16.ll index f7e2dfa35149..75da04447b3a 100644 --- a/test/CodeGen/SystemZ/frame-16.ll +++ b/test/CodeGen/SystemZ/frame-16.ll @@ -33,8 +33,8 @@ define void @f1(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [3912 x i8], align 8 %region2 = alloca [3912 x i8], align 8 - %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 7 - %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 7 + %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 7 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -51,8 +51,8 @@ define void @f2(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [3912 x i8], align 8 %region2 = alloca [3912 x i8], align 8 - %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 8 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -72,8 +72,8 @@ define void @f3(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 7 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 7 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 7 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -94,8 +94,8 @@ define void @f4(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -115,8 +115,8 @@ define void @f5(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4103 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4103 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4103 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4103 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -135,8 +135,8 @@ define void @f6(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4104 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4104 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4104 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4104 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -158,8 +158,8 @@ define void @f7(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [1048400 x i8], align 8 %region2 = alloca [1048400 x i8], align 8 - %ptr1 = getelementptr inbounds [1048400 x i8]* %region1, i64 0, i64 524287 - %ptr2 = getelementptr inbounds [1048400 x i8]* %region2, i64 0, i64 524287 + %ptr1 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region2, i64 0, i64 524287 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -179,8 +179,8 @@ define void @f8(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [1048408 x i8], align 8 %region2 = alloca [1048408 x i8], align 8 - %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287 - %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287 + %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524287 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -209,8 +209,8 @@ define void @f9(i8 %byte) { ; CHECK-FP: br %r14 %region1 = alloca [1048408 x i8], align 8 %region2 = alloca [1048408 x i8], align 8 - %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524288 - %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524288 + %ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524288 + %ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524288 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void @@ -233,14 +233,14 @@ define void @f10(i32 *%vptr, i8 %byte) { ; CHECK-FP: stc %r3, 0([[REGISTER]],%r11) ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11) ; CHECK-FP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 store volatile i32 %i0, i32 *%vptr @@ -272,23 +272,23 @@ define void @f11(i32 *%vptr, i8 %byte) { ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11) ; CHECK-FP: lmg %r6, %r15, ; CHECK-FP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr - %i6 = load volatile i32 *%vptr - %i7 = load volatile i32 *%vptr - %i8 = load volatile i32 *%vptr - %i9 = load volatile i32 *%vptr - %i10 = load volatile i32 *%vptr - %i11 = load volatile i32 *%vptr - %i12 = load volatile i32 *%vptr - %i13 = load volatile i32 *%vptr - %i14 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr + %i6 = load volatile i32 , i32 *%vptr + %i7 = load volatile i32 , i32 *%vptr + %i8 = load volatile i32 , i32 *%vptr + %i9 = load volatile i32 , i32 *%vptr + %i10 = load volatile i32 , i32 *%vptr + %i11 = load volatile i32 , i32 *%vptr + %i12 = load volatile i32 , i32 *%vptr + %i13 = load volatile i32 , i32 *%vptr + %i14 = load volatile i32 , i32 *%vptr %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 store volatile i32 %i0, i32 *%vptr @@ -323,8 +323,8 @@ define void @f12(i8 %byte, i64 %index) { %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 %index1 = add i64 %index, 8 - %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 %index1 - %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 %index1 + %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 %index1 + %ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 %index1 store volatile i8 %byte, i8 *%ptr1 store volatile i8 %byte, i8 *%ptr2 ret void diff --git a/test/CodeGen/SystemZ/frame-17.ll b/test/CodeGen/SystemZ/frame-17.ll index 97cf83dfd78e..502e541bafc1 100644 --- a/test/CodeGen/SystemZ/frame-17.ll +++ b/test/CodeGen/SystemZ/frame-17.ll @@ -1,6 +1,6 @@ ; Test spilling of FPRs. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; We need to save and restore 8 of the 16 FPRs and allocate an additional ; 4-byte spill slot, rounded to 8 bytes. The frame size should be exactly @@ -31,23 +31,23 @@ define void @f1(float *%ptr) { ; CHECK: ld %f15, 168(%r15) ; CHECK: aghi %r15, 232 ; CHECK: br %r14 - %l0 = load volatile float *%ptr - %l1 = load volatile float *%ptr - %l2 = load volatile float *%ptr - %l3 = load volatile float *%ptr - %l4 = load volatile float *%ptr - %l5 = load volatile float *%ptr - %l6 = load volatile float *%ptr - %l7 = load volatile float *%ptr - %l8 = load volatile float *%ptr - %l9 = load volatile float *%ptr - %l10 = load volatile float *%ptr - %l11 = load volatile float *%ptr - %l12 = load volatile float *%ptr - %l13 = load volatile float *%ptr - %l14 = load volatile float *%ptr - %l15 = load volatile float *%ptr - %lx = load volatile float *%ptr + %l0 = load volatile float , float *%ptr + %l1 = load volatile float , float *%ptr + %l2 = load volatile float , float *%ptr + %l3 = load volatile float , float *%ptr + %l4 = load volatile float , float *%ptr + %l5 = load volatile float , float *%ptr + %l6 = load volatile float , float *%ptr + %l7 = load volatile float , float *%ptr + %l8 = load volatile float , float *%ptr + %l9 = load volatile float , float *%ptr + %l10 = load volatile float , float *%ptr + %l11 = load volatile float , float *%ptr + %l12 = load volatile float , float *%ptr + %l13 = load volatile float , float *%ptr + %l14 = load volatile float , float *%ptr + %l15 = load volatile float , float *%ptr + %lx = load volatile float , float *%ptr store volatile float %lx, float *%ptr store volatile float %l15, float *%ptr store volatile float %l14, float *%ptr @@ -92,23 +92,23 @@ define void @f2(double *%ptr) { ; CHECK: ld %f15, 168(%r15) ; CHECK: aghi %r15, 232 ; CHECK: br %r14 - %l0 = load volatile double *%ptr - %l1 = load volatile double *%ptr - %l2 = load volatile double *%ptr - %l3 = load volatile double *%ptr - %l4 = load volatile double *%ptr - %l5 = load volatile double *%ptr - %l6 = load volatile double *%ptr - %l7 = load volatile double *%ptr - %l8 = load volatile double *%ptr - %l9 = load volatile double *%ptr - %l10 = load volatile double *%ptr - %l11 = load volatile double *%ptr - %l12 = load volatile double *%ptr - %l13 = load volatile double *%ptr - %l14 = load volatile double *%ptr - %l15 = load volatile double *%ptr - %lx = load volatile double *%ptr + %l0 = load volatile double , double *%ptr + %l1 = load volatile double , double *%ptr + %l2 = load volatile double , double *%ptr + %l3 = load volatile double , double *%ptr + %l4 = load volatile double , double *%ptr + %l5 = load volatile double , double *%ptr + %l6 = load volatile double , double *%ptr + %l7 = load volatile double , double *%ptr + %l8 = load volatile double , double *%ptr + %l9 = load volatile double , double *%ptr + %l10 = load volatile double , double *%ptr + %l11 = load volatile double , double *%ptr + %l12 = load volatile double , double *%ptr + %l13 = load volatile double , double *%ptr + %l14 = load volatile double , double *%ptr + %l15 = load volatile double , double *%ptr + %lx = load volatile double , double *%ptr store volatile double %lx, double *%ptr store volatile double %l15, double *%ptr store volatile double %l14, double *%ptr @@ -155,15 +155,15 @@ define void @f3(fp128 *%ptr) { ; CHECK: ld %f15, 176(%r15) ; CHECK: aghi %r15, 240 ; CHECK: br %r14 - %l0 = load volatile fp128 *%ptr - %l1 = load volatile fp128 *%ptr - %l4 = load volatile fp128 *%ptr - %l5 = load volatile fp128 *%ptr - %l8 = load volatile fp128 *%ptr - %l9 = load volatile fp128 *%ptr - %l12 = load volatile fp128 *%ptr - %l13 = load volatile fp128 *%ptr - %lx = load volatile fp128 *%ptr + %l0 = load volatile fp128 , fp128 *%ptr + %l1 = load volatile fp128 , fp128 *%ptr + %l4 = load volatile fp128 , fp128 *%ptr + %l5 = load volatile fp128 , fp128 *%ptr + %l8 = load volatile fp128 , fp128 *%ptr + %l9 = load volatile fp128 , fp128 *%ptr + %l12 = load volatile fp128 , fp128 *%ptr + %l13 = load volatile fp128 , fp128 *%ptr + %lx = load volatile fp128 , fp128 *%ptr store volatile fp128 %lx, fp128 *%ptr store volatile fp128 %l13, fp128 *%ptr store volatile fp128 %l12, fp128 *%ptr diff --git a/test/CodeGen/SystemZ/frame-18.ll b/test/CodeGen/SystemZ/frame-18.ll index 21dfc1238a13..0f58e437f9fd 100644 --- a/test/CodeGen/SystemZ/frame-18.ll +++ b/test/CodeGen/SystemZ/frame-18.ll @@ -16,21 +16,21 @@ define void @f1(i32 *%ptr) { ; CHECK-NOT: 160(%r15) ; CHECK: lmg %r6, %r15, 216(%r15) ; CHECK: br %r14 - %l0 = load volatile i32 *%ptr - %l1 = load volatile i32 *%ptr - %l3 = load volatile i32 *%ptr - %l4 = load volatile i32 *%ptr - %l5 = load volatile i32 *%ptr - %l6 = load volatile i32 *%ptr - %l7 = load volatile i32 *%ptr - %l8 = load volatile i32 *%ptr - %l9 = load volatile i32 *%ptr - %l10 = load volatile i32 *%ptr - %l11 = load volatile i32 *%ptr - %l12 = load volatile i32 *%ptr - %l13 = load volatile i32 *%ptr - %l14 = load volatile i32 *%ptr - %lx = load volatile i32 *%ptr + %l0 = load volatile i32 , i32 *%ptr + %l1 = load volatile i32 , i32 *%ptr + %l3 = load volatile i32 , i32 *%ptr + %l4 = load volatile i32 , i32 *%ptr + %l5 = load volatile i32 , i32 *%ptr + %l6 = load volatile i32 , i32 *%ptr + %l7 = load volatile i32 , i32 *%ptr + %l8 = load volatile i32 , i32 *%ptr + %l9 = load volatile i32 , i32 *%ptr + %l10 = load volatile i32 , i32 *%ptr + %l11 = load volatile i32 , i32 *%ptr + %l12 = load volatile i32 , i32 *%ptr + %l13 = load volatile i32 , i32 *%ptr + %l14 = load volatile i32 , i32 *%ptr + %lx = load volatile i32 , i32 *%ptr store volatile i32 %lx, i32 *%ptr store volatile i32 %l14, i32 *%ptr store volatile i32 %l13, i32 *%ptr @@ -58,21 +58,21 @@ define void @f2(i64 *%ptr) { ; CHECK: lg [[REGISTER]], 160(%r15) ; CHECK: lmg %r6, %r15, 216(%r15) ; CHECK: br %r14 - %l0 = load volatile i64 *%ptr - %l1 = load volatile i64 *%ptr - %l3 = load volatile i64 *%ptr - %l4 = load volatile i64 *%ptr - %l5 = load volatile i64 *%ptr - %l6 = load volatile i64 *%ptr - %l7 = load volatile i64 *%ptr - %l8 = load volatile i64 *%ptr - %l9 = load volatile i64 *%ptr - %l10 = load volatile i64 *%ptr - %l11 = load volatile i64 *%ptr - %l12 = load volatile i64 *%ptr - %l13 = load volatile i64 *%ptr - %l14 = load volatile i64 *%ptr - %lx = load volatile i64 *%ptr + %l0 = load volatile i64 , i64 *%ptr + %l1 = load volatile i64 , i64 *%ptr + %l3 = load volatile i64 , i64 *%ptr + %l4 = load volatile i64 , i64 *%ptr + %l5 = load volatile i64 , i64 *%ptr + %l6 = load volatile i64 , i64 *%ptr + %l7 = load volatile i64 , i64 *%ptr + %l8 = load volatile i64 , i64 *%ptr + %l9 = load volatile i64 , i64 *%ptr + %l10 = load volatile i64 , i64 *%ptr + %l11 = load volatile i64 , i64 *%ptr + %l12 = load volatile i64 , i64 *%ptr + %l13 = load volatile i64 , i64 *%ptr + %l14 = load volatile i64 , i64 *%ptr + %lx = load volatile i64 , i64 *%ptr store volatile i64 %lx, i64 *%ptr store volatile i64 %l14, i64 *%ptr store volatile i64 %l13, i64 *%ptr diff --git a/test/CodeGen/SystemZ/frame-19.ll b/test/CodeGen/SystemZ/frame-19.ll new file mode 100644 index 000000000000..f6e327c3ae39 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-19.ll @@ -0,0 +1,314 @@ +; Test spilling of vector registers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; We need to allocate a 16-byte spill slot and save the 8 call-saved FPRs. +; The frame size should be exactly 160 + 16 + 8 * 8 = 240. +define void @f1(<16 x i8> *%ptr) { +; CHECK-LABEL: f1: +; CHECK: aghi %r15, -240 +; CHECK-DAG: std %f8, +; CHECK-DAG: std %f9, +; CHECK-DAG: std %f10, +; CHECK-DAG: std %f11, +; CHECK-DAG: std %f12, +; CHECK-DAG: std %f13, +; CHECK-DAG: std %f14, +; CHECK-DAG: std %f15, +; CHECK: vst {{%v[0-9]+}}, 160(%r15) +; CHECK: vl {{%v[0-9]+}}, 160(%r15) +; CHECK-DAG: ld %f8, +; CHECK-DAG: ld %f9, +; CHECK-DAG: ld %f10, +; CHECK-DAG: ld %f11, +; CHECK-DAG: ld %f12, +; CHECK-DAG: ld %f13, +; CHECK-DAG: ld %f14, +; CHECK-DAG: ld %f15, +; CHECK: aghi %r15, 240 +; CHECK: br %r14 + %v0 = load volatile <16 x i8>, <16 x i8> *%ptr + %v1 = load volatile <16 x i8>, <16 x i8> *%ptr + %v2 = load volatile <16 x i8>, <16 x i8> *%ptr + %v3 = load volatile <16 x i8>, <16 x i8> *%ptr + %v4 = load volatile <16 x i8>, <16 x i8> *%ptr + %v5 = load volatile <16 x i8>, <16 x i8> *%ptr + %v6 = load volatile <16 x i8>, <16 x i8> *%ptr + %v7 = load volatile <16 x i8>, <16 x i8> *%ptr + %v8 = load volatile <16 x i8>, <16 x i8> *%ptr + %v9 = load volatile <16 x i8>, <16 x i8> *%ptr + %v10 = load volatile <16 x i8>, <16 x i8> *%ptr + %v11 = load volatile <16 x i8>, <16 x i8> *%ptr + %v12 = load volatile <16 x i8>, <16 x i8> *%ptr + %v13 = load volatile <16 x i8>, <16 x i8> *%ptr + %v14 = load volatile <16 x i8>, <16 x i8> *%ptr + %v15 = load volatile <16 x i8>, <16 x i8> *%ptr + %v16 = load volatile <16 x i8>, <16 x i8> *%ptr + %v17 = load volatile <16 x i8>, <16 x i8> *%ptr + %v18 = load volatile <16 x i8>, <16 x i8> *%ptr + %v19 = load volatile <16 x i8>, <16 x i8> *%ptr + %v20 = load volatile <16 x i8>, <16 x i8> *%ptr + %v21 = load volatile <16 x i8>, <16 x i8> *%ptr + %v22 = load volatile <16 x i8>, <16 x i8> *%ptr + %v23 = load volatile <16 x i8>, <16 x i8> *%ptr + %v24 = load volatile <16 x i8>, <16 x i8> *%ptr + %v25 = load volatile <16 x i8>, <16 x i8> *%ptr + %v26 = load volatile <16 x i8>, <16 x i8> *%ptr + %v27 = load volatile <16 x i8>, <16 x i8> *%ptr + %v28 = load volatile <16 x i8>, <16 x i8> *%ptr + %v29 = load volatile <16 x i8>, <16 x i8> *%ptr + %v30 = load volatile <16 x i8>, <16 x i8> *%ptr + %v31 = load volatile <16 x i8>, <16 x i8> *%ptr + %vx = load volatile <16 x i8>, <16 x i8> *%ptr + store volatile <16 x i8> %vx, <16 x i8> *%ptr + store volatile <16 x i8> %v31, <16 x i8> *%ptr + store volatile <16 x i8> %v30, <16 x i8> *%ptr + store volatile <16 x i8> %v29, <16 x i8> *%ptr + store volatile <16 x i8> %v28, <16 x i8> *%ptr + store volatile <16 x i8> %v27, <16 x i8> *%ptr + store volatile <16 x i8> %v26, <16 x i8> *%ptr + store volatile <16 x i8> %v25, <16 x i8> *%ptr + store volatile <16 x i8> %v24, <16 x i8> *%ptr + store volatile <16 x i8> %v23, <16 x i8> *%ptr + store volatile <16 x i8> %v22, <16 x i8> *%ptr + store volatile <16 x i8> %v21, <16 x i8> *%ptr + store volatile <16 x i8> %v20, <16 x i8> *%ptr + store volatile <16 x i8> %v19, <16 x i8> *%ptr + store volatile <16 x i8> %v18, <16 x i8> *%ptr + store volatile <16 x i8> %v17, <16 x i8> *%ptr + store volatile <16 x i8> %v16, <16 x i8> *%ptr + store volatile <16 x i8> %v15, <16 x i8> *%ptr + store volatile <16 x i8> %v14, <16 x i8> *%ptr + store volatile <16 x i8> %v13, <16 x i8> *%ptr + store volatile <16 x i8> %v12, <16 x i8> *%ptr + store volatile <16 x i8> %v11, <16 x i8> *%ptr + store volatile <16 x i8> %v10, <16 x i8> *%ptr + store volatile <16 x i8> %v9, <16 x i8> *%ptr + store volatile <16 x i8> %v8, <16 x i8> *%ptr + store volatile <16 x i8> %v7, <16 x i8> *%ptr + store volatile <16 x i8> %v6, <16 x i8> *%ptr + store volatile <16 x i8> %v5, <16 x i8> *%ptr + store volatile <16 x i8> %v4, <16 x i8> *%ptr + store volatile <16 x i8> %v3, <16 x i8> *%ptr + store volatile <16 x i8> %v2, <16 x i8> *%ptr + store volatile <16 x i8> %v1, <16 x i8> *%ptr + store volatile <16 x i8> %v0, <16 x i8> *%ptr + ret void +} + +; Like f1, but no 16-byte slot should be needed. +define void @f2(<16 x i8> *%ptr) { +; CHECK-LABEL: f2: +; CHECK: aghi %r15, -224 +; CHECK-DAG: std %f8, +; CHECK-DAG: std %f9, +; CHECK-DAG: std %f10, +; CHECK-DAG: std %f11, +; CHECK-DAG: std %f12, +; CHECK-DAG: std %f13, +; CHECK-DAG: std %f14, +; CHECK-DAG: std %f15, +; CHECK-NOT: vst {{.*}}(%r15) +; CHECK-NOT: vl {{.*}}(%r15) +; CHECK-DAG: ld %f8, +; CHECK-DAG: ld %f9, +; CHECK-DAG: ld %f10, +; CHECK-DAG: ld %f11, +; CHECK-DAG: ld %f12, +; CHECK-DAG: ld %f13, +; CHECK-DAG: ld %f14, +; CHECK-DAG: ld %f15, +; CHECK: aghi %r15, 224 +; CHECK: br %r14 + %v0 = load volatile <16 x i8>, <16 x i8> *%ptr + %v1 = load volatile <16 x i8>, <16 x i8> *%ptr + %v2 = load volatile <16 x i8>, <16 x i8> *%ptr + %v3 = load volatile <16 x i8>, <16 x i8> *%ptr + %v4 = load volatile <16 x i8>, <16 x i8> *%ptr + %v5 = load volatile <16 x i8>, <16 x i8> *%ptr + %v6 = load volatile <16 x i8>, <16 x i8> *%ptr + %v7 = load volatile <16 x i8>, <16 x i8> *%ptr + %v8 = load volatile <16 x i8>, <16 x i8> *%ptr + %v9 = load volatile <16 x i8>, <16 x i8> *%ptr + %v10 = load volatile <16 x i8>, <16 x i8> *%ptr + %v11 = load volatile <16 x i8>, <16 x i8> *%ptr + %v12 = load volatile <16 x i8>, <16 x i8> *%ptr + %v13 = load volatile <16 x i8>, <16 x i8> *%ptr + %v14 = load volatile <16 x i8>, <16 x i8> *%ptr + %v15 = load volatile <16 x i8>, <16 x i8> *%ptr + %v16 = load volatile <16 x i8>, <16 x i8> *%ptr + %v17 = load volatile <16 x i8>, <16 x i8> *%ptr + %v18 = load volatile <16 x i8>, <16 x i8> *%ptr + %v19 = load volatile <16 x i8>, <16 x i8> *%ptr + %v20 = load volatile <16 x i8>, <16 x i8> *%ptr + %v21 = load volatile <16 x i8>, <16 x i8> *%ptr + %v22 = load volatile <16 x i8>, <16 x i8> *%ptr + %v23 = load volatile <16 x i8>, <16 x i8> *%ptr + %v24 = load volatile <16 x i8>, <16 x i8> *%ptr + %v25 = load volatile <16 x i8>, <16 x i8> *%ptr + %v26 = load volatile <16 x i8>, <16 x i8> *%ptr + %v27 = load volatile <16 x i8>, <16 x i8> *%ptr + %v28 = load volatile <16 x i8>, <16 x i8> *%ptr + %v29 = load volatile <16 x i8>, <16 x i8> *%ptr + %v30 = load volatile <16 x i8>, <16 x i8> *%ptr + %v31 = load volatile <16 x i8>, <16 x i8> *%ptr + store volatile <16 x i8> %v31, <16 x i8> *%ptr + store volatile <16 x i8> %v30, <16 x i8> *%ptr + store volatile <16 x i8> %v29, <16 x i8> *%ptr + store volatile <16 x i8> %v28, <16 x i8> *%ptr + store volatile <16 x i8> %v27, <16 x i8> *%ptr + store volatile <16 x i8> %v26, <16 x i8> *%ptr + store volatile <16 x i8> %v25, <16 x i8> *%ptr + store volatile <16 x i8> %v24, <16 x i8> *%ptr + store volatile <16 x i8> %v23, <16 x i8> *%ptr + store volatile <16 x i8> %v22, <16 x i8> *%ptr + store volatile <16 x i8> %v21, <16 x i8> *%ptr + store volatile <16 x i8> %v20, <16 x i8> *%ptr + store volatile <16 x i8> %v19, <16 x i8> *%ptr + store volatile <16 x i8> %v18, <16 x i8> *%ptr + store volatile <16 x i8> %v17, <16 x i8> *%ptr + store volatile <16 x i8> %v16, <16 x i8> *%ptr + store volatile <16 x i8> %v15, <16 x i8> *%ptr + store volatile <16 x i8> %v14, <16 x i8> *%ptr + store volatile <16 x i8> %v13, <16 x i8> *%ptr + store volatile <16 x i8> %v12, <16 x i8> *%ptr + store volatile <16 x i8> %v11, <16 x i8> *%ptr + store volatile <16 x i8> %v10, <16 x i8> *%ptr + store volatile <16 x i8> %v9, <16 x i8> *%ptr + store volatile <16 x i8> %v8, <16 x i8> *%ptr + store volatile <16 x i8> %v7, <16 x i8> *%ptr + store volatile <16 x i8> %v6, <16 x i8> *%ptr + store volatile <16 x i8> %v5, <16 x i8> *%ptr + store volatile <16 x i8> %v4, <16 x i8> *%ptr + store volatile <16 x i8> %v3, <16 x i8> *%ptr + store volatile <16 x i8> %v2, <16 x i8> *%ptr + store volatile <16 x i8> %v1, <16 x i8> *%ptr + store volatile <16 x i8> %v0, <16 x i8> *%ptr + ret void +} + +; Like f2, but only %f8 should be saved. +define void @f3(<16 x i8> *%ptr) { +; CHECK-LABEL: f3: +; CHECK: aghi %r15, -168 +; CHECK-DAG: std %f8, +; CHECK-NOT: vst {{.*}}(%r15) +; CHECK-NOT: vl {{.*}}(%r15) +; CHECK-NOT: %v9 +; CHECK-NOT: %v10 +; CHECK-NOT: %v11 +; CHECK-NOT: %v12 +; CHECK-NOT: %v13 +; CHECK-NOT: %v14 +; CHECK-NOT: %v15 +; CHECK-DAG: ld %f8, +; CHECK: aghi %r15, 168 +; CHECK: br %r14 + %v0 = load volatile <16 x i8>, <16 x i8> *%ptr + %v1 = load volatile <16 x i8>, <16 x i8> *%ptr + %v2 = load volatile <16 x i8>, <16 x i8> *%ptr + %v3 = load volatile <16 x i8>, <16 x i8> *%ptr + %v4 = load volatile <16 x i8>, <16 x i8> *%ptr + %v5 = load volatile <16 x i8>, <16 x i8> *%ptr + %v6 = load volatile <16 x i8>, <16 x i8> *%ptr + %v7 = load volatile <16 x i8>, <16 x i8> *%ptr + %v8 = load volatile <16 x i8>, <16 x i8> *%ptr + %v16 = load volatile <16 x i8>, <16 x i8> *%ptr + %v17 = load volatile <16 x i8>, <16 x i8> *%ptr + %v18 = load volatile <16 x i8>, <16 x i8> *%ptr + %v19 = load volatile <16 x i8>, <16 x i8> *%ptr + %v20 = load volatile <16 x i8>, <16 x i8> *%ptr + %v21 = load volatile <16 x i8>, <16 x i8> *%ptr + %v22 = load volatile <16 x i8>, <16 x i8> *%ptr + %v23 = load volatile <16 x i8>, <16 x i8> *%ptr + %v24 = load volatile <16 x i8>, <16 x i8> *%ptr + %v25 = load volatile <16 x i8>, <16 x i8> *%ptr + %v26 = load volatile <16 x i8>, <16 x i8> *%ptr + %v27 = load volatile <16 x i8>, <16 x i8> *%ptr + %v28 = load volatile <16 x i8>, <16 x i8> *%ptr + %v29 = load volatile <16 x i8>, <16 x i8> *%ptr + %v30 = load volatile <16 x i8>, <16 x i8> *%ptr + %v31 = load volatile <16 x i8>, <16 x i8> *%ptr + store volatile <16 x i8> %v31, <16 x i8> *%ptr + store volatile <16 x i8> %v30, <16 x i8> *%ptr + store volatile <16 x i8> %v29, <16 x i8> *%ptr + store volatile <16 x i8> %v28, <16 x i8> *%ptr + store volatile <16 x i8> %v27, <16 x i8> *%ptr + store volatile <16 x i8> %v26, <16 x i8> *%ptr + store volatile <16 x i8> %v25, <16 x i8> *%ptr + store volatile <16 x i8> %v24, <16 x i8> *%ptr + store volatile <16 x i8> %v23, <16 x i8> *%ptr + store volatile <16 x i8> %v22, <16 x i8> *%ptr + store volatile <16 x i8> %v21, <16 x i8> *%ptr + store volatile <16 x i8> %v20, <16 x i8> *%ptr + store volatile <16 x i8> %v19, <16 x i8> *%ptr + store volatile <16 x i8> %v18, <16 x i8> *%ptr + store volatile <16 x i8> %v17, <16 x i8> *%ptr + store volatile <16 x i8> %v16, <16 x i8> *%ptr + store volatile <16 x i8> %v8, <16 x i8> *%ptr + store volatile <16 x i8> %v7, <16 x i8> *%ptr + store volatile <16 x i8> %v6, <16 x i8> *%ptr + store volatile <16 x i8> %v5, <16 x i8> *%ptr + store volatile <16 x i8> %v4, <16 x i8> *%ptr + store volatile <16 x i8> %v3, <16 x i8> *%ptr + store volatile <16 x i8> %v2, <16 x i8> *%ptr + store volatile <16 x i8> %v1, <16 x i8> *%ptr + store volatile <16 x i8> %v0, <16 x i8> *%ptr + ret void +} + +; Like f2, but no registers should be saved. +define void @f4(<16 x i8> *%ptr) { +; CHECK-LABEL: f4: +; CHECK-NOT: %r15 +; CHECK: br %r14 + %v0 = load volatile <16 x i8>, <16 x i8> *%ptr + %v1 = load volatile <16 x i8>, <16 x i8> *%ptr + %v2 = load volatile <16 x i8>, <16 x i8> *%ptr + %v3 = load volatile <16 x i8>, <16 x i8> *%ptr + %v4 = load volatile <16 x i8>, <16 x i8> *%ptr + %v5 = load volatile <16 x i8>, <16 x i8> *%ptr + %v6 = load volatile <16 x i8>, <16 x i8> *%ptr + %v7 = load volatile <16 x i8>, <16 x i8> *%ptr + %v16 = load volatile <16 x i8>, <16 x i8> *%ptr + %v17 = load volatile <16 x i8>, <16 x i8> *%ptr + %v18 = load volatile <16 x i8>, <16 x i8> *%ptr + %v19 = load volatile <16 x i8>, <16 x i8> *%ptr + %v20 = load volatile <16 x i8>, <16 x i8> *%ptr + %v21 = load volatile <16 x i8>, <16 x i8> *%ptr + %v22 = load volatile <16 x i8>, <16 x i8> *%ptr + %v23 = load volatile <16 x i8>, <16 x i8> *%ptr + %v24 = load volatile <16 x i8>, <16 x i8> *%ptr + %v25 = load volatile <16 x i8>, <16 x i8> *%ptr + %v26 = load volatile <16 x i8>, <16 x i8> *%ptr + %v27 = load volatile <16 x i8>, <16 x i8> *%ptr + %v28 = load volatile <16 x i8>, <16 x i8> *%ptr + %v29 = load volatile <16 x i8>, <16 x i8> *%ptr + %v30 = load volatile <16 x i8>, <16 x i8> *%ptr + %v31 = load volatile <16 x i8>, <16 x i8> *%ptr + store volatile <16 x i8> %v31, <16 x i8> *%ptr + store volatile <16 x i8> %v30, <16 x i8> *%ptr + store volatile <16 x i8> %v29, <16 x i8> *%ptr + store volatile <16 x i8> %v28, <16 x i8> *%ptr + store volatile <16 x i8> %v27, <16 x i8> *%ptr + store volatile <16 x i8> %v26, <16 x i8> *%ptr + store volatile <16 x i8> %v25, <16 x i8> *%ptr + store volatile <16 x i8> %v24, <16 x i8> *%ptr + store volatile <16 x i8> %v23, <16 x i8> *%ptr + store volatile <16 x i8> %v22, <16 x i8> *%ptr + store volatile <16 x i8> %v21, <16 x i8> *%ptr + store volatile <16 x i8> %v20, <16 x i8> *%ptr + store volatile <16 x i8> %v19, <16 x i8> *%ptr + store volatile <16 x i8> %v18, <16 x i8> *%ptr + store volatile <16 x i8> %v17, <16 x i8> *%ptr + store volatile <16 x i8> %v16, <16 x i8> *%ptr + store volatile <16 x i8> %v7, <16 x i8> *%ptr + store volatile <16 x i8> %v6, <16 x i8> *%ptr + store volatile <16 x i8> %v5, <16 x i8> *%ptr + store volatile <16 x i8> %v4, <16 x i8> *%ptr + store volatile <16 x i8> %v3, <16 x i8> *%ptr + store volatile <16 x i8> %v2, <16 x i8> *%ptr + store volatile <16 x i8> %v1, <16 x i8> *%ptr + store volatile <16 x i8> %v0, <16 x i8> *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-20.ll b/test/CodeGen/SystemZ/frame-20.ll new file mode 100644 index 000000000000..8d601c6f6d51 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-20.ll @@ -0,0 +1,445 @@ +; Like frame-03.ll, but for z13. In this case we have 16 more registers +; available. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; This function should require all FPRs, but no other spill slots. +; We need to save and restore 8 of the 16 FPRs, so the frame size +; should be exactly 160 + 8 * 8 = 224. The CFA offset is 160 +; (the caller-allocated part of the frame) + 224. +define void @f1(double *%ptr) { +; CHECK-LABEL: f1: +; CHECK: aghi %r15, -224 +; CHECK: .cfi_def_cfa_offset 384 +; CHECK: std %f8, 216(%r15) +; CHECK: std %f9, 208(%r15) +; CHECK: std %f10, 200(%r15) +; CHECK: std %f11, 192(%r15) +; CHECK: std %f12, 184(%r15) +; CHECK: std %f13, 176(%r15) +; CHECK: std %f14, 168(%r15) +; CHECK: std %f15, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f13, -208 +; CHECK: .cfi_offset %f14, -216 +; CHECK: .cfi_offset %f15, -224 +; CHECK-DAG: ld %f0, 0(%r2) +; CHECK-DAG: ld %f7, 0(%r2) +; CHECK-DAG: ld %f8, 0(%r2) +; CHECK-DAG: ld %f15, 0(%r2) +; CHECK-DAG: vlrepg %v16, 0(%r2) +; CHECK-DAG: vlrepg %v23, 0(%r2) +; CHECK-DAG: vlrepg %v24, 0(%r2) +; CHECK-DAG: vlrepg %v31, 0(%r2) +; CHECK: ld %f8, 216(%r15) +; CHECK: ld %f9, 208(%r15) +; CHECK: ld %f10, 200(%r15) +; CHECK: ld %f11, 192(%r15) +; CHECK: ld %f12, 184(%r15) +; CHECK: ld %f13, 176(%r15) +; CHECK: ld %f14, 168(%r15) +; CHECK: ld %f15, 160(%r15) +; CHECK: aghi %r15, 224 +; CHECK: br %r14 + %l0 = load volatile double, double *%ptr + %l1 = load volatile double, double *%ptr + %l2 = load volatile double, double *%ptr + %l3 = load volatile double, double *%ptr + %l4 = load volatile double, double *%ptr + %l5 = load volatile double, double *%ptr + %l6 = load volatile double, double *%ptr + %l7 = load volatile double, double *%ptr + %l8 = load volatile double, double *%ptr + %l9 = load volatile double, double *%ptr + %l10 = load volatile double, double *%ptr + %l11 = load volatile double, double *%ptr + %l12 = load volatile double, double *%ptr + %l13 = load volatile double, double *%ptr + %l14 = load volatile double, double *%ptr + %l15 = load volatile double, double *%ptr + %l16 = load volatile double, double *%ptr + %l17 = load volatile double, double *%ptr + %l18 = load volatile double, double *%ptr + %l19 = load volatile double, double *%ptr + %l20 = load volatile double, double *%ptr + %l21 = load volatile double, double *%ptr + %l22 = load volatile double, double *%ptr + %l23 = load volatile double, double *%ptr + %l24 = load volatile double, double *%ptr + %l25 = load volatile double, double *%ptr + %l26 = load volatile double, double *%ptr + %l27 = load volatile double, double *%ptr + %l28 = load volatile double, double *%ptr + %l29 = load volatile double, double *%ptr + %l30 = load volatile double, double *%ptr + %l31 = load volatile double, double *%ptr + %acc0 = fsub double %l0, %l0 + %acc1 = fsub double %l1, %acc0 + %acc2 = fsub double %l2, %acc1 + %acc3 = fsub double %l3, %acc2 + %acc4 = fsub double %l4, %acc3 + %acc5 = fsub double %l5, %acc4 + %acc6 = fsub double %l6, %acc5 + %acc7 = fsub double %l7, %acc6 + %acc8 = fsub double %l8, %acc7 + %acc9 = fsub double %l9, %acc8 + %acc10 = fsub double %l10, %acc9 + %acc11 = fsub double %l11, %acc10 + %acc12 = fsub double %l12, %acc11 + %acc13 = fsub double %l13, %acc12 + %acc14 = fsub double %l14, %acc13 + %acc15 = fsub double %l15, %acc14 + %acc16 = fsub double %l16, %acc15 + %acc17 = fsub double %l17, %acc16 + %acc18 = fsub double %l18, %acc17 + %acc19 = fsub double %l19, %acc18 + %acc20 = fsub double %l20, %acc19 + %acc21 = fsub double %l21, %acc20 + %acc22 = fsub double %l22, %acc21 + %acc23 = fsub double %l23, %acc22 + %acc24 = fsub double %l24, %acc23 + %acc25 = fsub double %l25, %acc24 + %acc26 = fsub double %l26, %acc25 + %acc27 = fsub double %l27, %acc26 + %acc28 = fsub double %l28, %acc27 + %acc29 = fsub double %l29, %acc28 + %acc30 = fsub double %l30, %acc29 + %acc31 = fsub double %l31, %acc30 + store volatile double %acc0, double *%ptr + store volatile double %acc1, double *%ptr + store volatile double %acc2, double *%ptr + store volatile double %acc3, double *%ptr + store volatile double %acc4, double *%ptr + store volatile double %acc5, double *%ptr + store volatile double %acc6, double *%ptr + store volatile double %acc7, double *%ptr + store volatile double %acc8, double *%ptr + store volatile double %acc9, double *%ptr + store volatile double %acc10, double *%ptr + store volatile double %acc11, double *%ptr + store volatile double %acc12, double *%ptr + store volatile double %acc13, double *%ptr + store volatile double %acc14, double *%ptr + store volatile double %acc15, double *%ptr + store volatile double %acc16, double *%ptr + store volatile double %acc17, double *%ptr + store volatile double %acc18, double *%ptr + store volatile double %acc19, double *%ptr + store volatile double %acc20, double *%ptr + store volatile double %acc21, double *%ptr + store volatile double %acc22, double *%ptr + store volatile double %acc23, double *%ptr + store volatile double %acc24, double *%ptr + store volatile double %acc25, double *%ptr + store volatile double %acc26, double *%ptr + store volatile double %acc27, double *%ptr + store volatile double %acc28, double *%ptr + store volatile double %acc29, double *%ptr + store volatile double %acc30, double *%ptr + store volatile double %acc31, double *%ptr + ret void +} + +; Like f1, but requires one fewer FPR. We allocate in numerical order, +; so %f15 is the one that gets dropped. +define void @f2(double *%ptr) { +; CHECK-LABEL: f2: +; CHECK: aghi %r15, -216 +; CHECK: .cfi_def_cfa_offset 376 +; CHECK: std %f8, 208(%r15) +; CHECK: std %f9, 200(%r15) +; CHECK: std %f10, 192(%r15) +; CHECK: std %f11, 184(%r15) +; CHECK: std %f12, 176(%r15) +; CHECK: std %f13, 168(%r15) +; CHECK: std %f14, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f13, -208 +; CHECK: .cfi_offset %f14, -216 +; CHECK-NOT: %v15 +; CHECK-NOT: %f15 +; CHECK: ld %f8, 208(%r15) +; CHECK: ld %f9, 200(%r15) +; CHECK: ld %f10, 192(%r15) +; CHECK: ld %f11, 184(%r15) +; CHECK: ld %f12, 176(%r15) +; CHECK: ld %f13, 168(%r15) +; CHECK: ld %f14, 160(%r15) +; CHECK: aghi %r15, 216 +; CHECK: br %r14 + %l0 = load volatile double, double *%ptr + %l1 = load volatile double, double *%ptr + %l2 = load volatile double, double *%ptr + %l3 = load volatile double, double *%ptr + %l4 = load volatile double, double *%ptr + %l5 = load volatile double, double *%ptr + %l6 = load volatile double, double *%ptr + %l7 = load volatile double, double *%ptr + %l8 = load volatile double, double *%ptr + %l9 = load volatile double, double *%ptr + %l10 = load volatile double, double *%ptr + %l11 = load volatile double, double *%ptr + %l12 = load volatile double, double *%ptr + %l13 = load volatile double, double *%ptr + %l14 = load volatile double, double *%ptr + %l16 = load volatile double, double *%ptr + %l17 = load volatile double, double *%ptr + %l18 = load volatile double, double *%ptr + %l19 = load volatile double, double *%ptr + %l20 = load volatile double, double *%ptr + %l21 = load volatile double, double *%ptr + %l22 = load volatile double, double *%ptr + %l23 = load volatile double, double *%ptr + %l24 = load volatile double, double *%ptr + %l25 = load volatile double, double *%ptr + %l26 = load volatile double, double *%ptr + %l27 = load volatile double, double *%ptr + %l28 = load volatile double, double *%ptr + %l29 = load volatile double, double *%ptr + %l30 = load volatile double, double *%ptr + %l31 = load volatile double, double *%ptr + %acc0 = fsub double %l0, %l0 + %acc1 = fsub double %l1, %acc0 + %acc2 = fsub double %l2, %acc1 + %acc3 = fsub double %l3, %acc2 + %acc4 = fsub double %l4, %acc3 + %acc5 = fsub double %l5, %acc4 + %acc6 = fsub double %l6, %acc5 + %acc7 = fsub double %l7, %acc6 + %acc8 = fsub double %l8, %acc7 + %acc9 = fsub double %l9, %acc8 + %acc10 = fsub double %l10, %acc9 + %acc11 = fsub double %l11, %acc10 + %acc12 = fsub double %l12, %acc11 + %acc13 = fsub double %l13, %acc12 + %acc14 = fsub double %l14, %acc13 + %acc16 = fsub double %l16, %acc14 + %acc17 = fsub double %l17, %acc16 + %acc18 = fsub double %l18, %acc17 + %acc19 = fsub double %l19, %acc18 + %acc20 = fsub double %l20, %acc19 + %acc21 = fsub double %l21, %acc20 + %acc22 = fsub double %l22, %acc21 + %acc23 = fsub double %l23, %acc22 + %acc24 = fsub double %l24, %acc23 + %acc25 = fsub double %l25, %acc24 + %acc26 = fsub double %l26, %acc25 + %acc27 = fsub double %l27, %acc26 + %acc28 = fsub double %l28, %acc27 + %acc29 = fsub double %l29, %acc28 + %acc30 = fsub double %l30, %acc29 + %acc31 = fsub double %l31, %acc30 + store volatile double %acc0, double *%ptr + store volatile double %acc1, double *%ptr + store volatile double %acc2, double *%ptr + store volatile double %acc3, double *%ptr + store volatile double %acc4, double *%ptr + store volatile double %acc5, double *%ptr + store volatile double %acc6, double *%ptr + store volatile double %acc7, double *%ptr + store volatile double %acc8, double *%ptr + store volatile double %acc9, double *%ptr + store volatile double %acc10, double *%ptr + store volatile double %acc11, double *%ptr + store volatile double %acc12, double *%ptr + store volatile double %acc13, double *%ptr + store volatile double %acc14, double *%ptr + store volatile double %acc16, double *%ptr + store volatile double %acc17, double *%ptr + store volatile double %acc18, double *%ptr + store volatile double %acc19, double *%ptr + store volatile double %acc20, double *%ptr + store volatile double %acc21, double *%ptr + store volatile double %acc22, double *%ptr + store volatile double %acc23, double *%ptr + store volatile double %acc24, double *%ptr + store volatile double %acc25, double *%ptr + store volatile double %acc26, double *%ptr + store volatile double %acc27, double *%ptr + store volatile double %acc28, double *%ptr + store volatile double %acc29, double *%ptr + store volatile double %acc30, double *%ptr + store volatile double %acc31, double *%ptr + ret void +} + +; Like f1, but should require only one call-saved FPR. +define void @f3(double *%ptr) { +; CHECK-LABEL: f3: +; CHECK: aghi %r15, -168 +; CHECK: .cfi_def_cfa_offset 328 +; CHECK: std %f8, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK-NOT: {{%[fv]9}} +; CHECK-NOT: {{%[fv]1[0-5]}} +; CHECK: ld %f8, 160(%r15) +; CHECK: aghi %r15, 168 +; CHECK: br %r14 + %l0 = load volatile double, double *%ptr + %l1 = load volatile double, double *%ptr + %l2 = load volatile double, double *%ptr + %l3 = load volatile double, double *%ptr + %l4 = load volatile double, double *%ptr + %l5 = load volatile double, double *%ptr + %l6 = load volatile double, double *%ptr + %l7 = load volatile double, double *%ptr + %l8 = load volatile double, double *%ptr + %l16 = load volatile double, double *%ptr + %l17 = load volatile double, double *%ptr + %l18 = load volatile double, double *%ptr + %l19 = load volatile double, double *%ptr + %l20 = load volatile double, double *%ptr + %l21 = load volatile double, double *%ptr + %l22 = load volatile double, double *%ptr + %l23 = load volatile double, double *%ptr + %l24 = load volatile double, double *%ptr + %l25 = load volatile double, double *%ptr + %l26 = load volatile double, double *%ptr + %l27 = load volatile double, double *%ptr + %l28 = load volatile double, double *%ptr + %l29 = load volatile double, double *%ptr + %l30 = load volatile double, double *%ptr + %l31 = load volatile double, double *%ptr + %acc0 = fsub double %l0, %l0 + %acc1 = fsub double %l1, %acc0 + %acc2 = fsub double %l2, %acc1 + %acc3 = fsub double %l3, %acc2 + %acc4 = fsub double %l4, %acc3 + %acc5 = fsub double %l5, %acc4 + %acc6 = fsub double %l6, %acc5 + %acc7 = fsub double %l7, %acc6 + %acc8 = fsub double %l8, %acc7 + %acc16 = fsub double %l16, %acc8 + %acc17 = fsub double %l17, %acc16 + %acc18 = fsub double %l18, %acc17 + %acc19 = fsub double %l19, %acc18 + %acc20 = fsub double %l20, %acc19 + %acc21 = fsub double %l21, %acc20 + %acc22 = fsub double %l22, %acc21 + %acc23 = fsub double %l23, %acc22 + %acc24 = fsub double %l24, %acc23 + %acc25 = fsub double %l25, %acc24 + %acc26 = fsub double %l26, %acc25 + %acc27 = fsub double %l27, %acc26 + %acc28 = fsub double %l28, %acc27 + %acc29 = fsub double %l29, %acc28 + %acc30 = fsub double %l30, %acc29 + %acc31 = fsub double %l31, %acc30 + store volatile double %acc0, double *%ptr + store volatile double %acc1, double *%ptr + store volatile double %acc2, double *%ptr + store volatile double %acc3, double *%ptr + store volatile double %acc4, double *%ptr + store volatile double %acc5, double *%ptr + store volatile double %acc6, double *%ptr + store volatile double %acc7, double *%ptr + store volatile double %acc8, double *%ptr + store volatile double %acc16, double *%ptr + store volatile double %acc17, double *%ptr + store volatile double %acc18, double *%ptr + store volatile double %acc19, double *%ptr + store volatile double %acc20, double *%ptr + store volatile double %acc21, double *%ptr + store volatile double %acc22, double *%ptr + store volatile double %acc23, double *%ptr + store volatile double %acc24, double *%ptr + store volatile double %acc25, double *%ptr + store volatile double %acc26, double *%ptr + store volatile double %acc27, double *%ptr + store volatile double %acc28, double *%ptr + store volatile double %acc29, double *%ptr + store volatile double %acc30, double *%ptr + store volatile double %acc31, double *%ptr + ret void +} + +; This function should use all call-clobbered FPRs and vector registers +; but no call-saved ones. It shouldn't need to create a frame. +define void @f4(double *%ptr) { +; CHECK-LABEL: f4: +; CHECK-NOT: %r15 +; CHECK-NOT: {{%[fv][89]}} +; CHECK-NOT: {{%[fv]1[0-5]}} +; CHECK: br %r14 + %l0 = load volatile double, double *%ptr + %l1 = load volatile double, double *%ptr + %l2 = load volatile double, double *%ptr + %l3 = load volatile double, double *%ptr + %l4 = load volatile double, double *%ptr + %l5 = load volatile double, double *%ptr + %l6 = load volatile double, double *%ptr + %l7 = load volatile double, double *%ptr + %l16 = load volatile double, double *%ptr + %l17 = load volatile double, double *%ptr + %l18 = load volatile double, double *%ptr + %l19 = load volatile double, double *%ptr + %l20 = load volatile double, double *%ptr + %l21 = load volatile double, double *%ptr + %l22 = load volatile double, double *%ptr + %l23 = load volatile double, double *%ptr + %l24 = load volatile double, double *%ptr + %l25 = load volatile double, double *%ptr + %l26 = load volatile double, double *%ptr + %l27 = load volatile double, double *%ptr + %l28 = load volatile double, double *%ptr + %l29 = load volatile double, double *%ptr + %l30 = load volatile double, double *%ptr + %l31 = load volatile double, double *%ptr + %acc0 = fsub double %l0, %l0 + %acc1 = fsub double %l1, %acc0 + %acc2 = fsub double %l2, %acc1 + %acc3 = fsub double %l3, %acc2 + %acc4 = fsub double %l4, %acc3 + %acc5 = fsub double %l5, %acc4 + %acc6 = fsub double %l6, %acc5 + %acc7 = fsub double %l7, %acc6 + %acc16 = fsub double %l16, %acc7 + %acc17 = fsub double %l17, %acc16 + %acc18 = fsub double %l18, %acc17 + %acc19 = fsub double %l19, %acc18 + %acc20 = fsub double %l20, %acc19 + %acc21 = fsub double %l21, %acc20 + %acc22 = fsub double %l22, %acc21 + %acc23 = fsub double %l23, %acc22 + %acc24 = fsub double %l24, %acc23 + %acc25 = fsub double %l25, %acc24 + %acc26 = fsub double %l26, %acc25 + %acc27 = fsub double %l27, %acc26 + %acc28 = fsub double %l28, %acc27 + %acc29 = fsub double %l29, %acc28 + %acc30 = fsub double %l30, %acc29 + %acc31 = fsub double %l31, %acc30 + store volatile double %acc0, double *%ptr + store volatile double %acc1, double *%ptr + store volatile double %acc2, double *%ptr + store volatile double %acc3, double *%ptr + store volatile double %acc4, double *%ptr + store volatile double %acc5, double *%ptr + store volatile double %acc6, double *%ptr + store volatile double %acc7, double *%ptr + store volatile double %acc16, double *%ptr + store volatile double %acc17, double *%ptr + store volatile double %acc18, double *%ptr + store volatile double %acc19, double *%ptr + store volatile double %acc20, double *%ptr + store volatile double %acc21, double *%ptr + store volatile double %acc22, double *%ptr + store volatile double %acc23, double *%ptr + store volatile double %acc24, double *%ptr + store volatile double %acc25, double *%ptr + store volatile double %acc26, double *%ptr + store volatile double %acc27, double *%ptr + store volatile double %acc28, double *%ptr + store volatile double %acc29, double *%ptr + store volatile double %acc30, double *%ptr + store volatile double %acc31, double *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/htm-intrinsics.ll b/test/CodeGen/SystemZ/htm-intrinsics.ll new file mode 100644 index 000000000000..6441ef94b406 --- /dev/null +++ b/test/CodeGen/SystemZ/htm-intrinsics.ll @@ -0,0 +1,352 @@ +; Test transactional-execution intrinsics. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s + +declare i32 @llvm.s390.tbegin(i8 *, i32) +declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32) +declare void @llvm.s390.tbeginc(i8 *, i32) +declare i32 @llvm.s390.tend() +declare void @llvm.s390.tabort(i64) +declare void @llvm.s390.ntstg(i64, i64 *) +declare i32 @llvm.s390.etnd() +declare void @llvm.s390.ppa.txassist(i32) + +; TBEGIN. +define void @test_tbegin() { +; CHECK-LABEL: test_tbegin: +; CHECK-NOT: stmg +; CHECK: std %f8, +; CHECK: std %f9, +; CHECK: std %f10, +; CHECK: std %f11, +; CHECK: std %f12, +; CHECK: std %f13, +; CHECK: std %f14, +; CHECK: std %f15, +; CHECK: tbegin 0, 65292 +; CHECK: ld %f8, +; CHECK: ld %f9, +; CHECK: ld %f10, +; CHECK: ld %f11, +; CHECK: ld %f12, +; CHECK: ld %f13, +; CHECK: ld %f14, +; CHECK: ld %f15, +; CHECK: br %r14 + call i32 @llvm.s390.tbegin(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat). +define void @test_tbegin_nofloat1() { +; CHECK-LABEL: test_tbegin_nofloat1: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret void +} + +; TBEGIN (nofloat) with integer CC return value. +define i32 @test_tbegin_nofloat2() { +; CHECK-LABEL: test_tbegin_nofloat2: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + ret i32 %res +} + +; TBEGIN (nofloat) with implicit CC check. +define void @test_tbegin_nofloat3(i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat3: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: jnh {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TBEGIN (nofloat) with dual CC use. +define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat4: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65292 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292) + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TBEGIN (nofloat) with register. +define void @test_tbegin_nofloat5(i8 *%ptr) { +; CHECK-LABEL: test_tbegin_nofloat5: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0(%r2), 65292 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292) + ret void +} + +; TBEGIN (nofloat) with GRSM 0x0f00. +define void @test_tbegin_nofloat6() { +; CHECK-LABEL: test_tbegin_nofloat6: +; CHECK: stmg %r6, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 3840 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xf100. +define void @test_tbegin_nofloat7() { +; CHECK-LABEL: test_tbegin_nofloat7: +; CHECK: stmg %r8, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 61696 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically. +define void @test_tbegin_nofloat8() { +; CHECK-LABEL: test_tbegin_nofloat8: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed. +define void @test_tbegin_nofloat9() { +; CHECK-LABEL: test_tbegin_nofloat9: +; CHECK: stmg %r10, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 64256 +; CHECK: br %r14 + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically. +define void @test_tbegin_nofloat10(i64 %n) { +; CHECK-LABEL: test_tbegin_nofloat10: +; CHECK: stmg %r11, %r15, +; CHECK-NOT: std +; CHECK: tbegin 0, 65280 +; CHECK: br %r14 + %buf = alloca i8, i64 %n + call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256) + ret void +} + +; TBEGINC. +define void @test_tbeginc() { +; CHECK-LABEL: test_tbeginc: +; CHECK-NOT: stmg +; CHECK-NOT: std +; CHECK: tbeginc 0, 65288 +; CHECK: br %r14 + call void @llvm.s390.tbeginc(i8 *null, i32 65288) + ret void +} + +; TEND with integer CC return value. +define i32 @test_tend1() { +; CHECK-LABEL: test_tend1: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + ret i32 %res +} + +; TEND with implicit CC check. +define void @test_tend3(i32 *%ptr) { +; CHECK-LABEL: test_tend3: +; CHECK: tend +; CHECK: je {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; TEND with dual CC use. +define i32 @test_tend2(i32 %pad, i32 *%ptr) { +; CHECK-LABEL: test_tend2: +; CHECK: tend +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: cijlh %r2, 2, {{\.L*}} +; CHECK: mvhi 0(%r3), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.tend() + %cmp = icmp eq i32 %res, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, i32* %ptr, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %res +} + +; TABORT with register only. +define void @test_tabort1(i64 %val) { +; CHECK-LABEL: test_tabort1: +; CHECK: tabort 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 %val) + ret void +} + +; TABORT with immediate only. +define void @test_tabort2(i64 %val) { +; CHECK-LABEL: test_tabort2: +; CHECK: tabort 1234 +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 1234) + ret void +} + +; TABORT with register + immediate. +define void @test_tabort3(i64 %val) { +; CHECK-LABEL: test_tabort3: +; CHECK: tabort 1234(%r2) +; CHECK: br %r14 + %sum = add i64 %val, 1234 + call void @llvm.s390.tabort(i64 %sum) + ret void +} + +; TABORT with out-of-range immediate. +define void @test_tabort4(i64 %val) { +; CHECK-LABEL: test_tabort4: +; CHECK: tabort 0({{%r[1-5]}}) +; CHECK: br %r14 + call void @llvm.s390.tabort(i64 4096) + ret void +} + +; NTSTG with base pointer only. +define void @test_ntstg1(i64 *%ptr, i64 %val) { +; CHECK-LABEL: test_ntstg1: +; CHECK: ntstg %r3, 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with base and index. +; Check that VSTL doesn't allow an index. +define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) { +; CHECK-LABEL: test_ntstg2: +; CHECK: sllg [[REG:%r[1-5]]], %r3, 3 +; CHECK: ntstg %r4, 0([[REG]],%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 %index + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the highest in-range displacement. +define void @test_ntstg3(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg3: +; CHECK: ntstg %r3, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65535 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range positive displacement. +define void @test_ntstg4(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg4: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with the lowest in-range displacement. +define void @test_ntstg5(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg5: +; CHECK: ntstg %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65536 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; NTSTG with an out-of-range negative displacement. +define void @test_ntstg6(i64 *%base, i64 %val) { +; CHECK-LABEL: test_ntstg6: +; CHECK: ntstg %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i64 -65537 + call void @llvm.s390.ntstg(i64 %val, i64 *%ptr) + ret void +} + +; ETND. +define i32 @test_etnd() { +; CHECK-LABEL: test_etnd: +; CHECK: etnd %r2 +; CHECK: br %r14 + %res = call i32 @llvm.s390.etnd() + ret i32 %res +} + +; PPA (Transaction-Abort Assist) +define void @test_ppa_txassist(i32 %val) { +; CHECK-LABEL: test_ppa_txassist: +; CHECK: ppa %r2, 0, 1 +; CHECK: br %r14 + call void @llvm.s390.ppa.txassist(i32 %val) + ret void +} + diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll index 0b54e85dc4ed..eb39552f1a2e 100644 --- a/test/CodeGen/SystemZ/insert-01.ll +++ b/test/CodeGen/SystemZ/insert-01.ll @@ -9,7 +9,7 @@ define i32 @f1(i32 %orig, i8 *%ptr) { ; CHECK-NOT: ni ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %ptr1 = and i32 %orig, -256 %or = or i32 %ptr1, %ptr2 @@ -22,7 +22,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) { ; CHECK-NOT: ni ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %ptr1 = and i32 %orig, -256 %or = or i32 %ptr2, %ptr1 @@ -36,7 +36,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) { ; CHECK: nill %r2, 65024 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %ptr1 = and i32 %orig, -512 %or = or i32 %ptr1, %ptr2 @@ -49,7 +49,7 @@ define i32 @f4(i32 %orig, i8 *%ptr) { ; CHECK: nill %r2, 65024 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %ptr1 = and i32 %orig, -512 %or = or i32 %ptr2, %ptr1 @@ -62,7 +62,7 @@ define i32 @f5(i32 %orig, i8 *%ptr) { ; CHECK: sll %r2, 8 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %ptr1 = shl i32 %orig, 8 %or = or i32 %ptr1, %ptr2 @@ -75,7 +75,7 @@ define i32 @f6(i32 %orig, i8 *%ptr) { ; CHECK: sll %r2, 8 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %ptr1 = shl i32 %orig, 8 %or = or i32 %ptr2, %ptr1 @@ -88,7 +88,7 @@ define i32 @f7(i32 %orig, i8 *%ptr) { ; CHECK: lhi %r2, 256 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %or = or i32 %ptr2, 256 ret i32 %or @@ -100,7 +100,7 @@ define i32 @f8(i32 %orig, i8 *%ptr) { ; CHECK: lhi %r2, 256 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i32 %or = or i32 256, %ptr2 ret i32 %or @@ -111,8 +111,8 @@ define i32 @f9(i32 %orig, i8 *%src) { ; CHECK-LABEL: f9: ; CHECK: ic %r2, 4095(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4095 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -124,8 +124,8 @@ define i32 @f10(i32 %orig, i8 *%src) { ; CHECK-LABEL: f10: ; CHECK: icy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4096 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -137,8 +137,8 @@ define i32 @f11(i32 %orig, i8 *%src) { ; CHECK-LABEL: f11: ; CHECK: icy %r2, 524287(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -152,8 +152,8 @@ define i32 @f12(i32 %orig, i8 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -165,8 +165,8 @@ define i32 @f13(i32 %orig, i8 *%src) { ; CHECK-LABEL: f13: ; CHECK: icy %r2, -1(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -178,8 +178,8 @@ define i32 @f14(i32 %orig, i8 *%src) { ; CHECK-LABEL: f14: ; CHECK: icy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -193,8 +193,8 @@ define i32 @f15(i32 %orig, i8 *%src) { ; CHECK: agfi %r3, -524289 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -206,9 +206,9 @@ define i32 @f16(i32 %orig, i8 *%src, i64 %index) { ; CHECK-LABEL: f16: ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}}) ; CHECK: br %r14 - %ptr1 = getelementptr i8 *%src, i64 %index - %ptr2 = getelementptr i8 *%ptr1, i64 4095 - %val = load i8 *%ptr2 + %ptr1 = getelementptr i8, i8 *%src, i64 %index + %ptr2 = getelementptr i8, i8 *%ptr1, i64 4095 + %val = load i8 , i8 *%ptr2 %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 @@ -220,9 +220,9 @@ define i32 @f17(i32 %orig, i8 *%src, i64 %index) { ; CHECK-LABEL: f17: ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}}) ; CHECK: br %r14 - %ptr1 = getelementptr i8 *%src, i64 %index - %ptr2 = getelementptr i8 *%ptr1, i64 4096 - %val = load i8 *%ptr2 + %ptr1 = getelementptr i8, i8 *%src, i64 %index + %ptr2 = getelementptr i8, i8 *%ptr1, i64 4096 + %val = load i8 , i8 *%ptr2 %src2 = zext i8 %val to i32 %src1 = and i32 %orig, -256 %or = or i32 %src2, %src1 diff --git a/test/CodeGen/SystemZ/insert-02.ll b/test/CodeGen/SystemZ/insert-02.ll index 7a85b0bee4d8..8ecfd1f16efe 100644 --- a/test/CodeGen/SystemZ/insert-02.ll +++ b/test/CodeGen/SystemZ/insert-02.ll @@ -9,7 +9,7 @@ define i64 @f1(i64 %orig, i8 *%ptr) { ; CHECK-NOT: ni ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %ptr1 = and i64 %orig, -256 %or = or i64 %ptr1, %ptr2 @@ -22,7 +22,7 @@ define i64 @f2(i64 %orig, i8 *%ptr) { ; CHECK-NOT: ni ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %ptr1 = and i64 %orig, -256 %or = or i64 %ptr2, %ptr1 @@ -36,7 +36,7 @@ define i64 @f3(i64 %orig, i8 *%ptr) { ; CHECK: nill %r2, 65024 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %ptr1 = and i64 %orig, -512 %or = or i64 %ptr1, %ptr2 @@ -49,7 +49,7 @@ define i64 @f4(i64 %orig, i8 *%ptr) { ; CHECK: nill %r2, 65024 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %ptr1 = and i64 %orig, -512 %or = or i64 %ptr2, %ptr1 @@ -62,7 +62,7 @@ define i64 @f5(i64 %orig, i8 *%ptr) { ; CHECK: sllg %r2, %r2, 8 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %ptr1 = shl i64 %orig, 8 %or = or i64 %ptr1, %ptr2 @@ -75,7 +75,7 @@ define i64 @f6(i64 %orig, i8 *%ptr) { ; CHECK: sllg %r2, %r2, 8 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %ptr1 = shl i64 %orig, 8 %or = or i64 %ptr2, %ptr1 @@ -88,7 +88,7 @@ define i64 @f7(i64 %orig, i8 *%ptr) { ; CHECK: lghi %r2, 256 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %or = or i64 %ptr2, 256 ret i64 %or @@ -100,7 +100,7 @@ define i64 @f8(i64 %orig, i8 *%ptr) { ; CHECK: lghi %r2, 256 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ptr2 = zext i8 %val to i64 %or = or i64 256, %ptr2 ret i64 %or @@ -111,8 +111,8 @@ define i64 @f9(i64 %orig, i8 *%src) { ; CHECK-LABEL: f9: ; CHECK: ic %r2, 4095(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4095 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -124,8 +124,8 @@ define i64 @f10(i64 %orig, i8 *%src) { ; CHECK-LABEL: f10: ; CHECK: icy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4096 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -137,8 +137,8 @@ define i64 @f11(i64 %orig, i8 *%src) { ; CHECK-LABEL: f11: ; CHECK: icy %r2, 524287(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -152,8 +152,8 @@ define i64 @f12(i64 %orig, i8 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -165,8 +165,8 @@ define i64 @f13(i64 %orig, i8 *%src) { ; CHECK-LABEL: f13: ; CHECK: icy %r2, -1(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -178,8 +178,8 @@ define i64 @f14(i64 %orig, i8 *%src) { ; CHECK-LABEL: f14: ; CHECK: icy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -193,8 +193,8 @@ define i64 @f15(i64 %orig, i8 *%src) { ; CHECK: agfi %r3, -524289 ; CHECK: ic %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %val = load i8 , i8 *%ptr %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -206,9 +206,9 @@ define i64 @f16(i64 %orig, i8 *%src, i64 %index) { ; CHECK-LABEL: f16: ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}}) ; CHECK: br %r14 - %ptr1 = getelementptr i8 *%src, i64 %index - %ptr2 = getelementptr i8 *%ptr1, i64 4095 - %val = load i8 *%ptr2 + %ptr1 = getelementptr i8, i8 *%src, i64 %index + %ptr2 = getelementptr i8, i8 *%ptr1, i64 4095 + %val = load i8 , i8 *%ptr2 %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 @@ -220,9 +220,9 @@ define i64 @f17(i64 %orig, i8 *%src, i64 %index) { ; CHECK-LABEL: f17: ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}}) ; CHECK: br %r14 - %ptr1 = getelementptr i8 *%src, i64 %index - %ptr2 = getelementptr i8 *%ptr1, i64 4096 - %val = load i8 *%ptr2 + %ptr1 = getelementptr i8, i8 *%src, i64 %index + %ptr2 = getelementptr i8, i8 *%ptr1, i64 4096 + %val = load i8 , i8 *%ptr2 %src2 = zext i8 %val to i64 %src1 = and i64 %orig, -256 %or = or i64 %src2, %src1 diff --git a/test/CodeGen/SystemZ/insert-06.ll b/test/CodeGen/SystemZ/insert-06.ll index 81a9c8770708..3243d9f4cb0c 100644 --- a/test/CodeGen/SystemZ/insert-06.ll +++ b/test/CodeGen/SystemZ/insert-06.ll @@ -85,7 +85,7 @@ define i64 @f7(i64 %a, i32 *%src) { ; CHECK-NOT: {{%r[23]}} ; CHECK: l %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %low = zext i32 %b to i64 %high = and i64 %a, -4294967296 %res = or i64 %high, %low @@ -98,7 +98,7 @@ define i64 @f8(i64 %a, i8 *%src) { ; CHECK-NOT: {{%r[23]}} ; CHECK: lb %r2, 0(%r3) ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %b = sext i8 %byte to i32 %low = zext i32 %b to i64 %high = and i64 %a, -4294967296 @@ -185,7 +185,7 @@ define i64 @f15(i64 %a, i8 *%src) { ; CHECK-NOT: {{%r[23]}} ; CHECK: lb %r2, 0(%r3) ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %b = sext i8 %byte to i64 %low = and i64 %b, 4294967295 %high = and i64 %a, -4294967296 diff --git a/test/CodeGen/SystemZ/int-add-01.ll b/test/CodeGen/SystemZ/int-add-01.ll index 4114686e41e8..f7a3a264913a 100644 --- a/test/CodeGen/SystemZ/int-add-01.ll +++ b/test/CodeGen/SystemZ/int-add-01.ll @@ -8,7 +8,7 @@ define i32 @f1(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f1: ; CHECK: ah %r2, 0(%r3) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -19,8 +19,8 @@ define i32 @f2(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f2: ; CHECK: ah %r2, 4094(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2047 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2047 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -31,8 +31,8 @@ define i32 @f3(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f3: ; CHECK: ahy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2048 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2048 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -43,8 +43,8 @@ define i32 @f4(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f4: ; CHECK: ahy %r2, 524286(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -57,8 +57,8 @@ define i32 @f5(i32 %lhs, i16 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: ah %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -69,8 +69,8 @@ define i32 @f6(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f6: ; CHECK: ahy %r2, -2(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -81,8 +81,8 @@ define i32 @f7(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f7: ; CHECK: ahy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -95,8 +95,8 @@ define i32 @f8(i32 %lhs, i16 *%src) { ; CHECK: agfi %r3, -524290 ; CHECK: ah %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -110,7 +110,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4094 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res @@ -124,7 +124,7 @@ define i32 @f10(i32 %lhs, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = add i32 %lhs, %rhs ret i32 %res diff --git a/test/CodeGen/SystemZ/int-add-02.ll b/test/CodeGen/SystemZ/int-add-02.ll index 4386b5a4d496..01e77de31b5f 100644 --- a/test/CodeGen/SystemZ/int-add-02.ll +++ b/test/CodeGen/SystemZ/int-add-02.ll @@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: a %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %add = add i32 %a, %b ret i32 %add } @@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: a %r2, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1023 + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: ay %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1024 + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: ay %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: a %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: ay %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) { ; CHECK-LABEL: f8: ; CHECK: ay %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: a %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %add = add i32 %a, %b ret i32 %add } @@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: a %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/int-add-03.ll b/test/CodeGen/SystemZ/int-add-03.ll index 56000a80cd9b..92e3c1656d7f 100644 --- a/test/CodeGen/SystemZ/int-add-03.ll +++ b/test/CodeGen/SystemZ/int-add-03.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: agf %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = sext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: agf %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: agf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: agf %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: agf %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: agf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: agf %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %frob0 = add i32 %val0, 100 %frob1 = add i32 %val1, 100 diff --git a/test/CodeGen/SystemZ/int-add-04.ll b/test/CodeGen/SystemZ/int-add-04.ll index 675e36babfa7..6828b615e238 100644 --- a/test/CodeGen/SystemZ/int-add-04.ll +++ b/test/CodeGen/SystemZ/int-add-04.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: algf %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = zext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: algf %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: algf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: algf %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: algf %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: algf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %add = add i64 %a, %bext ret i64 %add @@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: algf %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %frob0 = add i32 %val0, 100 %frob1 = add i32 %val1, 100 diff --git a/test/CodeGen/SystemZ/int-add-05.ll b/test/CodeGen/SystemZ/int-add-05.ll index a05fdd9059c1..f28e305dc407 100644 --- a/test/CodeGen/SystemZ/int-add-05.ll +++ b/test/CodeGen/SystemZ/int-add-05.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: ag %r2, 0(%r3) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %add = add i64 %a, %b ret i64 %add } @@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) { ; CHECK-LABEL: f3: ; CHECK: ag %r2, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %add = add i64 %a, %b ret i64 %add } @@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: ag %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %add = add i64 %a, %b ret i64 %add } @@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: ag %r2, -8(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %add = add i64 %a, %b ret i64 %add } @@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) { ; CHECK-LABEL: f6: ; CHECK: ag %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %add = add i64 %a, %b ret i64 %add } @@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) { ; CHECK: agfi %r3, -524296 ; CHECK: ag %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %add = add i64 %a, %b ret i64 %add } @@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %add = add i64 %a, %b ret i64 %add } @@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: ag %r2, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/int-add-08.ll b/test/CodeGen/SystemZ/int-add-08.ll index bcef914ed872..75b85d0888a2 100644 --- a/test/CodeGen/SystemZ/int-add-08.ll +++ b/test/CodeGen/SystemZ/int-add-08.ll @@ -11,7 +11,7 @@ define void @f1(i128 *%ptr) { ; CHECK: algr ; CHECK: alcgr ; CHECK: br %r14 - %value = load i128 *%ptr + %value = load i128 , i128 *%ptr %add = add i128 %value, %value store i128 %add, i128 *%ptr ret void @@ -25,8 +25,8 @@ define void @f2(i128 *%aptr, i64 %addr) { ; CHECK: alcg {{%r[0-5]}}, 0(%r3) ; CHECK: br %r14 %bptr = inttoptr i64 %addr to i128 * - %a = load volatile i128 *%aptr - %b = load i128 *%bptr + %a = load volatile i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %add = add i128 %a, %b store i128 %add, i128 *%aptr ret void @@ -40,8 +40,8 @@ define void @f3(i128 *%aptr, i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, 524272 %bptr = inttoptr i64 %addr to i128 * - %a = load volatile i128 *%aptr - %b = load i128 *%bptr + %a = load volatile i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %add = add i128 %a, %b store i128 %add, i128 *%aptr ret void @@ -57,8 +57,8 @@ define void @f4(i128 *%aptr, i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, 524280 %bptr = inttoptr i64 %addr to i128 * - %a = load volatile i128 *%aptr - %b = load i128 *%bptr + %a = load volatile i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %add = add i128 %a, %b store i128 %add, i128 *%aptr ret void @@ -74,8 +74,8 @@ define void @f5(i128 *%aptr, i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, 524288 %bptr = inttoptr i64 %addr to i128 * - %a = load volatile i128 *%aptr - %b = load i128 *%bptr + %a = load volatile i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %add = add i128 %a, %b store i128 %add, i128 *%aptr ret void @@ -89,8 +89,8 @@ define void @f6(i128 *%aptr, i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, -524288 %bptr = inttoptr i64 %addr to i128 * - %a = load volatile i128 *%aptr - %b = load i128 *%bptr + %a = load volatile i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %add = add i128 %a, %b store i128 %add, i128 *%aptr ret void @@ -104,8 +104,8 @@ define void @f7(i128 *%aptr, i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, -524296 %bptr = inttoptr i64 %addr to i128 * - %a = load volatile i128 *%aptr - %b = load i128 *%bptr + %a = load volatile i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %add = add i128 %a, %b store i128 %add, i128 *%aptr ret void @@ -119,20 +119,20 @@ define void @f8(i128 *%ptr0) { ; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15) ; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i128 *%ptr0, i128 2 - %ptr2 = getelementptr i128 *%ptr0, i128 4 - %ptr3 = getelementptr i128 *%ptr0, i128 6 - %ptr4 = getelementptr i128 *%ptr0, i128 8 + %ptr1 = getelementptr i128, i128 *%ptr0, i128 2 + %ptr2 = getelementptr i128, i128 *%ptr0, i128 4 + %ptr3 = getelementptr i128, i128 *%ptr0, i128 6 + %ptr4 = getelementptr i128, i128 *%ptr0, i128 8 - %val0 = load i128 *%ptr0 - %val1 = load i128 *%ptr1 - %val2 = load i128 *%ptr2 - %val3 = load i128 *%ptr3 - %val4 = load i128 *%ptr4 + %val0 = load i128 , i128 *%ptr0 + %val1 = load i128 , i128 *%ptr1 + %val2 = load i128 , i128 *%ptr2 + %val3 = load i128 , i128 *%ptr3 + %val4 = load i128 , i128 *%ptr4 %retptr = call i128 *@foo() - %ret = load i128 *%retptr + %ret = load i128 , i128 *%retptr %add0 = add i128 %ret, %val0 %add1 = add i128 %add0, %val1 %add2 = add i128 %add1, %val2 diff --git a/test/CodeGen/SystemZ/int-add-09.ll b/test/CodeGen/SystemZ/int-add-09.ll index fd151a7f979a..b7bcdc8b93a8 100644 --- a/test/CodeGen/SystemZ/int-add-09.ll +++ b/test/CodeGen/SystemZ/int-add-09.ll @@ -9,7 +9,7 @@ define void @f1(i128 *%aptr) { ; CHECK: algfi {{%r[0-5]}}, 1 ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 128 %add = add i128 %xor, 1 store i128 %add, i128 *%aptr @@ -22,7 +22,7 @@ define void @f2(i128 *%aptr) { ; CHECK: algfi {{%r[0-5]}}, 4294967295 ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 128 %add = add i128 %xor, 4294967295 store i128 %add, i128 *%aptr @@ -35,7 +35,7 @@ define void @f3(i128 *%aptr) { ; CHECK: algr ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 128 %add = add i128 %xor, 4294967296 store i128 %add, i128 *%aptr @@ -48,7 +48,7 @@ define void @f4(i128 *%aptr) { ; CHECK: algr ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 128 %add = add i128 %xor, -1 store i128 %add, i128 *%aptr diff --git a/test/CodeGen/SystemZ/int-add-10.ll b/test/CodeGen/SystemZ/int-add-10.ll index 01d0a661ed29..f55788dc8bb6 100644 --- a/test/CodeGen/SystemZ/int-add-10.ll +++ b/test/CodeGen/SystemZ/int-add-10.ll @@ -9,7 +9,7 @@ define void @f1(i128 *%aptr, i32 %b) { ; CHECK: algfr {{%r[0-5]}}, %r3 ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %bext = zext i32 %b to i128 %add = add i128 %xor, %bext @@ -23,7 +23,7 @@ define void @f2(i128 *%aptr, i64 %b) { ; CHECK: algfr {{%r[0-5]}}, %r3 ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %trunc = trunc i64 %b to i32 %bext = zext i32 %trunc to i128 @@ -39,7 +39,7 @@ define void @f3(i128 *%aptr, i64 %b) { ; CHECK: algfr {{%r[0-5]}}, %r3 ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %bext = zext i64 %b to i128 %and = and i128 %bext, 4294967295 @@ -54,9 +54,9 @@ define void @f4(i128 *%aptr, i32 *%bsrc) { ; CHECK: algf {{%r[0-5]}}, 0(%r3) ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %b = load i32 *%bsrc + %b = load i32 , i32 *%bsrc %bext = zext i32 %b to i128 %add = add i128 %xor, %bext store i128 %add, i128 *%aptr @@ -69,10 +69,10 @@ define void @f5(i128 *%aptr, i32 *%bsrc) { ; CHECK: algf {{%r[0-5]}}, 524284(%r3) ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i64 131071 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %add = add i128 %xor, %bext store i128 %add, i128 *%aptr @@ -87,10 +87,10 @@ define void @f6(i128 *%aptr, i32 *%bsrc) { ; CHECK: algf {{%r[0-5]}}, 0(%r3) ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i64 131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %add = add i128 %xor, %bext store i128 %add, i128 *%aptr @@ -103,10 +103,10 @@ define void @f7(i128 *%aptr, i32 *%bsrc) { ; CHECK: algf {{%r[0-5]}}, -4(%r3) ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i128 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i128 -1 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %add = add i128 %xor, %bext store i128 %add, i128 *%aptr @@ -119,10 +119,10 @@ define void @f8(i128 *%aptr, i32 *%bsrc) { ; CHECK: algf {{%r[0-5]}}, -524288(%r3) ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i128 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i128 -131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %add = add i128 %xor, %bext store i128 %add, i128 *%aptr @@ -137,10 +137,10 @@ define void @f9(i128 *%aptr, i32 *%bsrc) { ; CHECK: algf {{%r[0-5]}}, 0(%r3) ; CHECK: alcg ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i128 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i128 -131073 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %add = add i128 %xor, %bext store i128 %add, i128 *%aptr @@ -152,12 +152,12 @@ define void @f10(i128 *%aptr, i64 %src, i64 %index) { ; CHECK-LABEL: f10: ; CHECK: algf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}}) ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %add1 = add i64 %src, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %add = add i128 %xor, %bext store i128 %add, i128 *%aptr diff --git a/test/CodeGen/SystemZ/int-add-11.ll b/test/CodeGen/SystemZ/int-add-11.ll index 679c206094f3..b93555f5d357 100644 --- a/test/CodeGen/SystemZ/int-add-11.ll +++ b/test/CodeGen/SystemZ/int-add-11.ll @@ -8,7 +8,7 @@ define void @f1(i32 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: asi 0(%r2), 1 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %add = add i32 %val, 127 store i32 %add, i32 *%ptr ret void @@ -19,7 +19,7 @@ define void @f2(i32 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: asi 0(%r2), 127 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %add = add i32 %val, 127 store i32 %add, i32 *%ptr ret void @@ -32,7 +32,7 @@ define void @f3(i32 *%ptr) { ; CHECK-NOT: asi ; CHECK: st %r0, 0(%r2) ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %add = add i32 %val, 128 store i32 %add, i32 *%ptr ret void @@ -43,7 +43,7 @@ define void @f4(i32 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: asi 0(%r2), -128 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %add = add i32 %val, -128 store i32 %add, i32 *%ptr ret void @@ -55,7 +55,7 @@ define void @f5(i32 *%ptr) { ; CHECK-NOT: asi ; CHECK: st %r0, 0(%r2) ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %add = add i32 %val, -129 store i32 %add, i32 *%ptr ret void @@ -66,8 +66,8 @@ define void @f6(i32 *%base) { ; CHECK-LABEL: f6: ; CHECK: asi 524284(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131071 + %val = load i32 , i32 *%ptr %add = add i32 %val, 1 store i32 %add, i32 *%ptr ret void @@ -80,8 +80,8 @@ define void @f7(i32 *%base) { ; CHECK: agfi %r2, 524288 ; CHECK: asi 0(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131072 + %val = load i32 , i32 *%ptr %add = add i32 %val, 1 store i32 %add, i32 *%ptr ret void @@ -92,8 +92,8 @@ define void @f8(i32 *%base) { ; CHECK-LABEL: f8: ; CHECK: asi -524288(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131072 + %val = load i32 , i32 *%ptr %add = add i32 %val, 1 store i32 %add, i32 *%ptr ret void @@ -106,8 +106,8 @@ define void @f9(i32 *%base) { ; CHECK: agfi %r2, -524292 ; CHECK: asi 0(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131073 + %val = load i32 , i32 *%ptr %add = add i32 %val, 1 store i32 %add, i32 *%ptr ret void @@ -122,7 +122,7 @@ define void @f10(i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4 %ptr = inttoptr i64 %add2 to i32 * - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %add = add i32 %val, 1 store i32 %add, i32 *%ptr ret void @@ -134,22 +134,22 @@ define void @f11(i32 *%ptr, i32 %sel) { ; CHECK: asi {{[0-9]+}}(%r15), 127 ; CHECK: br %r14 entry: - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr %test = icmp ne i32 %sel, 0 br i1 %test, label %add, label %store @@ -217,22 +217,22 @@ define void @f12(i32 *%ptr, i32 %sel) { ; CHECK: asi {{[0-9]+}}(%r15), -128 ; CHECK: br %r14 entry: - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr %test = icmp ne i32 %sel, 0 br i1 %test, label %add, label %store diff --git a/test/CodeGen/SystemZ/int-add-12.ll b/test/CodeGen/SystemZ/int-add-12.ll index 741cce19d72c..496650f435c9 100644 --- a/test/CodeGen/SystemZ/int-add-12.ll +++ b/test/CodeGen/SystemZ/int-add-12.ll @@ -7,7 +7,7 @@ define void @f1(i64 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: agsi 0(%r2), 1 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %add = add i64 %val, 127 store i64 %add, i64 *%ptr ret void @@ -18,7 +18,7 @@ define void @f2(i64 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: agsi 0(%r2), 127 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %add = add i64 %val, 127 store i64 %add, i64 *%ptr ret void @@ -31,7 +31,7 @@ define void @f3(i64 *%ptr) { ; CHECK-NOT: agsi ; CHECK: stg %r0, 0(%r2) ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %add = add i64 %val, 128 store i64 %add, i64 *%ptr ret void @@ -42,7 +42,7 @@ define void @f4(i64 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: agsi 0(%r2), -128 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %add = add i64 %val, -128 store i64 %add, i64 *%ptr ret void @@ -54,7 +54,7 @@ define void @f5(i64 *%ptr) { ; CHECK-NOT: agsi ; CHECK: stg %r0, 0(%r2) ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %add = add i64 %val, -129 store i64 %add, i64 *%ptr ret void @@ -65,8 +65,8 @@ define void @f6(i64 *%base) { ; CHECK-LABEL: f6: ; CHECK: agsi 524280(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65535 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 65535 + %val = load i64 , i64 *%ptr %add = add i64 %val, 1 store i64 %add, i64 *%ptr ret void @@ -79,8 +79,8 @@ define void @f7(i64 *%base) { ; CHECK: agfi %r2, 524288 ; CHECK: agsi 0(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65536 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 65536 + %val = load i64 , i64 *%ptr %add = add i64 %val, 1 store i64 %add, i64 *%ptr ret void @@ -91,8 +91,8 @@ define void @f8(i64 *%base) { ; CHECK-LABEL: f8: ; CHECK: agsi -524288(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65536 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -65536 + %val = load i64 , i64 *%ptr %add = add i64 %val, 1 store i64 %add, i64 *%ptr ret void @@ -105,8 +105,8 @@ define void @f9(i64 *%base) { ; CHECK: agfi %r2, -524296 ; CHECK: agsi 0(%r2), 1 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65537 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -65537 + %val = load i64 , i64 *%ptr %add = add i64 %val, 1 store i64 %add, i64 *%ptr ret void @@ -121,7 +121,7 @@ define void @f10(i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 8 %ptr = inttoptr i64 %add2 to i64 * - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %add = add i64 %val, 1 store i64 %add, i64 *%ptr ret void @@ -133,22 +133,22 @@ define void @f11(i64 *%ptr, i32 %sel) { ; CHECK: agsi {{[0-9]+}}(%r15), 127 ; CHECK: br %r14 entry: - %val0 = load volatile i64 *%ptr - %val1 = load volatile i64 *%ptr - %val2 = load volatile i64 *%ptr - %val3 = load volatile i64 *%ptr - %val4 = load volatile i64 *%ptr - %val5 = load volatile i64 *%ptr - %val6 = load volatile i64 *%ptr - %val7 = load volatile i64 *%ptr - %val8 = load volatile i64 *%ptr - %val9 = load volatile i64 *%ptr - %val10 = load volatile i64 *%ptr - %val11 = load volatile i64 *%ptr - %val12 = load volatile i64 *%ptr - %val13 = load volatile i64 *%ptr - %val14 = load volatile i64 *%ptr - %val15 = load volatile i64 *%ptr + %val0 = load volatile i64 , i64 *%ptr + %val1 = load volatile i64 , i64 *%ptr + %val2 = load volatile i64 , i64 *%ptr + %val3 = load volatile i64 , i64 *%ptr + %val4 = load volatile i64 , i64 *%ptr + %val5 = load volatile i64 , i64 *%ptr + %val6 = load volatile i64 , i64 *%ptr + %val7 = load volatile i64 , i64 *%ptr + %val8 = load volatile i64 , i64 *%ptr + %val9 = load volatile i64 , i64 *%ptr + %val10 = load volatile i64 , i64 *%ptr + %val11 = load volatile i64 , i64 *%ptr + %val12 = load volatile i64 , i64 *%ptr + %val13 = load volatile i64 , i64 *%ptr + %val14 = load volatile i64 , i64 *%ptr + %val15 = load volatile i64 , i64 *%ptr %test = icmp ne i32 %sel, 0 br i1 %test, label %add, label %store @@ -216,22 +216,22 @@ define void @f12(i64 *%ptr, i32 %sel) { ; CHECK: agsi {{[0-9]+}}(%r15), -128 ; CHECK: br %r14 entry: - %val0 = load volatile i64 *%ptr - %val1 = load volatile i64 *%ptr - %val2 = load volatile i64 *%ptr - %val3 = load volatile i64 *%ptr - %val4 = load volatile i64 *%ptr - %val5 = load volatile i64 *%ptr - %val6 = load volatile i64 *%ptr - %val7 = load volatile i64 *%ptr - %val8 = load volatile i64 *%ptr - %val9 = load volatile i64 *%ptr - %val10 = load volatile i64 *%ptr - %val11 = load volatile i64 *%ptr - %val12 = load volatile i64 *%ptr - %val13 = load volatile i64 *%ptr - %val14 = load volatile i64 *%ptr - %val15 = load volatile i64 *%ptr + %val0 = load volatile i64 , i64 *%ptr + %val1 = load volatile i64 , i64 *%ptr + %val2 = load volatile i64 , i64 *%ptr + %val3 = load volatile i64 , i64 *%ptr + %val4 = load volatile i64 , i64 *%ptr + %val5 = load volatile i64 , i64 *%ptr + %val6 = load volatile i64 , i64 *%ptr + %val7 = load volatile i64 , i64 *%ptr + %val8 = load volatile i64 , i64 *%ptr + %val9 = load volatile i64 , i64 *%ptr + %val10 = load volatile i64 , i64 *%ptr + %val11 = load volatile i64 , i64 *%ptr + %val12 = load volatile i64 , i64 *%ptr + %val13 = load volatile i64 , i64 *%ptr + %val14 = load volatile i64 , i64 *%ptr + %val15 = load volatile i64 , i64 *%ptr %test = icmp ne i32 %sel, 0 br i1 %test, label %add, label %store diff --git a/test/CodeGen/SystemZ/int-cmp-01.ll b/test/CodeGen/SystemZ/int-cmp-01.ll index 6653b6f706f7..97b697db3bdb 100644 --- a/test/CodeGen/SystemZ/int-cmp-01.ll +++ b/test/CodeGen/SystemZ/int-cmp-01.ll @@ -8,7 +8,7 @@ define void @f1(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK-LABEL: f1: ; CHECK: ch %r2, 0(%r3) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -21,8 +21,8 @@ define void @f2(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK-LABEL: f2: ; CHECK: ch %r2, 4094(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2047 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2047 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -35,8 +35,8 @@ define void @f3(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK-LABEL: f3: ; CHECK: chy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2048 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2048 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -49,8 +49,8 @@ define void @f4(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK-LABEL: f4: ; CHECK: chy %r2, 524286(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -65,8 +65,8 @@ define void @f5(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK: agfi %r3, 524288 ; CHECK: ch %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -79,8 +79,8 @@ define void @f6(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK-LABEL: f6: ; CHECK: chy %r2, -2(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -93,8 +93,8 @@ define void @f7(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK-LABEL: f7: ; CHECK: chy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -109,8 +109,8 @@ define void @f8(i32 %lhs, i16 *%src, i32 *%dst) { ; CHECK: agfi %r3, -524290 ; CHECK: ch %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -126,7 +126,7 @@ define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4094 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -142,7 +142,7 @@ define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, i32 100, i32 200 @@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i32 %rhs, i16 *%src) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %lhs = sext i16 %half to i32 %cond = icmp slt i32 %lhs, %rhs %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-02.ll b/test/CodeGen/SystemZ/int-cmp-02.ll index 4a8a1a9ade33..d5aef0f0f977 100644 --- a/test/CodeGen/SystemZ/int-cmp-02.ll +++ b/test/CodeGen/SystemZ/int-cmp-02.ll @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i2 = load i32 *%ptr + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -35,8 +35,8 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1023 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1023 + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -49,8 +49,8 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1024 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1024 + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -63,8 +63,8 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131071 + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -79,8 +79,8 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131072 + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -93,8 +93,8 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -1 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -1 + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -107,8 +107,8 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131072 + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -123,8 +123,8 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131073 + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -140,7 +140,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %i2 = load i32 *%ptr + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -156,7 +156,7 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %i2 = load i32 *%ptr + %i2 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -189,7 +189,7 @@ define double @f13(double %a, double %b, i32 %i2, i32 *%ptr) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i1 = load i32 *%ptr + %i1 = load i32 , i32 *%ptr %cond = icmp slt i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-03.ll b/test/CodeGen/SystemZ/int-cmp-03.ll index aa654e086dc6..0246666f06fe 100644 --- a/test/CodeGen/SystemZ/int-cmp-03.ll +++ b/test/CodeGen/SystemZ/int-cmp-03.ll @@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i2 = load i32 *%ptr + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -33,8 +33,8 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1023 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1023 + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -47,8 +47,8 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1024 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1024 + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -61,8 +61,8 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131071 + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -77,8 +77,8 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131072 + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -91,8 +91,8 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -1 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -1 + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -105,8 +105,8 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131072 + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -121,8 +121,8 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 - %i2 = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131073 + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -138,7 +138,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %i2 = load i32 *%ptr + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -154,7 +154,7 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %i2 = load i32 *%ptr + %i2 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -167,7 +167,7 @@ define double @f12(double %a, double %b, i32 %i2, i32 *%ptr) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i1 = load i32 *%ptr + %i1 = load i32 , i32 *%ptr %cond = icmp ult i32 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll index a6606f392923..90f05ea38680 100644 --- a/test/CodeGen/SystemZ/int-cmp-04.ll +++ b/test/CodeGen/SystemZ/int-cmp-04.ll @@ -8,7 +8,7 @@ define void @f1(i64 %lhs, i16 *%src, i64 *%dst) { ; CHECK-LABEL: f1: ; CHECK: cgh %r2, 0(%r3) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %rhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, i64 100, i64 200 @@ -21,8 +21,8 @@ define void @f2(i64 %lhs, i16 *%src, i64 *%dst) { ; CHECK-LABEL: f2: ; CHECK: cgh %r2, 524286(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, i64 100, i64 200 @@ -37,8 +37,8 @@ define void @f3(i64 %lhs, i16 *%src, i64 *%dst) { ; CHECK: agfi %r3, 524288 ; CHECK: cgh %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, i64 100, i64 200 @@ -51,8 +51,8 @@ define void @f4(i64 %lhs, i16 *%src, i64 *%dst) { ; CHECK-LABEL: f4: ; CHECK: cgh %r2, -2(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, i64 100, i64 200 @@ -65,8 +65,8 @@ define void @f5(i64 %lhs, i16 *%src, i64 *%dst) { ; CHECK-LABEL: f5: ; CHECK: cgh %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, i64 100, i64 200 @@ -81,8 +81,8 @@ define void @f6(i64 %lhs, i16 *%src, i64 *%dst) { ; CHECK: agfi %r3, -524290 ; CHECK: cgh %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, i64 100, i64 200 @@ -98,7 +98,7 @@ define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, i64 100, i64 200 @@ -113,7 +113,7 @@ define double @f8(double %a, double %b, i64 %rhs, i16 *%src) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %lhs = sext i16 %half to i64 %cond = icmp slt i64 %lhs, %rhs %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-05.ll b/test/CodeGen/SystemZ/int-cmp-05.ll index 0be43a3ef1bf..70640b607bcd 100644 --- a/test/CodeGen/SystemZ/int-cmp-05.ll +++ b/test/CodeGen/SystemZ/int-cmp-05.ll @@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f6: ; CHECK-NOT: cgf ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -87,7 +87,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp eq i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -101,7 +101,7 @@ define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-NEXT: jlh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp ne i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -115,8 +115,8 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131071 + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -132,8 +132,8 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131072 + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -147,8 +147,8 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -1 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -1 + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -162,8 +162,8 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131072 + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -179,8 +179,8 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131073 + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -197,7 +197,7 @@ define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -210,26 +210,26 @@ define i64 @f15(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: cgf {{%r[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %frob0 = add i32 %val0, 100 %frob1 = add i32 %val1, 100 @@ -311,7 +311,7 @@ define double @f17(double %a, double %b, i64 %i2, i32 *%ptr) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i1 = sext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-06.ll b/test/CodeGen/SystemZ/int-cmp-06.ll index 82007e221766..16c2ade83553 100644 --- a/test/CodeGen/SystemZ/int-cmp-06.ll +++ b/test/CodeGen/SystemZ/int-cmp-06.ll @@ -111,7 +111,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -123,7 +123,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: clgf ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -137,7 +137,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp eq i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -151,7 +151,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) { ; CHECK-NEXT: jlh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ne i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -165,8 +165,8 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131071 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131071 + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -182,8 +182,8 @@ define double @f14(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 131072 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 131072 + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -197,8 +197,8 @@ define double @f15(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -1 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -1 + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -212,8 +212,8 @@ define double @f16(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131072 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131072 + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -229,8 +229,8 @@ define double @f17(double %a, double %b, i64 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -131073 - %unext = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -131073 + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -247,7 +247,7 @@ define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i2 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b @@ -260,26 +260,26 @@ define i64 @f19(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: clgf {{%r[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %frob0 = add i32 %val0, 100 %frob1 = add i32 %val1, 100 @@ -374,7 +374,7 @@ define double @f22(double %a, double %b, i64 %i2, i32 *%ptr) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %unext = load i32 *%ptr + %unext = load i32 , i32 *%ptr %i1 = zext i32 %unext to i64 %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-07.ll b/test/CodeGen/SystemZ/int-cmp-07.ll index 530d1787a770..0a787c9ea01d 100644 --- a/test/CodeGen/SystemZ/int-cmp-07.ll +++ b/test/CodeGen/SystemZ/int-cmp-07.ll @@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i2 = load i64 *%ptr + %i2 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -33,8 +33,8 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65535 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 65535 + %i2 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -49,8 +49,8 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65536 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 65536 + %i2 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -63,8 +63,8 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -1 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -1 + %i2 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -77,8 +77,8 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65536 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -65536 + %i2 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -93,8 +93,8 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65537 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -65537 + %i2 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %i2 = load i64 *%ptr + %i2 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -123,7 +123,7 @@ define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i1 = load i64 *%ptr + %i1 = load i64 , i64 *%ptr %cond = icmp slt i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-08.ll b/test/CodeGen/SystemZ/int-cmp-08.ll index ebf158a1144b..384b41b549b9 100644 --- a/test/CodeGen/SystemZ/int-cmp-08.ll +++ b/test/CodeGen/SystemZ/int-cmp-08.ll @@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i2 = load i64 *%ptr + %i2 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -33,8 +33,8 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65535 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 65535 + %i2 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -49,8 +49,8 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 65536 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 65536 + %i2 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -63,8 +63,8 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -1 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -1 + %i2 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -77,8 +77,8 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65536 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -65536 + %i2 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -93,8 +93,8 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -65537 - %i2 = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -65537 + %i2 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %i2 = load i64 *%ptr + %i2 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res @@ -123,7 +123,7 @@ define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %i1 = load i64 *%ptr + %i1 = load i64 , i64 *%ptr %cond = icmp ult i64 %i1, %i2 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-12.ll b/test/CodeGen/SystemZ/int-cmp-12.ll index 077b22423e06..d9c6a9fc4efc 100644 --- a/test/CodeGen/SystemZ/int-cmp-12.ll +++ b/test/CodeGen/SystemZ/int-cmp-12.ll @@ -49,13 +49,24 @@ define double @f4(double %a, double %b, i64 %i1) { ret double %res } -; Check the next value up, which must use a register comparison. +; Check the next value up, which can use a shifted comparison define double @f5(double %a, double %b, i64 %i1) { ; CHECK-LABEL: f5: -; CHECK: clgrjl %r2, +; CHECK: srlg [[REG:%r[0-5]]], %r2, 32 +; CHECK: cgije [[REG]], 0 ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 %cond = icmp ult i64 %i1, 4294967296 %res = select i1 %cond, double %a, double %b ret double %res } +; Check the next value up, which must use a register comparison. +define double @f6(double %a, double %b, i64 %i1) { +; CHECK-LABEL: f6: +; CHECK: clgrjl %r2, +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ult i64 %i1, 4294967297 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-15.ll b/test/CodeGen/SystemZ/int-cmp-15.ll index 48a068e49e8f..3c1e052bc35f 100644 --- a/test/CodeGen/SystemZ/int-cmp-15.ll +++ b/test/CodeGen/SystemZ/int-cmp-15.ll @@ -8,7 +8,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp ugt i8 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -20,7 +20,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 254 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 254 %res = select i1 %cond, double %a, double %b ret double %res @@ -32,7 +32,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp slt i8 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -44,7 +44,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp sle i8 %val, -1 %res = select i1 %cond, double %a, double %b ret double %res @@ -56,7 +56,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp sge i8 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -68,7 +68,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp sgt i8 %val, -1 %res = select i1 %cond, double %a, double %b ret double %res @@ -80,7 +80,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, -128 %res = select i1 %cond, double %a, double %b ret double %res @@ -92,7 +92,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -104,7 +104,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -116,7 +116,7 @@ define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp eq i8 %val, 255 %res = select i1 %cond, double %a, double %b ret double %res @@ -127,8 +127,8 @@ define double @f11(double %a, double %b, i8 *%src) { ; CHECK-LABEL: f11: ; CHECK: cli 4095(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4095 + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -139,8 +139,8 @@ define double @f12(double %a, double %b, i8 *%src) { ; CHECK-LABEL: f12: ; CHECK: cliy 4096(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4096 + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -151,8 +151,8 @@ define double @f13(double %a, double %b, i8 *%src) { ; CHECK-LABEL: f13: ; CHECK: cliy 524287(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -165,8 +165,8 @@ define double @f14(double %a, double %b, i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: cli 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -177,8 +177,8 @@ define double @f15(double %a, double %b, i8 *%src) { ; CHECK-LABEL: f15: ; CHECK: cliy -1(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -189,8 +189,8 @@ define double @f16(double %a, double %b, i8 *%src) { ; CHECK-LABEL: f16: ; CHECK: cliy -524288(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -203,8 +203,8 @@ define double @f17(double %a, double %b, i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: cli 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -219,7 +219,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4095 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res @@ -234,7 +234,7 @@ define double @f19(double %a, double %b, i64 %base, i64 %index) { %add1 = add i64 %base, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %cond = icmp ult i8 %val, 127 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-16.ll b/test/CodeGen/SystemZ/int-cmp-16.ll index be206d9c9470..37508b5e740f 100644 --- a/test/CodeGen/SystemZ/int-cmp-16.ll +++ b/test/CodeGen/SystemZ/int-cmp-16.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp eq i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp eq i32 %ext, 255 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp eq i32 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp eq i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp eq i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp eq i32 %ext, 127 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp eq i32 %ext, 128 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp eq i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp eq i32 %ext, -128 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp eq i32 %ext, -129 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-17.ll b/test/CodeGen/SystemZ/int-cmp-17.ll index 3df4ecc66803..a22fb604d453 100644 --- a/test/CodeGen/SystemZ/int-cmp-17.ll +++ b/test/CodeGen/SystemZ/int-cmp-17.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp ne i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp ne i32 %ext, 255 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp ne i32 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp ne i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ne i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ne i32 %ext, 127 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ne i32 %ext, 128 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ne i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ne i32 %ext, -128 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ne i32 %ext, -129 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-18.ll b/test/CodeGen/SystemZ/int-cmp-18.ll index d03d6ac9a2c7..f4bc5c0e5ce9 100644 --- a/test/CodeGen/SystemZ/int-cmp-18.ll +++ b/test/CodeGen/SystemZ/int-cmp-18.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp eq i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp eq i64 %ext, 255 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp eq i64 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp eq i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp eq i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp eq i64 %ext, 127 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp eq i64 %ext, 128 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp eq i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp eq i64 %ext, -128 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp eq i64 %ext, -129 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-19.ll b/test/CodeGen/SystemZ/int-cmp-19.ll index b5f0856b4002..0a23f06a0581 100644 --- a/test/CodeGen/SystemZ/int-cmp-19.ll +++ b/test/CodeGen/SystemZ/int-cmp-19.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp ne i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp ne i64 %ext, 255 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp ne i64 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp ne i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ne i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ne i64 %ext, 127 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ne i64 %ext, 128 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 255 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ne i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ne i64 %ext, -128 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ne i64 %ext, -129 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-20.ll b/test/CodeGen/SystemZ/int-cmp-20.ll index 98c41cd3a240..2acff55af59c 100644 --- a/test/CodeGen/SystemZ/int-cmp-20.ll +++ b/test/CodeGen/SystemZ/int-cmp-20.ll @@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp ugt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ugt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 254 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp ult i32 %ext, 254 %res = select i1 %cond, double %a, double %b @@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 254 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ult i32 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK-NOT: cli {{.*}} ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp ult i32 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -81,7 +81,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK-NOT: cli {{.*}} ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ult i32 %ext, 128 %res = select i1 %cond, double %a, double %b @@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: cli {{.*}} ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp ult i32 %ext, -129 %res = select i1 %cond, double %a, double %b @@ -107,7 +107,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp sgt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -120,7 +120,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f9: ; CHECK-NOT: cli {{.*}} ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp sgt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -134,7 +134,7 @@ define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 254 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp slt i32 %ext, 254 %res = select i1 %cond, double %a, double %b @@ -147,7 +147,7 @@ define double @f11(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f11: ; CHECK-NOT: cli {{.*}} ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp slt i32 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -160,7 +160,7 @@ define double @f12(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f12: ; CHECK-NOT: cli {{.*}} ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %cond = icmp slt i32 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -173,7 +173,7 @@ define double @f13(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp sge i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -186,7 +186,7 @@ define double @f14(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp sgt i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -199,7 +199,7 @@ define double @f15(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp slt i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -212,7 +212,7 @@ define double @f16(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %cond = icmp sle i32 %ext, -1 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-21.ll b/test/CodeGen/SystemZ/int-cmp-21.ll index ca9225dead92..5be97324f643 100644 --- a/test/CodeGen/SystemZ/int-cmp-21.ll +++ b/test/CodeGen/SystemZ/int-cmp-21.ll @@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp ugt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ugt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 254 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp ult i64 %ext, 254 %res = select i1 %cond, double %a, double %b @@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 254 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ult i64 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp ult i64 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -81,7 +81,7 @@ define double @f6(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ult i64 %ext, 128 %res = select i1 %cond, double %a, double %b @@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp ult i64 %ext, -129 %res = select i1 %cond, double %a, double %b @@ -107,7 +107,7 @@ define double @f8(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp sgt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -120,7 +120,7 @@ define double @f9(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f9: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp sgt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -134,7 +134,7 @@ define double @f10(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 254 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp slt i64 %ext, 254 %res = select i1 %cond, double %a, double %b @@ -147,7 +147,7 @@ define double @f11(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f11: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp slt i64 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -160,7 +160,7 @@ define double @f12(double %a, double %b, i8 *%ptr) { ; CHECK-LABEL: f12: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %cond = icmp slt i64 %ext, 256 %res = select i1 %cond, double %a, double %b @@ -173,7 +173,7 @@ define double @f13(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp sge i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -186,7 +186,7 @@ define double @f14(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 128 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp sgt i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -199,7 +199,7 @@ define double @f15(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp slt i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -212,7 +212,7 @@ define double @f16(double %a, double %b, i8 *%ptr) { ; CHECK: cli 0(%r2), 127 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %cond = icmp sle i64 %ext, -1 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-22.ll b/test/CodeGen/SystemZ/int-cmp-22.ll index 43daec95b7d8..f29023cf02ae 100644 --- a/test/CodeGen/SystemZ/int-cmp-22.ll +++ b/test/CodeGen/SystemZ/int-cmp-22.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jle ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, 32766 %res = select i1 %cond, double %a, double %b ret double %res @@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, -1 %res = select i1 %cond, double %a, double %b ret double %res @@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, -32766 %res = select i1 %cond, double %a, double %b ret double %res @@ -74,8 +74,8 @@ define double @f6(double %a, double %b, i16 %i1, i16 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 2047 - %val = load i16 *%ptr + %ptr = getelementptr i16, i16 *%base, i64 2047 + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -89,8 +89,8 @@ define double @f7(double %a, double %b, i16 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 2048 - %val = load i16 *%ptr + %ptr = getelementptr i16, i16 *%base, i64 2048 + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -104,8 +104,8 @@ define double @f8(double %a, double %b, i16 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 -1 - %val = load i16 *%ptr + %ptr = getelementptr i16, i16 *%base, i64 -1 + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -121,7 +121,7 @@ define double @f9(double %a, double %b, i64 %base, i64 %index) { ; CHECK: br %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i16 * - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp slt i16 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-23.ll b/test/CodeGen/SystemZ/int-cmp-23.ll index 99fe74b1c787..df6b62616a79 100644 --- a/test/CodeGen/SystemZ/int-cmp-23.ll +++ b/test/CodeGen/SystemZ/int-cmp-23.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp ugt i16 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp ult i16 %val, 65534 %res = select i1 %cond, double %a, double %b ret double %res @@ -35,8 +35,8 @@ define double @f3(double %a, double %b, i16 %i1, i16 *%base) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 2047 - %val = load i16 *%ptr + %ptr = getelementptr i16, i16 *%base, i64 2047 + %val = load i16 , i16 *%ptr %cond = icmp ugt i16 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -50,8 +50,8 @@ define double @f4(double %a, double %b, i16 *%base) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 2048 - %val = load i16 *%ptr + %ptr = getelementptr i16, i16 *%base, i64 2048 + %val = load i16 , i16 *%ptr %cond = icmp ugt i16 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -65,8 +65,8 @@ define double @f5(double %a, double %b, i16 *%base) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i16 *%base, i64 -1 - %val = load i16 *%ptr + %ptr = getelementptr i16, i16 *%base, i64 -1 + %val = load i16 , i16 *%ptr %cond = icmp ugt i16 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i64 %base, i64 %index) { ; CHECK: br %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i16 * - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp ugt i16 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-24.ll b/test/CodeGen/SystemZ/int-cmp-24.ll index 1a8e587b0341..e1141a78ddda 100644 --- a/test/CodeGen/SystemZ/int-cmp-24.ll +++ b/test/CodeGen/SystemZ/int-cmp-24.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp eq i16 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp eq i16 %val, 65535 %res = select i1 %cond, double %a, double %b ret double %res @@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp eq i16 %val, -32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp eq i16 %val, 32767 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-25.ll b/test/CodeGen/SystemZ/int-cmp-25.ll index 50803df1ba91..268530316506 100644 --- a/test/CodeGen/SystemZ/int-cmp-25.ll +++ b/test/CodeGen/SystemZ/int-cmp-25.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jlh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp ne i16 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jlh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp ne i16 %val, 65535 %res = select i1 %cond, double %a, double %b ret double %res @@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jlh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp ne i16 %val, -32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-NEXT: jlh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %cond = icmp ne i16 %val, 32767 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-26.ll b/test/CodeGen/SystemZ/int-cmp-26.ll index 60778654b275..ba93f081e9b9 100644 --- a/test/CodeGen/SystemZ/int-cmp-26.ll +++ b/test/CodeGen/SystemZ/int-cmp-26.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp eq i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp eq i32 %ext, 65535 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp eq i32 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp eq i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp eq i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32767 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp eq i32 %ext, 32767 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp eq i32 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp eq i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32768 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp eq i32 %ext, -32768 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp eq i32 %ext, -32769 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-27.ll b/test/CodeGen/SystemZ/int-cmp-27.ll index 3102f5c5faa4..9a503c9254a2 100644 --- a/test/CodeGen/SystemZ/int-cmp-27.ll +++ b/test/CodeGen/SystemZ/int-cmp-27.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp ne i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp ne i32 %ext, 65535 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp ne i32 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp ne i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ne i32 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32767 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ne i32 %ext, 32767 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ne i32 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ne i32 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32768 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ne i32 %ext, -32768 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ne i32 %ext, -32769 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-28.ll b/test/CodeGen/SystemZ/int-cmp-28.ll index c3b905974ebc..68f1cd28c62d 100644 --- a/test/CodeGen/SystemZ/int-cmp-28.ll +++ b/test/CodeGen/SystemZ/int-cmp-28.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp eq i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp eq i64 %ext, 65535 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp eq i64 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp eq i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp eq i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32767 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp eq i64 %ext, 32767 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp eq i64 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp eq i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32768 ; CHECK-NEXT: je ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp eq i64 %ext, -32768 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp eq i64 %ext, -32769 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-29.ll b/test/CodeGen/SystemZ/int-cmp-29.ll index 1b40d8cfb2ae..4fb2e8577699 100644 --- a/test/CodeGen/SystemZ/int-cmp-29.ll +++ b/test/CodeGen/SystemZ/int-cmp-29.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp ne i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp ne i64 %ext, 65535 %res = select i1 %cond, double %a, double %b @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp ne i64 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -47,7 +47,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp ne i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -60,7 +60,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 0 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ne i64 %ext, 0 %res = select i1 %cond, double %a, double %b @@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32767 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ne i64 %ext, 32767 %res = select i1 %cond, double %a, double %b @@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ne i64 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -99,7 +99,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65535 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ne i64 %ext, -1 %res = select i1 %cond, double %a, double %b @@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 32768 ; CHECK-NEXT: jlh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ne i64 %ext, -32768 %res = select i1 %cond, double %a, double %b @@ -125,7 +125,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f10: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ne i64 %ext, -32769 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-30.ll b/test/CodeGen/SystemZ/int-cmp-30.ll index 6c9498cb3320..043ff484c145 100644 --- a/test/CodeGen/SystemZ/int-cmp-30.ll +++ b/test/CodeGen/SystemZ/int-cmp-30.ll @@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp ugt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ugt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65534 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp ult i32 %ext, 65534 %res = select i1 %cond, double %a, double %b @@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65534 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ult i32 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f5: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp ult i32 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f6: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ult i32 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp ult i32 %ext, -32769 %res = select i1 %cond, double %a, double %b @@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp sgt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp sgt i32 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -136,7 +136,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65534 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp slt i32 %ext, 65534 %res = select i1 %cond, double %a, double %b @@ -150,7 +150,7 @@ define double @f11(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), -2 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp slt i32 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -163,7 +163,7 @@ define double @f12(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f12: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i32 %cond = icmp slt i32 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -177,7 +177,7 @@ define double @f13(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), 32766 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp slt i32 %ext, 32766 %res = select i1 %cond, double %a, double %b @@ -190,7 +190,7 @@ define double @f14(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f14: ; CHECK-NOT: chhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp slt i32 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -204,7 +204,7 @@ define double @f15(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), -32767 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp sgt i32 %ext, -32767 %res = select i1 %cond, double %a, double %b @@ -217,7 +217,7 @@ define double @f16(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f16: ; CHECK-NOT: chhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i32 %cond = icmp sgt i32 %ext, -32769 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-31.ll b/test/CodeGen/SystemZ/int-cmp-31.ll index 21539f20470e..298b446e7f1d 100644 --- a/test/CodeGen/SystemZ/int-cmp-31.ll +++ b/test/CodeGen/SystemZ/int-cmp-31.ll @@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp ugt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -24,7 +24,7 @@ define double @f2(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ugt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65534 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp ult i64 %ext, 65534 %res = select i1 %cond, double %a, double %b @@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65534 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ult i64 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -65,7 +65,7 @@ define double @f5(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f5: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp ult i64 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f6: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ult i64 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: clhhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp ult i64 %ext, -32769 %res = select i1 %cond, double %a, double %b @@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp sgt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), 1 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp sgt i64 %ext, 1 %res = select i1 %cond, double %a, double %b @@ -136,7 +136,7 @@ define double @f10(double %a, double %b, i16 *%ptr) { ; CHECK: clhhsi 0(%r2), 65534 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp slt i64 %ext, 65534 %res = select i1 %cond, double %a, double %b @@ -150,7 +150,7 @@ define double @f11(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), -2 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp slt i64 %ext, -2 %res = select i1 %cond, double %a, double %b @@ -163,7 +163,7 @@ define double @f12(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f12: ; CHECK-NOT: cli ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = zext i16 %val to i64 %cond = icmp slt i64 %ext, 65536 %res = select i1 %cond, double %a, double %b @@ -177,7 +177,7 @@ define double @f13(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), 32766 ; CHECK-NEXT: jl ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp slt i64 %ext, 32766 %res = select i1 %cond, double %a, double %b @@ -190,7 +190,7 @@ define double @f14(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f14: ; CHECK-NOT: chhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp slt i64 %ext, 32768 %res = select i1 %cond, double %a, double %b @@ -204,7 +204,7 @@ define double @f15(double %a, double %b, i16 *%ptr) { ; CHECK: chhsi 0(%r2), -32767 ; CHECK-NEXT: jh ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp sgt i64 %ext, -32767 %res = select i1 %cond, double %a, double %b @@ -217,7 +217,7 @@ define double @f16(double %a, double %b, i16 *%ptr) { ; CHECK-LABEL: f16: ; CHECK-NOT: chhsi ; CHECK: br %r14 - %val = load i16 *%ptr + %val = load i16 , i16 *%ptr %ext = sext i16 %val to i64 %cond = icmp sgt i64 %ext, -32769 %res = select i1 %cond, double %a, double %b diff --git a/test/CodeGen/SystemZ/int-cmp-32.ll b/test/CodeGen/SystemZ/int-cmp-32.ll index 6596f9f3ad84..da0e2d7562dd 100644 --- a/test/CodeGen/SystemZ/int-cmp-32.ll +++ b/test/CodeGen/SystemZ/int-cmp-32.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: jle ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 32767 %res = select i1 %cond, double %a, double %b ret double %res @@ -46,7 +46,7 @@ define double @f4(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: chsi ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -59,7 +59,7 @@ define double @f5(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, -1 %res = select i1 %cond, double %a, double %b ret double %res @@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, -32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -83,7 +83,7 @@ define double @f7(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: chsi ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, -32769 %res = select i1 %cond, double %a, double %b ret double %res @@ -96,7 +96,7 @@ define double @f8(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -122,7 +122,7 @@ define double @f10(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, 32767 %res = select i1 %cond, double %a, double %b ret double %res @@ -133,7 +133,7 @@ define double @f11(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f11: ; CHECK-NOT: chsi ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, 32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -146,7 +146,7 @@ define double @f12(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, -1 %res = select i1 %cond, double %a, double %b ret double %res @@ -159,7 +159,7 @@ define double @f13(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, -32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -170,7 +170,7 @@ define double @f14(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f14: ; CHECK-NOT: chsi ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, -32769 %res = select i1 %cond, double %a, double %b ret double %res @@ -183,8 +183,8 @@ define double @f15(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1023 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1023 + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -198,8 +198,8 @@ define double @f16(double %a, double %b, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1024 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1024 + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -213,8 +213,8 @@ define double @f17(double %a, double %b, i32 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -1 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -1 + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -230,7 +230,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) { ; CHECK: br %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i32 * - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp slt i32 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-33.ll b/test/CodeGen/SystemZ/int-cmp-33.ll index e5a653b3815d..94f3e705391e 100644 --- a/test/CodeGen/SystemZ/int-cmp-33.ll +++ b/test/CodeGen/SystemZ/int-cmp-33.ll @@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp ugt i32 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -23,7 +23,7 @@ define double @f2(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp ult i32 %val, 65535 %res = select i1 %cond, double %a, double %b ret double %res @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: clfhsi ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp ult i32 %val, 65536 %res = select i1 %cond, double %a, double %b ret double %res @@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, 32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i32 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, 65535 %res = select i1 %cond, double %a, double %b ret double %res @@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i32 *%ptr) { ; CHECK-LABEL: f6: ; CHECK-NOT: clfhsi ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp eq i32 %val, 65536 %res = select i1 %cond, double %a, double %b ret double %res @@ -85,8 +85,8 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1023 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1023 + %val = load i32 , i32 *%ptr %cond = icmp ugt i32 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -100,8 +100,8 @@ define double @f8(double %a, double %b, i32 *%base) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 1024 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 1024 + %val = load i32 , i32 *%ptr %cond = icmp ugt i32 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -115,8 +115,8 @@ define double @f9(double %a, double %b, i32 *%base) { ; CHECK-NEXT: jh ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i32 *%base, i64 -1 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%base, i64 -1 + %val = load i32 , i32 *%ptr %cond = icmp ugt i32 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -132,7 +132,7 @@ define double @f10(double %a, double %b, i64 %base, i64 %index) { ; CHECK: br %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i32 * - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %cond = icmp ugt i32 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-34.ll b/test/CodeGen/SystemZ/int-cmp-34.ll index 8a0219775a4e..114b694a3b09 100644 --- a/test/CodeGen/SystemZ/int-cmp-34.ll +++ b/test/CodeGen/SystemZ/int-cmp-34.ll @@ -9,7 +9,7 @@ define double @f1(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -22,7 +22,7 @@ define double @f2(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: jle ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -35,7 +35,7 @@ define double @f3(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 32767 %res = select i1 %cond, double %a, double %b ret double %res @@ -46,7 +46,7 @@ define double @f4(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f4: ; CHECK-NOT: cghsi ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -59,7 +59,7 @@ define double @f5(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, -1 %res = select i1 %cond, double %a, double %b ret double %res @@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, -32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -83,7 +83,7 @@ define double @f7(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f7: ; CHECK-NOT: cghsi ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, -32769 %res = select i1 %cond, double %a, double %b ret double %res @@ -96,7 +96,7 @@ define double @f8(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, 1 %res = select i1 %cond, double %a, double %b ret double %res @@ -122,7 +122,7 @@ define double @f10(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, 32767 %res = select i1 %cond, double %a, double %b ret double %res @@ -133,7 +133,7 @@ define double @f11(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f11: ; CHECK-NOT: cghsi ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, 32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -146,7 +146,7 @@ define double @f12(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, -1 %res = select i1 %cond, double %a, double %b ret double %res @@ -159,7 +159,7 @@ define double @f13(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, -32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -170,7 +170,7 @@ define double @f14(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f14: ; CHECK-NOT: cghsi ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, -32769 %res = select i1 %cond, double %a, double %b ret double %res @@ -183,8 +183,8 @@ define double @f15(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 511 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 511 + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -198,8 +198,8 @@ define double @f16(double %a, double %b, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 512 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 512 + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -213,8 +213,8 @@ define double @f17(double %a, double %b, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -1 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -1 + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res @@ -230,7 +230,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) { ; CHECK: br %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i64 * - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp slt i64 %val, 0 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-35.ll b/test/CodeGen/SystemZ/int-cmp-35.ll index 539248a86a7b..0eaf4fa0a075 100644 --- a/test/CodeGen/SystemZ/int-cmp-35.ll +++ b/test/CodeGen/SystemZ/int-cmp-35.ll @@ -10,7 +10,7 @@ define double @f1(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp ult i64 %val, 2 %res = select i1 %cond, double %a, double %b ret double %res @@ -23,7 +23,7 @@ define double @f2(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp ult i64 %val, 65535 %res = select i1 %cond, double %a, double %b ret double %res @@ -34,7 +34,7 @@ define double @f3(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f3: ; CHECK-NOT: clghsi ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp ult i64 %val, 65536 %res = select i1 %cond, double %a, double %b ret double %res @@ -48,7 +48,7 @@ define double @f4(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, 32768 %res = select i1 %cond, double %a, double %b ret double %res @@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i64 *%ptr) { ; CHECK-NEXT: je ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, 65535 %res = select i1 %cond, double %a, double %b ret double %res @@ -72,7 +72,7 @@ define double @f6(double %a, double %b, i64 *%ptr) { ; CHECK-LABEL: f6: ; CHECK-NOT: clghsi ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp eq i64 %val, 65536 %res = select i1 %cond, double %a, double %b ret double %res @@ -85,8 +85,8 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 511 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 511 + %val = load i64 , i64 *%ptr %cond = icmp ult i64 %val, 2 %res = select i1 %cond, double %a, double %b ret double %res @@ -100,8 +100,8 @@ define double @f8(double %a, double %b, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 512 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 512 + %val = load i64 , i64 *%ptr %cond = icmp ult i64 %val, 2 %res = select i1 %cond, double %a, double %b ret double %res @@ -115,8 +115,8 @@ define double @f9(double %a, double %b, i64 *%base) { ; CHECK-NEXT: jl ; CHECK: ldr %f0, %f2 ; CHECK: br %r14 - %ptr = getelementptr i64 *%base, i64 -1 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%base, i64 -1 + %val = load i64 , i64 *%ptr %cond = icmp ult i64 %val, 2 %res = select i1 %cond, double %a, double %b ret double %res @@ -132,7 +132,7 @@ define double @f10(double %a, double %b, i64 %base, i64 %index) { ; CHECK: br %r14 %add = add i64 %base, %index %ptr = inttoptr i64 %add to i64 * - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr %cond = icmp ult i64 %val, 2 %res = select i1 %cond, double %a, double %b ret double %res diff --git a/test/CodeGen/SystemZ/int-cmp-36.ll b/test/CodeGen/SystemZ/int-cmp-36.ll index fa2d4bf6c617..113d2c1587e0 100644 --- a/test/CodeGen/SystemZ/int-cmp-36.ll +++ b/test/CodeGen/SystemZ/int-cmp-36.ll @@ -13,7 +13,7 @@ define i32 @f1(i32 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i32 %cond = icmp slt i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -31,7 +31,7 @@ define i32 @f2(i32 %src1) { ; CHECK-NOT: chrl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i32 %cond = icmp ult i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -50,7 +50,7 @@ define i32 @f3(i32 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i32 %cond = icmp eq i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -69,7 +69,7 @@ define i32 @f4(i32 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i32 %cond = icmp ne i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -89,7 +89,7 @@ define i32 @f5(i32 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i16 *@h, align 1 + %val = load i16 , i16 *@h, align 1 %src2 = sext i16 %val to i32 %cond = icmp slt i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -108,7 +108,7 @@ define i32 @f6(i32 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src1 = sext i16 %val to i32 %cond = icmp slt i32 %src1, %src2 br i1 %cond, label %exit, label %mulb diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll index 8095ed173012..ac5d39f96511 100644 --- a/test/CodeGen/SystemZ/int-cmp-37.ll +++ b/test/CodeGen/SystemZ/int-cmp-37.ll @@ -13,7 +13,7 @@ define i32 @f1(i32 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i32 %cond = icmp ult i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -31,7 +31,7 @@ define i32 @f2(i32 %src1) { ; CHECK-NOT: clhrl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i32 %cond = icmp slt i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -50,7 +50,7 @@ define i32 @f3(i32 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i32 %cond = icmp eq i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -69,7 +69,7 @@ define i32 @f4(i32 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i32 %cond = icmp ne i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -89,7 +89,7 @@ define i32 @f5(i32 %src1) { ; CHECK: clrjl %r2, [[VAL]], ; CHECK: br %r14 entry: - %val = load i16 *@h, align 1 + %val = load i16 , i16 *@h, align 1 %src2 = zext i16 %val to i32 %cond = icmp ult i32 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -108,7 +108,7 @@ define i32 @f6(i32 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src1 = zext i16 %val to i32 %cond = icmp ult i32 %src1, %src2 br i1 %cond, label %exit, label %mulb diff --git a/test/CodeGen/SystemZ/int-cmp-38.ll b/test/CodeGen/SystemZ/int-cmp-38.ll index 901758378729..0d8913b02861 100644 --- a/test/CodeGen/SystemZ/int-cmp-38.ll +++ b/test/CodeGen/SystemZ/int-cmp-38.ll @@ -13,7 +13,7 @@ define i32 @f1(i32 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %src2 = load i32 *@g + %src2 = load i32 , i32 *@g %cond = icmp slt i32 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -31,7 +31,7 @@ define i32 @f2(i32 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %src2 = load i32 *@g + %src2 = load i32 , i32 *@g %cond = icmp ult i32 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -49,7 +49,7 @@ define i32 @f3(i32 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %src2 = load i32 *@g + %src2 = load i32 , i32 *@g %cond = icmp eq i32 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -67,7 +67,7 @@ define i32 @f4(i32 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %src2 = load i32 *@g + %src2 = load i32 , i32 *@g %cond = icmp ne i32 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -86,7 +86,7 @@ define i32 @f5(i32 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %src2 = load i32 *@h, align 2 + %src2 = load i32 , i32 *@h, align 2 %cond = icmp slt i32 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -105,7 +105,7 @@ define i32 @f6(i32 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %src2 = load i32 *@h, align 2 + %src2 = load i32 , i32 *@h, align 2 %cond = icmp ult i32 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -123,7 +123,7 @@ define i32 @f7(i32 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %src1 = load i32 *@g + %src1 = load i32 , i32 *@g %cond = icmp slt i32 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: diff --git a/test/CodeGen/SystemZ/int-cmp-39.ll b/test/CodeGen/SystemZ/int-cmp-39.ll index fc9547d4ceb4..5e3abceeca45 100644 --- a/test/CodeGen/SystemZ/int-cmp-39.ll +++ b/test/CodeGen/SystemZ/int-cmp-39.ll @@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) { ; CHECK-NOT: cghrl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i64 %cond = icmp eq i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = sext i16 %val to i64 %cond = icmp ne i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i16 *@h, align 1 + %val = load i16 , i16 *@h, align 1 %src2 = sext i16 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src1 = sext i16 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb diff --git a/test/CodeGen/SystemZ/int-cmp-40.ll b/test/CodeGen/SystemZ/int-cmp-40.ll index 9c532f1cbc6b..92696d71fc48 100644 --- a/test/CodeGen/SystemZ/int-cmp-40.ll +++ b/test/CodeGen/SystemZ/int-cmp-40.ll @@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) { ; CHECK-NOT: clghrl ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i64 %cond = icmp eq i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src2 = zext i16 %val to i64 %cond = icmp ne i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) { ; CHECK: clgrjl %r2, [[VAL]], ; CHECK: br %r14 entry: - %val = load i16 *@h, align 1 + %val = load i16 , i16 *@h, align 1 %src2 = zext i16 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %val = load i16 *@g + %val = load i16 , i16 *@g %src1 = zext i16 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb diff --git a/test/CodeGen/SystemZ/int-cmp-41.ll b/test/CodeGen/SystemZ/int-cmp-41.ll index 77f6e7d76f1c..f4f5b4a0cf16 100644 --- a/test/CodeGen/SystemZ/int-cmp-41.ll +++ b/test/CodeGen/SystemZ/int-cmp-41.ll @@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = sext i32 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) { ; CHECK-NOT: cgfrl ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = sext i32 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = sext i32 %val to i64 %cond = icmp eq i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = sext i32 %val to i64 %cond = icmp ne i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i32 *@h, align 2 + %val = load i32 , i32 *@h, align 2 %src2 = sext i32 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src1 = sext i32 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb diff --git a/test/CodeGen/SystemZ/int-cmp-42.ll b/test/CodeGen/SystemZ/int-cmp-42.ll index 94ef0082c441..ca87b865ad14 100644 --- a/test/CodeGen/SystemZ/int-cmp-42.ll +++ b/test/CodeGen/SystemZ/int-cmp-42.ll @@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = zext i32 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) { ; CHECK-NOT: clgfrl ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = zext i32 %val to i64 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -50,7 +50,7 @@ define i64 @f3(i64 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = zext i32 %val to i64 %cond = icmp eq i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -69,7 +69,7 @@ define i64 @f4(i64 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src2 = zext i32 %val to i64 %cond = icmp ne i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -89,7 +89,7 @@ define i64 @f5(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %val = load i32 *@h, align 2 + %val = load i32 , i32 *@h, align 2 %src2 = zext i32 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb @@ -108,7 +108,7 @@ define i64 @f6(i64 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %val = load i32 *@g + %val = load i32 , i32 *@g %src1 = zext i32 %val to i64 %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb diff --git a/test/CodeGen/SystemZ/int-cmp-43.ll b/test/CodeGen/SystemZ/int-cmp-43.ll index 1a625886dec2..108b041fa377 100644 --- a/test/CodeGen/SystemZ/int-cmp-43.ll +++ b/test/CodeGen/SystemZ/int-cmp-43.ll @@ -13,7 +13,7 @@ define i64 @f1(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %src2 = load i64 *@g + %src2 = load i64 , i64 *@g %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -31,7 +31,7 @@ define i64 @f2(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %src2 = load i64 *@g + %src2 = load i64 , i64 *@g %cond = icmp ult i64 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -49,7 +49,7 @@ define i64 @f3(i64 %src1) { ; CHECK-NEXT: je ; CHECK: br %r14 entry: - %src2 = load i64 *@g + %src2 = load i64 , i64 *@g %cond = icmp eq i64 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -67,7 +67,7 @@ define i64 @f4(i64 %src1) { ; CHECK-NEXT: jlh ; CHECK: br %r14 entry: - %src2 = load i64 *@g + %src2 = load i64 , i64 *@g %cond = icmp ne i64 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -86,7 +86,7 @@ define i64 @f5(i64 %src1) { ; CHECK-NEXT: jl ; CHECK: br %r14 entry: - %src2 = load i64 *@h, align 4 + %src2 = load i64 , i64 *@h, align 4 %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: @@ -104,7 +104,7 @@ define i64 @f6(i64 %src2) { ; CHECK-NEXT: jh {{\.L.*}} ; CHECK: br %r14 entry: - %src1 = load i64 *@g + %src1 = load i64 , i64 *@g %cond = icmp slt i64 %src1, %src2 br i1 %cond, label %exit, label %mulb mulb: diff --git a/test/CodeGen/SystemZ/int-cmp-44.ll b/test/CodeGen/SystemZ/int-cmp-44.ll index 30c1c4f1ed6c..97d48521254d 100644 --- a/test/CodeGen/SystemZ/int-cmp-44.ll +++ b/test/CodeGen/SystemZ/int-cmp-44.ll @@ -127,7 +127,7 @@ define i32 @f7(i32 %a, i32 %b, i32 *%dest) { ; CHECK-NEXT: jne .L{{.*}} ; CHECK: br %r14 entry: - %cur = load i32 *%dest + %cur = load i32 , i32 *%dest %res = sub i32 %a, %cur %cmp = icmp ne i32 %res, 0 br i1 %cmp, label %exit, label %store @@ -147,7 +147,7 @@ define i32 @f8(i32 %a, i32 %b, i32 *%dest) { ; CHECK-NEXT: cijl %r2, 0, .L{{.*}} ; CHECK: br %r14 entry: - %cur = load i32 *%dest + %cur = load i32 , i32 *%dest %res = sub i32 %a, %cur %cmp = icmp slt i32 %res, 0 br i1 %cmp, label %exit, label %store @@ -468,7 +468,7 @@ define void @f24(i32 *%ptr) { ; CHECK-NEXT: cijlh [[REG]], 0, .L{{.*}} ; CHECK: br %r14 entry: - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %xor = xor i32 %val, 1 %add = add i32 %xor, 1000000 call void @foo() @@ -561,7 +561,7 @@ define void @f28(i64 %a, i64 *%dest) { ; CHECK: br %r14 entry: %ptr = inttoptr i64 %a to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 15 store i8 %xor, i8 *%ptr %cmp = icmp eq i64 %a, 0 @@ -584,7 +584,7 @@ define i32 @f29(i64 %base, i64 %index, i32 *%dest) { entry: %add = add i64 %base, %index %ptr = inttoptr i64 %add to i32 * - %res = load i32 *%ptr + %res = load i32 , i32 *%ptr %cmp = icmp sle i32 %res, 0 br i1 %cmp, label %exit, label %store @@ -606,7 +606,7 @@ entry: %add1 = add i64 %base, %index %add2 = add i64 %add1, 100000 %ptr = inttoptr i64 %add2 to i32 * - %res = load i32 *%ptr + %res = load i32 , i32 *%ptr %cmp = icmp sle i32 %res, 0 br i1 %cmp, label %exit, label %store @@ -627,7 +627,7 @@ define i64 @f31(i64 %base, i64 %index, i64 *%dest) { entry: %add = add i64 %base, %index %ptr = inttoptr i64 %add to i64 * - %res = load i64 *%ptr + %res = load i64 , i64 *%ptr %cmp = icmp sge i64 %res, 0 br i1 %cmp, label %exit, label %store @@ -648,7 +648,7 @@ define i64 @f32(i64 %base, i64 %index, i64 *%dest) { entry: %add = add i64 %base, %index %ptr = inttoptr i64 %add to i32 * - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %res = sext i32 %val to i64 %cmp = icmp sgt i64 %res, 0 br i1 %cmp, label %exit, label %store @@ -853,7 +853,7 @@ define i32 @f41(i32 %a, i32 %b, i32 *%dest) { ; CHECK-NEXT: jne .L{{.*}} ; CHECK: br %r14 entry: - %cur = load i32 *%dest + %cur = load i32 , i32 *%dest %res = sub i32 %a, %cur %cmp = icmp ne i32 %a, %cur br i1 %cmp, label %exit, label %store @@ -875,7 +875,7 @@ define i64 @f42(i64 %base, i64 %index, i64 *%dest) { entry: %add = add i64 %base, %index %ptr = inttoptr i64 %add to i32 * - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr %res = sext i32 %val to i64 %cmp = icmp sgt i32 %val, 0 br i1 %cmp, label %exit, label %store diff --git a/test/CodeGen/SystemZ/int-cmp-45.ll b/test/CodeGen/SystemZ/int-cmp-45.ll index c9affa672d54..e5474fa4863d 100644 --- a/test/CodeGen/SystemZ/int-cmp-45.ll +++ b/test/CodeGen/SystemZ/int-cmp-45.ll @@ -12,7 +12,7 @@ define i32 @f1(i32 %a, i32 %b, i32 *%cptr) { ; CHECK: br %r14 %add = add i32 %a, 1000000 %cmp = icmp eq i32 %add, 0 - %c = load i32 *%cptr + %c = load i32 , i32 *%cptr %arg = select i1 %cmp, i32 %c, i32 %b call void asm sideeffect "blah $0", "{r3}"(i32 %arg) ret i32 %add @@ -26,7 +26,7 @@ define i32 @f2(i32 %a, i32 %b, i32 *%cptr) { ; CHECK: br %r14 %add = add i32 %a, 1000000 %cmp = icmp eq i32 %add, 0 - %c = load i32 *%cptr + %c = load i32 , i32 *%cptr %newval = select i1 %cmp, i32 %b, i32 %c store i32 %newval, i32 *%cptr ret i32 %add @@ -53,7 +53,7 @@ define i32 @f4(i32 %a, i32 %b, i32 *%cptr) { ; CHECK: br %r14 %add = add i32 %a, 1000000 %cmp = icmp eq i32 %add, 0 - %c = load i32 *%cptr + %c = load i32 , i32 *%cptr %arg = select i1 %cmp, i32 %b, i32 %c call void asm sideeffect "blah $0", "{r3}"(i32 %arg) ret i32 %add @@ -67,7 +67,7 @@ define i32 @f5(i32 %a, i32 %b, i32 *%cptr) { ; CHECK: br %r14 %add = add i32 %a, 1000000 %cmp = icmp eq i32 %add, 0 - %c = load i32 *%cptr + %c = load i32 , i32 *%cptr %newval = select i1 %cmp, i32 %c, i32 %b store i32 %newval, i32 *%cptr ret i32 %add @@ -94,7 +94,7 @@ define i32 @f7(i32 %a, i32 %b, i32 *%cptr) { ; CHECK: br %r14 %add = add i32 %a, 1000000 %cmp = icmp ne i32 %add, 0 - %c = load i32 *%cptr + %c = load i32 , i32 *%cptr %arg = select i1 %cmp, i32 %b, i32 %c call void asm sideeffect "blah $0", "{r3}"(i32 %arg) ret i32 %add @@ -108,7 +108,7 @@ define i32 @f8(i32 %a, i32 %b, i32 *%cptr) { ; CHECK: br %r14 %add = add i32 %a, 1000000 %cmp = icmp ne i32 %add, 0 - %c = load i32 *%cptr + %c = load i32 , i32 *%cptr %newval = select i1 %cmp, i32 %c, i32 %b store i32 %newval, i32 *%cptr ret i32 %add diff --git a/test/CodeGen/SystemZ/int-cmp-47.ll b/test/CodeGen/SystemZ/int-cmp-47.ll index 038a25b2a6ed..274350d24de1 100644 --- a/test/CodeGen/SystemZ/int-cmp-47.ll +++ b/test/CodeGen/SystemZ/int-cmp-47.ll @@ -309,7 +309,8 @@ exit: define void @f17(i64 %a) { ; CHECK-LABEL: f17: ; CHECK-NOT: tmhh -; CHECK: llihh {{%r[0-5]}}, 49151 +; CHECK: srlg [[REG:%r[0-5]]], %r2, 48 +; CHECK: cgfi [[REG]], 49151 ; CHECK-NOT: tmhh ; CHECK: br %r14 entry: diff --git a/test/CodeGen/SystemZ/int-cmp-48.ll b/test/CodeGen/SystemZ/int-cmp-48.ll index d7c6370a2323..e26694753e7c 100644 --- a/test/CodeGen/SystemZ/int-cmp-48.ll +++ b/test/CodeGen/SystemZ/int-cmp-48.ll @@ -11,7 +11,7 @@ define void @f1(i8 *%src) { ; CHECK: je {{\.L.*}} ; CHECK: br %r14 entry: - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 br i1 %cmp, label %exit, label %store @@ -34,7 +34,7 @@ define void @f2(i8 *%src) { ; CHECK: je {{\.L.*}} ; CHECK: br %r14 entry: - %byte = load i8 *%src + %byte = load i8 , i8 *%src store i8 0, i8 *%src %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 @@ -54,7 +54,7 @@ define double @f3(i8 *%src, double %a, double %b) { ; CHECK: tm 0(%r2), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -68,7 +68,7 @@ define double @f4(i8 *%src, double %a, double %b) { ; CHECK: je {{\.L.*}} ; CHECK: mvi 0(%r2), 0 ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -82,7 +82,7 @@ define double @f5(i8 *%src, double %a, double %b) { ; CHECK: tm 0(%r2), 1 ; CHECK: jne {{\.L.*}} ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 1 %cmp = icmp ne i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -95,7 +95,7 @@ define double @f6(i8 *%src, double %a, double %b) { ; CHECK: tm 0(%r2), 254 ; CHECK: jo {{\.L.*}} ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 254 %cmp = icmp eq i8 %and, 254 %res = select i1 %cmp, double %b, double %a @@ -108,7 +108,7 @@ define double @f7(i8 *%src, double %a, double %b) { ; CHECK: tm 0(%r2), 254 ; CHECK: jno {{\.L.*}} ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 254 %cmp = icmp ne i8 %and, 254 %res = select i1 %cmp, double %b, double %a @@ -123,7 +123,7 @@ define double @f8(i8 *%src, double %a, double %b) { ; CHECK: tmll [[REG]], 3 ; CHECK: jh {{\.L.*}} ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 3 %cmp = icmp eq i8 %and, 2 %res = select i1 %cmp, double %b, double %a @@ -137,7 +137,7 @@ define double @f9(i8 *%src, double %a, double %b) { ; CHECK: tmll [[REG]], 3 ; CHECK: jl {{\.L.*}} ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %and = and i8 %byte, 3 %cmp = icmp eq i8 %and, 1 %res = select i1 %cmp, double %b, double %a @@ -150,8 +150,8 @@ define double @f10(i8 *%src, double %a, double %b) { ; CHECK: tm 4095(%r2), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4095 + %byte = load i8 , i8 *%ptr %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -164,8 +164,8 @@ define double @f11(i8 *%src, double %a, double %b) { ; CHECK: tmy 4096(%r2), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4096 + %byte = load i8 , i8 *%ptr %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -178,8 +178,8 @@ define double @f12(i8 *%src, double %a, double %b) { ; CHECK: tmy 524287(%r2), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %byte = load i8 , i8 *%ptr %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -193,8 +193,8 @@ define double @f13(i8 *%src, double %a, double %b) { ; CHECK: tm 0(%r2), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %byte = load i8 , i8 *%ptr %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -207,8 +207,8 @@ define double @f14(i8 *%src, double %a, double %b) { ; CHECK: tmy -524288(%r2), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %byte = load i8 , i8 *%ptr %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -222,8 +222,8 @@ define double @f15(i8 *%src, double %a, double %b) { ; CHECK: tm 0(%r2), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %byte = load i8 , i8 *%ptr %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a @@ -236,8 +236,8 @@ define double @f16(i8 *%src, i64 %index, double %a, double %b) { ; CHECK: tm 0({{%r[1-5]}}), 1 ; CHECK: je {{\.L.*}} ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 %index - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 %index + %byte = load i8 , i8 *%ptr %and = and i8 %byte, 1 %cmp = icmp eq i8 %and, 0 %res = select i1 %cmp, double %b, double %a diff --git a/test/CodeGen/SystemZ/int-cmp-50.ll b/test/CodeGen/SystemZ/int-cmp-50.ll new file mode 100644 index 000000000000..287ac2c49a78 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-50.ll @@ -0,0 +1,30 @@ +; Verify that we do not crash on always-true conditions +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -O0 +; +; This test was compiled using clang -O0 from the following source code: +; +; int test(unsigned long x) +; { +; return x >= 0 && x <= 15; +; } + +define signext i32 @test(i64 %x) { +entry: + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %cmp = icmp uge i64 %0, 0 + br i1 %cmp, label %land.rhs, label %land.end + +land.rhs: ; preds = %entry + %1 = load i64, i64* %x.addr, align 8 + %cmp1 = icmp ule i64 %1, 15 + br label %land.end + +land.end: ; preds = %land.rhs, %entry + %2 = phi i1 [ false, %entry ], [ %cmp1, %land.rhs ] + %land.ext = zext i1 %2 to i32 + ret i32 %land.ext +} + diff --git a/test/CodeGen/SystemZ/int-const-03.ll b/test/CodeGen/SystemZ/int-const-03.ll index af1cef2c138a..7352ea32e76a 100644 --- a/test/CodeGen/SystemZ/int-const-03.ll +++ b/test/CodeGen/SystemZ/int-const-03.ll @@ -70,7 +70,7 @@ define void @f8(i8 *%src) { ; CHECK-LABEL: f8: ; CHECK: mvi 4095(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 + %ptr = getelementptr i8, i8 *%src, i64 4095 store i8 42, i8 *%ptr ret void } @@ -80,7 +80,7 @@ define void @f9(i8 *%src) { ; CHECK-LABEL: f9: ; CHECK: mviy 4096(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 + %ptr = getelementptr i8, i8 *%src, i64 4096 store i8 42, i8 *%ptr ret void } @@ -90,7 +90,7 @@ define void @f10(i8 *%src) { ; CHECK-LABEL: f10: ; CHECK: mviy 524287(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 + %ptr = getelementptr i8, i8 *%src, i64 524287 store i8 42, i8 *%ptr ret void } @@ -102,7 +102,7 @@ define void @f11(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: mvi 0(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 + %ptr = getelementptr i8, i8 *%src, i64 524288 store i8 42, i8 *%ptr ret void } @@ -112,7 +112,7 @@ define void @f12(i8 *%src) { ; CHECK-LABEL: f12: ; CHECK: mviy -1(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 + %ptr = getelementptr i8, i8 *%src, i64 -1 store i8 42, i8 *%ptr ret void } @@ -122,7 +122,7 @@ define void @f13(i8 *%src) { ; CHECK-LABEL: f13: ; CHECK: mviy -524288(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 + %ptr = getelementptr i8, i8 *%src, i64 -524288 store i8 42, i8 *%ptr ret void } @@ -134,7 +134,7 @@ define void @f14(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: mvi 0(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 + %ptr = getelementptr i8, i8 *%src, i64 -524289 store i8 42, i8 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-const-04.ll b/test/CodeGen/SystemZ/int-const-04.ll index aced50b5601b..fd943991196e 100644 --- a/test/CodeGen/SystemZ/int-const-04.ll +++ b/test/CodeGen/SystemZ/int-const-04.ll @@ -70,7 +70,7 @@ define void @f8(i16 *%a) { ; CHECK-LABEL: f8: ; CHECK: mvhhi 4094(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i16 *%a, i64 2047 + %ptr = getelementptr i16, i16 *%a, i64 2047 store i16 42, i16 *%ptr ret void } @@ -82,7 +82,7 @@ define void @f9(i16 *%a) { ; CHECK: lhi [[TMP:%r[0-5]]], 42 ; CHECK: sthy [[TMP]], 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%a, i64 2048 + %ptr = getelementptr i16, i16 *%a, i64 2048 store i16 42, i16 *%ptr ret void } @@ -93,7 +93,7 @@ define void @f10(i16 *%a) { ; CHECK: lhi [[TMP:%r[0-5]]], 42 ; CHECK: sthy [[TMP]], -2(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%a, i64 -1 + %ptr = getelementptr i16, i16 *%a, i64 -1 store i16 42, i16 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-const-05.ll b/test/CodeGen/SystemZ/int-const-05.ll index 98d6851c197d..c7b455168990 100644 --- a/test/CodeGen/SystemZ/int-const-05.ll +++ b/test/CodeGen/SystemZ/int-const-05.ll @@ -61,7 +61,7 @@ define void @f7(i32 *%a) { ; CHECK-LABEL: f7: ; CHECK: mvhi 4092(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i32 *%a, i64 1023 + %ptr = getelementptr i32, i32 *%a, i64 1023 store i32 42, i32 *%ptr ret void } @@ -72,7 +72,7 @@ define void @f8(i32 *%a) { ; CHECK: lhi [[TMP:%r[0-5]]], 42 ; CHECK: sty [[TMP]], 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%a, i64 1024 + %ptr = getelementptr i32, i32 *%a, i64 1024 store i32 42, i32 *%ptr ret void } @@ -83,7 +83,7 @@ define void @f9(i32 *%a) { ; CHECK: lhi [[TMP:%r[0-5]]], 42 ; CHECK: sty [[TMP]], -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%a, i64 -1 + %ptr = getelementptr i32, i32 *%a, i64 -1 store i32 42, i32 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-const-06.ll b/test/CodeGen/SystemZ/int-const-06.ll index cf07c665dde7..fc47a04094b5 100644 --- a/test/CodeGen/SystemZ/int-const-06.ll +++ b/test/CodeGen/SystemZ/int-const-06.ll @@ -61,7 +61,7 @@ define void @f7(i64 *%a) { ; CHECK-LABEL: f7: ; CHECK: mvghi 4088(%r2), 42 ; CHECK: br %r14 - %ptr = getelementptr i64 *%a, i64 511 + %ptr = getelementptr i64, i64 *%a, i64 511 store i64 42, i64 *%ptr ret void } @@ -73,7 +73,7 @@ define void @f8(i64 *%a) { ; CHECK: lghi [[TMP:%r[0-5]]], 42 ; CHECK: stg [[TMP]], 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%a, i64 512 + %ptr = getelementptr i64, i64 *%a, i64 512 store i64 42, i64 *%ptr ret void } @@ -84,7 +84,7 @@ define void @f9(i64 *%a) { ; CHECK: lghi [[TMP:%r[0-5]]], 42 ; CHECK: stg [[TMP]], -8(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%a, i64 -1 + %ptr = getelementptr i64, i64 *%a, i64 -1 store i64 42, i64 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-conv-01.ll b/test/CodeGen/SystemZ/int-conv-01.ll index e5c411cdec1d..70ef78a06110 100644 --- a/test/CodeGen/SystemZ/int-conv-01.ll +++ b/test/CodeGen/SystemZ/int-conv-01.ll @@ -27,7 +27,7 @@ define i32 @f3(i8 *%src) { ; CHECK-LABEL: f3: ; CHECK: lb %r2, 0(%r2) ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %ext = sext i8 %byte to i32 ret i32 %ext } @@ -37,8 +37,8 @@ define i32 @f4(i8 *%src) { ; CHECK-LABEL: f4: ; CHECK: lb %r2, 524287(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i32 ret i32 %ext } @@ -50,8 +50,8 @@ define i32 @f5(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lb %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i32 ret i32 %ext } @@ -61,8 +61,8 @@ define i32 @f6(i8 *%src) { ; CHECK-LABEL: f6: ; CHECK: lb %r2, -1(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i32 ret i32 %ext } @@ -72,8 +72,8 @@ define i32 @f7(i8 *%src) { ; CHECK-LABEL: f7: ; CHECK: lb %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i32 ret i32 %ext } @@ -85,8 +85,8 @@ define i32 @f8(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: lb %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i32 ret i32 %ext } @@ -99,7 +99,7 @@ define i32 @f9(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i8 * - %byte = load i8 *%ptr + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i32 ret i32 %ext } @@ -110,22 +110,22 @@ define void @f10(i32 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: lb {{%r[0-9]+}}, 16{{[37]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr %trunc0 = trunc i32 %val0 to i8 %trunc1 = trunc i32 %val1 to i8 diff --git a/test/CodeGen/SystemZ/int-conv-02.ll b/test/CodeGen/SystemZ/int-conv-02.ll index dd7760d08cf5..5b248cce1efc 100644 --- a/test/CodeGen/SystemZ/int-conv-02.ll +++ b/test/CodeGen/SystemZ/int-conv-02.ll @@ -37,7 +37,7 @@ define i32 @f4(i8 *%src) { ; CHECK-LABEL: f4: ; CHECK: llc %r2, 0(%r2) ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %ext = zext i8 %byte to i32 ret i32 %ext } @@ -47,8 +47,8 @@ define i32 @f5(i8 *%src) { ; CHECK-LABEL: f5: ; CHECK: llc %r2, 524287(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i32 ret i32 %ext } @@ -60,8 +60,8 @@ define i32 @f6(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: llc %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i32 ret i32 %ext } @@ -71,8 +71,8 @@ define i32 @f7(i8 *%src) { ; CHECK-LABEL: f7: ; CHECK: llc %r2, -1(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i32 ret i32 %ext } @@ -82,8 +82,8 @@ define i32 @f8(i8 *%src) { ; CHECK-LABEL: f8: ; CHECK: llc %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i32 ret i32 %ext } @@ -95,8 +95,8 @@ define i32 @f9(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: llc %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i32 ret i32 %ext } @@ -109,7 +109,7 @@ define i32 @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i8 * - %byte = load i8 *%ptr + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i32 ret i32 %ext } @@ -120,22 +120,22 @@ define void @f11(i32 *%ptr) { ; CHECK-LABEL: f11: ; CHECK: llc {{%r[0-9]+}}, 16{{[37]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr %trunc0 = trunc i32 %val0 to i8 %trunc1 = trunc i32 %val1 to i8 diff --git a/test/CodeGen/SystemZ/int-conv-03.ll b/test/CodeGen/SystemZ/int-conv-03.ll index cad9581296a4..e621bcd69dee 100644 --- a/test/CodeGen/SystemZ/int-conv-03.ll +++ b/test/CodeGen/SystemZ/int-conv-03.ll @@ -27,7 +27,7 @@ define i64 @f3(i8 *%src) { ; CHECK-LABEL: f3: ; CHECK: lgb %r2, 0(%r2) ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %ext = sext i8 %byte to i64 ret i64 %ext } @@ -37,8 +37,8 @@ define i64 @f4(i8 *%src) { ; CHECK-LABEL: f4: ; CHECK: lgb %r2, 524287(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i64 ret i64 %ext } @@ -50,8 +50,8 @@ define i64 @f5(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lgb %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i64 ret i64 %ext } @@ -61,8 +61,8 @@ define i64 @f6(i8 *%src) { ; CHECK-LABEL: f6: ; CHECK: lgb %r2, -1(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i64 ret i64 %ext } @@ -72,8 +72,8 @@ define i64 @f7(i8 *%src) { ; CHECK-LABEL: f7: ; CHECK: lgb %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i64 ret i64 %ext } @@ -85,8 +85,8 @@ define i64 @f8(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: lgb %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i64 ret i64 %ext } @@ -99,7 +99,7 @@ define i64 @f9(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i8 * - %byte = load i8 *%ptr + %byte = load i8 , i8 *%ptr %ext = sext i8 %byte to i64 ret i64 %ext } @@ -110,22 +110,22 @@ define void @f10(i64 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: lgb {{%r[0-9]+}}, 167(%r15) ; CHECK: br %r14 - %val0 = load volatile i64 *%ptr - %val1 = load volatile i64 *%ptr - %val2 = load volatile i64 *%ptr - %val3 = load volatile i64 *%ptr - %val4 = load volatile i64 *%ptr - %val5 = load volatile i64 *%ptr - %val6 = load volatile i64 *%ptr - %val7 = load volatile i64 *%ptr - %val8 = load volatile i64 *%ptr - %val9 = load volatile i64 *%ptr - %val10 = load volatile i64 *%ptr - %val11 = load volatile i64 *%ptr - %val12 = load volatile i64 *%ptr - %val13 = load volatile i64 *%ptr - %val14 = load volatile i64 *%ptr - %val15 = load volatile i64 *%ptr + %val0 = load volatile i64 , i64 *%ptr + %val1 = load volatile i64 , i64 *%ptr + %val2 = load volatile i64 , i64 *%ptr + %val3 = load volatile i64 , i64 *%ptr + %val4 = load volatile i64 , i64 *%ptr + %val5 = load volatile i64 , i64 *%ptr + %val6 = load volatile i64 , i64 *%ptr + %val7 = load volatile i64 , i64 *%ptr + %val8 = load volatile i64 , i64 *%ptr + %val9 = load volatile i64 , i64 *%ptr + %val10 = load volatile i64 , i64 *%ptr + %val11 = load volatile i64 , i64 *%ptr + %val12 = load volatile i64 , i64 *%ptr + %val13 = load volatile i64 , i64 *%ptr + %val14 = load volatile i64 , i64 *%ptr + %val15 = load volatile i64 , i64 *%ptr %trunc0 = trunc i64 %val0 to i8 %trunc1 = trunc i64 %val1 to i8 diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll index 1c6be7b6e8a4..a0f5d63d2605 100644 --- a/test/CodeGen/SystemZ/int-conv-04.ll +++ b/test/CodeGen/SystemZ/int-conv-04.ll @@ -36,7 +36,7 @@ define i64 @f4(i8 *%src) { ; CHECK-LABEL: f4: ; CHECK: llgc %r2, 0(%r2) ; CHECK: br %r14 - %byte = load i8 *%src + %byte = load i8 , i8 *%src %ext = zext i8 %byte to i64 ret i64 %ext } @@ -46,8 +46,8 @@ define i64 @f5(i8 *%src) { ; CHECK-LABEL: f5: ; CHECK: llgc %r2, 524287(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i64 ret i64 %ext } @@ -59,8 +59,8 @@ define i64 @f6(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: llgc %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i64 ret i64 %ext } @@ -70,8 +70,8 @@ define i64 @f7(i8 *%src) { ; CHECK-LABEL: f7: ; CHECK: llgc %r2, -1(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i64 ret i64 %ext } @@ -81,8 +81,8 @@ define i64 @f8(i8 *%src) { ; CHECK-LABEL: f8: ; CHECK: llgc %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i64 ret i64 %ext } @@ -94,8 +94,8 @@ define i64 @f9(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: llgc %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %byte = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i64 ret i64 %ext } @@ -108,7 +108,7 @@ define i64 @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i8 * - %byte = load i8 *%ptr + %byte = load i8 , i8 *%ptr %ext = zext i8 %byte to i64 ret i64 %ext } @@ -119,22 +119,22 @@ define void @f11(i64 *%ptr) { ; CHECK-LABEL: f11: ; CHECK: llgc {{%r[0-9]+}}, 167(%r15) ; CHECK: br %r14 - %val0 = load volatile i64 *%ptr - %val1 = load volatile i64 *%ptr - %val2 = load volatile i64 *%ptr - %val3 = load volatile i64 *%ptr - %val4 = load volatile i64 *%ptr - %val5 = load volatile i64 *%ptr - %val6 = load volatile i64 *%ptr - %val7 = load volatile i64 *%ptr - %val8 = load volatile i64 *%ptr - %val9 = load volatile i64 *%ptr - %val10 = load volatile i64 *%ptr - %val11 = load volatile i64 *%ptr - %val12 = load volatile i64 *%ptr - %val13 = load volatile i64 *%ptr - %val14 = load volatile i64 *%ptr - %val15 = load volatile i64 *%ptr + %val0 = load volatile i64 , i64 *%ptr + %val1 = load volatile i64 , i64 *%ptr + %val2 = load volatile i64 , i64 *%ptr + %val3 = load volatile i64 , i64 *%ptr + %val4 = load volatile i64 , i64 *%ptr + %val5 = load volatile i64 , i64 *%ptr + %val6 = load volatile i64 , i64 *%ptr + %val7 = load volatile i64 , i64 *%ptr + %val8 = load volatile i64 , i64 *%ptr + %val9 = load volatile i64 , i64 *%ptr + %val10 = load volatile i64 , i64 *%ptr + %val11 = load volatile i64 , i64 *%ptr + %val12 = load volatile i64 , i64 *%ptr + %val13 = load volatile i64 , i64 *%ptr + %val14 = load volatile i64 , i64 *%ptr + %val15 = load volatile i64 , i64 *%ptr %trunc0 = trunc i64 %val0 to i8 %trunc1 = trunc i64 %val1 to i8 diff --git a/test/CodeGen/SystemZ/int-conv-05.ll b/test/CodeGen/SystemZ/int-conv-05.ll index 5eade93ac584..55299529c480 100644 --- a/test/CodeGen/SystemZ/int-conv-05.ll +++ b/test/CodeGen/SystemZ/int-conv-05.ll @@ -27,7 +27,7 @@ define i32 @f3(i16 *%src) { ; CHECK-LABEL: f3: ; CHECK: lh %r2, 0(%r2) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %ext = sext i16 %half to i32 ret i32 %ext } @@ -37,8 +37,8 @@ define i32 @f4(i16 *%src) { ; CHECK-LABEL: f4: ; CHECK: lh %r2, 4094(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2047 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2047 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -48,8 +48,8 @@ define i32 @f5(i16 *%src) { ; CHECK-LABEL: f5: ; CHECK: lhy %r2, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2048 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2048 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -59,8 +59,8 @@ define i32 @f6(i16 *%src) { ; CHECK-LABEL: f6: ; CHECK: lhy %r2, 524286(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -72,8 +72,8 @@ define i32 @f7(i16 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -83,8 +83,8 @@ define i32 @f8(i16 *%src) { ; CHECK-LABEL: f8: ; CHECK: lhy %r2, -2(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -94,8 +94,8 @@ define i32 @f9(i16 *%src) { ; CHECK-LABEL: f9: ; CHECK: lhy %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -107,8 +107,8 @@ define i32 @f10(i16 *%src) { ; CHECK: agfi %r2, -524290 ; CHECK: lh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -121,7 +121,7 @@ define i32 @f11(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4094 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -134,7 +134,7 @@ define i32 @f12(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i32 ret i32 %ext } @@ -145,22 +145,22 @@ define void @f13(i32 *%ptr) { ; CHECK-LABEL: f13: ; CHECK: lh {{%r[0-9]+}}, 16{{[26]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr %trunc0 = trunc i32 %val0 to i16 %trunc1 = trunc i32 %val1 to i16 diff --git a/test/CodeGen/SystemZ/int-conv-06.ll b/test/CodeGen/SystemZ/int-conv-06.ll index 33860d12270f..99ff84efbe76 100644 --- a/test/CodeGen/SystemZ/int-conv-06.ll +++ b/test/CodeGen/SystemZ/int-conv-06.ll @@ -37,7 +37,7 @@ define i32 @f4(i16 *%src) { ; CHECK-LABEL: f4: ; CHECK: llh %r2, 0(%r2) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %ext = zext i16 %half to i32 ret i32 %ext } @@ -47,8 +47,8 @@ define i32 @f5(i16 *%src) { ; CHECK-LABEL: f5: ; CHECK: llh %r2, 524286(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i32 ret i32 %ext } @@ -60,8 +60,8 @@ define i32 @f6(i16 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: llh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i32 ret i32 %ext } @@ -71,8 +71,8 @@ define i32 @f7(i16 *%src) { ; CHECK-LABEL: f7: ; CHECK: llh %r2, -2(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i32 ret i32 %ext } @@ -82,8 +82,8 @@ define i32 @f8(i16 *%src) { ; CHECK-LABEL: f8: ; CHECK: llh %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i32 ret i32 %ext } @@ -95,8 +95,8 @@ define i32 @f9(i16 *%src) { ; CHECK: agfi %r2, -524290 ; CHECK: llh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i32 ret i32 %ext } @@ -109,7 +109,7 @@ define i32 @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i32 ret i32 %ext } @@ -120,22 +120,22 @@ define void @f11(i32 *%ptr) { ; CHECK-LABEL: f11: ; CHECK: llh {{%r[0-9]+}}, 16{{[26]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr %trunc0 = trunc i32 %val0 to i16 %trunc1 = trunc i32 %val1 to i16 diff --git a/test/CodeGen/SystemZ/int-conv-07.ll b/test/CodeGen/SystemZ/int-conv-07.ll index 4b78c773d1ea..5e989e4737e8 100644 --- a/test/CodeGen/SystemZ/int-conv-07.ll +++ b/test/CodeGen/SystemZ/int-conv-07.ll @@ -27,7 +27,7 @@ define i64 @f3(i16 *%src) { ; CHECK-LABEL: f3: ; CHECK: lgh %r2, 0(%r2) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %ext = sext i16 %half to i64 ret i64 %ext } @@ -37,8 +37,8 @@ define i64 @f4(i16 *%src) { ; CHECK-LABEL: f4: ; CHECK: lgh %r2, 524286(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i64 ret i64 %ext } @@ -50,8 +50,8 @@ define i64 @f5(i16 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lgh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i64 ret i64 %ext } @@ -61,8 +61,8 @@ define i64 @f6(i16 *%src) { ; CHECK-LABEL: f6: ; CHECK: lgh %r2, -2(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i64 ret i64 %ext } @@ -72,8 +72,8 @@ define i64 @f7(i16 *%src) { ; CHECK-LABEL: f7: ; CHECK: lgh %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i64 ret i64 %ext } @@ -85,8 +85,8 @@ define i64 @f8(i16 *%src) { ; CHECK: agfi %r2, -524290 ; CHECK: lgh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i64 ret i64 %ext } @@ -99,7 +99,7 @@ define i64 @f9(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %ext = sext i16 %half to i64 ret i64 %ext } @@ -110,22 +110,22 @@ define void @f10(i64 *%ptr) { ; CHECK-LABEL: f10: ; CHECK: lgh {{%r[0-9]+}}, 166(%r15) ; CHECK: br %r14 - %val0 = load volatile i64 *%ptr - %val1 = load volatile i64 *%ptr - %val2 = load volatile i64 *%ptr - %val3 = load volatile i64 *%ptr - %val4 = load volatile i64 *%ptr - %val5 = load volatile i64 *%ptr - %val6 = load volatile i64 *%ptr - %val7 = load volatile i64 *%ptr - %val8 = load volatile i64 *%ptr - %val9 = load volatile i64 *%ptr - %val10 = load volatile i64 *%ptr - %val11 = load volatile i64 *%ptr - %val12 = load volatile i64 *%ptr - %val13 = load volatile i64 *%ptr - %val14 = load volatile i64 *%ptr - %val15 = load volatile i64 *%ptr + %val0 = load volatile i64 , i64 *%ptr + %val1 = load volatile i64 , i64 *%ptr + %val2 = load volatile i64 , i64 *%ptr + %val3 = load volatile i64 , i64 *%ptr + %val4 = load volatile i64 , i64 *%ptr + %val5 = load volatile i64 , i64 *%ptr + %val6 = load volatile i64 , i64 *%ptr + %val7 = load volatile i64 , i64 *%ptr + %val8 = load volatile i64 , i64 *%ptr + %val9 = load volatile i64 , i64 *%ptr + %val10 = load volatile i64 , i64 *%ptr + %val11 = load volatile i64 , i64 *%ptr + %val12 = load volatile i64 , i64 *%ptr + %val13 = load volatile i64 , i64 *%ptr + %val14 = load volatile i64 , i64 *%ptr + %val15 = load volatile i64 , i64 *%ptr %trunc0 = trunc i64 %val0 to i16 %trunc1 = trunc i64 %val1 to i16 diff --git a/test/CodeGen/SystemZ/int-conv-08.ll b/test/CodeGen/SystemZ/int-conv-08.ll index 6b6cb672fb9a..8524dfebe277 100644 --- a/test/CodeGen/SystemZ/int-conv-08.ll +++ b/test/CodeGen/SystemZ/int-conv-08.ll @@ -36,7 +36,7 @@ define i64 @f4(i16 *%src) { ; CHECK-LABEL: f4: ; CHECK: llgh %r2, 0(%r2) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %ext = zext i16 %half to i64 ret i64 %ext } @@ -46,8 +46,8 @@ define i64 @f5(i16 *%src) { ; CHECK-LABEL: f5: ; CHECK: llgh %r2, 524286(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i64 ret i64 %ext } @@ -59,8 +59,8 @@ define i64 @f6(i16 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: llgh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i64 ret i64 %ext } @@ -70,8 +70,8 @@ define i64 @f7(i16 *%src) { ; CHECK-LABEL: f7: ; CHECK: llgh %r2, -2(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i64 ret i64 %ext } @@ -81,8 +81,8 @@ define i64 @f8(i16 *%src) { ; CHECK-LABEL: f8: ; CHECK: llgh %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i64 ret i64 %ext } @@ -94,8 +94,8 @@ define i64 @f9(i16 *%src) { ; CHECK: agfi %r2, -524290 ; CHECK: llgh %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i64 ret i64 %ext } @@ -108,7 +108,7 @@ define i64 @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %ext = zext i16 %half to i64 ret i64 %ext } @@ -119,22 +119,22 @@ define void @f11(i64 *%ptr) { ; CHECK-LABEL: f11: ; CHECK: llgh {{%r[0-9]+}}, 166(%r15) ; CHECK: br %r14 - %val0 = load volatile i64 *%ptr - %val1 = load volatile i64 *%ptr - %val2 = load volatile i64 *%ptr - %val3 = load volatile i64 *%ptr - %val4 = load volatile i64 *%ptr - %val5 = load volatile i64 *%ptr - %val6 = load volatile i64 *%ptr - %val7 = load volatile i64 *%ptr - %val8 = load volatile i64 *%ptr - %val9 = load volatile i64 *%ptr - %val10 = load volatile i64 *%ptr - %val11 = load volatile i64 *%ptr - %val12 = load volatile i64 *%ptr - %val13 = load volatile i64 *%ptr - %val14 = load volatile i64 *%ptr - %val15 = load volatile i64 *%ptr + %val0 = load volatile i64 , i64 *%ptr + %val1 = load volatile i64 , i64 *%ptr + %val2 = load volatile i64 , i64 *%ptr + %val3 = load volatile i64 , i64 *%ptr + %val4 = load volatile i64 , i64 *%ptr + %val5 = load volatile i64 , i64 *%ptr + %val6 = load volatile i64 , i64 *%ptr + %val7 = load volatile i64 , i64 *%ptr + %val8 = load volatile i64 , i64 *%ptr + %val9 = load volatile i64 , i64 *%ptr + %val10 = load volatile i64 , i64 *%ptr + %val11 = load volatile i64 , i64 *%ptr + %val12 = load volatile i64 , i64 *%ptr + %val13 = load volatile i64 , i64 *%ptr + %val14 = load volatile i64 , i64 *%ptr + %val15 = load volatile i64 , i64 *%ptr %trunc0 = trunc i64 %val0 to i16 %trunc1 = trunc i64 %val1 to i16 diff --git a/test/CodeGen/SystemZ/int-conv-09.ll b/test/CodeGen/SystemZ/int-conv-09.ll index b9c508917d4d..ffd20491030a 100644 --- a/test/CodeGen/SystemZ/int-conv-09.ll +++ b/test/CodeGen/SystemZ/int-conv-09.ll @@ -26,7 +26,7 @@ define i64 @f3(i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: lgf %r2, 0(%r2) ; CHECK: br %r14 - %word = load i32 *%src + %word = load i32 , i32 *%src %ext = sext i32 %word to i64 ret i64 %ext } @@ -36,8 +36,8 @@ define i64 @f4(i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: lgf %r2, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %word = load i32 , i32 *%ptr %ext = sext i32 %word to i64 ret i64 %ext } @@ -49,8 +49,8 @@ define i64 @f5(i32 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lgf %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %word = load i32 , i32 *%ptr %ext = sext i32 %word to i64 ret i64 %ext } @@ -60,8 +60,8 @@ define i64 @f6(i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: lgf %r2, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %word = load i32 , i32 *%ptr %ext = sext i32 %word to i64 ret i64 %ext } @@ -71,8 +71,8 @@ define i64 @f7(i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: lgf %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %word = load i32 , i32 *%ptr %ext = sext i32 %word to i64 ret i64 %ext } @@ -84,8 +84,8 @@ define i64 @f8(i32 *%src) { ; CHECK: agfi %r2, -524292 ; CHECK: lgf %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %word = load i32 , i32 *%ptr %ext = sext i32 %word to i64 ret i64 %ext } @@ -98,7 +98,7 @@ define i64 @f9(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i32 * - %word = load i32 *%ptr + %word = load i32 , i32 *%ptr %ext = sext i32 %word to i64 ret i64 %ext } diff --git a/test/CodeGen/SystemZ/int-conv-10.ll b/test/CodeGen/SystemZ/int-conv-10.ll index 781c74c7fa23..a5e74061017e 100644 --- a/test/CodeGen/SystemZ/int-conv-10.ll +++ b/test/CodeGen/SystemZ/int-conv-10.ll @@ -35,7 +35,7 @@ define i64 @f4(i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: llgf %r2, 0(%r2) ; CHECK: br %r14 - %word = load i32 *%src + %word = load i32 , i32 *%src %ext = zext i32 %word to i64 ret i64 %ext } @@ -45,8 +45,8 @@ define i64 @f5(i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: llgf %r2, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %word = load i32 , i32 *%ptr %ext = zext i32 %word to i64 ret i64 %ext } @@ -58,8 +58,8 @@ define i64 @f6(i32 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: llgf %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %word = load i32 , i32 *%ptr %ext = zext i32 %word to i64 ret i64 %ext } @@ -69,8 +69,8 @@ define i64 @f7(i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: llgf %r2, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %word = load i32 , i32 *%ptr %ext = zext i32 %word to i64 ret i64 %ext } @@ -80,8 +80,8 @@ define i64 @f8(i32 *%src) { ; CHECK-LABEL: f8: ; CHECK: llgf %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %word = load i32 , i32 *%ptr %ext = zext i32 %word to i64 ret i64 %ext } @@ -93,8 +93,8 @@ define i64 @f9(i32 *%src) { ; CHECK: agfi %r2, -524292 ; CHECK: llgf %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %word = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %word = load i32 , i32 *%ptr %ext = zext i32 %word to i64 ret i64 %ext } @@ -107,7 +107,7 @@ define i64 @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i32 * - %word = load i32 *%ptr + %word = load i32 , i32 *%ptr %ext = zext i32 %word to i64 ret i64 %ext } diff --git a/test/CodeGen/SystemZ/int-conv-11.ll b/test/CodeGen/SystemZ/int-conv-11.ll index 30769621bf82..cfa0870cd5d2 100644 --- a/test/CodeGen/SystemZ/int-conv-11.ll +++ b/test/CodeGen/SystemZ/int-conv-11.ll @@ -8,38 +8,38 @@ define void @f1(i32 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: llc{{h?}} {{%r[0-9]+}}, 16{{[37]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr - %val16 = load volatile i32 *%ptr - %val17 = load volatile i32 *%ptr - %val18 = load volatile i32 *%ptr - %val19 = load volatile i32 *%ptr - %val20 = load volatile i32 *%ptr - %val21 = load volatile i32 *%ptr - %val22 = load volatile i32 *%ptr - %val23 = load volatile i32 *%ptr - %val24 = load volatile i32 *%ptr - %val25 = load volatile i32 *%ptr - %val26 = load volatile i32 *%ptr - %val27 = load volatile i32 *%ptr - %val28 = load volatile i32 *%ptr - %val29 = load volatile i32 *%ptr - %val30 = load volatile i32 *%ptr - %val31 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr + %val16 = load volatile i32 , i32 *%ptr + %val17 = load volatile i32 , i32 *%ptr + %val18 = load volatile i32 , i32 *%ptr + %val19 = load volatile i32 , i32 *%ptr + %val20 = load volatile i32 , i32 *%ptr + %val21 = load volatile i32 , i32 *%ptr + %val22 = load volatile i32 , i32 *%ptr + %val23 = load volatile i32 , i32 *%ptr + %val24 = load volatile i32 , i32 *%ptr + %val25 = load volatile i32 , i32 *%ptr + %val26 = load volatile i32 , i32 *%ptr + %val27 = load volatile i32 , i32 *%ptr + %val28 = load volatile i32 , i32 *%ptr + %val29 = load volatile i32 , i32 *%ptr + %val30 = load volatile i32 , i32 *%ptr + %val31 = load volatile i32 , i32 *%ptr %trunc0 = trunc i32 %val0 to i8 %trunc1 = trunc i32 %val1 to i8 @@ -181,38 +181,38 @@ define void @f2(i32 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: llh{{h?}} {{%r[0-9]+}}, 16{{[26]}}(%r15) ; CHECK: br %r14 - %val0 = load volatile i32 *%ptr - %val1 = load volatile i32 *%ptr - %val2 = load volatile i32 *%ptr - %val3 = load volatile i32 *%ptr - %val4 = load volatile i32 *%ptr - %val5 = load volatile i32 *%ptr - %val6 = load volatile i32 *%ptr - %val7 = load volatile i32 *%ptr - %val8 = load volatile i32 *%ptr - %val9 = load volatile i32 *%ptr - %val10 = load volatile i32 *%ptr - %val11 = load volatile i32 *%ptr - %val12 = load volatile i32 *%ptr - %val13 = load volatile i32 *%ptr - %val14 = load volatile i32 *%ptr - %val15 = load volatile i32 *%ptr - %val16 = load volatile i32 *%ptr - %val17 = load volatile i32 *%ptr - %val18 = load volatile i32 *%ptr - %val19 = load volatile i32 *%ptr - %val20 = load volatile i32 *%ptr - %val21 = load volatile i32 *%ptr - %val22 = load volatile i32 *%ptr - %val23 = load volatile i32 *%ptr - %val24 = load volatile i32 *%ptr - %val25 = load volatile i32 *%ptr - %val26 = load volatile i32 *%ptr - %val27 = load volatile i32 *%ptr - %val28 = load volatile i32 *%ptr - %val29 = load volatile i32 *%ptr - %val30 = load volatile i32 *%ptr - %val31 = load volatile i32 *%ptr + %val0 = load volatile i32 , i32 *%ptr + %val1 = load volatile i32 , i32 *%ptr + %val2 = load volatile i32 , i32 *%ptr + %val3 = load volatile i32 , i32 *%ptr + %val4 = load volatile i32 , i32 *%ptr + %val5 = load volatile i32 , i32 *%ptr + %val6 = load volatile i32 , i32 *%ptr + %val7 = load volatile i32 , i32 *%ptr + %val8 = load volatile i32 , i32 *%ptr + %val9 = load volatile i32 , i32 *%ptr + %val10 = load volatile i32 , i32 *%ptr + %val11 = load volatile i32 , i32 *%ptr + %val12 = load volatile i32 , i32 *%ptr + %val13 = load volatile i32 , i32 *%ptr + %val14 = load volatile i32 , i32 *%ptr + %val15 = load volatile i32 , i32 *%ptr + %val16 = load volatile i32 , i32 *%ptr + %val17 = load volatile i32 , i32 *%ptr + %val18 = load volatile i32 , i32 *%ptr + %val19 = load volatile i32 , i32 *%ptr + %val20 = load volatile i32 , i32 *%ptr + %val21 = load volatile i32 , i32 *%ptr + %val22 = load volatile i32 , i32 *%ptr + %val23 = load volatile i32 , i32 *%ptr + %val24 = load volatile i32 , i32 *%ptr + %val25 = load volatile i32 , i32 *%ptr + %val26 = load volatile i32 , i32 *%ptr + %val27 = load volatile i32 , i32 *%ptr + %val28 = load volatile i32 , i32 *%ptr + %val29 = load volatile i32 , i32 *%ptr + %val30 = load volatile i32 , i32 *%ptr + %val31 = load volatile i32 , i32 *%ptr %trunc0 = trunc i32 %val0 to i16 %trunc1 = trunc i32 %val1 to i16 diff --git a/test/CodeGen/SystemZ/int-div-01.ll b/test/CodeGen/SystemZ/int-div-01.ll index 2c21186e3369..1442109dc23c 100644 --- a/test/CodeGen/SystemZ/int-div-01.ll +++ b/test/CodeGen/SystemZ/int-div-01.ll @@ -69,7 +69,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { ; CHECK-NOT: dsgfr ; CHECK: or %r2, %r3 ; CHECK: br %r14 - %a = load i32 *%src + %a = load i32 , i32 *%src %div = sdiv i32 %a, %b %rem = srem i32 %a, %b %or = or i32 %rem, %div @@ -83,7 +83,7 @@ define void @f6(i32 *%dest, i32 %a, i32 *%src) { ; CHECK: dsgf %r0, 0(%r4) ; CHECK: st %r1, 0(%r2) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %div = sdiv i32 %a, %b store i32 %div, i32 *%dest ret void @@ -96,7 +96,7 @@ define void @f7(i32 *%dest, i32 %a, i32 *%src) { ; CHECK: dsgf %r0, 0(%r4) ; CHECK: st %r0, 0(%r2) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %rem = srem i32 %a, %b store i32 %rem, i32 *%dest ret void @@ -112,7 +112,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-NOT: {{dsgf|dsgfr}} ; CHECK: or %r2, %r3 ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %div = sdiv i32 %a, %b %rem = srem i32 %a, %b %or = or i32 %rem, %div @@ -124,8 +124,8 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-LABEL: f9: ; CHECK: dsgf %r2, 524284(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %rem = srem i32 %a, %b ret i32 %rem } @@ -137,8 +137,8 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: dsgf %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %rem = srem i32 %a, %b ret i32 %rem } @@ -148,8 +148,8 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-LABEL: f11: ; CHECK: dsgf %r2, -4(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %rem = srem i32 %a, %b ret i32 %rem } @@ -159,8 +159,8 @@ define i32 @f12(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-LABEL: f12: ; CHECK: dsgf %r2, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %rem = srem i32 %a, %b ret i32 %rem } @@ -172,8 +172,8 @@ define i32 @f13(i32 %dummy, i32 %a, i32 *%src) { ; CHECK: agfi %r4, -524292 ; CHECK: dsgf %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %rem = srem i32 %a, %b ret i32 %rem } @@ -186,7 +186,7 @@ define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %rem = srem i32 %a, %b ret i32 %rem } @@ -200,7 +200,7 @@ define void @f15(i32 *%dest, i32 *%src) { ; CHECK: lgfr %r1, %r2 ; CHECK: dsgfr %r0, [[B]] ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %a = call i32 @foo() %div = sdiv i32 %a, %b store i32 %div, i32 *%dest @@ -213,26 +213,26 @@ define i32 @f16(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll index f3287a56c6cd..1a4b4d95c936 100644 --- a/test/CodeGen/SystemZ/int-div-02.ll +++ b/test/CodeGen/SystemZ/int-div-02.ll @@ -57,7 +57,7 @@ define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) { ; CHECK: dl %r2, 0(%r4) ; CHECK: st %r3, 0(%r5) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %div = udiv i32 %a, %b store i32 %div, i32 *%dest ret void @@ -72,7 +72,7 @@ define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) { ; CHECK: dl %r2, 0(%r4) ; CHECK: st %r2, 0(%r5) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %rem = urem i32 %a, %b store i32 %rem, i32 *%dest ret void @@ -88,7 +88,7 @@ define i32 @f6(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-NOT: {{dl|dlr}} ; CHECK: or %r2, %r3 ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %div = udiv i32 %a, %b %rem = urem i32 %a, %b %or = or i32 %rem, %div @@ -100,8 +100,8 @@ define i32 @f7(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: dl %r2, 524284(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %rem = urem i32 %a, %b ret i32 %rem } @@ -113,8 +113,8 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: dl %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %rem = urem i32 %a, %b ret i32 %rem } @@ -124,8 +124,8 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-LABEL: f9: ; CHECK: dl %r2, -4(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %rem = urem i32 %a, %b ret i32 %rem } @@ -135,8 +135,8 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) { ; CHECK-LABEL: f10: ; CHECK: dl %r2, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %rem = urem i32 %a, %b ret i32 %rem } @@ -148,8 +148,8 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) { ; CHECK: agfi %r4, -524292 ; CHECK: dl %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %rem = urem i32 %a, %b ret i32 %rem } @@ -162,7 +162,7 @@ define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %rem = urem i32 %a, %b ret i32 %rem } @@ -173,26 +173,26 @@ define i32 @f13(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/int-div-03.ll b/test/CodeGen/SystemZ/int-div-03.ll index 7c0409018f16..37a7c4f748c9 100644 --- a/test/CodeGen/SystemZ/int-div-03.ll +++ b/test/CodeGen/SystemZ/int-div-03.ll @@ -75,7 +75,7 @@ define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) { ; CHECK: dsgf %r2, 0(%r4) ; CHECK: stg %r3, 0(%r5) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = sext i32 %b to i64 %div = sdiv i64 %a, %bext store i64 %div, i64 *%dest @@ -89,7 +89,7 @@ define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) { ; CHECK: dsgf %r2, 0(%r4) ; CHECK: stg %r2, 0(%r5) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = sext i32 %b to i64 %rem = srem i64 %a, %bext store i64 %rem, i64 *%dest @@ -104,7 +104,7 @@ define i64 @f8(i64 %dummy, i64 %a, i32 *%src) { ; CHECK-NOT: {{dsgf|dsgfr}} ; CHECK: ogr %r2, %r3 ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = sext i32 %b to i64 %div = sdiv i64 %a, %bext %rem = srem i64 %a, %bext @@ -117,8 +117,8 @@ define i64 @f9(i64 %dummy, i64 %a, i32 *%src) { ; CHECK-LABEL: f9: ; CHECK: dsgf %r2, 524284(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %rem = srem i64 %a, %bext ret i64 %rem @@ -131,8 +131,8 @@ define i64 @f10(i64 %dummy, i64 %a, i32 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: dsgf %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %rem = srem i64 %a, %bext ret i64 %rem @@ -143,8 +143,8 @@ define i64 @f11(i64 %dummy, i64 %a, i32 *%src) { ; CHECK-LABEL: f11: ; CHECK: dsgf %r2, -4(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %rem = srem i64 %a, %bext ret i64 %rem @@ -155,8 +155,8 @@ define i64 @f12(i64 %dummy, i64 %a, i32 *%src) { ; CHECK-LABEL: f12: ; CHECK: dsgf %r2, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %rem = srem i64 %a, %bext ret i64 %rem @@ -169,8 +169,8 @@ define i64 @f13(i64 %dummy, i64 %a, i32 *%src) { ; CHECK: agfi %r4, -524292 ; CHECK: dsgf %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %rem = srem i64 %a, %bext ret i64 %rem @@ -184,7 +184,7 @@ define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %rem = srem i64 %a, %bext ret i64 %rem @@ -199,7 +199,7 @@ define void @f15(i64 *%dest, i32 *%src) { ; CHECK: lgr %r1, %r2 ; CHECK: dsgfr %r0, [[B]] ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %a = call i64 @foo() %ext = sext i32 %b to i64 %div = sdiv i64 %a, %ext diff --git a/test/CodeGen/SystemZ/int-div-04.ll b/test/CodeGen/SystemZ/int-div-04.ll index 87f1e105f6a4..e8c6f3e03c6a 100644 --- a/test/CodeGen/SystemZ/int-div-04.ll +++ b/test/CodeGen/SystemZ/int-div-04.ll @@ -49,7 +49,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { ; CHECK: dsg %r2, 0(%r4) ; CHECK: stg %r3, 0(%r5) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %div = sdiv i64 %a, %b store i64 %div, i64 *%dest ret void @@ -62,7 +62,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { ; CHECK: dsg %r2, 0(%r4) ; CHECK: stg %r2, 0(%r5) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %rem = srem i64 %a, %b store i64 %rem, i64 *%dest ret void @@ -76,7 +76,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-NOT: {{dsg|dsgr}} ; CHECK: ogr %r2, %r3 ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %div = sdiv i64 %a, %b %rem = srem i64 %a, %b %or = or i64 %rem, %div @@ -88,8 +88,8 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f7: ; CHECK: dsg %r2, 524280(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %rem = srem i64 %a, %b ret i64 %rem } @@ -101,8 +101,8 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: dsg %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %rem = srem i64 %a, %b ret i64 %rem } @@ -112,8 +112,8 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f9: ; CHECK: dsg %r2, -8(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %rem = srem i64 %a, %b ret i64 %rem } @@ -123,8 +123,8 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f10: ; CHECK: dsg %r2, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %rem = srem i64 %a, %b ret i64 %rem } @@ -136,8 +136,8 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) { ; CHECK: agfi %r4, -524296 ; CHECK: dsg %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %rem = srem i64 %a, %b ret i64 %rem } @@ -150,7 +150,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %rem = srem i64 %a, %b ret i64 %rem } @@ -161,28 +161,28 @@ define i64 @f13(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: dsg {{%r[0-9]+}}, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 - %ptr10 = getelementptr i64 *%ptr0, i64 20 - - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 - %val10 = load i64 *%ptr10 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 + %ptr10 = getelementptr i64, i64 *%ptr0, i64 20 + + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 + %val10 = load i64 , i64 *%ptr10 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/int-div-05.ll b/test/CodeGen/SystemZ/int-div-05.ll index 817983005a9d..f80a139238ea 100644 --- a/test/CodeGen/SystemZ/int-div-05.ll +++ b/test/CodeGen/SystemZ/int-div-05.ll @@ -57,7 +57,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { ; CHECK: dlg %r2, 0(%r4) ; CHECK: stg %r3, 0(%r5) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %div = udiv i64 %a, %b store i64 %div, i64 *%dest ret void @@ -72,7 +72,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { ; CHECK: dlg %r2, 0(%r4) ; CHECK: stg %r2, 0(%r5) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %rem = urem i64 %a, %b store i64 %rem, i64 *%dest ret void @@ -88,7 +88,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-NOT: {{dlg|dlgr}} ; CHECK: ogr %r2, %r3 ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %div = udiv i64 %a, %b %rem = urem i64 %a, %b %or = or i64 %rem, %div @@ -100,8 +100,8 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f7: ; CHECK: dlg %r2, 524280(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %rem = urem i64 %a, %b ret i64 %rem } @@ -113,8 +113,8 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: dlg %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %rem = urem i64 %a, %b ret i64 %rem } @@ -124,8 +124,8 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f9: ; CHECK: dlg %r2, -8(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %rem = urem i64 %a, %b ret i64 %rem } @@ -135,8 +135,8 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f10: ; CHECK: dlg %r2, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %rem = urem i64 %a, %b ret i64 %rem } @@ -148,8 +148,8 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) { ; CHECK: agfi %r4, -524296 ; CHECK: dlg %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %rem = urem i64 %a, %b ret i64 %rem } @@ -162,7 +162,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %rem = urem i64 %a, %b ret i64 %rem } @@ -173,28 +173,28 @@ define i64 @f13(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: dlg {{%r[0-9]+}}, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 - %ptr10 = getelementptr i64 *%ptr0, i64 20 - - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 - %val10 = load i64 *%ptr10 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 + %ptr10 = getelementptr i64, i64 *%ptr0, i64 20 + + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 + %val10 = load i64 , i64 *%ptr10 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/int-move-02.ll b/test/CodeGen/SystemZ/int-move-02.ll index 5fc0843290f9..7ec0f418502a 100644 --- a/test/CodeGen/SystemZ/int-move-02.ll +++ b/test/CodeGen/SystemZ/int-move-02.ll @@ -7,7 +7,7 @@ define i32 @f1(i32 *%src) { ; CHECK-LABEL: f1: ; CHECK: l %r2, 0(%r2) ; CHECK: br %r14 - %val = load i32 *%src + %val = load i32 , i32 *%src ret i32 %val } @@ -16,8 +16,8 @@ define i32 @f2(i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: l %r2, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1023 + %val = load i32 , i32 *%ptr ret i32 %val } @@ -26,8 +26,8 @@ define i32 @f3(i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: ly %r2, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1024 + %val = load i32 , i32 *%ptr ret i32 %val } @@ -36,8 +36,8 @@ define i32 @f4(i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: ly %r2, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %val = load i32 , i32 *%ptr ret i32 %val } @@ -48,8 +48,8 @@ define i32 @f5(i32 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: l %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %val = load i32 , i32 *%ptr ret i32 %val } @@ -58,8 +58,8 @@ define i32 @f6(i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: ly %r2, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %val = load i32 , i32 *%ptr ret i32 %val } @@ -68,8 +68,8 @@ define i32 @f7(i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: ly %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %val = load i32 , i32 *%ptr ret i32 %val } @@ -80,8 +80,8 @@ define i32 @f8(i32 *%src) { ; CHECK: agfi %r2, -524292 ; CHECK: l %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %val = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %val = load i32 , i32 *%ptr ret i32 %val } @@ -93,7 +93,7 @@ define i32 @f9(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4095 %ptr = inttoptr i64 %add2 to i32 * - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr ret i32 %val } @@ -105,6 +105,6 @@ define i32 @f10(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr ret i32 %val } diff --git a/test/CodeGen/SystemZ/int-move-03.ll b/test/CodeGen/SystemZ/int-move-03.ll index 2894512e8eea..60eb0042ca87 100644 --- a/test/CodeGen/SystemZ/int-move-03.ll +++ b/test/CodeGen/SystemZ/int-move-03.ll @@ -7,7 +7,7 @@ define i64 @f1(i64 *%src) { ; CHECK-LABEL: f1: ; CHECK: lg %r2, 0(%r2) ; CHECK: br %r14 - %val = load i64 *%src + %val = load i64 , i64 *%src ret i64 %val } @@ -16,8 +16,8 @@ define i64 @f2(i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: lg %r2, 524280(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %val = load i64 , i64 *%ptr ret i64 %val } @@ -28,8 +28,8 @@ define i64 @f3(i64 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: lg %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %val = load i64 , i64 *%ptr ret i64 %val } @@ -38,8 +38,8 @@ define i64 @f4(i64 *%src) { ; CHECK-LABEL: f4: ; CHECK: lg %r2, -8(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %val = load i64 , i64 *%ptr ret i64 %val } @@ -48,8 +48,8 @@ define i64 @f5(i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: lg %r2, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %val = load i64 , i64 *%ptr ret i64 %val } @@ -60,8 +60,8 @@ define i64 @f6(i64 *%src) { ; CHECK: agfi %r2, -524296 ; CHECK: lg %r2, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %val = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %val = load i64 , i64 *%ptr ret i64 %val } @@ -73,6 +73,6 @@ define i64 @f7(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i64 * - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr ret i64 %val } diff --git a/test/CodeGen/SystemZ/int-move-04.ll b/test/CodeGen/SystemZ/int-move-04.ll index d97ed2f54a4b..cb7d86428b7e 100644 --- a/test/CodeGen/SystemZ/int-move-04.ll +++ b/test/CodeGen/SystemZ/int-move-04.ll @@ -36,7 +36,7 @@ define void @f4(i8 *%dst, i8 %val) { ; CHECK-LABEL: f4: ; CHECK: stc %r3, 4095(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%dst, i64 4095 + %ptr = getelementptr i8, i8 *%dst, i64 4095 store i8 %val, i8 *%ptr ret void } @@ -46,7 +46,7 @@ define void @f5(i8 *%dst, i8 %val) { ; CHECK-LABEL: f5: ; CHECK: stcy %r3, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%dst, i64 4096 + %ptr = getelementptr i8, i8 *%dst, i64 4096 store i8 %val, i8 *%ptr ret void } @@ -56,7 +56,7 @@ define void @f6(i8 *%dst, i8 %val) { ; CHECK-LABEL: f6: ; CHECK: stcy %r3, 524287(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%dst, i64 524287 + %ptr = getelementptr i8, i8 *%dst, i64 524287 store i8 %val, i8 *%ptr ret void } @@ -68,7 +68,7 @@ define void @f7(i8 *%dst, i8 %val) { ; CHECK: agfi %r2, 524288 ; CHECK: stc %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%dst, i64 524288 + %ptr = getelementptr i8, i8 *%dst, i64 524288 store i8 %val, i8 *%ptr ret void } @@ -78,7 +78,7 @@ define void @f8(i8 *%dst, i8 %val) { ; CHECK-LABEL: f8: ; CHECK: stcy %r3, -1(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%dst, i64 -1 + %ptr = getelementptr i8, i8 *%dst, i64 -1 store i8 %val, i8 *%ptr ret void } @@ -88,7 +88,7 @@ define void @f9(i8 *%dst, i8 %val) { ; CHECK-LABEL: f9: ; CHECK: stcy %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%dst, i64 -524288 + %ptr = getelementptr i8, i8 *%dst, i64 -524288 store i8 %val, i8 *%ptr ret void } @@ -100,7 +100,7 @@ define void @f10(i8 *%dst, i8 %val) { ; CHECK: agfi %r2, -524289 ; CHECK: stc %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i8 *%dst, i64 -524289 + %ptr = getelementptr i8, i8 *%dst, i64 -524289 store i8 %val, i8 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-move-05.ll b/test/CodeGen/SystemZ/int-move-05.ll index c21b88aa7baa..2bfe03447c84 100644 --- a/test/CodeGen/SystemZ/int-move-05.ll +++ b/test/CodeGen/SystemZ/int-move-05.ll @@ -36,7 +36,7 @@ define void @f4(i16 *%dst, i16 %val) { ; CHECK-LABEL: f4: ; CHECK: sth %r3, 4094(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%dst, i64 2047 + %ptr = getelementptr i16, i16 *%dst, i64 2047 store i16 %val, i16 *%ptr ret void } @@ -46,7 +46,7 @@ define void @f5(i16 *%dst, i16 %val) { ; CHECK-LABEL: f5: ; CHECK: sthy %r3, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%dst, i64 2048 + %ptr = getelementptr i16, i16 *%dst, i64 2048 store i16 %val, i16 *%ptr ret void } @@ -56,7 +56,7 @@ define void @f6(i16 *%dst, i16 %val) { ; CHECK-LABEL: f6: ; CHECK: sthy %r3, 524286(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%dst, i64 262143 + %ptr = getelementptr i16, i16 *%dst, i64 262143 store i16 %val, i16 *%ptr ret void } @@ -68,7 +68,7 @@ define void @f7(i16 *%dst, i16 %val) { ; CHECK: agfi %r2, 524288 ; CHECK: sth %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%dst, i64 262144 + %ptr = getelementptr i16, i16 *%dst, i64 262144 store i16 %val, i16 *%ptr ret void } @@ -78,7 +78,7 @@ define void @f8(i16 *%dst, i16 %val) { ; CHECK-LABEL: f8: ; CHECK: sthy %r3, -2(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%dst, i64 -1 + %ptr = getelementptr i16, i16 *%dst, i64 -1 store i16 %val, i16 *%ptr ret void } @@ -88,7 +88,7 @@ define void @f9(i16 *%dst, i16 %val) { ; CHECK-LABEL: f9: ; CHECK: sthy %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%dst, i64 -262144 + %ptr = getelementptr i16, i16 *%dst, i64 -262144 store i16 %val, i16 *%ptr ret void } @@ -100,7 +100,7 @@ define void @f10(i16 *%dst, i16 %val) { ; CHECK: agfi %r2, -524290 ; CHECK: sth %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i16 *%dst, i64 -262145 + %ptr = getelementptr i16, i16 *%dst, i64 -262145 store i16 %val, i16 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-move-06.ll b/test/CodeGen/SystemZ/int-move-06.ll index b8c6f53e15d8..f078ec62341f 100644 --- a/test/CodeGen/SystemZ/int-move-06.ll +++ b/test/CodeGen/SystemZ/int-move-06.ll @@ -23,7 +23,7 @@ define void @f3(i32 *%dst, i32 %val) { ; CHECK-LABEL: f3: ; CHECK: st %r3, 4092(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 1023 + %ptr = getelementptr i32, i32 *%dst, i64 1023 store i32 %val, i32 *%ptr ret void } @@ -33,7 +33,7 @@ define void @f4(i32 *%dst, i32 %val) { ; CHECK-LABEL: f4: ; CHECK: sty %r3, 4096(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 1024 + %ptr = getelementptr i32, i32 *%dst, i64 1024 store i32 %val, i32 *%ptr ret void } @@ -43,7 +43,7 @@ define void @f5(i32 *%dst, i32 %val) { ; CHECK-LABEL: f5: ; CHECK: sty %r3, 524284(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 131071 + %ptr = getelementptr i32, i32 *%dst, i64 131071 store i32 %val, i32 *%ptr ret void } @@ -55,7 +55,7 @@ define void @f6(i32 *%dst, i32 %val) { ; CHECK: agfi %r2, 524288 ; CHECK: st %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 131072 + %ptr = getelementptr i32, i32 *%dst, i64 131072 store i32 %val, i32 *%ptr ret void } @@ -65,7 +65,7 @@ define void @f7(i32 *%dst, i32 %val) { ; CHECK-LABEL: f7: ; CHECK: sty %r3, -4(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 -1 + %ptr = getelementptr i32, i32 *%dst, i64 -1 store i32 %val, i32 *%ptr ret void } @@ -75,7 +75,7 @@ define void @f8(i32 *%dst, i32 %val) { ; CHECK-LABEL: f8: ; CHECK: sty %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 -131072 + %ptr = getelementptr i32, i32 *%dst, i64 -131072 store i32 %val, i32 *%ptr ret void } @@ -87,7 +87,7 @@ define void @f9(i32 *%dst, i32 %val) { ; CHECK: agfi %r2, -524292 ; CHECK: st %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i32 *%dst, i64 -131073 + %ptr = getelementptr i32, i32 *%dst, i64 -131073 store i32 %val, i32 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-move-07.ll b/test/CodeGen/SystemZ/int-move-07.ll index 5cac1e5b1a2e..77713adeebe3 100644 --- a/test/CodeGen/SystemZ/int-move-07.ll +++ b/test/CodeGen/SystemZ/int-move-07.ll @@ -16,7 +16,7 @@ define void @f2(i64 *%dst, i64 %val) { ; CHECK-LABEL: f2: ; CHECK: stg %r3, 524280(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 65535 + %ptr = getelementptr i64, i64 *%dst, i64 65535 store i64 %val, i64 *%ptr ret void } @@ -28,7 +28,7 @@ define void @f3(i64 *%dst, i64 %val) { ; CHECK: agfi %r2, 524288 ; CHECK: stg %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 65536 + %ptr = getelementptr i64, i64 *%dst, i64 65536 store i64 %val, i64 *%ptr ret void } @@ -38,7 +38,7 @@ define void @f4(i64 *%dst, i64 %val) { ; CHECK-LABEL: f4: ; CHECK: stg %r3, -8(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 -1 + %ptr = getelementptr i64, i64 *%dst, i64 -1 store i64 %val, i64 *%ptr ret void } @@ -48,7 +48,7 @@ define void @f5(i64 *%dst, i64 %val) { ; CHECK-LABEL: f5: ; CHECK: stg %r3, -524288(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 -65536 + %ptr = getelementptr i64, i64 *%dst, i64 -65536 store i64 %val, i64 *%ptr ret void } @@ -60,7 +60,7 @@ define void @f6(i64 *%dst, i64 %val) { ; CHECK: agfi %r2, -524296 ; CHECK: stg %r3, 0(%r2) ; CHECK: br %r14 - %ptr = getelementptr i64 *%dst, i64 -65537 + %ptr = getelementptr i64, i64 *%dst, i64 -65537 store i64 %val, i64 *%ptr ret void } diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll index 56fcbc6d802b..d28d298013ff 100644 --- a/test/CodeGen/SystemZ/int-move-08.ll +++ b/test/CodeGen/SystemZ/int-move-08.ll @@ -18,7 +18,7 @@ define i32 @f1() { ; CHECK-LABEL: f1: ; CHECK: lhrl %r2, gsrc16 ; CHECK: br %r14 - %val = load i16 *@gsrc16 + %val = load i16 , i16 *@gsrc16 %ext = sext i16 %val to i32 ret i32 %ext } @@ -28,7 +28,7 @@ define i32 @f2() { ; CHECK-LABEL: f2: ; CHECK: llhrl %r2, gsrc16 ; CHECK: br %r14 - %val = load i16 *@gsrc16 + %val = load i16 , i16 *@gsrc16 %ext = zext i16 %val to i32 ret i32 %ext } @@ -49,7 +49,7 @@ define void @f4() { ; CHECK: lrl %r0, gsrc32 ; CHECK: strl %r0, gdst32 ; CHECK: br %r14 - %val = load i32 *@gsrc32 + %val = load i32 , i32 *@gsrc32 store i32 %val, i32 *@gdst32 ret void } @@ -60,7 +60,7 @@ define i32 @f5() { ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u ; CHECK: lh %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i16 *@gsrc16u, align 1 + %val = load i16 , i16 *@gsrc16u, align 1 %ext = sext i16 %val to i32 ret i32 %ext } @@ -71,7 +71,7 @@ define i32 @f6() { ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u ; CHECK: llh %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i16 *@gsrc16u, align 1 + %val = load i16 , i16 *@gsrc16u, align 1 %ext = zext i16 %val to i32 ret i32 %ext } @@ -95,7 +95,7 @@ define void @f8() { ; CHECK: larl [[REG:%r[0-5]]], gdst32u ; CHECK: st [[VAL]], 0([[REG]]) ; CHECK: br %r14 - %val = load i32 *@gsrc32u, align 2 + %val = load i32 , i32 *@gsrc32u, align 2 store i32 %val, i32 *@gdst32u, align 2 ret void } @@ -109,9 +109,9 @@ define void @f9() { ; CHECK: srl [[VAL]], 1 ; CHECK: stc [[VAL]], 1([[REG]]) ; CHECK: br %r14 - %ptr1 = getelementptr [2 x i8] *@garray8, i64 0, i64 0 - %ptr2 = getelementptr [2 x i8] *@garray8, i64 0, i64 1 - %val = load i8 *%ptr1 + %ptr1 = getelementptr [2 x i8], [2 x i8] *@garray8, i64 0, i64 0 + %ptr2 = getelementptr [2 x i8], [2 x i8] *@garray8, i64 0, i64 1 + %val = load i8 , i8 *%ptr1 %shr = lshr i8 %val, 1 store i8 %shr, i8 *%ptr2 ret void @@ -125,9 +125,9 @@ define void @f10() { ; CHECK: srl [[VAL]], 1 ; CHECK: sthrl [[VAL]], garray16+2 ; CHECK: br %r14 - %ptr1 = getelementptr [2 x i16] *@garray16, i64 0, i64 0 - %ptr2 = getelementptr [2 x i16] *@garray16, i64 0, i64 1 - %val = load i16 *%ptr1 + %ptr1 = getelementptr [2 x i16], [2 x i16] *@garray16, i64 0, i64 0 + %ptr2 = getelementptr [2 x i16], [2 x i16] *@garray16, i64 0, i64 1 + %val = load i16 , i16 *%ptr1 %shr = lshr i16 %val, 1 store i16 %shr, i16 *%ptr2 ret void diff --git a/test/CodeGen/SystemZ/int-move-09.ll b/test/CodeGen/SystemZ/int-move-09.ll index b5c9cb13d288..6476842dd12b 100644 --- a/test/CodeGen/SystemZ/int-move-09.ll +++ b/test/CodeGen/SystemZ/int-move-09.ll @@ -20,7 +20,7 @@ define i64 @f1() { ; CHECK-LABEL: f1: ; CHECK: lghrl %r2, gsrc16 ; CHECK: br %r14 - %val = load i16 *@gsrc16 + %val = load i16 , i16 *@gsrc16 %ext = sext i16 %val to i64 ret i64 %ext } @@ -30,7 +30,7 @@ define i64 @f2() { ; CHECK-LABEL: f2: ; CHECK: llghrl %r2, gsrc16 ; CHECK: br %r14 - %val = load i16 *@gsrc16 + %val = load i16 , i16 *@gsrc16 %ext = zext i16 %val to i64 ret i64 %ext } @@ -40,7 +40,7 @@ define i64 @f3() { ; CHECK-LABEL: f3: ; CHECK: lgfrl %r2, gsrc32 ; CHECK: br %r14 - %val = load i32 *@gsrc32 + %val = load i32 , i32 *@gsrc32 %ext = sext i32 %val to i64 ret i64 %ext } @@ -50,7 +50,7 @@ define i64 @f4() { ; CHECK-LABEL: f4: ; CHECK: llgfrl %r2, gsrc32 ; CHECK: br %r14 - %val = load i32 *@gsrc32 + %val = load i32 , i32 *@gsrc32 %ext = zext i32 %val to i64 ret i64 %ext } @@ -81,7 +81,7 @@ define void @f7() { ; CHECK: lgrl %r0, gsrc64 ; CHECK: stgrl %r0, gdst64 ; CHECK: br %r14 - %val = load i64 *@gsrc64 + %val = load i64 , i64 *@gsrc64 store i64 %val, i64 *@gdst64 ret void } @@ -92,7 +92,7 @@ define i64 @f8() { ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT ; CHECK: lgh %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i16 *@gsrc16u, align 1 + %val = load i16 , i16 *@gsrc16u, align 1 %ext = sext i16 %val to i64 ret i64 %ext } @@ -103,7 +103,7 @@ define i64 @f9() { ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT ; CHECK: llgh %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i16 *@gsrc16u, align 1 + %val = load i16 , i16 *@gsrc16u, align 1 %ext = zext i16 %val to i64 ret i64 %ext } @@ -114,7 +114,7 @@ define i64 @f10() { ; CHECK: larl [[REG:%r[0-5]]], gsrc32u ; CHECK: lgf %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i32 *@gsrc32u, align 2 + %val = load i32 , i32 *@gsrc32u, align 2 %ext = sext i32 %val to i64 ret i64 %ext } @@ -125,7 +125,7 @@ define i64 @f11() { ; CHECK: larl [[REG:%r[0-5]]], gsrc32u ; CHECK: llgf %r2, 0([[REG]]) ; CHECK: br %r14 - %val = load i32 *@gsrc32u, align 2 + %val = load i32 , i32 *@gsrc32u, align 2 %ext = zext i32 %val to i64 ret i64 %ext } @@ -160,7 +160,7 @@ define void @f14() { ; CHECK: larl [[REG:%r[0-5]]], gdst64u ; CHECK: stg [[VAL]], 0([[REG]]) ; CHECK: br %r14 - %val = load i64 *@gsrc64u, align 4 + %val = load i64 , i64 *@gsrc64u, align 4 store i64 %val, i64 *@gdst64u, align 4 ret void } diff --git a/test/CodeGen/SystemZ/int-mul-01.ll b/test/CodeGen/SystemZ/int-mul-01.ll index d5f7155f8c48..b0adc1874b9f 100644 --- a/test/CodeGen/SystemZ/int-mul-01.ll +++ b/test/CodeGen/SystemZ/int-mul-01.ll @@ -8,7 +8,7 @@ define i32 @f1(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f1: ; CHECK: mh %r2, 0(%r3) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -19,8 +19,8 @@ define i32 @f2(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f2: ; CHECK: mh %r2, 4094(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2047 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2047 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -31,8 +31,8 @@ define i32 @f3(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f3: ; CHECK: mhy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2048 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2048 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -43,8 +43,8 @@ define i32 @f4(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f4: ; CHECK: mhy %r2, 524286(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -57,8 +57,8 @@ define i32 @f5(i32 %lhs, i16 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: mh %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -69,8 +69,8 @@ define i32 @f6(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f6: ; CHECK: mhy %r2, -2(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -81,8 +81,8 @@ define i32 @f7(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f7: ; CHECK: mhy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -95,8 +95,8 @@ define i32 @f8(i32 %lhs, i16 *%src) { ; CHECK: agfi %r3, -524290 ; CHECK: mh %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -110,7 +110,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4094 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res @@ -124,7 +124,7 @@ define i32 @f10(i32 %lhs, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = mul i32 %lhs, %rhs ret i32 %res diff --git a/test/CodeGen/SystemZ/int-mul-02.ll b/test/CodeGen/SystemZ/int-mul-02.ll index d002a7f2f9bd..265674f6c667 100644 --- a/test/CodeGen/SystemZ/int-mul-02.ll +++ b/test/CodeGen/SystemZ/int-mul-02.ll @@ -18,7 +18,7 @@ define i32 @f2(i32 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: ms %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %mul = mul i32 %a, %b ret i32 %mul } @@ -28,8 +28,8 @@ define i32 @f3(i32 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: ms %r2, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1023 + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -39,8 +39,8 @@ define i32 @f4(i32 %a, i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: msy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1024 + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -50,8 +50,8 @@ define i32 @f5(i32 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: msy %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -63,8 +63,8 @@ define i32 @f6(i32 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: ms %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -74,8 +74,8 @@ define i32 @f7(i32 %a, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: msy %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -85,8 +85,8 @@ define i32 @f8(i32 %a, i32 *%src) { ; CHECK-LABEL: f8: ; CHECK: msy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -98,8 +98,8 @@ define i32 @f9(i32 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: ms %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -112,7 +112,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -125,7 +125,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %mul = mul i32 %a, %b ret i32 %mul } @@ -136,26 +136,26 @@ define i32 @f12(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: ms %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/int-mul-03.ll b/test/CodeGen/SystemZ/int-mul-03.ll index df18050d0242..c4d16cefc1c2 100644 --- a/test/CodeGen/SystemZ/int-mul-03.ll +++ b/test/CodeGen/SystemZ/int-mul-03.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: msgf %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = sext i32 %b to i64 %mul = mul i64 %a, %bext ret i64 %mul @@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: msgf %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %mul = mul i64 %a, %bext ret i64 %mul @@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: msgf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %mul = mul i64 %a, %bext ret i64 %mul @@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: msgf %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %mul = mul i64 %a, %bext ret i64 %mul @@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: msgf %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %mul = mul i64 %a, %bext ret i64 %mul @@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: msgf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %mul = mul i64 %a, %bext ret i64 %mul @@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %mul = mul i64 %a, %bext ret i64 %mul @@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: msgf %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %frob0 = add i32 %val0, 100 %frob1 = add i32 %val1, 100 diff --git a/test/CodeGen/SystemZ/int-mul-04.ll b/test/CodeGen/SystemZ/int-mul-04.ll index 183a9a748c37..1ec466174bc7 100644 --- a/test/CodeGen/SystemZ/int-mul-04.ll +++ b/test/CodeGen/SystemZ/int-mul-04.ll @@ -18,7 +18,7 @@ define i64 @f2(i64 %a, i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: msg %r2, 0(%r3) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %mul = mul i64 %a, %b ret i64 %mul } @@ -28,8 +28,8 @@ define i64 @f3(i64 %a, i64 *%src) { ; CHECK-LABEL: f3: ; CHECK: msg %r2, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %mul = mul i64 %a, %b ret i64 %mul } @@ -41,8 +41,8 @@ define i64 @f4(i64 %a, i64 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: msg %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %mul = mul i64 %a, %b ret i64 %mul } @@ -52,8 +52,8 @@ define i64 @f5(i64 %a, i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: msg %r2, -8(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %mul = mul i64 %a, %b ret i64 %mul } @@ -63,8 +63,8 @@ define i64 @f6(i64 %a, i64 *%src) { ; CHECK-LABEL: f6: ; CHECK: msg %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %mul = mul i64 %a, %b ret i64 %mul } @@ -76,8 +76,8 @@ define i64 @f7(i64 %a, i64 *%src) { ; CHECK: agfi %r3, -524296 ; CHECK: msg %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %mul = mul i64 %a, %b ret i64 %mul } @@ -90,7 +90,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %mul = mul i64 %a, %b ret i64 %mul } @@ -101,26 +101,26 @@ define i64 @f9(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: msg %r2, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/int-mul-08.ll b/test/CodeGen/SystemZ/int-mul-08.ll index 90b26a4f3dde..c43089677ff5 100644 --- a/test/CodeGen/SystemZ/int-mul-08.ll +++ b/test/CodeGen/SystemZ/int-mul-08.ll @@ -88,7 +88,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-NOT: {{%r[234]}} ; CHECK: mlg %r2, 0(%r4) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %ax = zext i64 %a to i128 %bx = zext i64 %b to i128 %mulx = mul i128 %ax, %bx @@ -102,8 +102,8 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f7: ; CHECK: mlg %r2, 524280(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %ax = zext i64 %a to i128 %bx = zext i64 %b to i128 %mulx = mul i128 %ax, %bx @@ -119,8 +119,8 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { ; CHECK: agfi %r4, 524288 ; CHECK: mlg %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %ax = zext i64 %a to i128 %bx = zext i64 %b to i128 %mulx = mul i128 %ax, %bx @@ -134,8 +134,8 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f9: ; CHECK: mlg %r2, -8(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %ax = zext i64 %a to i128 %bx = zext i64 %b to i128 %mulx = mul i128 %ax, %bx @@ -149,8 +149,8 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) { ; CHECK-LABEL: f10: ; CHECK: mlg %r2, -524288(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %ax = zext i64 %a to i128 %bx = zext i64 %b to i128 %mulx = mul i128 %ax, %bx @@ -166,8 +166,8 @@ define i64 @f11(i64 *%dest, i64 %a, i64 *%src) { ; CHECK: agfi %r4, -524296 ; CHECK: mlg %r2, 0(%r4) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %ax = zext i64 %a to i128 %bx = zext i64 %b to i128 %mulx = mul i128 %ax, %bx @@ -184,7 +184,7 @@ define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524287 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %ax = zext i64 %a to i128 %bx = zext i64 %b to i128 %mulx = mul i128 %ax, %bx @@ -199,26 +199,26 @@ define i64 @f13(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: mlg {{%r[0-9]+}}, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/int-sub-01.ll b/test/CodeGen/SystemZ/int-sub-01.ll index 8d1e56ddcaba..c04a619298da 100644 --- a/test/CodeGen/SystemZ/int-sub-01.ll +++ b/test/CodeGen/SystemZ/int-sub-01.ll @@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: s %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %sub = sub i32 %a, %b ret i32 %sub } @@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: s %r2, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1023 + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: sy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1024 + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: sy %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: s %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: sy %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) { ; CHECK-LABEL: f8: ; CHECK: sy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: s %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %sub = sub i32 %a, %b ret i32 %sub } @@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: s %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/int-sub-02.ll b/test/CodeGen/SystemZ/int-sub-02.ll index a1c5ec50ee9c..23be240b0c5b 100644 --- a/test/CodeGen/SystemZ/int-sub-02.ll +++ b/test/CodeGen/SystemZ/int-sub-02.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: sgf %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = sext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: sgf %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: sgf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: sgf %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: sgf %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: sgf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = sext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: sgf %r2, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %frob0 = add i32 %val0, 100 %frob1 = add i32 %val1, 100 diff --git a/test/CodeGen/SystemZ/int-sub-03.ll b/test/CodeGen/SystemZ/int-sub-03.ll index 44edd84bda4f..9d5100644102 100644 --- a/test/CodeGen/SystemZ/int-sub-03.ll +++ b/test/CodeGen/SystemZ/int-sub-03.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: slgf %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %bext = zext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -30,8 +30,8 @@ define i64 @f3(i64 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: slgf %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -44,8 +44,8 @@ define i64 @f4(i64 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: slgf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -56,8 +56,8 @@ define i64 @f5(i64 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: slgf %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -68,8 +68,8 @@ define i64 @f6(i64 %a, i32 *%src) { ; CHECK-LABEL: f6: ; CHECK: slgf %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -82,8 +82,8 @@ define i64 @f7(i64 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: slgf %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i64 %sub = sub i64 %a, %bext ret i64 %sub @@ -109,26 +109,26 @@ define i64 @f9(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: slgf %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %frob0 = add i32 %val0, 100 %frob1 = add i32 %val1, 100 diff --git a/test/CodeGen/SystemZ/int-sub-04.ll b/test/CodeGen/SystemZ/int-sub-04.ll index 85104536c5d7..ec2944d12709 100644 --- a/test/CodeGen/SystemZ/int-sub-04.ll +++ b/test/CodeGen/SystemZ/int-sub-04.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: sg %r2, 0(%r3) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %sub = sub i64 %a, %b ret i64 %sub } @@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) { ; CHECK-LABEL: f3: ; CHECK: sg %r2, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %sub = sub i64 %a, %b ret i64 %sub } @@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: sg %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %sub = sub i64 %a, %b ret i64 %sub } @@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: sg %r2, -8(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %sub = sub i64 %a, %b ret i64 %sub } @@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) { ; CHECK-LABEL: f6: ; CHECK: sg %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %sub = sub i64 %a, %b ret i64 %sub } @@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) { ; CHECK: agfi %r3, -524296 ; CHECK: sg %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %sub = sub i64 %a, %b ret i64 %sub } @@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %sub = sub i64 %a, %b ret i64 %sub } @@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: sg %r2, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/int-sub-05.ll b/test/CodeGen/SystemZ/int-sub-05.ll index 85ea14cd15f3..9775298a7a2e 100644 --- a/test/CodeGen/SystemZ/int-sub-05.ll +++ b/test/CodeGen/SystemZ/int-sub-05.ll @@ -11,7 +11,7 @@ define void @f1(i128 *%ptr, i64 %high, i64 %low) { ; CHECK: slgr {{%r[0-5]}}, %r4 ; CHECK: slbgr {{%r[0-5]}}, %r3 ; CHECK: br %r14 - %a = load i128 *%ptr + %a = load i128 , i128 *%ptr %highx = zext i64 %high to i128 %lowx = zext i64 %low to i128 %bhigh = shl i128 %highx, 64 @@ -28,9 +28,9 @@ define void @f2(i64 %addr) { ; CHECK: slbg {{%r[0-5]}}, 0(%r2) ; CHECK: br %r14 %bptr = inttoptr i64 %addr to i128 * - %aptr = getelementptr i128 *%bptr, i64 -8 - %a = load i128 *%aptr - %b = load i128 *%bptr + %aptr = getelementptr i128, i128 *%bptr, i64 -8 + %a = load i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %sub = sub i128 %a, %b store i128 %sub, i128 *%aptr ret void @@ -44,9 +44,9 @@ define void @f3(i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, 524272 %bptr = inttoptr i64 %addr to i128 * - %aptr = getelementptr i128 *%bptr, i64 -8 - %a = load i128 *%aptr - %b = load i128 *%bptr + %aptr = getelementptr i128, i128 *%bptr, i64 -8 + %a = load i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %sub = sub i128 %a, %b store i128 %sub, i128 *%aptr ret void @@ -62,9 +62,9 @@ define void @f4(i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, 524280 %bptr = inttoptr i64 %addr to i128 * - %aptr = getelementptr i128 *%bptr, i64 -8 - %a = load i128 *%aptr - %b = load i128 *%bptr + %aptr = getelementptr i128, i128 *%bptr, i64 -8 + %a = load i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %sub = sub i128 %a, %b store i128 %sub, i128 *%aptr ret void @@ -80,9 +80,9 @@ define void @f5(i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, 524288 %bptr = inttoptr i64 %addr to i128 * - %aptr = getelementptr i128 *%bptr, i64 -8 - %a = load i128 *%aptr - %b = load i128 *%bptr + %aptr = getelementptr i128, i128 *%bptr, i64 -8 + %a = load i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %sub = sub i128 %a, %b store i128 %sub, i128 *%aptr ret void @@ -96,9 +96,9 @@ define void @f6(i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, -524288 %bptr = inttoptr i64 %addr to i128 * - %aptr = getelementptr i128 *%bptr, i64 -8 - %a = load i128 *%aptr - %b = load i128 *%bptr + %aptr = getelementptr i128, i128 *%bptr, i64 -8 + %a = load i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %sub = sub i128 %a, %b store i128 %sub, i128 *%aptr ret void @@ -112,9 +112,9 @@ define void @f7(i64 %base) { ; CHECK: br %r14 %addr = add i64 %base, -524296 %bptr = inttoptr i64 %addr to i128 * - %aptr = getelementptr i128 *%bptr, i64 -8 - %a = load i128 *%aptr - %b = load i128 *%bptr + %aptr = getelementptr i128, i128 *%bptr, i64 -8 + %a = load i128 , i128 *%aptr + %b = load i128 , i128 *%bptr %sub = sub i128 %a, %b store i128 %sub, i128 *%aptr ret void @@ -128,20 +128,20 @@ define void @f8(i128 *%ptr0) { ; CHECK: slg {{%r[0-9]+}}, {{[0-9]+}}(%r15) ; CHECK: slbg {{%r[0-9]+}}, {{[0-9]+}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i128 *%ptr0, i128 2 - %ptr2 = getelementptr i128 *%ptr0, i128 4 - %ptr3 = getelementptr i128 *%ptr0, i128 6 - %ptr4 = getelementptr i128 *%ptr0, i128 8 + %ptr1 = getelementptr i128, i128 *%ptr0, i128 2 + %ptr2 = getelementptr i128, i128 *%ptr0, i128 4 + %ptr3 = getelementptr i128, i128 *%ptr0, i128 6 + %ptr4 = getelementptr i128, i128 *%ptr0, i128 8 - %val0 = load i128 *%ptr0 - %val1 = load i128 *%ptr1 - %val2 = load i128 *%ptr2 - %val3 = load i128 *%ptr3 - %val4 = load i128 *%ptr4 + %val0 = load i128 , i128 *%ptr0 + %val1 = load i128 , i128 *%ptr1 + %val2 = load i128 , i128 *%ptr2 + %val3 = load i128 , i128 *%ptr3 + %val4 = load i128 , i128 *%ptr4 %retptr = call i128 *@foo() - %ret = load i128 *%retptr + %ret = load i128 , i128 *%retptr %sub0 = sub i128 %ret, %val0 %sub1 = sub i128 %sub0, %val1 %sub2 = sub i128 %sub1, %val2 diff --git a/test/CodeGen/SystemZ/int-sub-06.ll b/test/CodeGen/SystemZ/int-sub-06.ll index 395d584b23de..c26383e9df03 100644 --- a/test/CodeGen/SystemZ/int-sub-06.ll +++ b/test/CodeGen/SystemZ/int-sub-06.ll @@ -9,7 +9,7 @@ define void @f1(i128 *%aptr, i32 %b) { ; CHECK: slgfr {{%r[0-5]}}, %r3 ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext @@ -23,7 +23,7 @@ define void @f2(i128 *%aptr, i64 %b) { ; CHECK: slgfr {{%r[0-5]}}, %r3 ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %trunc = trunc i64 %b to i32 %bext = zext i32 %trunc to i128 @@ -39,7 +39,7 @@ define void @f3(i128 *%aptr, i64 %b) { ; CHECK: slgfr {{%r[0-5]}}, %r3 ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %bext = zext i64 %b to i128 %and = and i128 %bext, 4294967295 @@ -54,9 +54,9 @@ define void @f4(i128 *%aptr, i32 *%bsrc) { ; CHECK: slgf {{%r[0-5]}}, 0(%r3) ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %b = load i32 *%bsrc + %b = load i32 , i32 *%bsrc %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext store i128 %sub, i128 *%aptr @@ -69,10 +69,10 @@ define void @f5(i128 *%aptr, i32 *%bsrc) { ; CHECK: slgf {{%r[0-5]}}, 524284(%r3) ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i64 131071 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext store i128 %sub, i128 *%aptr @@ -87,10 +87,10 @@ define void @f6(i128 *%aptr, i32 *%bsrc) { ; CHECK: slgf {{%r[0-5]}}, 0(%r3) ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i64 131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext store i128 %sub, i128 *%aptr @@ -103,10 +103,10 @@ define void @f7(i128 *%aptr, i32 *%bsrc) { ; CHECK: slgf {{%r[0-5]}}, -4(%r3) ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i128 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i128 -1 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext store i128 %sub, i128 *%aptr @@ -119,10 +119,10 @@ define void @f8(i128 *%aptr, i32 *%bsrc) { ; CHECK: slgf {{%r[0-5]}}, -524288(%r3) ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i128 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i128 -131072 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext store i128 %sub, i128 *%aptr @@ -137,10 +137,10 @@ define void @f9(i128 *%aptr, i32 *%bsrc) { ; CHECK: slgf {{%r[0-5]}}, 0(%r3) ; CHECK: slbgr ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 - %ptr = getelementptr i32 *%bsrc, i128 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%bsrc, i128 -131073 + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext store i128 %sub, i128 *%aptr @@ -152,12 +152,12 @@ define void @f10(i128 *%aptr, i64 %src, i64 %index) { ; CHECK-LABEL: f10: ; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}}) ; CHECK: br %r14 - %a = load i128 *%aptr + %a = load i128 , i128 *%aptr %xor = xor i128 %a, 127 %add1 = add i64 %src, %index %add2 = add i64 %add1, 524284 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %bext = zext i32 %b to i128 %sub = sub i128 %xor, %bext store i128 %sub, i128 *%aptr diff --git a/test/CodeGen/SystemZ/int-sub-07.ll b/test/CodeGen/SystemZ/int-sub-07.ll index 5c1f42c1cc96..1d54fd6714cf 100644 --- a/test/CodeGen/SystemZ/int-sub-07.ll +++ b/test/CodeGen/SystemZ/int-sub-07.ll @@ -8,7 +8,7 @@ define i32 @f1(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f1: ; CHECK: sh %r2, 0(%r3) ; CHECK: br %r14 - %half = load i16 *%src + %half = load i16 , i16 *%src %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -19,8 +19,8 @@ define i32 @f2(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f2: ; CHECK: sh %r2, 4094(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2047 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2047 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -31,8 +31,8 @@ define i32 @f3(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f3: ; CHECK: shy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 2048 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 2048 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -43,8 +43,8 @@ define i32 @f4(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f4: ; CHECK: shy %r2, 524286(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262143 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262143 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -57,8 +57,8 @@ define i32 @f5(i32 %lhs, i16 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: sh %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -69,8 +69,8 @@ define i32 @f6(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f6: ; CHECK: shy %r2, -2(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -1 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -1 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -81,8 +81,8 @@ define i32 @f7(i32 %lhs, i16 *%src) { ; CHECK-LABEL: f7: ; CHECK: shy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262144 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -95,8 +95,8 @@ define i32 @f8(i32 %lhs, i16 *%src) { ; CHECK: agfi %r3, -524290 ; CHECK: sh %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i16 *%src, i64 -262145 - %half = load i16 *%ptr + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -110,7 +110,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) { %sub1 = add i64 %src, %index %sub2 = add i64 %sub1, 4094 %ptr = inttoptr i64 %sub2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res @@ -124,7 +124,7 @@ define i32 @f10(i32 %lhs, i64 %src, i64 %index) { %sub1 = add i64 %src, %index %sub2 = add i64 %sub1, 4096 %ptr = inttoptr i64 %sub2 to i16 * - %half = load i16 *%ptr + %half = load i16 , i16 *%ptr %rhs = sext i16 %half to i32 %res = sub i32 %lhs, %rhs ret i32 %res diff --git a/test/CodeGen/SystemZ/loop-01.ll b/test/CodeGen/SystemZ/loop-01.ll index 580080173563..b51c96d52e3a 100644 --- a/test/CodeGen/SystemZ/loop-01.ll +++ b/test/CodeGen/SystemZ/loop-01.ll @@ -14,7 +14,7 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %next, %loop ] - %ptr = getelementptr i32 *%dest, i64 %index + %ptr = getelementptr i32, i32 *%dest, i64 %index store i32 %a, i32 *%ptr %next = add i64 %index, 1 %cmp = icmp ne i64 %next, 100 @@ -37,7 +37,7 @@ entry: loop: %count = phi i32 [ 0, %entry ], [ %next, %loop.next ] %next = add i32 %count, 1 - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cmp = icmp eq i32 %val, 0 br i1 %cmp, label %loop.next, label %loop.store @@ -67,7 +67,7 @@ entry: loop: %count = phi i64 [ 0, %entry ], [ %next, %loop.next ] %next = add i64 %count, 1 - %val = load volatile i64 *%src + %val = load volatile i64 , i64 *%src %cmp = icmp eq i64 %val, 0 br i1 %cmp, label %loop.next, label %loop.store @@ -100,7 +100,7 @@ entry: loop: %left = phi i64 [ %count, %entry ], [ %next, %loop.next ] store volatile i64 %left, i64 *%dest2 - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src %cmp = icmp eq i32 %val, 0 br i1 %cmp, label %loop.next, label %loop.store diff --git a/test/CodeGen/SystemZ/memchr-02.ll b/test/CodeGen/SystemZ/memchr-02.ll index 8986627a6057..71b2cf02b352 100644 --- a/test/CodeGen/SystemZ/memchr-02.ll +++ b/test/CodeGen/SystemZ/memchr-02.ll @@ -29,7 +29,7 @@ define i8 *@f2(i8 *%src, i8 *%charptr, i64 %len) { ; CHECK-NOT: %r0 ; CHECK: srst %r2, [[RES1]] ; CHECK: br %r14 - %char = load volatile i8 *%charptr + %char = load volatile i8 , i8 *%charptr %charext = zext i8 %char to i32 %res1 = call i8 *@memchr(i8 *%src, i32 %charext, i64 %len) %res2 = call i8 *@memchr(i8 *%res1, i32 %charext, i64 %len) @@ -48,7 +48,7 @@ define i8 *@f3(i8 *%src, i8 *%charptr, i64 %len) { ; CHECK: lr %r0, [[CHAR]] ; CHECK: srst %r2, [[RES1]] ; CHECK: br %r14 - %char = load volatile i8 *%charptr + %char = load volatile i8 , i8 *%charptr %charext = zext i8 %char to i32 %res1 = call i8 *@memchr(i8 *%src, i32 %charext, i64 %len) call void asm sideeffect "blah $0", "{r0}" (i32 0) diff --git a/test/CodeGen/SystemZ/memcpy-01.ll b/test/CodeGen/SystemZ/memcpy-01.ll index b53ec5452e25..1d7b28e940b9 100644 --- a/test/CodeGen/SystemZ/memcpy-01.ll +++ b/test/CodeGen/SystemZ/memcpy-01.ll @@ -126,8 +126,8 @@ define void @f11(i8 *%srcbase, i8 *%destbase) { ; CHECK: mvc 512(256,[[NEWDEST]]), 0([[NEWSRC]]) ; CHECK: mvc 768(255,[[NEWDEST]]), 256([[NEWSRC]]) ; CHECK: br %r14 - %dest = getelementptr i8 *%srcbase, i64 4000 - %src = getelementptr i8* %destbase, i64 3500 + %dest = getelementptr i8, i8 *%srcbase, i64 4000 + %src = getelementptr i8, i8* %destbase, i64 3500 call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1279, i32 1, i1 false) ret void @@ -146,8 +146,8 @@ define void @f12() { ; CHECK: brasl %r14, foo@PLT ; CHECK: br %r14 %arr = alloca [6000 x i8] - %dest = getelementptr [6000 x i8] *%arr, i64 0, i64 3900 - %src = getelementptr [6000 x i8] *%arr, i64 0, i64 1924 + %dest = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 3900 + %src = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 1924 call void @foo(i8 *%dest, i8 *%src) call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1279, i32 1, i1 false) @@ -168,8 +168,8 @@ define void @f13() { ; CHECK: brasl %r14, foo@PLT ; CHECK: br %r14 %arr = alloca [6000 x i8] - %dest = getelementptr [6000 x i8] *%arr, i64 0, i64 24 - %src = getelementptr [6000 x i8] *%arr, i64 0, i64 3650 + %dest = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 24 + %src = getelementptr [6000 x i8], [6000 x i8] *%arr, i64 0, i64 3650 call void @foo(i8 *%dest, i8 *%src) call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1279, i32 1, i1 false) @@ -225,8 +225,8 @@ define void @f16() { ; CHECK: brasl %r14, foo@PLT ; CHECK: br %r14 %arr = alloca [3200 x i8] - %dest = getelementptr [3200 x i8] *%arr, i64 0, i64 1600 - %src = getelementptr [3200 x i8] *%arr, i64 0, i64 0 + %dest = getelementptr [3200 x i8], [3200 x i8] *%arr, i64 0, i64 1600 + %src = getelementptr [3200 x i8], [3200 x i8] *%arr, i64 0, i64 0 call void @foo(i8 *%dest, i8 *%src) call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1537, i32 1, i1 false) diff --git a/test/CodeGen/SystemZ/memcpy-02.ll b/test/CodeGen/SystemZ/memcpy-02.ll index 776cfee50be9..df44502a8098 100644 --- a/test/CodeGen/SystemZ/memcpy-02.ll +++ b/test/CodeGen/SystemZ/memcpy-02.ll @@ -16,8 +16,8 @@ define void @f1(i8 *%ptr1) { ; CHECK-LABEL: f1: ; CHECK: mvc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 store i8 %val, i8 *%ptr2 ret void } @@ -27,8 +27,8 @@ define void @f2(i8 *%ptr1) { ; CHECK-LABEL: f2: ; CHECK: mvc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %ext = zext i8 %val to i32 %trunc = trunc i32 %ext to i8 store i8 %trunc, i8 *%ptr2 @@ -40,8 +40,8 @@ define void @f3(i8 *%ptr1) { ; CHECK-LABEL: f3: ; CHECK: mvc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %ext = zext i8 %val to i64 %trunc = trunc i64 %ext to i8 store i8 %trunc, i8 *%ptr2 @@ -53,8 +53,8 @@ define void @f4(i8 *%ptr1) { ; CHECK-LABEL: f4: ; CHECK: mvc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %ext = sext i8 %val to i32 %trunc = trunc i32 %ext to i8 store i8 %trunc, i8 *%ptr2 @@ -66,8 +66,8 @@ define void @f5(i8 *%ptr1) { ; CHECK-LABEL: f5: ; CHECK: mvc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 %ext = sext i8 %val to i64 %trunc = trunc i64 %ext to i8 store i8 %trunc, i8 *%ptr2 @@ -79,8 +79,8 @@ define void @f6(i16 *%ptr1) { ; CHECK-LABEL: f6: ; CHECK: mvc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 store i16 %val, i16 *%ptr2 ret void } @@ -90,8 +90,8 @@ define void @f7(i16 *%ptr1) { ; CHECK-LABEL: f7: ; CHECK: mvc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 %ext = zext i16 %val to i32 %trunc = trunc i32 %ext to i16 store i16 %trunc, i16 *%ptr2 @@ -103,8 +103,8 @@ define void @f8(i16 *%ptr1) { ; CHECK-LABEL: f8: ; CHECK: mvc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 %ext = zext i16 %val to i64 %trunc = trunc i64 %ext to i16 store i16 %trunc, i16 *%ptr2 @@ -116,8 +116,8 @@ define void @f9(i16 *%ptr1) { ; CHECK-LABEL: f9: ; CHECK: mvc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 %ext = sext i16 %val to i32 %trunc = trunc i32 %ext to i16 store i16 %trunc, i16 *%ptr2 @@ -129,8 +129,8 @@ define void @f10(i16 *%ptr1) { ; CHECK-LABEL: f10: ; CHECK: mvc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 %ext = sext i16 %val to i64 %trunc = trunc i64 %ext to i16 store i16 %trunc, i16 *%ptr2 @@ -142,8 +142,8 @@ define void @f11(i32 *%ptr1) { ; CHECK-LABEL: f11: ; CHECK: mvc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i32 *%ptr1, i64 1 - %val = load i32 *%ptr1 + %ptr2 = getelementptr i32, i32 *%ptr1, i64 1 + %val = load i32 , i32 *%ptr1 store i32 %val, i32 *%ptr2 ret void } @@ -153,8 +153,8 @@ define void @f12(i32 *%ptr1) { ; CHECK-LABEL: f12: ; CHECK: mvc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i32 *%ptr1, i64 1 - %val = load i32 *%ptr1 + %ptr2 = getelementptr i32, i32 *%ptr1, i64 1 + %val = load i32 , i32 *%ptr1 %ext = zext i32 %val to i64 %trunc = trunc i64 %ext to i32 store i32 %trunc, i32 *%ptr2 @@ -166,8 +166,8 @@ define void @f13(i32 *%ptr1) { ; CHECK-LABEL: f13: ; CHECK: mvc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i32 *%ptr1, i64 1 - %val = load i32 *%ptr1 + %ptr2 = getelementptr i32, i32 *%ptr1, i64 1 + %val = load i32 , i32 *%ptr1 %ext = sext i32 %val to i64 %trunc = trunc i64 %ext to i32 store i32 %trunc, i32 *%ptr2 @@ -179,8 +179,8 @@ define void @f14(i64 *%ptr1) { ; CHECK-LABEL: f14: ; CHECK: mvc 8(8,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1 store i64 %val, i64 *%ptr2 ret void } @@ -190,8 +190,8 @@ define void @f15(float *%ptr1) { ; CHECK-LABEL: f15: ; CHECK: mvc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr float *%ptr1, i64 1 - %val = load float *%ptr1 + %ptr2 = getelementptr float, float *%ptr1, i64 1 + %val = load float , float *%ptr1 store float %val, float *%ptr2 ret void } @@ -201,8 +201,8 @@ define void @f16(double *%ptr1) { ; CHECK-LABEL: f16: ; CHECK: mvc 8(8,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr double *%ptr1, i64 1 - %val = load double *%ptr1 + %ptr2 = getelementptr double, double *%ptr1, i64 1 + %val = load double , double *%ptr1 store double %val, double *%ptr2 ret void } @@ -212,8 +212,8 @@ define void @f17(fp128 *%ptr1) { ; CHECK-LABEL: f17: ; CHECK: mvc 16(16,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr fp128 *%ptr1, i64 1 - %val = load fp128 *%ptr1 + %ptr2 = getelementptr fp128, fp128 *%ptr1, i64 1 + %val = load fp128 , fp128 *%ptr1 store fp128 %val, fp128 *%ptr2 ret void } @@ -223,8 +223,8 @@ define void @f18(i64 *%ptr1) { ; CHECK-LABEL: f18: ; CHECK-NOT: mvc ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load volatile i64 *%ptr1 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load volatile i64 , i64 *%ptr1 store i64 %val, i64 *%ptr2 ret void } @@ -234,8 +234,8 @@ define void @f19(i64 *%ptr1) { ; CHECK-LABEL: f19: ; CHECK-NOT: mvc ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1 store volatile i64 %val, i64 *%ptr2 ret void } @@ -247,7 +247,7 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f20: ; CHECK-NOT: mvc ; CHECK: br %r14 - %val = load i64 *%ptr1 + %val = load i64 , i64 *%ptr1 store i64 %val, i64 *%ptr2 ret void } @@ -257,7 +257,7 @@ define void @f21(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f21: ; CHECK-NOT: mvc ; CHECK: br %r14 - %val = load i64 *%ptr1, align 2 + %val = load i64 , i64 *%ptr1, align 2 store i64 %val, i64 *%ptr2, align 2 ret void } @@ -270,7 +270,7 @@ define void @f22(i64 %base) { %add = add i64 %base, 1 %ptr1 = inttoptr i64 %base to i64 * %ptr2 = inttoptr i64 %add to i64 * - %val = load i64 *%ptr1, align 1 + %val = load i64 , i64 *%ptr1, align 1 store i64 %val, i64 *%ptr2, align 1 ret void } @@ -282,7 +282,7 @@ define void @f23(i8 *%ptr) { ; CHECK-DAG: larl [[DST:%r[0-5]]], g1dst ; CHECK: mvc 0(1,[[DST]]), 0([[SRC]]) ; CHECK: br %r14 - %val = load i8 *@g1src + %val = load i8 , i8 *@g1src store i8 %val, i8 *@g1dst ret void } @@ -293,7 +293,7 @@ define void @f24(i16 *%ptr) { ; CHECK: lhrl [[REG:%r[0-5]]], g2src ; CHECK: sthrl [[REG]], g2dst ; CHECK: br %r14 - %val = load i16 *@g2src + %val = load i16 , i16 *@g2src store i16 %val, i16 *@g2dst ret void } @@ -304,7 +304,7 @@ define void @f25(i32 *%ptr) { ; CHECK: lrl [[REG:%r[0-5]]], g3 ; CHECK: st [[REG]], 0(%r2) ; CHECK: br %r14 - %val = load i32 *@g3 + %val = load i32 , i32 *@g3 store i32 %val, i32 *%ptr ret void } @@ -315,7 +315,7 @@ define void @f26(i32 *%ptr) { ; CHECK: l [[REG:%r[0-5]]], 0(%r2) ; CHECK: strl [[REG]], g3 ; CHECK: br %r14 - %val = load i32 *%ptr + %val = load i32 , i32 *%ptr store i32 %val, i32 *@g3 ret void } @@ -326,7 +326,7 @@ define void @f27(i64 *%ptr) { ; CHECK: lgrl [[REG:%r[0-5]]], g4 ; CHECK: stg [[REG]], 0(%r2) ; CHECK: br %r14 - %val = load i64 *@g4 + %val = load i64 , i64 *@g4 store i64 %val, i64 *%ptr ret void } @@ -337,7 +337,7 @@ define void @f28(i64 *%ptr) { ; CHECK: lg [[REG:%r[0-5]]], 0(%r2) ; CHECK: stgrl [[REG]], g4 ; CHECK: br %r14 - %val = load i64 *%ptr + %val = load i64 , i64 *%ptr store i64 %val, i64 *@g4 ret void } @@ -349,7 +349,7 @@ define void @f29(fp128 *%ptr) { ; CHECK-DAG: larl [[DST:%r[0-5]]], g5dst ; CHECK: mvc 0(16,[[DST]]), 0([[SRC]]) ; CHECK: br %r14 - %val = load fp128 *@g5src, align 16 + %val = load fp128 , fp128 *@g5src, align 16 store fp128 %val, fp128 *@g5dst, align 16 ret void } @@ -359,8 +359,8 @@ define void @f30(i64 *%ptr1) { ; CHECK-LABEL: f30: ; CHECK: mvc 8(8,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1, align 1 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1, align 1 store i64 %val, i64 *%ptr2, align 1 ret void } @@ -370,7 +370,7 @@ define void @f31(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f31: ; CHECK: mvc 0(8,%r3), 0(%r2) ; CHECK: br %r14 - %val = load i64 *%ptr1, align 2, !tbaa !1 + %val = load i64 , i64 *%ptr1, align 2, !tbaa !1 store i64 %val, i64 *%ptr2, align 2, !tbaa !2 ret void } @@ -380,7 +380,7 @@ define void @f32(i64 *%ptr1, i64 *%ptr2) { ; CHECK-LABEL: f32: ; CHECK-NOT: mvc ; CHECK: br %r14 - %val = load i64 *%ptr1, align 2, !tbaa !1 + %val = load i64 , i64 *%ptr1, align 2, !tbaa !1 store i64 %val, i64 *%ptr2, align 2, !tbaa !1 ret void } diff --git a/test/CodeGen/SystemZ/or-01.ll b/test/CodeGen/SystemZ/or-01.ll index 23946d320678..ce556ef85a1b 100644 --- a/test/CodeGen/SystemZ/or-01.ll +++ b/test/CodeGen/SystemZ/or-01.ll @@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: o %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %or = or i32 %a, %b ret i32 %or } @@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: o %r2, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1023 + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: oy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1024 + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: oy %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: o %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: oy %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) { ; CHECK-LABEL: f8: ; CHECK: oy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: o %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %or = or i32 %a, %b ret i32 %or } @@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: o %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/or-03.ll b/test/CodeGen/SystemZ/or-03.ll index 5fdbdfd1ed1f..f29953796b06 100644 --- a/test/CodeGen/SystemZ/or-03.ll +++ b/test/CodeGen/SystemZ/or-03.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: og %r2, 0(%r3) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %or = or i64 %a, %b ret i64 %or } @@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) { ; CHECK-LABEL: f3: ; CHECK: og %r2, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %or = or i64 %a, %b ret i64 %or } @@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: og %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %or = or i64 %a, %b ret i64 %or } @@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: og %r2, -8(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %or = or i64 %a, %b ret i64 %or } @@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) { ; CHECK-LABEL: f6: ; CHECK: og %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %or = or i64 %a, %b ret i64 %or } @@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) { ; CHECK: agfi %r3, -524296 ; CHECK: og %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %or = or i64 %a, %b ret i64 %or } @@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %or = or i64 %a, %b ret i64 %or } @@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: og %r2, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/or-05.ll b/test/CodeGen/SystemZ/or-05.ll index d90589128674..3fb70d94b37d 100644 --- a/test/CodeGen/SystemZ/or-05.ll +++ b/test/CodeGen/SystemZ/or-05.ll @@ -7,7 +7,7 @@ define void @f1(i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: oi 0(%r2), 1 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %or = or i8 %val, -255 store i8 %or, i8 *%ptr ret void @@ -18,7 +18,7 @@ define void @f2(i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %or = or i8 %val, -2 store i8 %or, i8 *%ptr ret void @@ -29,7 +29,7 @@ define void @f3(i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: oi 0(%r2), 1 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %or = or i8 %val, 1 store i8 %or, i8 *%ptr ret void @@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %or = or i8 %val, 254 store i8 %or, i8 *%ptr ret void @@ -51,8 +51,8 @@ define void @f5(i8 *%src) { ; CHECK-LABEL: f5: ; CHECK: oi 4095(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4095 + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -63,8 +63,8 @@ define void @f6(i8 *%src) { ; CHECK-LABEL: f6: ; CHECK: oiy 4096(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4096 + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -75,8 +75,8 @@ define void @f7(i8 *%src) { ; CHECK-LABEL: f7: ; CHECK: oiy 524287(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -89,8 +89,8 @@ define void @f8(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: oi 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -101,8 +101,8 @@ define void @f9(i8 *%src) { ; CHECK-LABEL: f9: ; CHECK: oiy -1(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -113,8 +113,8 @@ define void @f10(i8 *%src) { ; CHECK-LABEL: f10: ; CHECK: oiy -524288(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -127,8 +127,8 @@ define void @f11(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: oi 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -143,7 +143,7 @@ define void @f12(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4095 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void @@ -158,7 +158,7 @@ define void @f13(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %or = or i8 %val, 127 store i8 %or, i8 *%ptr ret void diff --git a/test/CodeGen/SystemZ/or-06.ll b/test/CodeGen/SystemZ/or-06.ll index 0a865d350942..6f441f44b96a 100644 --- a/test/CodeGen/SystemZ/or-06.ll +++ b/test/CodeGen/SystemZ/or-06.ll @@ -8,7 +8,7 @@ define void @f1(i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %or = or i32 %ext, -2 %trunc = trunc i32 %or to i8 @@ -21,7 +21,7 @@ define void @f2(i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %or = or i64 %ext, -2 %trunc = trunc i64 %or to i8 @@ -34,7 +34,7 @@ define void @f3(i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %or = or i32 %ext, 254 %trunc = trunc i32 %or to i8 @@ -47,7 +47,7 @@ define void @f4(i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %or = or i64 %ext, 254 %trunc = trunc i64 %or to i8 @@ -60,7 +60,7 @@ define void @f5(i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %or = or i32 %ext, -2 %trunc = trunc i32 %or to i8 @@ -73,7 +73,7 @@ define void @f6(i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %or = or i64 %ext, -2 %trunc = trunc i64 %or to i8 @@ -86,7 +86,7 @@ define void @f7(i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %or = or i32 %ext, 254 %trunc = trunc i32 %or to i8 @@ -99,7 +99,7 @@ define void @f8(i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: oi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %or = or i64 %ext, 254 %trunc = trunc i64 %or to i8 diff --git a/test/CodeGen/SystemZ/or-08.ll b/test/CodeGen/SystemZ/or-08.ll index 8f5bf3170bed..a9921b11e227 100644 --- a/test/CodeGen/SystemZ/or-08.ll +++ b/test/CodeGen/SystemZ/or-08.ll @@ -7,9 +7,9 @@ define void @f1(i8 *%ptr1) { ; CHECK-LABEL: f1: ; CHECK: oc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 - %old = load i8 *%ptr2 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 + %old = load i8 , i8 *%ptr2 %or = or i8 %val, %old store i8 %or, i8 *%ptr2 ret void @@ -20,9 +20,9 @@ define void @f2(i16 *%ptr1) { ; CHECK-LABEL: f2: ; CHECK: oc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 - %old = load i16 *%ptr2 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 + %old = load i16 , i16 *%ptr2 %or = or i16 %val, %old store i16 %or, i16 *%ptr2 ret void @@ -33,9 +33,9 @@ define void @f3(i32 *%ptr1) { ; CHECK-LABEL: f3: ; CHECK: oc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i32 *%ptr1, i64 1 - %val = load i32 *%ptr1 - %old = load i32 *%ptr2 + %ptr2 = getelementptr i32, i32 *%ptr1, i64 1 + %val = load i32 , i32 *%ptr1 + %old = load i32 , i32 *%ptr2 %or = or i32 %old, %val store i32 %or, i32 *%ptr2 ret void @@ -46,9 +46,9 @@ define void @f4(i64 *%ptr1) { ; CHECK-LABEL: f4: ; CHECK: oc 8(8,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1 - %old = load i64 *%ptr2 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2 %or = or i64 %old, %val store i64 %or, i64 *%ptr2 ret void diff --git a/test/CodeGen/SystemZ/prefetch-01.ll b/test/CodeGen/SystemZ/prefetch-01.ll index bb7fea99ca7c..814738022269 100644 --- a/test/CodeGen/SystemZ/prefetch-01.ll +++ b/test/CodeGen/SystemZ/prefetch-01.ll @@ -48,7 +48,7 @@ define void @f5(i8 *%base, i64 %index) { ; CHECK: pfd 2, -524288({{%r2,%r3|%r3,%r2}}) ; CHECK: br %r14 %add = add i64 %index, -524288 - %ptr = getelementptr i8 *%base, i64 %add + %ptr = getelementptr i8, i8 *%base, i64 %add call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1) ret void } @@ -59,7 +59,7 @@ define void @f6(i8 *%base, i64 %index) { ; CHECK: pfd 2, 524287({{%r2,%r3|%r3,%r2}}) ; CHECK: br %r14 %add = add i64 %index, 524287 - %ptr = getelementptr i8 *%base, i64 %add + %ptr = getelementptr i8, i8 *%base, i64 %add call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1) ret void } @@ -71,7 +71,7 @@ define void @f7(i8 *%base, i64 %index) { ; CHECK: pfd 2, ; CHECK: br %r14 %add = add i64 %index, 524288 - %ptr = getelementptr i8 *%base, i64 %add + %ptr = getelementptr i8, i8 *%base, i64 %add call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1) ret void } @@ -81,7 +81,7 @@ define void @f8() { ; CHECK-LABEL: f8: ; CHECK: pfdrl 2, g ; CHECK: br %r14 - %ptr = getelementptr [4096 x i8] *@g, i64 0, i64 0 + %ptr = getelementptr [4096 x i8], [4096 x i8] *@g, i64 0, i64 0 call void @llvm.prefetch(i8 *%ptr, i32 1, i32 0, i32 1) ret void } diff --git a/test/CodeGen/SystemZ/risbg-03.ll b/test/CodeGen/SystemZ/risbg-03.ll new file mode 100644 index 000000000000..c3c08ad17961 --- /dev/null +++ b/test/CodeGen/SystemZ/risbg-03.ll @@ -0,0 +1,30 @@ +; Test use of RISBG vs RISBGN on zEC12. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s + +; On zEC12, we generally prefer RISBGN. +define i64 @f1(i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK: risbgn %r2, %r3, 60, 62, 0 +; CHECK: br %r14 + %anda = and i64 %a, -15 + %andb = and i64 %b, 14 + %or = or i64 %anda, %andb + ret i64 %or +} + +; But we may fall back to RISBG if we can use the condition code. +define i64 @f2(i64 %a, i64 %b, i32* %c) { +; CHECK-LABEL: f2: +; CHECK: risbg %r2, %r3, 60, 62, 0 +; CHECK-NEXT: ipm +; CHECK: br %r14 + %anda = and i64 %a, -15 + %andb = and i64 %b, 14 + %or = or i64 %anda, %andb + %cmp = icmp sgt i64 %or, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* %c, align 4 + ret i64 %or +} + diff --git a/test/CodeGen/SystemZ/serialize-01.ll b/test/CodeGen/SystemZ/serialize-01.ll index 7801fac8d472..4a245172465f 100644 --- a/test/CodeGen/SystemZ/serialize-01.ll +++ b/test/CodeGen/SystemZ/serialize-01.ll @@ -16,6 +16,6 @@ define i32 @f1(i32 *%src) { ; CHECK-FAST: bcr 14, %r0 ; CHECK-FAST: l %r2, 0(%r2) ; CHECK-FAST: br %r14 - %val = load volatile i32 *%src + %val = load volatile i32 , i32 *%src ret i32 %val } diff --git a/test/CodeGen/SystemZ/shift-01.ll b/test/CodeGen/SystemZ/shift-01.ll index 5dab36b379c4..3e838f56ae3f 100644 --- a/test/CodeGen/SystemZ/shift-01.ll +++ b/test/CodeGen/SystemZ/shift-01.ll @@ -108,7 +108,7 @@ define i32 @f11(i32 %a, i32 *%ptr) { ; CHECK: l %r1, 0(%r3) ; CHECK: sll %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i32 *%ptr + %amt = load i32 , i32 *%ptr %shift = shl i32 %a, %amt ret i32 %shift } diff --git a/test/CodeGen/SystemZ/shift-02.ll b/test/CodeGen/SystemZ/shift-02.ll index 27e73cd3a1f8..43576dbddeb1 100644 --- a/test/CodeGen/SystemZ/shift-02.ll +++ b/test/CodeGen/SystemZ/shift-02.ll @@ -108,7 +108,7 @@ define i32 @f11(i32 %a, i32 *%ptr) { ; CHECK: l %r1, 0(%r3) ; CHECK: srl %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i32 *%ptr + %amt = load i32 , i32 *%ptr %shift = lshr i32 %a, %amt ret i32 %shift } diff --git a/test/CodeGen/SystemZ/shift-03.ll b/test/CodeGen/SystemZ/shift-03.ll index c45ae48b4071..6803ff5ae311 100644 --- a/test/CodeGen/SystemZ/shift-03.ll +++ b/test/CodeGen/SystemZ/shift-03.ll @@ -108,7 +108,7 @@ define i32 @f11(i32 %a, i32 *%ptr) { ; CHECK: l %r1, 0(%r3) ; CHECK: sra %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i32 *%ptr + %amt = load i32 , i32 *%ptr %shift = ashr i32 %a, %amt ret i32 %shift } diff --git a/test/CodeGen/SystemZ/shift-04.ll b/test/CodeGen/SystemZ/shift-04.ll index de2d74f27fa3..2a32872a69ce 100644 --- a/test/CodeGen/SystemZ/shift-04.ll +++ b/test/CodeGen/SystemZ/shift-04.ll @@ -180,7 +180,7 @@ define i32 @f14(i32 %a, i32 *%ptr) { ; CHECK: l %r1, 0(%r3) ; CHECK: rll %r2, %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i32 *%ptr + %amt = load i32 , i32 *%ptr %amtb = sub i32 32, %amt %parta = shl i32 %a, %amt %partb = lshr i32 %a, %amtb diff --git a/test/CodeGen/SystemZ/shift-05.ll b/test/CodeGen/SystemZ/shift-05.ll index 833b2fbae1e5..240be3f9df1f 100644 --- a/test/CodeGen/SystemZ/shift-05.ll +++ b/test/CodeGen/SystemZ/shift-05.ll @@ -143,7 +143,7 @@ define i64 @f14(i64 %a, i64 *%ptr) { ; CHECK: l %r1, 4(%r3) ; CHECK: sllg %r2, %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i64 *%ptr + %amt = load i64 , i64 *%ptr %shift = shl i64 %a, %amt ret i64 %shift } diff --git a/test/CodeGen/SystemZ/shift-06.ll b/test/CodeGen/SystemZ/shift-06.ll index 74cae1213a3e..d9b9f473fe7c 100644 --- a/test/CodeGen/SystemZ/shift-06.ll +++ b/test/CodeGen/SystemZ/shift-06.ll @@ -143,7 +143,7 @@ define i64 @f14(i64 %a, i64 *%ptr) { ; CHECK: l %r1, 4(%r3) ; CHECK: srlg %r2, %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i64 *%ptr + %amt = load i64 , i64 *%ptr %shift = lshr i64 %a, %amt ret i64 %shift } diff --git a/test/CodeGen/SystemZ/shift-07.ll b/test/CodeGen/SystemZ/shift-07.ll index 712849df8ad1..161628864e1b 100644 --- a/test/CodeGen/SystemZ/shift-07.ll +++ b/test/CodeGen/SystemZ/shift-07.ll @@ -143,7 +143,7 @@ define i64 @f14(i64 %a, i64 *%ptr) { ; CHECK: l %r1, 4(%r3) ; CHECK: srag %r2, %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i64 *%ptr + %amt = load i64 , i64 *%ptr %shift = ashr i64 %a, %amt ret i64 %shift } diff --git a/test/CodeGen/SystemZ/shift-08.ll b/test/CodeGen/SystemZ/shift-08.ll index 47283b50221c..0db53c92246d 100644 --- a/test/CodeGen/SystemZ/shift-08.ll +++ b/test/CodeGen/SystemZ/shift-08.ll @@ -181,7 +181,7 @@ define i64 @f14(i64 %a, i64 *%ptr) { ; CHECK: l %r1, 4(%r3) ; CHECK: rllg %r2, %r2, 0(%r1) ; CHECK: br %r14 - %amt = load i64 *%ptr + %amt = load i64 , i64 *%ptr %amtb = sub i64 64, %amt %parta = shl i64 %a, %amt %partb = lshr i64 %a, %amtb diff --git a/test/CodeGen/SystemZ/spill-01.ll b/test/CodeGen/SystemZ/spill-01.ll index c1f780c55d3c..a59c06f192b6 100644 --- a/test/CodeGen/SystemZ/spill-01.ll +++ b/test/CodeGen/SystemZ/spill-01.ll @@ -37,20 +37,20 @@ define void @f1(i32 *%ptr0) { ; CHECK-NOT: %r15 ; CHECK: lmg ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i32 2 - %ptr2 = getelementptr i32 *%ptr0, i32 4 - %ptr3 = getelementptr i32 *%ptr0, i32 6 - %ptr4 = getelementptr i32 *%ptr0, i32 8 - %ptr5 = getelementptr i32 *%ptr0, i32 10 - %ptr6 = getelementptr i32 *%ptr0, i32 12 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 + %ptr1 = getelementptr i32, i32 *%ptr0, i32 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i32 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i32 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i32 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i32 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i32 12 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 call void @foo() @@ -73,24 +73,24 @@ define void @f2(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 call void @foo() @@ -115,24 +115,24 @@ define void @f3(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 call void @foo() @@ -160,26 +160,26 @@ define void @f4(float *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15) ; CHECK: br %r14 - %ptr1 = getelementptr float *%ptr0, i64 2 - %ptr2 = getelementptr float *%ptr0, i64 4 - %ptr3 = getelementptr float *%ptr0, i64 6 - %ptr4 = getelementptr float *%ptr0, i64 8 - %ptr5 = getelementptr float *%ptr0, i64 10 - %ptr6 = getelementptr float *%ptr0, i64 12 - %ptr7 = getelementptr float *%ptr0, i64 14 - %ptr8 = getelementptr float *%ptr0, i64 16 - %ptr9 = getelementptr float *%ptr0, i64 18 - - %val0 = load float *%ptr0 - %val1 = load float *%ptr1 - %val2 = load float *%ptr2 - %val3 = load float *%ptr3 - %val4 = load float *%ptr4 - %val5 = load float *%ptr5 - %val6 = load float *%ptr6 - %val7 = load float *%ptr7 - %val8 = load float *%ptr8 - %val9 = load float *%ptr9 + %ptr1 = getelementptr float, float *%ptr0, i64 2 + %ptr2 = getelementptr float, float *%ptr0, i64 4 + %ptr3 = getelementptr float, float *%ptr0, i64 6 + %ptr4 = getelementptr float, float *%ptr0, i64 8 + %ptr5 = getelementptr float, float *%ptr0, i64 10 + %ptr6 = getelementptr float, float *%ptr0, i64 12 + %ptr7 = getelementptr float, float *%ptr0, i64 14 + %ptr8 = getelementptr float, float *%ptr0, i64 16 + %ptr9 = getelementptr float, float *%ptr0, i64 18 + + %val0 = load float , float *%ptr0 + %val1 = load float , float *%ptr1 + %val2 = load float , float *%ptr2 + %val3 = load float , float *%ptr3 + %val4 = load float , float *%ptr4 + %val5 = load float , float *%ptr5 + %val6 = load float , float *%ptr6 + %val7 = load float , float *%ptr7 + %val8 = load float , float *%ptr8 + %val9 = load float , float *%ptr9 call void @foo() @@ -204,26 +204,26 @@ define void @f5(double *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr double *%ptr0, i64 2 - %ptr2 = getelementptr double *%ptr0, i64 4 - %ptr3 = getelementptr double *%ptr0, i64 6 - %ptr4 = getelementptr double *%ptr0, i64 8 - %ptr5 = getelementptr double *%ptr0, i64 10 - %ptr6 = getelementptr double *%ptr0, i64 12 - %ptr7 = getelementptr double *%ptr0, i64 14 - %ptr8 = getelementptr double *%ptr0, i64 16 - %ptr9 = getelementptr double *%ptr0, i64 18 - - %val0 = load double *%ptr0 - %val1 = load double *%ptr1 - %val2 = load double *%ptr2 - %val3 = load double *%ptr3 - %val4 = load double *%ptr4 - %val5 = load double *%ptr5 - %val6 = load double *%ptr6 - %val7 = load double *%ptr7 - %val8 = load double *%ptr8 - %val9 = load double *%ptr9 + %ptr1 = getelementptr double, double *%ptr0, i64 2 + %ptr2 = getelementptr double, double *%ptr0, i64 4 + %ptr3 = getelementptr double, double *%ptr0, i64 6 + %ptr4 = getelementptr double, double *%ptr0, i64 8 + %ptr5 = getelementptr double, double *%ptr0, i64 10 + %ptr6 = getelementptr double, double *%ptr0, i64 12 + %ptr7 = getelementptr double, double *%ptr0, i64 14 + %ptr8 = getelementptr double, double *%ptr0, i64 16 + %ptr9 = getelementptr double, double *%ptr0, i64 18 + + %val0 = load double , double *%ptr0 + %val1 = load double , double *%ptr1 + %val2 = load double , double *%ptr2 + %val3 = load double , double *%ptr3 + %val4 = load double , double *%ptr4 + %val5 = load double , double *%ptr5 + %val6 = load double , double *%ptr6 + %val7 = load double , double *%ptr7 + %val8 = load double , double *%ptr8 + %val9 = load double , double *%ptr9 call void @foo() @@ -246,24 +246,24 @@ define void @f6(i32 *%ptr0) { ; CHECK-LABEL: f6: ; CHECK-NOT: mvc ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - - %val0 = load atomic i32 *%ptr0 unordered, align 4 - %val1 = load atomic i32 *%ptr1 unordered, align 4 - %val2 = load atomic i32 *%ptr2 unordered, align 4 - %val3 = load atomic i32 *%ptr3 unordered, align 4 - %val4 = load atomic i32 *%ptr4 unordered, align 4 - %val5 = load atomic i32 *%ptr5 unordered, align 4 - %val6 = load atomic i32 *%ptr6 unordered, align 4 - %val7 = load atomic i32 *%ptr7 unordered, align 4 - %val8 = load atomic i32 *%ptr8 unordered, align 4 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + + %val0 = load atomic i32 , i32 *%ptr0 unordered, align 4 + %val1 = load atomic i32 , i32 *%ptr1 unordered, align 4 + %val2 = load atomic i32 , i32 *%ptr2 unordered, align 4 + %val3 = load atomic i32 , i32 *%ptr3 unordered, align 4 + %val4 = load atomic i32 , i32 *%ptr4 unordered, align 4 + %val5 = load atomic i32 , i32 *%ptr5 unordered, align 4 + %val6 = load atomic i32 , i32 *%ptr6 unordered, align 4 + %val7 = load atomic i32 , i32 *%ptr7 unordered, align 4 + %val8 = load atomic i32 , i32 *%ptr8 unordered, align 4 call void @foo() @@ -285,24 +285,24 @@ define void @f7(i32 *%ptr0) { ; CHECK-LABEL: f7: ; CHECK-NOT: mvc ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - - %val0 = load volatile i32 *%ptr0 - %val1 = load volatile i32 *%ptr1 - %val2 = load volatile i32 *%ptr2 - %val3 = load volatile i32 *%ptr3 - %val4 = load volatile i32 *%ptr4 - %val5 = load volatile i32 *%ptr5 - %val6 = load volatile i32 *%ptr6 - %val7 = load volatile i32 *%ptr7 - %val8 = load volatile i32 *%ptr8 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + + %val0 = load volatile i32 , i32 *%ptr0 + %val1 = load volatile i32 , i32 *%ptr1 + %val2 = load volatile i32 , i32 *%ptr2 + %val3 = load volatile i32 , i32 *%ptr3 + %val4 = load volatile i32 , i32 *%ptr4 + %val5 = load volatile i32 , i32 *%ptr5 + %val6 = load volatile i32 , i32 *%ptr6 + %val7 = load volatile i32 , i32 *%ptr7 + %val8 = load volatile i32 , i32 *%ptr8 call void @foo() @@ -324,16 +324,16 @@ define void @f8() { ; CHECK-LABEL: f8: ; CHECK-NOT: mvc ; CHECK: br %r14 - %val0 = load i32 *@g0 - %val1 = load i32 *@g1 - %val2 = load i32 *@g2 - %val3 = load i32 *@g3 - %val4 = load i32 *@g4 - %val5 = load i32 *@g5 - %val6 = load i32 *@g6 - %val7 = load i32 *@g7 - %val8 = load i32 *@g8 - %val9 = load i32 *@g9 + %val0 = load i32 , i32 *@g0 + %val1 = load i32 , i32 *@g1 + %val2 = load i32 , i32 *@g2 + %val3 = load i32 , i32 *@g3 + %val4 = load i32 , i32 *@g4 + %val5 = load i32 , i32 *@g5 + %val6 = load i32 , i32 *@g6 + %val7 = load i32 , i32 *@g7 + %val8 = load i32 , i32 *@g8 + %val9 = load i32 , i32 *@g9 call void @foo() @@ -356,16 +356,16 @@ define void @f9() { ; CHECK-LABEL: f9: ; CHECK-NOT: mvc ; CHECK: br %r14 - %val0 = load i64 *@h0 - %val1 = load i64 *@h1 - %val2 = load i64 *@h2 - %val3 = load i64 *@h3 - %val4 = load i64 *@h4 - %val5 = load i64 *@h5 - %val6 = load i64 *@h6 - %val7 = load i64 *@h7 - %val8 = load i64 *@h8 - %val9 = load i64 *@h9 + %val0 = load i64 , i64 *@h0 + %val1 = load i64 , i64 *@h1 + %val2 = load i64 , i64 *@h2 + %val3 = load i64 , i64 *@h3 + %val4 = load i64 , i64 *@h4 + %val5 = load i64 , i64 *@h5 + %val6 = load i64 , i64 *@h6 + %val7 = load i64 , i64 *@h7 + %val8 = load i64 , i64 *@h8 + %val9 = load i64 , i64 *@h9 call void @foo() @@ -400,16 +400,16 @@ define void @f10() { ; CHECK: stgrl [[REG]], h8 ; CHECK: br %r14 entry: - %val8 = load volatile i64 *@h8 - %val0 = load volatile i64 *@h0 - %val1 = load volatile i64 *@h1 - %val2 = load volatile i64 *@h2 - %val3 = load volatile i64 *@h3 - %val4 = load volatile i64 *@h4 - %val5 = load volatile i64 *@h5 - %val6 = load volatile i64 *@h6 - %val7 = load volatile i64 *@h7 - %val9 = load volatile i64 *@h9 + %val8 = load volatile i64 , i64 *@h8 + %val0 = load volatile i64 , i64 *@h0 + %val1 = load volatile i64 , i64 *@h1 + %val2 = load volatile i64 , i64 *@h2 + %val3 = load volatile i64 , i64 *@h3 + %val4 = load volatile i64 , i64 *@h4 + %val5 = load volatile i64 , i64 *@h5 + %val6 = load volatile i64 , i64 *@h6 + %val7 = load volatile i64 , i64 *@h7 + %val9 = load volatile i64 , i64 *@h9 call void @foo() @@ -422,7 +422,7 @@ entry: store volatile i64 %val6, i64 *@h6 store volatile i64 %val7, i64 *@h7 - %check = load volatile i64 *@h0 + %check = load volatile i64 , i64 *@h0 %cond = icmp eq i64 %check, 0 br i1 %cond, label %skip, label %fallthru @@ -464,17 +464,17 @@ define void @f11() { ; CHECK-NOT: mvc [[OFFSET:[0-9]+]](8,%r15), [[OFFSET]](%r15) ; CHECK: br %r14 entry: - %val0 = load volatile i64 *@h0 - %val1 = load volatile i64 *@h1 - %val2 = load volatile i64 *@h2 - %val3 = load volatile i64 *@h3 - %val4 = load volatile i64 *@h4 - %val5 = load volatile i64 *@h5 - %val6 = load volatile i64 *@h6 - %val7 = load volatile i64 *@h7 - - %altval0 = load volatile i64 *@h0 - %altval1 = load volatile i64 *@h1 + %val0 = load volatile i64 , i64 *@h0 + %val1 = load volatile i64 , i64 *@h1 + %val2 = load volatile i64 , i64 *@h2 + %val3 = load volatile i64 , i64 *@h3 + %val4 = load volatile i64 , i64 *@h4 + %val5 = load volatile i64 , i64 *@h5 + %val6 = load volatile i64 , i64 *@h6 + %val7 = load volatile i64 , i64 *@h7 + + %altval0 = load volatile i64 , i64 *@h0 + %altval1 = load volatile i64 , i64 *@h1 call void @foo() @@ -487,7 +487,7 @@ entry: store volatile i64 %val6, i64 *@h6 store volatile i64 %val7, i64 *@h7 - %check = load volatile i64 *@h0 + %check = load volatile i64 , i64 *@h0 %cond = icmp eq i64 %check, 0 br i1 %cond, label %a1, label %b1 diff --git a/test/CodeGen/SystemZ/strcpy-01.ll b/test/CodeGen/SystemZ/strcpy-01.ll index 29bab629ecf8..d6d0edf494b1 100644 --- a/test/CodeGen/SystemZ/strcpy-01.ll +++ b/test/CodeGen/SystemZ/strcpy-01.ll @@ -43,7 +43,7 @@ define i32 @f3(i32 %dummy, i8 *%dest, i8 *%src, i32 *%resptr, i32 *%storeptr) { ; CHECK-NEXT: jo [[LABEL]] ; CHECK: mvhi 0(%r6), 0 ; CHECK: br %r14 - %res = load i32 *%resptr + %res = load i32 , i32 *%resptr %unused = call i8 *@strcpy(i8 *%dest, i8 *%src) store i32 0, i32 *%storeptr ret i32 %res diff --git a/test/CodeGen/SystemZ/tail-call-mem-intrinsics.ll b/test/CodeGen/SystemZ/tail-call-mem-intrinsics.ll new file mode 100644 index 000000000000..65cc394f8a98 --- /dev/null +++ b/test/CodeGen/SystemZ/tail-call-mem-intrinsics.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=systemz < %s | FileCheck %s + +; CHECK-LABEL: tail_memcpy: +; CHECK: jg memcpy +define void @tail_memcpy(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 { +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false) + ret void +} + +; CHECK-LABEL: tail_memmove: +; CHECK: jg memmove +define void @tail_memmove(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 { +entry: + tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false) + ret void +} + +; CHECK-LABEL: tail_memset: +; CHECK: jg memset +define void @tail_memset(i8* nocapture %p, i8 %c, i32 %n) #0 { +entry: + tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i32 1, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0 +declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0 +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/SystemZ/tls-01.ll b/test/CodeGen/SystemZ/tls-01.ll index 16bc8f6e500f..da7176c0599f 100644 --- a/test/CodeGen/SystemZ/tls-01.ll +++ b/test/CodeGen/SystemZ/tls-01.ll @@ -1,7 +1,7 @@ -; Test initial-exec TLS accesses. +; Test local-exec TLS accesses. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-CP +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-CP @x = thread_local global i32 0 diff --git a/test/CodeGen/SystemZ/tls-02.ll b/test/CodeGen/SystemZ/tls-02.ll new file mode 100644 index 000000000000..15918d08a936 --- /dev/null +++ b/test/CodeGen/SystemZ/tls-02.ll @@ -0,0 +1,18 @@ +; Test initial-exec TLS accesses. +; +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-MAIN + +@x = thread_local(initialexec) global i32 0 + +; The offset must be loaded from the GOT. This TLS access model does +; not use literal pool constants. +define i32 *@foo() { +; CHECK-MAIN-LABEL: foo: +; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0 +; CHECK-MAIN: sllg %r2, [[HIGH]], 32 +; CHECK-MAIN: ear %r2, %a1 +; CHECK-MAIN: larl %r1, x@INDNTPOFF +; CHECK-MAIN: ag %r2, 0(%r1) +; CHECK-MAIN: br %r14 + ret i32 *@x +} diff --git a/test/CodeGen/SystemZ/tls-03.ll b/test/CodeGen/SystemZ/tls-03.ll new file mode 100644 index 000000000000..c9f7bd632904 --- /dev/null +++ b/test/CodeGen/SystemZ/tls-03.ll @@ -0,0 +1,23 @@ +; Test general-dynamic TLS accesses. +; +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-CP + +@x = thread_local global i32 0 + +; Call __tls_get_offset to retrieve the symbol's TLS offset. +define i32 *@foo() { +; CHECK-CP: .LCP{{.*}}: +; CHECK-CP: .quad x@TLSGD +; +; CHECK-MAIN-LABEL: foo: +; CHECK-MAIN-DAG: larl %r12, _GLOBAL_OFFSET_TABLE_ +; CHECK-MAIN-DAG: lgrl %r2, .LCP{{.*}} +; CHECK-MAIN: brasl %r14, __tls_get_offset@PLT:tls_gdcall:x +; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0 +; CHECK-MAIN: sllg [[TP:%r[0-5]]], [[HIGH]], 32 +; CHECK-MAIN: ear [[TP]], %a1 +; CHECK-MAIN: agr %r2, [[TP]] +; CHECK-MAIN: br %r14 + ret i32 *@x +} diff --git a/test/CodeGen/SystemZ/tls-04.ll b/test/CodeGen/SystemZ/tls-04.ll new file mode 100644 index 000000000000..dcb210a71272 --- /dev/null +++ b/test/CodeGen/SystemZ/tls-04.ll @@ -0,0 +1,28 @@ +; Test local-dynamic TLS accesses. +; +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-CP + +@x = thread_local(localdynamic) global i32 0 + +; Call __tls_get_offset to retrieve the module's TLS base offset. +; Add the per-symbol offset and the thread pointer. +define i32 *@foo() { +; CHECK-CP: .LCP{{.*}}_0: +; CHECK-CP: .quad x@TLSLDM +; CHECK-CP: .LCP{{.*}}_1: +; CHECK-CP: .quad x@DTPOFF +; +; CHECK-MAIN-LABEL: foo: +; CHECK-MAIN-DAG: larl %r12, _GLOBAL_OFFSET_TABLE_ +; CHECK-MAIN-DAG: lgrl %r2, .LCP{{.*}}_0 +; CHECK-MAIN: brasl %r14, __tls_get_offset@PLT:tls_ldcall:x +; CHECK-MAIN: larl %r1, .LCP{{.*}}_1 +; CHECK-MAIN: ag %r2, 0(%r1) +; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0 +; CHECK-MAIN: sllg [[TP:%r[0-5]]], [[HIGH]], 32 +; CHECK-MAIN: ear [[TP]], %a1 +; CHECK-MAIN: agr %r2, [[TP]] +; CHECK-MAIN: br %r14 + ret i32 *@x +} diff --git a/test/CodeGen/SystemZ/tls-05.ll b/test/CodeGen/SystemZ/tls-05.ll new file mode 100644 index 000000000000..502d6d45852c --- /dev/null +++ b/test/CodeGen/SystemZ/tls-05.ll @@ -0,0 +1,15 @@ +; Test general-dynamic TLS access optimizations. +; +; If we access the same TLS variable twice, there should only be +; a single call to __tls_get_offset. +; +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "__tls_get_offset" | count 1 + +@x = thread_local global i32 0 + +define i32 @foo() { + %val = load i32, i32* @x + %inc = add nsw i32 %val, 1 + store i32 %inc, i32* @x + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/tls-06.ll b/test/CodeGen/SystemZ/tls-06.ll new file mode 100644 index 000000000000..8f1796df7291 --- /dev/null +++ b/test/CodeGen/SystemZ/tls-06.ll @@ -0,0 +1,17 @@ +; Test general-dynamic TLS access optimizations. +; +; If we access two different TLS variables, we need two calls to +; __tls_get_offset, but should load _GLOBAL_OFFSET_TABLE only once. +; +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "__tls_get_offset" | count 2 +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "_GLOBAL_OFFSET_TABLE_" | count 1 + +@x = thread_local global i32 0 +@y = thread_local global i32 0 + +define i32 @foo() { + %valx = load i32, i32* @x + %valy = load i32, i32* @y + %add = add nsw i32 %valx, %valy + ret i32 %add +} diff --git a/test/CodeGen/SystemZ/tls-07.ll b/test/CodeGen/SystemZ/tls-07.ll new file mode 100644 index 000000000000..be66c093bd42 --- /dev/null +++ b/test/CodeGen/SystemZ/tls-07.ll @@ -0,0 +1,16 @@ +; Test local-dynamic TLS access optimizations. +; +; If we access two different local-dynamic TLS variables, we only +; need a single call to __tls_get_offset. +; +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu -relocation-model=pic | grep "__tls_get_offset" | count 1 + +@x = thread_local(localdynamic) global i32 0 +@y = thread_local(localdynamic) global i32 0 + +define i32 @foo() { + %valx = load i32, i32* @x + %valy = load i32, i32* @y + %add = add nsw i32 %valx, %valy + ret i32 %add +} diff --git a/test/CodeGen/SystemZ/unaligned-01.ll b/test/CodeGen/SystemZ/unaligned-01.ll index 526a068100ef..94cad0e1743a 100644 --- a/test/CodeGen/SystemZ/unaligned-01.ll +++ b/test/CodeGen/SystemZ/unaligned-01.ll @@ -12,9 +12,9 @@ define void @f1(i8 *%ptr) { ; CHECK: iilf [[REG:%r[0-5]]], 66051 ; CHECK: st [[REG]], 0(%r2) ; CHECK: br %r14 - %off1 = getelementptr i8 *%ptr, i64 1 - %off2 = getelementptr i8 *%ptr, i64 2 - %off3 = getelementptr i8 *%ptr, i64 3 + %off1 = getelementptr i8, i8 *%ptr, i64 1 + %off2 = getelementptr i8, i8 *%ptr, i64 2 + %off3 = getelementptr i8, i8 *%ptr, i64 3 store i8 0, i8 *%ptr store i8 1, i8 *%off1 store i8 2, i8 *%off2 @@ -28,7 +28,7 @@ define i16 @f2(i16 *%src, i16 *%dst) { ; CHECK: lh %r2, 0(%r2) ; CHECK: sth %r2, 0(%r3) ; CHECK: br %r14 - %val = load i16 *%src, align 1 + %val = load i16 , i16 *%src, align 1 store i16 %val, i16 *%dst, align 1 ret i16 %val } @@ -40,8 +40,8 @@ define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) { ; CHECK: s %r2, 0(%r3) ; CHECK: st %r2, 0(%r4) ; CHECK: br %r14 - %val1 = load i32 *%src1, align 1 - %val2 = load i32 *%src2, align 2 + %val1 = load i32 , i32 *%src1, align 1 + %val2 = load i32 , i32 *%src2, align 2 %sub = sub i32 %val1, %val2 store i32 %sub, i32 *%dst, align 1 ret i32 %sub @@ -54,8 +54,8 @@ define i64 @f4(i64 *%src1, i64 *%src2, i64 *%dst) { ; CHECK: sg %r2, 0(%r3) ; CHECK: stg %r2, 0(%r4) ; CHECK: br %r14 - %val1 = load i64 *%src1, align 1 - %val2 = load i64 *%src2, align 2 + %val1 = load i64 , i64 *%src1, align 1 + %val2 = load i64 , i64 *%src2, align 2 %sub = sub i64 %val1, %val2 store i64 %sub, i64 *%dst, align 4 ret i64 %sub diff --git a/test/CodeGen/SystemZ/vec-abi-align.ll b/test/CodeGen/SystemZ/vec-abi-align.ll new file mode 100644 index 000000000000..01b97a8583eb --- /dev/null +++ b/test/CodeGen/SystemZ/vec-abi-align.ll @@ -0,0 +1,49 @@ +; Verify that we use the vector ABI datalayout if and only if +; the vector facility is present. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=generic | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s + +; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=vector | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=+vector | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-vector,vector | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-vector,+vector | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=-vector | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=vector,-vector | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=+vector,-vector | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s + +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -mattr=-vector | \ +; RUN: FileCheck -check-prefix=CHECK-NOVECTOR %s + +%struct.S = type { i8, <2 x i64> } + +define void @test(%struct.S* %s) nounwind { +; CHECK-VECTOR-LABEL: @test +; CHECK-VECTOR: vl %v0, 8(%r2) +; CHECK-NOVECTOR-LABEL: @test +; CHECK-NOVECTOR-DAG: agsi 16(%r2), 1 +; CHECK-NOVECTOR-DAG: agsi 24(%r2), 1 + %ptr = getelementptr %struct.S, %struct.S* %s, i64 0, i32 1 + %vec = load <2 x i64>, <2 x i64>* %ptr + %add = add <2 x i64> %vec, <i64 1, i64 1> + store <2 x i64> %add, <2 x i64>* %ptr + ret void +} + diff --git a/test/CodeGen/SystemZ/vec-abs-01.ll b/test/CodeGen/SystemZ/vec-abs-01.ll new file mode 100644 index 000000000000..aec3b9314f19 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-abs-01.ll @@ -0,0 +1,146 @@ +; Test v16i8 absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <16 x i8> @f1(<16 x i8> %val) { +; CHECK-LABEL: f1: +; CHECK: vlpb %v24, %v24 +; CHECK: br %r14 + %cmp = icmp slt <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val + ret <16 x i8> %ret +} + +; Test with sle. +define <16 x i8> @f2(<16 x i8> %val) { +; CHECK-LABEL: f2: +; CHECK: vlpb %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sle <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val + ret <16 x i8> %ret +} + +; Test with sgt. +define <16 x i8> @f3(<16 x i8> %val) { +; CHECK-LABEL: f3: +; CHECK: vlpb %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sgt <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg + ret <16 x i8> %ret +} + +; Test with sge. +define <16 x i8> @f4(<16 x i8> %val) { +; CHECK-LABEL: f4: +; CHECK: vlpb %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sge <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg + ret <16 x i8> %ret +} + +; Test that negative absolute uses VLPB too. There is no vector equivalent +; of LOAD NEGATIVE. +define <16 x i8> @f5(<16 x i8> %val) { +; CHECK-LABEL: f5: +; CHECK: vlpb [[REG:%v[0-9]+]], %v24 +; CHECK: vlcb %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %abs = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val + %ret = sub <16 x i8> zeroinitializer, %abs + ret <16 x i8> %ret +} + +; Try another form of negative absolute (slt version). +define <16 x i8> @f6(<16 x i8> %val) { +; CHECK-LABEL: f6: +; CHECK: vlpb [[REG:%v[0-9]+]], %v24 +; CHECK: vlcb %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg + ret <16 x i8> %ret +} + +; Test with sle. +define <16 x i8> @f7(<16 x i8> %val) { +; CHECK-LABEL: f7: +; CHECK: vlpb [[REG:%v[0-9]+]], %v24 +; CHECK: vlcb %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sle <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg + ret <16 x i8> %ret +} + +; Test with sgt. +define <16 x i8> @f8(<16 x i8> %val) { +; CHECK-LABEL: f8: +; CHECK: vlpb [[REG:%v[0-9]+]], %v24 +; CHECK: vlcb %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sgt <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val + ret <16 x i8> %ret +} + +; Test with sge. +define <16 x i8> @f9(<16 x i8> %val) { +; CHECK-LABEL: f9: +; CHECK: vlpb [[REG:%v[0-9]+]], %v24 +; CHECK: vlcb %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sge <16 x i8> %val, zeroinitializer + %neg = sub <16 x i8> zeroinitializer, %val + %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val + ret <16 x i8> %ret +} + +; Test with an SRA-based boolean vector. +define <16 x i8> @f10(<16 x i8> %val) { +; CHECK-LABEL: f10: +; CHECK: vlpb %v24, %v24 +; CHECK: br %r14 + %shr = ashr <16 x i8> %val, + <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> + %neg = sub <16 x i8> zeroinitializer, %val + %and1 = and <16 x i8> %shr, %neg + %not = xor <16 x i8> %shr, + <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> + %and2 = and <16 x i8> %not, %val + %ret = or <16 x i8> %and1, %and2 + ret <16 x i8> %ret +} + +; ...and again in reverse +define <16 x i8> @f11(<16 x i8> %val) { +; CHECK-LABEL: f11: +; CHECK: vlpb [[REG:%v[0-9]+]], %v24 +; CHECK: vlcb %v24, [[REG]] +; CHECK: br %r14 + %shr = ashr <16 x i8> %val, + <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> + %and1 = and <16 x i8> %shr, %val + %not = xor <16 x i8> %shr, + <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> + %neg = sub <16 x i8> zeroinitializer, %val + %and2 = and <16 x i8> %not, %neg + %ret = or <16 x i8> %and1, %and2 + ret <16 x i8> %ret +} diff --git a/test/CodeGen/SystemZ/vec-abs-02.ll b/test/CodeGen/SystemZ/vec-abs-02.ll new file mode 100644 index 000000000000..c5af619f0ba6 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-abs-02.ll @@ -0,0 +1,142 @@ +; Test v8i16 absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <8 x i16> @f1(<8 x i16> %val) { +; CHECK-LABEL: f1: +; CHECK: vlph %v24, %v24 +; CHECK: br %r14 + %cmp = icmp slt <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val + ret <8 x i16> %ret +} + +; Test with sle. +define <8 x i16> @f2(<8 x i16> %val) { +; CHECK-LABEL: f2: +; CHECK: vlph %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sle <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val + ret <8 x i16> %ret +} + +; Test with sgt. +define <8 x i16> @f3(<8 x i16> %val) { +; CHECK-LABEL: f3: +; CHECK: vlph %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sgt <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg + ret <8 x i16> %ret +} + +; Test with sge. +define <8 x i16> @f4(<8 x i16> %val) { +; CHECK-LABEL: f4: +; CHECK: vlph %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sge <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg + ret <8 x i16> %ret +} + +; Test that negative absolute uses VLPH too. There is no vector equivalent +; of LOAD NEGATIVE. +define <8 x i16> @f5(<8 x i16> %val) { +; CHECK-LABEL: f5: +; CHECK: vlph [[REG:%v[0-9]+]], %v24 +; CHECK: vlch %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %abs = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val + %ret = sub <8 x i16> zeroinitializer, %abs + ret <8 x i16> %ret +} + +; Try another form of negative absolute (slt version). +define <8 x i16> @f6(<8 x i16> %val) { +; CHECK-LABEL: f6: +; CHECK: vlph [[REG:%v[0-9]+]], %v24 +; CHECK: vlch %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg + ret <8 x i16> %ret +} + +; Test with sle. +define <8 x i16> @f7(<8 x i16> %val) { +; CHECK-LABEL: f7: +; CHECK: vlph [[REG:%v[0-9]+]], %v24 +; CHECK: vlch %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sle <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg + ret <8 x i16> %ret +} + +; Test with sgt. +define <8 x i16> @f8(<8 x i16> %val) { +; CHECK-LABEL: f8: +; CHECK: vlph [[REG:%v[0-9]+]], %v24 +; CHECK: vlch %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sgt <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val + ret <8 x i16> %ret +} + +; Test with sge. +define <8 x i16> @f9(<8 x i16> %val) { +; CHECK-LABEL: f9: +; CHECK: vlph [[REG:%v[0-9]+]], %v24 +; CHECK: vlch %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sge <8 x i16> %val, zeroinitializer + %neg = sub <8 x i16> zeroinitializer, %val + %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val + ret <8 x i16> %ret +} + +; Test with an SRA-based boolean vector. +define <8 x i16> @f10(<8 x i16> %val) { +; CHECK-LABEL: f10: +; CHECK: vlph %v24, %v24 +; CHECK: br %r14 + %shr = ashr <8 x i16> %val, + <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> + %neg = sub <8 x i16> zeroinitializer, %val + %and1 = and <8 x i16> %shr, %neg + %not = xor <8 x i16> %shr, + <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> + %and2 = and <8 x i16> %not, %val + %ret = or <8 x i16> %and1, %and2 + ret <8 x i16> %ret +} + +; ...and again in reverse +define <8 x i16> @f11(<8 x i16> %val) { +; CHECK-LABEL: f11: +; CHECK: vlph [[REG:%v[0-9]+]], %v24 +; CHECK: vlch %v24, [[REG]] +; CHECK: br %r14 + %shr = ashr <8 x i16> %val, + <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> + %and1 = and <8 x i16> %shr, %val + %not = xor <8 x i16> %shr, + <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> + %neg = sub <8 x i16> zeroinitializer, %val + %and2 = and <8 x i16> %not, %neg + %ret = or <8 x i16> %and1, %and2 + ret <8 x i16> %ret +} diff --git a/test/CodeGen/SystemZ/vec-abs-03.ll b/test/CodeGen/SystemZ/vec-abs-03.ll new file mode 100644 index 000000000000..cb17a8895e1a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-abs-03.ll @@ -0,0 +1,138 @@ +; Test v4i32 absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <4 x i32> @f1(<4 x i32> %val) { +; CHECK-LABEL: f1: +; CHECK: vlpf %v24, %v24 +; CHECK: br %r14 + %cmp = icmp slt <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val + ret <4 x i32> %ret +} + +; Test with sle. +define <4 x i32> @f2(<4 x i32> %val) { +; CHECK-LABEL: f2: +; CHECK: vlpf %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sle <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val + ret <4 x i32> %ret +} + +; Test with sgt. +define <4 x i32> @f3(<4 x i32> %val) { +; CHECK-LABEL: f3: +; CHECK: vlpf %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sgt <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg + ret <4 x i32> %ret +} + +; Test with sge. +define <4 x i32> @f4(<4 x i32> %val) { +; CHECK-LABEL: f4: +; CHECK: vlpf %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sge <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg + ret <4 x i32> %ret +} + +; Test that negative absolute uses VLPF too. There is no vector equivalent +; of LOAD NEGATIVE. +define <4 x i32> @f5(<4 x i32> %val) { +; CHECK-LABEL: f5: +; CHECK: vlpf [[REG:%v[0-9]+]], %v24 +; CHECK: vlcf %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %abs = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val + %ret = sub <4 x i32> zeroinitializer, %abs + ret <4 x i32> %ret +} + +; Try another form of negative absolute (slt version). +define <4 x i32> @f6(<4 x i32> %val) { +; CHECK-LABEL: f6: +; CHECK: vlpf [[REG:%v[0-9]+]], %v24 +; CHECK: vlcf %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg + ret <4 x i32> %ret +} + +; Test with sle. +define <4 x i32> @f7(<4 x i32> %val) { +; CHECK-LABEL: f7: +; CHECK: vlpf [[REG:%v[0-9]+]], %v24 +; CHECK: vlcf %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sle <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %neg + ret <4 x i32> %ret +} + +; Test with sgt. +define <4 x i32> @f8(<4 x i32> %val) { +; CHECK-LABEL: f8: +; CHECK: vlpf [[REG:%v[0-9]+]], %v24 +; CHECK: vlcf %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sgt <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val + ret <4 x i32> %ret +} + +; Test with sge. +define <4 x i32> @f9(<4 x i32> %val) { +; CHECK-LABEL: f9: +; CHECK: vlpf [[REG:%v[0-9]+]], %v24 +; CHECK: vlcf %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sge <4 x i32> %val, zeroinitializer + %neg = sub <4 x i32> zeroinitializer, %val + %ret = select <4 x i1> %cmp, <4 x i32> %neg, <4 x i32> %val + ret <4 x i32> %ret +} + +; Test with an SRA-based boolean vector. +define <4 x i32> @f10(<4 x i32> %val) { +; CHECK-LABEL: f10: +; CHECK: vlpf %v24, %v24 +; CHECK: br %r14 + %shr = ashr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31> + %neg = sub <4 x i32> zeroinitializer, %val + %and1 = and <4 x i32> %shr, %neg + %not = xor <4 x i32> %shr, <i32 -1, i32 -1, i32 -1, i32 -1> + %and2 = and <4 x i32> %not, %val + %ret = or <4 x i32> %and1, %and2 + ret <4 x i32> %ret +} + +; ...and again in reverse +define <4 x i32> @f11(<4 x i32> %val) { +; CHECK-LABEL: f11: +; CHECK: vlpf [[REG:%v[0-9]+]], %v24 +; CHECK: vlcf %v24, [[REG]] +; CHECK: br %r14 + %shr = ashr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31> + %and1 = and <4 x i32> %shr, %val + %not = xor <4 x i32> %shr, <i32 -1, i32 -1, i32 -1, i32 -1> + %neg = sub <4 x i32> zeroinitializer, %val + %and2 = and <4 x i32> %not, %neg + %ret = or <4 x i32> %and1, %and2 + ret <4 x i32> %ret +} diff --git a/test/CodeGen/SystemZ/vec-abs-04.ll b/test/CodeGen/SystemZ/vec-abs-04.ll new file mode 100644 index 000000000000..31c489b00b35 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-abs-04.ll @@ -0,0 +1,138 @@ +; Test v2i64 absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <2 x i64> @f1(<2 x i64> %val) { +; CHECK-LABEL: f1: +; CHECK: vlpg %v24, %v24 +; CHECK: br %r14 + %cmp = icmp slt <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val + ret <2 x i64> %ret +} + +; Test with sle. +define <2 x i64> @f2(<2 x i64> %val) { +; CHECK-LABEL: f2: +; CHECK: vlpg %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sle <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val + ret <2 x i64> %ret +} + +; Test with sgt. +define <2 x i64> @f3(<2 x i64> %val) { +; CHECK-LABEL: f3: +; CHECK: vlpg %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sgt <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg + ret <2 x i64> %ret +} + +; Test with sge. +define <2 x i64> @f4(<2 x i64> %val) { +; CHECK-LABEL: f4: +; CHECK: vlpg %v24, %v24 +; CHECK: br %r14 + %cmp = icmp sge <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg + ret <2 x i64> %ret +} + +; Test that negative absolute uses VLPG too. There is no vector equivalent +; of LOAD NEGATIVE. +define <2 x i64> @f5(<2 x i64> %val) { +; CHECK-LABEL: f5: +; CHECK: vlpg [[REG:%v[0-9]+]], %v24 +; CHECK: vlcg %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %abs = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val + %ret = sub <2 x i64> zeroinitializer, %abs + ret <2 x i64> %ret +} + +; Try another form of negative absolute (slt version). +define <2 x i64> @f6(<2 x i64> %val) { +; CHECK-LABEL: f6: +; CHECK: vlpg [[REG:%v[0-9]+]], %v24 +; CHECK: vlcg %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp slt <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg + ret <2 x i64> %ret +} + +; Test with sle. +define <2 x i64> @f7(<2 x i64> %val) { +; CHECK-LABEL: f7: +; CHECK: vlpg [[REG:%v[0-9]+]], %v24 +; CHECK: vlcg %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sle <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg + ret <2 x i64> %ret +} + +; Test with sgt. +define <2 x i64> @f8(<2 x i64> %val) { +; CHECK-LABEL: f8: +; CHECK: vlpg [[REG:%v[0-9]+]], %v24 +; CHECK: vlcg %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sgt <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val + ret <2 x i64> %ret +} + +; Test with sge. +define <2 x i64> @f9(<2 x i64> %val) { +; CHECK-LABEL: f9: +; CHECK: vlpg [[REG:%v[0-9]+]], %v24 +; CHECK: vlcg %v24, [[REG]] +; CHECK: br %r14 + %cmp = icmp sge <2 x i64> %val, zeroinitializer + %neg = sub <2 x i64> zeroinitializer, %val + %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val + ret <2 x i64> %ret +} + +; Test with an SRA-based boolean vector. +define <2 x i64> @f10(<2 x i64> %val) { +; CHECK-LABEL: f10: +; CHECK: vlpg %v24, %v24 +; CHECK: br %r14 + %shr = ashr <2 x i64> %val, <i64 63, i64 63> + %neg = sub <2 x i64> zeroinitializer, %val + %and1 = and <2 x i64> %shr, %neg + %not = xor <2 x i64> %shr, <i64 -1, i64 -1> + %and2 = and <2 x i64> %not, %val + %ret = or <2 x i64> %and1, %and2 + ret <2 x i64> %ret +} + +; ...and again in reverse +define <2 x i64> @f11(<2 x i64> %val) { +; CHECK-LABEL: f11: +; CHECK: vlpg [[REG:%v[0-9]+]], %v24 +; CHECK: vlcg %v24, [[REG]] +; CHECK: br %r14 + %shr = ashr <2 x i64> %val, <i64 63, i64 63> + %and1 = and <2 x i64> %shr, %val + %not = xor <2 x i64> %shr, <i64 -1, i64 -1> + %neg = sub <2 x i64> zeroinitializer, %val + %and2 = and <2 x i64> %not, %neg + %ret = or <2 x i64> %and1, %and2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-abs-05.ll b/test/CodeGen/SystemZ/vec-abs-05.ll new file mode 100644 index 000000000000..63210f87b94e --- /dev/null +++ b/test/CodeGen/SystemZ/vec-abs-05.ll @@ -0,0 +1,46 @@ +; Test f64 and v2f64 absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare double @llvm.fabs.f64(double) +declare <2 x double> @llvm.fabs.v2f64(<2 x double>) + +; Test a plain absolute. +define <2 x double> @f1(<2 x double> %val) { +; CHECK-LABEL: f1: +; CHECK: vflpdb %v24, %v24 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val) + ret <2 x double> %ret +} + +; Test a negative absolute. +define <2 x double> @f2(<2 x double> %val) { +; CHECK-LABEL: f2: +; CHECK: vflndb %v24, %v24 +; CHECK: br %r14 + %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val) + %ret = fsub <2 x double> <double -0.0, double -0.0>, %abs + ret <2 x double> %ret +} + +; Test an f64 absolute that uses vector registers. +define double @f3(<2 x double> %val) { +; CHECK-LABEL: f3: +; CHECK: wflpdb %f0, %v24 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %ret = call double @llvm.fabs.f64(double %scalar) + ret double %ret +} + +; Test an f64 negative absolute that uses vector registers. +define double @f4(<2 x double> %val) { +; CHECK-LABEL: f4: +; CHECK: wflndb %f0, %v24 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %abs = call double @llvm.fabs.f64(double %scalar) + %ret = fsub double -0.0, %abs + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-add-01.ll b/test/CodeGen/SystemZ/vec-add-01.ll new file mode 100644 index 000000000000..317034377671 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-add-01.ll @@ -0,0 +1,60 @@ +; Test vector addition. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 addition. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vab %v24, %v26, %v28 +; CHECK: br %r14 + %ret = add <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 addition. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vah %v24, %v26, %v28 +; CHECK: br %r14 + %ret = add <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 addition. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vaf %v24, %v26, %v28 +; CHECK: br %r14 + %ret = add <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 addition. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vag %v24, %v26, %v28 +; CHECK: br %r14 + %ret = add <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} + +; Test a v2f64 addition. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfadb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = fadd <2 x double> %val1, %val2 + ret <2 x double> %ret +} + +; Test an f64 addition that uses vector registers. +define double @f6(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f6: +; CHECK: wfadb %f0, %v24, %v26 +; CHECK: br %r14 + %scalar1 = extractelement <2 x double> %val1, i32 0 + %scalar2 = extractelement <2 x double> %val2, i32 0 + %ret = fadd double %scalar1, %scalar2 + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-and-01.ll b/test/CodeGen/SystemZ/vec-and-01.ll new file mode 100644 index 000000000000..d467de69cea2 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-and-01.ll @@ -0,0 +1,39 @@ +; Test vector AND. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 AND. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 AND. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 AND. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 AND. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-and-02.ll b/test/CodeGen/SystemZ/vec-and-02.ll new file mode 100644 index 000000000000..30bc92416892 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-and-02.ll @@ -0,0 +1,91 @@ +; Test vector AND-NOT. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 AND-NOT. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vnc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <16 x i8> %val2, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + %ret = and <16 x i8> %val1, %not + ret <16 x i8> %ret +} + +; ...and again with the reverse. +define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vnc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <16 x i8> %val1, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + %ret = and <16 x i8> %not, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 AND-NOT. +define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f3: +; CHECK: vnc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <8 x i16> %val2, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + %ret = and <8 x i16> %val1, %not + ret <8 x i16> %ret +} + +; ...and again with the reverse. +define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f4: +; CHECK: vnc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <8 x i16> %val1, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + %ret = and <8 x i16> %not, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 AND-NOT. +define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f5: +; CHECK: vnc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <4 x i32> %val2, <i32 -1, i32 -1, i32 -1, i32 -1> + %ret = and <4 x i32> %val1, %not + ret <4 x i32> %ret +} + +; ...and again with the reverse. +define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f6: +; CHECK: vnc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <4 x i32> %val1, <i32 -1, i32 -1, i32 -1, i32 -1> + %ret = and <4 x i32> %not, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 AND-NOT. +define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f7: +; CHECK: vnc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <2 x i64> %val2, <i64 -1, i64 -1> + %ret = and <2 x i64> %val1, %not + ret <2 x i64> %ret +} + +; ...and again with the reverse. +define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f8: +; CHECK: vnc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <2 x i64> %val1, <i64 -1, i64 -1> + %ret = and <2 x i64> %not, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-and-03.ll b/test/CodeGen/SystemZ/vec-and-03.ll new file mode 100644 index 000000000000..c73d570fb7b0 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-and-03.ll @@ -0,0 +1,113 @@ +; Test vector zero extensions, which need to be implemented as ANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i1->v16i8 extension. +define <16 x i8> @f1(<16 x i8> %val) { +; CHECK-LABEL: f1: +; CHECK: vrepib [[REG:%v[0-9]+]], 1 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <16 x i8> %val to <16 x i1> + %ret = zext <16 x i1> %trunc to <16 x i8> + ret <16 x i8> %ret +} + +; Test a v8i1->v8i16 extension. +define <8 x i16> @f2(<8 x i16> %val) { +; CHECK-LABEL: f2: +; CHECK: vrepih [[REG:%v[0-9]+]], 1 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <8 x i16> %val to <8 x i1> + %ret = zext <8 x i1> %trunc to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v8i8->v8i16 extension. +define <8 x i16> @f3(<8 x i16> %val) { +; CHECK-LABEL: f3: +; CHECK: vgbm [[REG:%v[0-9]+]], 21845 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <8 x i16> %val to <8 x i8> + %ret = zext <8 x i8> %trunc to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v4i1->v4i32 extension. +define <4 x i32> @f4(<4 x i32> %val) { +; CHECK-LABEL: f4: +; CHECK: vrepif [[REG:%v[0-9]+]], 1 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i1> + %ret = zext <4 x i1> %trunc to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i8->v4i32 extension. +define <4 x i32> @f5(<4 x i32> %val) { +; CHECK-LABEL: f5: +; CHECK: vgbm [[REG:%v[0-9]+]], 4369 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i8> + %ret = zext <4 x i8> %trunc to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i16->v4i32 extension. +define <4 x i32> @f6(<4 x i32> %val) { +; CHECK-LABEL: f6: +; CHECK: vgbm [[REG:%v[0-9]+]], 13107 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i16> + %ret = zext <4 x i16> %trunc to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v2i1->v2i64 extension. +define <2 x i64> @f7(<2 x i64> %val) { +; CHECK-LABEL: f7: +; CHECK: vrepig [[REG:%v[0-9]+]], 1 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i1> + %ret = zext <2 x i1> %trunc to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i8->v2i64 extension. +define <2 x i64> @f8(<2 x i64> %val) { +; CHECK-LABEL: f8: +; CHECK: vgbm [[REG:%v[0-9]+]], 257 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i8> + %ret = zext <2 x i8> %trunc to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i16->v2i64 extension. +define <2 x i64> @f9(<2 x i64> %val) { +; CHECK-LABEL: f9: +; CHECK: vgbm [[REG:%v[0-9]+]], 771 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i16> + %ret = zext <2 x i16> %trunc to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i32->v2i64 extension. +define <2 x i64> @f10(<2 x i64> %val) { +; CHECK-LABEL: f10: +; CHECK: vgbm [[REG:%v[0-9]+]], 3855 +; CHECK: vn %v24, %v24, [[REG]] +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i32> + %ret = zext <2 x i32> %trunc to <2 x i64> + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-args-01.ll b/test/CodeGen/SystemZ/vec-args-01.ll new file mode 100644 index 000000000000..e07ab7447b2a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-01.ll @@ -0,0 +1,48 @@ +; Test the handling of named vector arguments. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK + +; This routine has 6 integer arguments, which fill up r2-r5 and +; the stack slot at offset 160, and 10 vector arguments, which +; fill up v24-v31 and the two double-wide stack slots at 168 +; and 184. +declare void @bar(i64, i64, i64, i64, i64, i64, + <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, + <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, + <4 x i32>, <4 x i32>) + +define void @foo() { +; CHECK-VEC-LABEL: foo: +; CHECK-VEC-DAG: vrepif %v24, 1 +; CHECK-VEC-DAG: vrepif %v26, 2 +; CHECK-VEC-DAG: vrepif %v28, 3 +; CHECK-VEC-DAG: vrepif %v30, 4 +; CHECK-VEC-DAG: vrepif %v25, 5 +; CHECK-VEC-DAG: vrepif %v27, 6 +; CHECK-VEC-DAG: vrepif %v29, 7 +; CHECK-VEC-DAG: vrepif %v31, 8 +; CHECK-VEC: brasl %r14, bar@PLT +; +; CHECK-STACK-LABEL: foo: +; CHECK-STACK: aghi %r15, -200 +; CHECK-STACK-DAG: mvghi 160(%r15), 6 +; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 9 +; CHECK-STACK-DAG: vst [[REG1]], 168(%r15) +; CHECK-STACK-DAG: vrepif [[REG2:%v[0-9]+]], 10 +; CHECK-STACK-DAG: vst [[REG2]], 184(%r15) +; CHECK-STACK: brasl %r14, bar@PLT + + call void @bar (i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, + <4 x i32> <i32 1, i32 1, i32 1, i32 1>, + <4 x i32> <i32 2, i32 2, i32 2, i32 2>, + <4 x i32> <i32 3, i32 3, i32 3, i32 3>, + <4 x i32> <i32 4, i32 4, i32 4, i32 4>, + <4 x i32> <i32 5, i32 5, i32 5, i32 5>, + <4 x i32> <i32 6, i32 6, i32 6, i32 6>, + <4 x i32> <i32 7, i32 7, i32 7, i32 7>, + <4 x i32> <i32 8, i32 8, i32 8, i32 8>, + <4 x i32> <i32 9, i32 9, i32 9, i32 9>, + <4 x i32> <i32 10, i32 10, i32 10, i32 10>) + ret void +} diff --git a/test/CodeGen/SystemZ/vec-args-02.ll b/test/CodeGen/SystemZ/vec-args-02.ll new file mode 100644 index 000000000000..b6081598326a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-02.ll @@ -0,0 +1,31 @@ +; Test the handling of unnamed vector arguments. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK + +; This routine is called with two named vector argument (passed +; in %v24 and %v26) and two unnamed vector arguments (passed +; in the double-wide stack slots at 160 and 176). +declare void @bar(<4 x i32>, <4 x i32>, ...) + +define void @foo() { +; CHECK-VEC-LABEL: foo: +; CHECK-VEC-DAG: vrepif %v24, 1 +; CHECK-VEC-DAG: vrepif %v26, 2 +; CHECK-VEC: brasl %r14, bar@PLT +; +; CHECK-STACK-LABEL: foo: +; CHECK-STACK: aghi %r15, -192 +; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 3 +; CHECK-STACK-DAG: vst [[REG1]], 160(%r15) +; CHECK-STACK-DAG: vrepif [[REG2:%v[0-9]+]], 4 +; CHECK-STACK-DAG: vst [[REG2]], 176(%r15) +; CHECK-STACK: brasl %r14, bar@PLT + + call void (<4 x i32>, <4 x i32>, ...) @bar + (<4 x i32> <i32 1, i32 1, i32 1, i32 1>, + <4 x i32> <i32 2, i32 2, i32 2, i32 2>, + <4 x i32> <i32 3, i32 3, i32 3, i32 3>, + <4 x i32> <i32 4, i32 4, i32 4, i32 4>) + ret void +} diff --git a/test/CodeGen/SystemZ/vec-args-03.ll b/test/CodeGen/SystemZ/vec-args-03.ll new file mode 100644 index 000000000000..c47d8461021a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-03.ll @@ -0,0 +1,30 @@ +; Test the handling of incoming vector arguments. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; This routine has 10 vector arguments, which fill up %v24-%v31 and +; the two double-wide stack slots at 160 and 176. +define <4 x i32> @foo(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, + <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8, + <4 x i32> %v9, <4 x i32> %v10) { +; CHECK-LABEL: foo: +; CHECK: vl [[REG1:%v[0-9]+]], 176(%r15) +; CHECK: vsf %v24, %v26, [[REG1]] +; CHECK: br %r14 + %y = sub <4 x i32> %v2, %v10 + ret <4 x i32> %y +} + +; This routine has 10 vector arguments, which fill up %v24-%v31 and +; the two single-wide stack slots at 160 and 168. +define <4 x i8> @bar(<4 x i8> %v1, <4 x i8> %v2, <4 x i8> %v3, <4 x i8> %v4, + <4 x i8> %v5, <4 x i8> %v6, <4 x i8> %v7, <4 x i8> %v8, + <4 x i8> %v9, <4 x i8> %v10) { +; CHECK-LABEL: bar: +; CHECK: vlrepg [[REG1:%v[0-9]+]], 168(%r15) +; CHECK: vsb %v24, %v26, [[REG1]] +; CHECK: br %r14 + %y = sub <4 x i8> %v2, %v10 + ret <4 x i8> %y +} + diff --git a/test/CodeGen/SystemZ/vec-args-04.ll b/test/CodeGen/SystemZ/vec-args-04.ll new file mode 100644 index 000000000000..3a25404934e2 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-04.ll @@ -0,0 +1,50 @@ +; Test the handling of named short vector arguments. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK + +; This routine has 12 vector arguments, which fill up %v24-%v31 +; and the four single-wide stack slots starting at 160. +declare void @bar(<1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>, + <1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>, + <1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>) + +define void @foo() { +; CHECK-VEC-LABEL: foo: +; CHECK-VEC-DAG: vrepib %v24, 1 +; CHECK-VEC-DAG: vrepib %v26, 2 +; CHECK-VEC-DAG: vrepib %v28, 3 +; CHECK-VEC-DAG: vrepib %v30, 4 +; CHECK-VEC-DAG: vrepib %v25, 5 +; CHECK-VEC-DAG: vrepib %v27, 6 +; CHECK-VEC-DAG: vrepib %v29, 7 +; CHECK-VEC-DAG: vrepib %v31, 8 +; CHECK-VEC: brasl %r14, bar@PLT +; +; CHECK-STACK-LABEL: foo: +; CHECK-STACK: aghi %r15, -192 +; CHECK-STACK-DAG: llihh [[REG1:%r[0-9]+]], 2304 +; CHECK-STACK-DAG: stg [[REG1]], 160(%r15) +; CHECK-STACK-DAG: llihh [[REG2:%r[0-9]+]], 2570 +; CHECK-STACK-DAG: stg [[REG2]], 168(%r15) +; CHECK-STACK-DAG: llihf [[REG3:%r[0-9]+]], 185273099 +; CHECK-STACK-DAG: stg [[REG3]], 176(%r15) +; CHECK-STACK-DAG: llihf [[REG4:%r[0-9]+]], 202116108 +; CHECK-STACK-DAG: oilf [[REG4]], 202116108 +; CHECK-STACK-DAG: stg [[REG4]], 176(%r15) +; CHECK-STACK: brasl %r14, bar@PLT + + call void @bar (<1 x i8> <i8 1>, + <2 x i8> <i8 2, i8 2>, + <4 x i8> <i8 3, i8 3, i8 3, i8 3>, + <8 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>, + <1 x i8> <i8 5>, + <2 x i8> <i8 6, i8 6>, + <4 x i8> <i8 7, i8 7, i8 7, i8 7>, + <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>, + <1 x i8> <i8 9>, + <2 x i8> <i8 10, i8 10>, + <4 x i8> <i8 11, i8 11, i8 11, i8 11>, + <8 x i8> <i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12, i8 12>) + ret void +} diff --git a/test/CodeGen/SystemZ/vec-args-05.ll b/test/CodeGen/SystemZ/vec-args-05.ll new file mode 100644 index 000000000000..cd1448b8611e --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-05.ll @@ -0,0 +1,32 @@ +; Test the handling of unnamed short vector arguments. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK + +; This routine is called with two named vector argument (passed +; in %v24 and %v26) and two unnamed vector arguments (passed +; in the single-wide stack slots at 160 and 168). +declare void @bar(<4 x i8>, <4 x i8>, ...) + +define void @foo() { +; CHECK-VEC-LABEL: foo: +; CHECK-VEC-DAG: vrepib %v24, 1 +; CHECK-VEC-DAG: vrepib %v26, 2 +; CHECK-VEC: brasl %r14, bar@PLT +; +; CHECK-STACK-LABEL: foo: +; CHECK-STACK: aghi %r15, -176 +; CHECK-STACK-DAG: llihf [[REG1:%r[0-9]+]], 50529027 +; CHECK-STACK-DAG: stg [[REG1]], 160(%r15) +; CHECK-STACK-DAG: llihf [[REG2:%r[0-9]+]], 67372036 +; CHECK-STACK-DAG: stg [[REG2]], 168(%r15) +; CHECK-STACK: brasl %r14, bar@PLT + + call void (<4 x i8>, <4 x i8>, ...) @bar + (<4 x i8> <i8 1, i8 1, i8 1, i8 1>, + <4 x i8> <i8 2, i8 2, i8 2, i8 2>, + <4 x i8> <i8 3, i8 3, i8 3, i8 3>, + <4 x i8> <i8 4, i8 4, i8 4, i8 4>) + ret void +} + diff --git a/test/CodeGen/SystemZ/vec-args-error-01.ll b/test/CodeGen/SystemZ/vec-args-error-01.ll new file mode 100644 index 000000000000..e2f537949595 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-01.ll @@ -0,0 +1,9 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +define void @foo(<1 x i128>) { + ret void +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-args-error-02.ll b/test/CodeGen/SystemZ/vec-args-error-02.ll new file mode 100644 index 000000000000..a5ae1102a748 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-02.ll @@ -0,0 +1,9 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +define <1 x i128> @foo() { + ret <1 x i128><i128 0> +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-args-error-03.ll b/test/CodeGen/SystemZ/vec-args-error-03.ll new file mode 100644 index 000000000000..14698aae43bc --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-03.ll @@ -0,0 +1,12 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +declare void @bar(<1 x i128>) + +define void @foo() { + call void @bar (<1 x i128> <i128 0>) + ret void +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-args-error-04.ll b/test/CodeGen/SystemZ/vec-args-error-04.ll new file mode 100644 index 000000000000..a54ee90022c8 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-04.ll @@ -0,0 +1,12 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +declare <1 x i128> @bar() + +define void @foo() { + %res = call <1 x i128> @bar () + ret void +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-args-error-05.ll b/test/CodeGen/SystemZ/vec-args-error-05.ll new file mode 100644 index 000000000000..067deb1c88b8 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-05.ll @@ -0,0 +1,9 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +define void @foo(<1 x fp128>) { + ret void +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-args-error-06.ll b/test/CodeGen/SystemZ/vec-args-error-06.ll new file mode 100644 index 000000000000..a9184d735750 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-06.ll @@ -0,0 +1,9 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +define <1 x fp128> @foo() { + ret <1 x fp128><fp128 0xL00000000000000000000000000000000> +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-args-error-07.ll b/test/CodeGen/SystemZ/vec-args-error-07.ll new file mode 100644 index 000000000000..4e9140093915 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-07.ll @@ -0,0 +1,12 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +declare void @bar(<1 x fp128>) + +define void @foo() { + call void @bar (<1 x fp128> <fp128 0xL00000000000000000000000000000000>) + ret void +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-args-error-08.ll b/test/CodeGen/SystemZ/vec-args-error-08.ll new file mode 100644 index 000000000000..7b16b9f46e39 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-args-error-08.ll @@ -0,0 +1,12 @@ +; Verify that we detect unsupported single-element vector types. + +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s + +declare <1 x fp128> @bar() + +define void @foo() { + %res = call <1 x fp128> @bar () + ret void +} + +; CHECK: LLVM ERROR: Unsupported vector argument or return type diff --git a/test/CodeGen/SystemZ/vec-cmp-01.ll b/test/CodeGen/SystemZ/vec-cmp-01.ll new file mode 100644 index 000000000000..a7546db8d7f1 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-cmp-01.ll @@ -0,0 +1,228 @@ +; Test v16i8 comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test eq. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vceqb %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp eq <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test ne. +define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vceqb [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test sgt. +define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vchb %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test sge. +define <16 x i8> @f4(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f4: +; CHECK: vchb [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test sle. +define <16 x i8> @f5(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f5: +; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test slt. +define <16 x i8> @f6(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f6: +; CHECK: vchb %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp slt <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test ugt. +define <16 x i8> @f7(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f7: +; CHECK: vchlb %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test uge. +define <16 x i8> @f8(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f8: +; CHECK: vchlb [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test ule. +define <16 x i8> @f9(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f9: +; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test ult. +define <16 x i8> @f10(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f10: +; CHECK: vchlb %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp ult <16 x i8> %val1, %val2 + %ret = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %ret +} + +; Test eq selects. +define <16 x i8> @f11(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f11: +; CHECK: vceqb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp eq <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test ne selects. +define <16 x i8> @f12(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f12: +; CHECK: vceqb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test sgt selects. +define <16 x i8> @f13(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f13: +; CHECK: vchb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test sge selects. +define <16 x i8> @f14(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f14: +; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test sle selects. +define <16 x i8> @f15(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f15: +; CHECK: vchb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test slt selects. +define <16 x i8> @f16(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f16: +; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp slt <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test ugt selects. +define <16 x i8> @f17(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f17: +; CHECK: vchlb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test uge selects. +define <16 x i8> @f18(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f18: +; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test ule selects. +define <16 x i8> @f19(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f19: +; CHECK: vchlb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} + +; Test ult selects. +define <16 x i8> @f20(<16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3, <16 x i8> %val4) { +; CHECK-LABEL: f20: +; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ult <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4 + ret <16 x i8> %ret +} diff --git a/test/CodeGen/SystemZ/vec-cmp-02.ll b/test/CodeGen/SystemZ/vec-cmp-02.ll new file mode 100644 index 000000000000..78fb46c01c08 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-cmp-02.ll @@ -0,0 +1,228 @@ +; Test v8i16 comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test eq. +define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f1: +; CHECK: vceqh %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp eq <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test ne. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vceqh [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test sgt. +define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f3: +; CHECK: vchh %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test sge. +define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f4: +; CHECK: vchh [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test sle. +define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f5: +; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test slt. +define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f6: +; CHECK: vchh %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp slt <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test ugt. +define <8 x i16> @f7(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f7: +; CHECK: vchlh %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test uge. +define <8 x i16> @f8(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f8: +; CHECK: vchlh [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test ule. +define <8 x i16> @f9(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f9: +; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test ult. +define <8 x i16> @f10(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f10: +; CHECK: vchlh %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp ult <8 x i16> %val1, %val2 + %ret = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret +} + +; Test eq selects. +define <8 x i16> @f11(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f11: +; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp eq <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test ne selects. +define <8 x i16> @f12(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f12: +; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test sgt selects. +define <8 x i16> @f13(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f13: +; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test sge selects. +define <8 x i16> @f14(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f14: +; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test sle selects. +define <8 x i16> @f15(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f15: +; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test slt selects. +define <8 x i16> @f16(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f16: +; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp slt <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test ugt selects. +define <8 x i16> @f17(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f17: +; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test uge selects. +define <8 x i16> @f18(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f18: +; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test ule selects. +define <8 x i16> @f19(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f19: +; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} + +; Test ult selects. +define <8 x i16> @f20(<8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3, <8 x i16> %val4) { +; CHECK-LABEL: f20: +; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ult <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4 + ret <8 x i16> %ret +} diff --git a/test/CodeGen/SystemZ/vec-cmp-03.ll b/test/CodeGen/SystemZ/vec-cmp-03.ll new file mode 100644 index 000000000000..4b070acc935b --- /dev/null +++ b/test/CodeGen/SystemZ/vec-cmp-03.ll @@ -0,0 +1,228 @@ +; Test v4i32 comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test eq. +define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f1: +; CHECK: vceqf %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp eq <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ne. +define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f2: +; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test sgt. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vchf %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test sge. +define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f4: +; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test sle. +define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f5: +; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test slt. +define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f6: +; CHECK: vchf %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp slt <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ugt. +define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f7: +; CHECK: vchlf %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test uge. +define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f8: +; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ule. +define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f9: +; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ult. +define <4 x i32> @f10(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f10: +; CHECK: vchlf %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp ult <4 x i32> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test eq selects. +define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f11: +; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp eq <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test ne selects. +define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f12: +; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test sgt selects. +define <4 x i32> @f13(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f13: +; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test sge selects. +define <4 x i32> @f14(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f14: +; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test sle selects. +define <4 x i32> @f15(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f15: +; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test slt selects. +define <4 x i32> @f16(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f16: +; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp slt <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test ugt selects. +define <4 x i32> @f17(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f17: +; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test uge selects. +define <4 x i32> @f18(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f18: +; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test ule selects. +define <4 x i32> @f19(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f19: +; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} + +; Test ult selects. +define <4 x i32> @f20(<4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3, <4 x i32> %val4) { +; CHECK-LABEL: f20: +; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ult <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4 + ret <4 x i32> %ret +} diff --git a/test/CodeGen/SystemZ/vec-cmp-04.ll b/test/CodeGen/SystemZ/vec-cmp-04.ll new file mode 100644 index 000000000000..5cecaa7251b7 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-cmp-04.ll @@ -0,0 +1,228 @@ +; Test v2i64 comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test eq. +define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f1: +; CHECK: vceqg %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp eq <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ne. +define <2 x i64> @f2(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f2: +; CHECK: vceqg [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test sgt. +define <2 x i64> @f3(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f3: +; CHECK: vchg %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test sge. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vchg [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test sle. +define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f5: +; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test slt. +define <2 x i64> @f6(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f6: +; CHECK: vchg %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp slt <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ugt. +define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f7: +; CHECK: vchlg %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test uge. +define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f8: +; CHECK: vchlg [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ule. +define <2 x i64> @f9(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f9: +; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ult. +define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f10: +; CHECK: vchlg %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = icmp ult <2 x i64> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test eq selects. +define <2 x i64> @f11(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f11: +; CHECK: vceqg [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp eq <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test ne selects. +define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f12: +; CHECK: vceqg [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ne <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test sgt selects. +define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f13: +; CHECK: vchg [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sgt <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test sge selects. +define <2 x i64> @f14(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f14: +; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sge <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test sle selects. +define <2 x i64> @f15(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f15: +; CHECK: vchg [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp sle <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test slt selects. +define <2 x i64> @f16(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f16: +; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp slt <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test ugt selects. +define <2 x i64> @f17(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f17: +; CHECK: vchlg [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ugt <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test uge selects. +define <2 x i64> @f18(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f18: +; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp uge <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test ule selects. +define <2 x i64> @f19(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f19: +; CHECK: vchlg [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ule <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} + +; Test ult selects. +define <2 x i64> @f20(<2 x i64> %val1, <2 x i64> %val2, + <2 x i64> %val3, <2 x i64> %val4) { +; CHECK-LABEL: f20: +; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = icmp ult <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-cmp-05.ll b/test/CodeGen/SystemZ/vec-cmp-05.ll new file mode 100644 index 000000000000..74e990960972 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-cmp-05.ll @@ -0,0 +1,472 @@ +; Test v4f32 comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test oeq. +define <4 x i32> @f1(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f1: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp oeq <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test one. +define <4 x i32> @f2(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f2: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]] +; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]] +; CHECK: vo %v24, [[RES1]], [[RES0]] +; CHECK-NEXT: br %r14 + %cmp = fcmp one <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ogt. +define <4 x i32> @f3(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f3: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ogt <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test oge. +define <4 x i32> @f4(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f4: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp oge <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ole. +define <4 x i32> @f5(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f5: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ole <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test olt. +define <4 x i32> @f6(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f6: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp olt <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ueq. +define <4 x i32> @f7(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f7: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]] +; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]] +; CHECK: vno %v24, [[RES1]], [[RES0]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ueq <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test une. +define <4 x i32> @f8(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f8: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: vno %v24, [[RES]], [[RES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp une <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ugt. +define <4 x i32> @f9(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f9: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: vno %v24, [[RES]], [[RES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ugt <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test uge. +define <4 x i32> @f10(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f10: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: vno %v24, [[RES]], [[RES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uge <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ule. +define <4 x i32> @f11(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f11: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: vno %v24, [[RES]], [[RES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ule <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ult. +define <4 x i32> @f12(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f12: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]] +; CHECK-NEXT: vno %v24, [[RES]], [[RES]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ult <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test ord. +define <4 x i32> @f13(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f13: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]] +; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]] +; CHECK: vo %v24, [[RES1]], [[RES0]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ord <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test uno. +define <4 x i32> @f14(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f14: +; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24 +; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26 +; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]] +; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]] +; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]] +; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]] +; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]] +; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]] +; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]] +; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]] +; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]] +; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]] +; CHECK: vno %v24, [[RES1]], [[RES0]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uno <4 x float> %val1, %val2 + %ret = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %ret +} + +; Test oeq selects. +define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f15: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp oeq <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test one selects. +define <4 x float> @f16(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f16: +; CHECK: vo [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp one <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test ogt selects. +define <4 x float> @f17(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f17: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ogt <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test oge selects. +define <4 x float> @f18(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f18: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp oge <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test ole selects. +define <4 x float> @f19(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f19: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ole <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test olt selects. +define <4 x float> @f20(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f20: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp olt <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test ueq selects. +define <4 x float> @f21(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f21: +; CHECK: vo [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ueq <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test une selects. +define <4 x float> @f22(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f22: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp une <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test ugt selects. +define <4 x float> @f23(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f23: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ugt <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test uge selects. +define <4 x float> @f24(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f24: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uge <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test ule selects. +define <4 x float> @f25(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f25: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ule <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test ult selects. +define <4 x float> @f26(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f26: +; CHECK: vpkg [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ult <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test ord selects. +define <4 x float> @f27(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f27: +; CHECK: vo [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ord <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} + +; Test uno selects. +define <4 x float> @f28(<4 x float> %val1, <4 x float> %val2, + <4 x float> %val3, <4 x float> %val4) { +; CHECK-LABEL: f28: +; CHECK: vo [[REG:%v[0-9]+]], +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uno <4 x float> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4 + ret <4 x float> %ret +} diff --git a/test/CodeGen/SystemZ/vec-cmp-06.ll b/test/CodeGen/SystemZ/vec-cmp-06.ll new file mode 100644 index 000000000000..eef57555b482 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-cmp-06.ll @@ -0,0 +1,349 @@ +; Test f64 and v2f64 comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test oeq. +define <2 x i64> @f1(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f1: +; CHECK: vfcedb %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = fcmp oeq <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test one. +define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f2: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 +; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28 +; CHECK: vo %v24, [[REG1]], [[REG2]] +; CHECK-NEXT: br %r14 + %cmp = fcmp one <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ogt. +define <2 x i64> @f3(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f3: +; CHECK: vfchdb %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = fcmp ogt <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test oge. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f4: +; CHECK: vfchedb %v24, %v26, %v28 +; CHECK-NEXT: br %r14 + %cmp = fcmp oge <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ole. +define <2 x i64> @f5(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfchedb %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = fcmp ole <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test olt. +define <2 x i64> @f6(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f6: +; CHECK: vfchdb %v24, %v28, %v26 +; CHECK-NEXT: br %r14 + %cmp = fcmp olt <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ueq. +define <2 x i64> @f7(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f7: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 +; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28 +; CHECK: vno %v24, [[REG1]], [[REG2]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ueq <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test une. +define <2 x i64> @f8(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f8: +; CHECK: vfcedb [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp une <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ugt. +define <2 x i64> @f9(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f9: +; CHECK: vfchedb [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ugt <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test uge. +define <2 x i64> @f10(<2 x i64> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f10: +; CHECK: vfchdb [[REG:%v[0-9]+]], %v28, %v26 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uge <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ule. +define <2 x i64> @f11(<2 x i64> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f11: +; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ule <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ult. +define <2 x i64> @f12(<2 x i64> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f12: +; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v28 +; CHECK-NEXT: vno %v24, [[REG]], [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ult <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test ord. +define <2 x i64> @f13(<2 x i64> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f13: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 +; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28 +; CHECK: vo %v24, [[REG1]], [[REG2]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ord <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test uno. +define <2 x i64> @f14(<2 x i64> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f14: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26 +; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28 +; CHECK: vno %v24, [[REG1]], [[REG2]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uno <2 x double> %val1, %val2 + %ret = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %ret +} + +; Test oeq selects. +define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f15: +; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp oeq <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test one selects. +define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f16: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 +; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26 +; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp one <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test ogt selects. +define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f17: +; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ogt <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test oge selects. +define <2 x double> @f18(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f18: +; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp oge <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test ole selects. +define <2 x double> @f19(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f19: +; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ole <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test olt selects. +define <2 x double> @f20(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f20: +; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp olt <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test ueq selects. +define <2 x double> @f21(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f21: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 +; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26 +; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ueq <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test une selects. +define <2 x double> @f22(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f22: +; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp une <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test ugt selects. +define <2 x double> @f23(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f23: +; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ugt <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test uge selects. +define <2 x double> @f24(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f24: +; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uge <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test ule selects. +define <2 x double> @f25(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f25: +; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ule <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test ult selects. +define <2 x double> @f26(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f26: +; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ult <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test ord selects. +define <2 x double> @f27(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f27: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 +; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26 +; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] +; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp ord <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test uno selects. +define <2 x double> @f28(<2 x double> %val1, <2 x double> %val2, + <2 x double> %val3, <2 x double> %val4) { +; CHECK-LABEL: f28: +; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24 +; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26 +; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]] +; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] +; CHECK-NEXT: br %r14 + %cmp = fcmp uno <2 x double> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4 + ret <2 x double> %ret +} + +; Test an f64 comparison that uses vector registers. +define i64 @f29(i64 %a, i64 %b, double %f1, <2 x double> %vec) { +; CHECK-LABEL: f29: +; CHECK: wfcdb %f0, %v24 +; CHECK-NEXT: locgrne %r2, %r3 +; CHECK: br %r14 + %f2 = extractelement <2 x double> %vec, i32 0 + %cond = fcmp oeq double %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/vec-combine-01.ll b/test/CodeGen/SystemZ/vec-combine-01.ll new file mode 100644 index 000000000000..a35934421726 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-combine-01.ll @@ -0,0 +1,155 @@ +; Test various target-specific DAG combiner patterns. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Check that an extraction followed by a truncation is effectively treated +; as a bitcast. +define void @f1(<4 x i32> %v1, <4 x i32> %v2, i8 *%ptr1, i8 *%ptr2) { +; CHECK-LABEL: f1: +; CHECK: vaf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vsteb [[REG]], 0(%r2), 3 +; CHECK-DAG: vsteb [[REG]], 0(%r3), 15 +; CHECK: br %r14 + %add = add <4 x i32> %v1, %v2 + %elem1 = extractelement <4 x i32> %add, i32 0 + %elem2 = extractelement <4 x i32> %add, i32 3 + %trunc1 = trunc i32 %elem1 to i8 + %trunc2 = trunc i32 %elem2 to i8 + store i8 %trunc1, i8 *%ptr1 + store i8 %trunc2, i8 *%ptr2 + ret void +} + +; Test a case where a pack-type shuffle can be eliminated. +define i16 @f2(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { +; CHECK-LABEL: f2: +; CHECK-NOT: vpk +; CHECK-DAG: vaf [[REG1:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vaf [[REG2:%v[0-9]+]], %v26, %v28 +; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG1]], 3 +; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG2]], 7 +; CHECK: br %r14 + %add1 = add <4 x i32> %v1, %v2 + %add2 = add <4 x i32> %v2, %v3 + %shuffle = shufflevector <4 x i32> %add1, <4 x i32> %add2, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %bitcast = bitcast <4 x i32> %shuffle to <8 x i16> + %elem1 = extractelement <8 x i16> %bitcast, i32 1 + %elem2 = extractelement <8 x i16> %bitcast, i32 7 + %res = add i16 %elem1, %elem2 + ret i16 %res +} + +; ...and again in a case where there's also a splat and a bitcast. +define i16 @f3(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) { +; CHECK-LABEL: f3: +; CHECK-NOT: vrepg +; CHECK-NOT: vpk +; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 6 +; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3 +; CHECK: br %r14 + %add = add <4 x i32> %v1, %v2 + %splat = shufflevector <2 x i64> %v3, <2 x i64> undef, + <2 x i32> <i32 0, i32 0> + %splatcast = bitcast <2 x i64> %splat to <4 x i32> + %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %bitcast = bitcast <4 x i32> %shuffle to <8 x i16> + %elem1 = extractelement <8 x i16> %bitcast, i32 2 + %elem2 = extractelement <8 x i16> %bitcast, i32 7 + %res = add i16 %elem1, %elem2 + ret i16 %res +} + +; ...and again with a merge low instead of a pack. +define i16 @f4(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) { +; CHECK-LABEL: f4: +; CHECK-NOT: vrepg +; CHECK-NOT: vmr +; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 6 +; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3 +; CHECK: br %r14 + %add = add <4 x i32> %v1, %v2 + %splat = shufflevector <2 x i64> %v3, <2 x i64> undef, + <2 x i32> <i32 0, i32 0> + %splatcast = bitcast <2 x i64> %splat to <4 x i32> + %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast, + <4 x i32> <i32 2, i32 6, i32 3, i32 7> + %bitcast = bitcast <4 x i32> %shuffle to <8 x i16> + %elem1 = extractelement <8 x i16> %bitcast, i32 4 + %elem2 = extractelement <8 x i16> %bitcast, i32 7 + %res = add i16 %elem1, %elem2 + ret i16 %res +} + +; ...and again with a merge high. +define i16 @f5(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) { +; CHECK-LABEL: f5: +; CHECK-NOT: vrepg +; CHECK-NOT: vmr +; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 2 +; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 3 +; CHECK: br %r14 + %add = add <4 x i32> %v1, %v2 + %splat = shufflevector <2 x i64> %v3, <2 x i64> undef, + <2 x i32> <i32 0, i32 0> + %splatcast = bitcast <2 x i64> %splat to <4 x i32> + %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast, + <4 x i32> <i32 0, i32 4, i32 1, i32 5> + %bitcast = bitcast <4 x i32> %shuffle to <8 x i16> + %elem1 = extractelement <8 x i16> %bitcast, i32 4 + %elem2 = extractelement <8 x i16> %bitcast, i32 7 + %res = add i16 %elem1, %elem2 + ret i16 %res +} + +; Test a case where an unpack high can be eliminated from the usual +; load-extend sequence. +define void @f6(<8 x i8> *%ptr1, i8 *%ptr2, i8 *%ptr3, i8 *%ptr4) { +; CHECK-LABEL: f6: +; CHECK: vlrepg [[REG:%v[0-9]+]], 0(%r2) +; CHECK-NOT: vup +; CHECK-DAG: vsteb [[REG]], 0(%r3), 1 +; CHECK-DAG: vsteb [[REG]], 0(%r4), 2 +; CHECK-DAG: vsteb [[REG]], 0(%r5), 7 +; CHECK: br %r14 + %vec = load <8 x i8>, <8 x i8> *%ptr1 + %ext = sext <8 x i8> %vec to <8 x i16> + %elem1 = extractelement <8 x i16> %ext, i32 1 + %elem2 = extractelement <8 x i16> %ext, i32 2 + %elem3 = extractelement <8 x i16> %ext, i32 7 + %trunc1 = trunc i16 %elem1 to i8 + %trunc2 = trunc i16 %elem2 to i8 + %trunc3 = trunc i16 %elem3 to i8 + store i8 %trunc1, i8 *%ptr2 + store i8 %trunc2, i8 *%ptr3 + store i8 %trunc3, i8 *%ptr4 + ret void +} + +; ...and again with a bitcast inbetween. +define void @f7(<4 x i8> *%ptr1, i8 *%ptr2, i8 *%ptr3, i8 *%ptr4) { +; CHECK-LABEL: f7: +; CHECK: vlrepf [[REG:%v[0-9]+]], 0(%r2) +; CHECK-NOT: vup +; CHECK-DAG: vsteb [[REG]], 0(%r3), 0 +; CHECK-DAG: vsteb [[REG]], 0(%r4), 1 +; CHECK-DAG: vsteb [[REG]], 0(%r5), 3 +; CHECK: br %r14 + %vec = load <4 x i8>, <4 x i8> *%ptr1 + %ext = sext <4 x i8> %vec to <4 x i32> + %bitcast = bitcast <4 x i32> %ext to <8 x i16> + %elem1 = extractelement <8 x i16> %bitcast, i32 1 + %elem2 = extractelement <8 x i16> %bitcast, i32 3 + %elem3 = extractelement <8 x i16> %bitcast, i32 7 + %trunc1 = trunc i16 %elem1 to i8 + %trunc2 = trunc i16 %elem2 to i8 + %trunc3 = trunc i16 %elem3 to i8 + store i8 %trunc1, i8 *%ptr2 + store i8 %trunc2, i8 *%ptr3 + store i8 %trunc3, i8 *%ptr4 + ret void +} diff --git a/test/CodeGen/SystemZ/vec-combine-02.ll b/test/CodeGen/SystemZ/vec-combine-02.ll new file mode 100644 index 000000000000..db0bf849017b --- /dev/null +++ b/test/CodeGen/SystemZ/vec-combine-02.ll @@ -0,0 +1,433 @@ +; Test various representations of pack-like operations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; One way of writing a <4 x i32> -> <8 x i16> pack. +define <8 x i16> @f1(<4 x i32> %val0, <4 x i32> %val1) { +; CHECK-LABEL: f1: +; CHECK: vpkf %v24, %v24, %v26 +; CHECK: br %r14 + %elem0 = extractelement <4 x i32> %val0, i32 0 + %elem1 = extractelement <4 x i32> %val0, i32 1 + %elem2 = extractelement <4 x i32> %val0, i32 2 + %elem3 = extractelement <4 x i32> %val0, i32 3 + %elem4 = extractelement <4 x i32> %val1, i32 0 + %elem5 = extractelement <4 x i32> %val1, i32 1 + %elem6 = extractelement <4 x i32> %val1, i32 2 + %elem7 = extractelement <4 x i32> %val1, i32 3 + %hboth0 = bitcast i32 %elem0 to <2 x i16> + %hboth1 = bitcast i32 %elem1 to <2 x i16> + %hboth2 = bitcast i32 %elem2 to <2 x i16> + %hboth3 = bitcast i32 %elem3 to <2 x i16> + %hboth4 = bitcast i32 %elem4 to <2 x i16> + %hboth5 = bitcast i32 %elem5 to <2 x i16> + %hboth6 = bitcast i32 %elem6 to <2 x i16> + %hboth7 = bitcast i32 %elem7 to <2 x i16> + %hlow0 = shufflevector <2 x i16> %hboth0, <2 x i16> %hboth1, + <2 x i32> <i32 1, i32 3> + %hlow1 = shufflevector <2 x i16> %hboth2, <2 x i16> %hboth3, + <2 x i32> <i32 1, i32 3> + %hlow2 = shufflevector <2 x i16> %hboth4, <2 x i16> %hboth5, + <2 x i32> <i32 1, i32 3> + %hlow3 = shufflevector <2 x i16> %hboth6, <2 x i16> %hboth7, + <2 x i32> <i32 1, i32 3> + %join0 = shufflevector <2 x i16> %hlow0, <2 x i16> %hlow1, + <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %join1 = shufflevector <2 x i16> %hlow2, <2 x i16> %hlow3, + <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %ret = shufflevector <4 x i16> %join0, <4 x i16> %join1, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %ret +} + +; A different way of writing a <4 x i32> -> <8 x i16> pack. +define <8 x i16> @f2(<4 x i32> %val0, <4 x i32> %val1) { +; CHECK-LABEL: f2: +; CHECK: vpkf %v24, %v24, %v26 +; CHECK: br %r14 + %elem0 = extractelement <4 x i32> %val0, i32 0 + %elem1 = extractelement <4 x i32> %val0, i32 1 + %elem2 = extractelement <4 x i32> %val0, i32 2 + %elem3 = extractelement <4 x i32> %val0, i32 3 + %elem4 = extractelement <4 x i32> %val1, i32 0 + %elem5 = extractelement <4 x i32> %val1, i32 1 + %elem6 = extractelement <4 x i32> %val1, i32 2 + %elem7 = extractelement <4 x i32> %val1, i32 3 + %wvec0 = insertelement <4 x i32> undef, i32 %elem0, i32 0 + %wvec1 = insertelement <4 x i32> undef, i32 %elem1, i32 0 + %wvec2 = insertelement <4 x i32> undef, i32 %elem2, i32 0 + %wvec3 = insertelement <4 x i32> undef, i32 %elem3, i32 0 + %wvec4 = insertelement <4 x i32> undef, i32 %elem4, i32 0 + %wvec5 = insertelement <4 x i32> undef, i32 %elem5, i32 0 + %wvec6 = insertelement <4 x i32> undef, i32 %elem6, i32 0 + %wvec7 = insertelement <4 x i32> undef, i32 %elem7, i32 0 + %hvec0 = bitcast <4 x i32> %wvec0 to <8 x i16> + %hvec1 = bitcast <4 x i32> %wvec1 to <8 x i16> + %hvec2 = bitcast <4 x i32> %wvec2 to <8 x i16> + %hvec3 = bitcast <4 x i32> %wvec3 to <8 x i16> + %hvec4 = bitcast <4 x i32> %wvec4 to <8 x i16> + %hvec5 = bitcast <4 x i32> %wvec5 to <8 x i16> + %hvec6 = bitcast <4 x i32> %wvec6 to <8 x i16> + %hvec7 = bitcast <4 x i32> %wvec7 to <8 x i16> + %hlow0 = shufflevector <8 x i16> %hvec0, <8 x i16> %hvec1, + <8 x i32> <i32 1, i32 9, i32 undef, i32 undef, + i32 undef, i32 undef, i32 undef, i32 undef> + %hlow1 = shufflevector <8 x i16> %hvec2, <8 x i16> %hvec3, + <8 x i32> <i32 1, i32 9, i32 undef, i32 undef, + i32 undef, i32 undef, i32 undef, i32 undef> + %hlow2 = shufflevector <8 x i16> %hvec4, <8 x i16> %hvec5, + <8 x i32> <i32 1, i32 9, i32 undef, i32 undef, + i32 undef, i32 undef, i32 undef, i32 undef> + %hlow3 = shufflevector <8 x i16> %hvec6, <8 x i16> %hvec7, + <8 x i32> <i32 1, i32 9, i32 undef, i32 undef, + i32 undef, i32 undef, i32 undef, i32 undef> + %join0 = shufflevector <8 x i16> %hlow0, <8 x i16> %hlow1, + <8 x i32> <i32 0, i32 1, i32 8, i32 9, + i32 undef, i32 undef, i32 undef, i32 undef> + %join1 = shufflevector <8 x i16> %hlow2, <8 x i16> %hlow3, + <8 x i32> <i32 0, i32 1, i32 8, i32 9, + i32 undef, i32 undef, i32 undef, i32 undef> + %ret = shufflevector <8 x i16> %join0, <8 x i16> %join1, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 8, i32 9, i32 10, i32 11> + ret <8 x i16> %ret +} + +; A direct pack operation. +define <8 x i16> @f3(<4 x i32> %val0, <4 x i32> %val1) { +; CHECK-LABEL: f3: +; CHECK: vpkf %v24, %v24, %v26 +; CHECK: br %r14 + %bitcast0 = bitcast <4 x i32> %val0 to <8 x i16> + %bitcast1 = bitcast <4 x i32> %val1 to <8 x i16> + %ret = shufflevector <8 x i16> %bitcast0, <8 x i16> %bitcast1, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + ret <8 x i16> %ret +} + +; One way of writing a <4 x i32> -> <16 x i8> pack. It doesn't matter +; whether the first pack is VPKF or VPKH since the even bytes of the +; result are discarded. +define <16 x i8> @f4(<4 x i32> %val0, <4 x i32> %val1, + <4 x i32> %val2, <4 x i32> %val3) { +; CHECK-LABEL: f4: +; CHECK-DAG: vpk{{[hf]}} [[REG1:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vpk{{[hf]}} [[REG2:%v[0-9]+]], %v28, %v30 +; CHECK: vpkh %v24, [[REG1]], [[REG2]] +; CHECK: br %r14 + %bitcast0 = bitcast <4 x i32> %val0 to <8 x i16> + %bitcast1 = bitcast <4 x i32> %val1 to <8 x i16> + %bitcast2 = bitcast <4 x i32> %val2 to <8 x i16> + %bitcast3 = bitcast <4 x i32> %val3 to <8 x i16> + %join0 = shufflevector <8 x i16> %bitcast0, <8 x i16> %bitcast1, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + %join1 = shufflevector <8 x i16> %bitcast2, <8 x i16> %bitcast3, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + %bitcast4 = bitcast <8 x i16> %join0 to <16 x i8> + %bitcast5 = bitcast <8 x i16> %join1 to <16 x i8> + %ret = shufflevector <16 x i8> %bitcast4, <16 x i8> %bitcast5, + <16 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15, + i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31> + ret <16 x i8> %ret +} + +; Check the same operation, but with elements being extracted from the result. +define void @f5(<4 x i32> %val0, <4 x i32> %val1, + <4 x i32> %val2, <4 x i32> %val3, + i8 *%base) { +; CHECK-LABEL: f5: +; CHECK-DAG: vsteb %v24, 0(%r2), 11 +; CHECK-DAG: vsteb %v26, 1(%r2), 15 +; CHECK-DAG: vsteb %v28, 2(%r2), 3 +; CHECK-DAG: vsteb %v30, 3(%r2), 7 +; CHECK: br %r14 + %bitcast0 = bitcast <4 x i32> %val0 to <8 x i16> + %bitcast1 = bitcast <4 x i32> %val1 to <8 x i16> + %bitcast2 = bitcast <4 x i32> %val2 to <8 x i16> + %bitcast3 = bitcast <4 x i32> %val3 to <8 x i16> + %join0 = shufflevector <8 x i16> %bitcast0, <8 x i16> %bitcast1, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + %join1 = shufflevector <8 x i16> %bitcast2, <8 x i16> %bitcast3, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + %bitcast4 = bitcast <8 x i16> %join0 to <16 x i8> + %bitcast5 = bitcast <8 x i16> %join1 to <16 x i8> + %vec = shufflevector <16 x i8> %bitcast4, <16 x i8> %bitcast5, + <16 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15, + i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31> + + %ptr0 = getelementptr i8, i8 *%base, i64 0 + %ptr1 = getelementptr i8, i8 *%base, i64 1 + %ptr2 = getelementptr i8, i8 *%base, i64 2 + %ptr3 = getelementptr i8, i8 *%base, i64 3 + + %byte0 = extractelement <16 x i8> %vec, i32 2 + %byte1 = extractelement <16 x i8> %vec, i32 7 + %byte2 = extractelement <16 x i8> %vec, i32 8 + %byte3 = extractelement <16 x i8> %vec, i32 13 + + store i8 %byte0, i8 *%ptr0 + store i8 %byte1, i8 *%ptr1 + store i8 %byte2, i8 *%ptr2 + store i8 %byte3, i8 *%ptr3 + + ret void +} + +; A different way of writing a <4 x i32> -> <16 x i8> pack. +define <16 x i8> @f6(<4 x i32> %val0, <4 x i32> %val1, + <4 x i32> %val2, <4 x i32> %val3) { +; CHECK-LABEL: f6: +; CHECK-DAG: vpk{{[hf]}} [[REG1:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vpk{{[hf]}} [[REG2:%v[0-9]+]], %v28, %v30 +; CHECK: vpkh %v24, [[REG1]], [[REG2]] +; CHECK: br %r14 + %elem0 = extractelement <4 x i32> %val0, i32 0 + %elem1 = extractelement <4 x i32> %val0, i32 1 + %elem2 = extractelement <4 x i32> %val0, i32 2 + %elem3 = extractelement <4 x i32> %val0, i32 3 + %elem4 = extractelement <4 x i32> %val1, i32 0 + %elem5 = extractelement <4 x i32> %val1, i32 1 + %elem6 = extractelement <4 x i32> %val1, i32 2 + %elem7 = extractelement <4 x i32> %val1, i32 3 + %elem8 = extractelement <4 x i32> %val2, i32 0 + %elem9 = extractelement <4 x i32> %val2, i32 1 + %elem10 = extractelement <4 x i32> %val2, i32 2 + %elem11 = extractelement <4 x i32> %val2, i32 3 + %elem12 = extractelement <4 x i32> %val3, i32 0 + %elem13 = extractelement <4 x i32> %val3, i32 1 + %elem14 = extractelement <4 x i32> %val3, i32 2 + %elem15 = extractelement <4 x i32> %val3, i32 3 + %bitcast0 = bitcast i32 %elem0 to <2 x i16> + %bitcast1 = bitcast i32 %elem1 to <2 x i16> + %bitcast2 = bitcast i32 %elem2 to <2 x i16> + %bitcast3 = bitcast i32 %elem3 to <2 x i16> + %bitcast4 = bitcast i32 %elem4 to <2 x i16> + %bitcast5 = bitcast i32 %elem5 to <2 x i16> + %bitcast6 = bitcast i32 %elem6 to <2 x i16> + %bitcast7 = bitcast i32 %elem7 to <2 x i16> + %bitcast8 = bitcast i32 %elem8 to <2 x i16> + %bitcast9 = bitcast i32 %elem9 to <2 x i16> + %bitcast10 = bitcast i32 %elem10 to <2 x i16> + %bitcast11 = bitcast i32 %elem11 to <2 x i16> + %bitcast12 = bitcast i32 %elem12 to <2 x i16> + %bitcast13 = bitcast i32 %elem13 to <2 x i16> + %bitcast14 = bitcast i32 %elem14 to <2 x i16> + %bitcast15 = bitcast i32 %elem15 to <2 x i16> + %low0 = shufflevector <2 x i16> %bitcast0, <2 x i16> %bitcast1, + <2 x i32> <i32 1, i32 3> + %low1 = shufflevector <2 x i16> %bitcast2, <2 x i16> %bitcast3, + <2 x i32> <i32 1, i32 3> + %low2 = shufflevector <2 x i16> %bitcast4, <2 x i16> %bitcast5, + <2 x i32> <i32 1, i32 3> + %low3 = shufflevector <2 x i16> %bitcast6, <2 x i16> %bitcast7, + <2 x i32> <i32 1, i32 3> + %low4 = shufflevector <2 x i16> %bitcast8, <2 x i16> %bitcast9, + <2 x i32> <i32 1, i32 3> + %low5 = shufflevector <2 x i16> %bitcast10, <2 x i16> %bitcast11, + <2 x i32> <i32 1, i32 3> + %low6 = shufflevector <2 x i16> %bitcast12, <2 x i16> %bitcast13, + <2 x i32> <i32 1, i32 3> + %low7 = shufflevector <2 x i16> %bitcast14, <2 x i16> %bitcast15, + <2 x i32> <i32 1, i32 3> + %bytes0 = bitcast <2 x i16> %low0 to <4 x i8> + %bytes1 = bitcast <2 x i16> %low1 to <4 x i8> + %bytes2 = bitcast <2 x i16> %low2 to <4 x i8> + %bytes3 = bitcast <2 x i16> %low3 to <4 x i8> + %bytes4 = bitcast <2 x i16> %low4 to <4 x i8> + %bytes5 = bitcast <2 x i16> %low5 to <4 x i8> + %bytes6 = bitcast <2 x i16> %low6 to <4 x i8> + %bytes7 = bitcast <2 x i16> %low7 to <4 x i8> + %blow0 = shufflevector <4 x i8> %bytes0, <4 x i8> %bytes1, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %blow1 = shufflevector <4 x i8> %bytes2, <4 x i8> %bytes3, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %blow2 = shufflevector <4 x i8> %bytes4, <4 x i8> %bytes5, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %blow3 = shufflevector <4 x i8> %bytes6, <4 x i8> %bytes7, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %join0 = shufflevector <4 x i8> %blow0, <4 x i8> %blow1, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7> + %join1 = shufflevector <4 x i8> %blow2, <4 x i8> %blow3, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7> + %ret = shufflevector <8 x i8> %join0, <8 x i8> %join1, + <16 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7, + i32 8, i32 9, i32 10, i32 11, + i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %ret +} + +; One way of writing a <2 x i64> -> <16 x i8> pack. +define <16 x i8> @f7(<2 x i64> %val0, <2 x i64> %val1, + <2 x i64> %val2, <2 x i64> %val3, + <2 x i64> %val4, <2 x i64> %val5, + <2 x i64> %val6, <2 x i64> %val7) { +; CHECK-LABEL: f7: +; CHECK-DAG: vpk{{[hfg]}} [[REG1:%v[0-9]+]], %v24, %v26 +; CHECK-DAG: vpk{{[hfg]}} [[REG2:%v[0-9]+]], %v28, %v30 +; CHECK-DAG: vpk{{[hfg]}} [[REG3:%v[0-9]+]], %v25, %v27 +; CHECK-DAG: vpk{{[hfg]}} [[REG4:%v[0-9]+]], %v29, %v31 +; CHECK-DAG: vpk{{[hf]}} [[REG5:%v[0-9]+]], [[REG1]], [[REG2]] +; CHECK-DAG: vpk{{[hf]}} [[REG6:%v[0-9]+]], [[REG3]], [[REG4]] +; CHECK: vpkh %v24, [[REG5]], [[REG6]] +; CHECK: br %r14 + %elem0 = extractelement <2 x i64> %val0, i32 0 + %elem1 = extractelement <2 x i64> %val0, i32 1 + %elem2 = extractelement <2 x i64> %val1, i32 0 + %elem3 = extractelement <2 x i64> %val1, i32 1 + %elem4 = extractelement <2 x i64> %val2, i32 0 + %elem5 = extractelement <2 x i64> %val2, i32 1 + %elem6 = extractelement <2 x i64> %val3, i32 0 + %elem7 = extractelement <2 x i64> %val3, i32 1 + %elem8 = extractelement <2 x i64> %val4, i32 0 + %elem9 = extractelement <2 x i64> %val4, i32 1 + %elem10 = extractelement <2 x i64> %val5, i32 0 + %elem11 = extractelement <2 x i64> %val5, i32 1 + %elem12 = extractelement <2 x i64> %val6, i32 0 + %elem13 = extractelement <2 x i64> %val6, i32 1 + %elem14 = extractelement <2 x i64> %val7, i32 0 + %elem15 = extractelement <2 x i64> %val7, i32 1 + %bitcast0 = bitcast i64 %elem0 to <2 x i32> + %bitcast1 = bitcast i64 %elem1 to <2 x i32> + %bitcast2 = bitcast i64 %elem2 to <2 x i32> + %bitcast3 = bitcast i64 %elem3 to <2 x i32> + %bitcast4 = bitcast i64 %elem4 to <2 x i32> + %bitcast5 = bitcast i64 %elem5 to <2 x i32> + %bitcast6 = bitcast i64 %elem6 to <2 x i32> + %bitcast7 = bitcast i64 %elem7 to <2 x i32> + %bitcast8 = bitcast i64 %elem8 to <2 x i32> + %bitcast9 = bitcast i64 %elem9 to <2 x i32> + %bitcast10 = bitcast i64 %elem10 to <2 x i32> + %bitcast11 = bitcast i64 %elem11 to <2 x i32> + %bitcast12 = bitcast i64 %elem12 to <2 x i32> + %bitcast13 = bitcast i64 %elem13 to <2 x i32> + %bitcast14 = bitcast i64 %elem14 to <2 x i32> + %bitcast15 = bitcast i64 %elem15 to <2 x i32> + %low0 = shufflevector <2 x i32> %bitcast0, <2 x i32> %bitcast1, + <2 x i32> <i32 1, i32 3> + %low1 = shufflevector <2 x i32> %bitcast2, <2 x i32> %bitcast3, + <2 x i32> <i32 1, i32 3> + %low2 = shufflevector <2 x i32> %bitcast4, <2 x i32> %bitcast5, + <2 x i32> <i32 1, i32 3> + %low3 = shufflevector <2 x i32> %bitcast6, <2 x i32> %bitcast7, + <2 x i32> <i32 1, i32 3> + %low4 = shufflevector <2 x i32> %bitcast8, <2 x i32> %bitcast9, + <2 x i32> <i32 1, i32 3> + %low5 = shufflevector <2 x i32> %bitcast10, <2 x i32> %bitcast11, + <2 x i32> <i32 1, i32 3> + %low6 = shufflevector <2 x i32> %bitcast12, <2 x i32> %bitcast13, + <2 x i32> <i32 1, i32 3> + %low7 = shufflevector <2 x i32> %bitcast14, <2 x i32> %bitcast15, + <2 x i32> <i32 1, i32 3> + %half0 = bitcast <2 x i32> %low0 to <4 x i16> + %half1 = bitcast <2 x i32> %low1 to <4 x i16> + %half2 = bitcast <2 x i32> %low2 to <4 x i16> + %half3 = bitcast <2 x i32> %low3 to <4 x i16> + %half4 = bitcast <2 x i32> %low4 to <4 x i16> + %half5 = bitcast <2 x i32> %low5 to <4 x i16> + %half6 = bitcast <2 x i32> %low6 to <4 x i16> + %half7 = bitcast <2 x i32> %low7 to <4 x i16> + %hlow0 = shufflevector <4 x i16> %half0, <4 x i16> %half1, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %hlow1 = shufflevector <4 x i16> %half2, <4 x i16> %half3, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %hlow2 = shufflevector <4 x i16> %half4, <4 x i16> %half5, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %hlow3 = shufflevector <4 x i16> %half6, <4 x i16> %half7, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %bytes0 = bitcast <4 x i16> %hlow0 to <8 x i8> + %bytes1 = bitcast <4 x i16> %hlow1 to <8 x i8> + %bytes2 = bitcast <4 x i16> %hlow2 to <8 x i8> + %bytes3 = bitcast <4 x i16> %hlow3 to <8 x i8> + %join0 = shufflevector <8 x i8> %bytes0, <8 x i8> %bytes1, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + %join1 = shufflevector <8 x i8> %bytes2, <8 x i8> %bytes3, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + %ret = shufflevector <8 x i8> %join0, <8 x i8> %join1, + <16 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7, + i32 8, i32 9, i32 10, i32 11, + i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %ret +} + +; Test a <2 x i64> -> <4 x f32> pack in which only individual elements are +; needed. +define float @f8(i64 %scalar0, i64 %scalar1, i64 %scalar2, i64 %scalar3) { +; CHECK-LABEL: f8: +; CHECK-NOT: vperm +; CHECK-NOT: vpk +; CHECK-NOT: vmrh +; CHECK: aebr {{%f[0-7]}}, +; CHECK: aebr {{%f[0-7]}}, +; CHECK: meebr %f0, +; CHECK: br %r14 + %vec0 = insertelement <2 x i64> undef, i64 %scalar0, i32 0 + %vec1 = insertelement <2 x i64> undef, i64 %scalar1, i32 0 + %vec2 = insertelement <2 x i64> undef, i64 %scalar2, i32 0 + %vec3 = insertelement <2 x i64> undef, i64 %scalar3, i32 0 + %join0 = shufflevector <2 x i64> %vec0, <2 x i64> %vec1, + <2 x i32> <i32 0, i32 2> + %join1 = shufflevector <2 x i64> %vec2, <2 x i64> %vec3, + <2 x i32> <i32 0, i32 2> + %bitcast0 = bitcast <2 x i64> %join0 to <4 x float> + %bitcast1 = bitcast <2 x i64> %join1 to <4 x float> + %pack = shufflevector <4 x float> %bitcast0, <4 x float> %bitcast1, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %elt0 = extractelement <4 x float> %pack, i32 0 + %elt1 = extractelement <4 x float> %pack, i32 1 + %elt2 = extractelement <4 x float> %pack, i32 2 + %elt3 = extractelement <4 x float> %pack, i32 3 + %add0 = fadd float %elt0, %elt2 + %add1 = fadd float %elt1, %elt3 + %ret = fmul float %add0, %add1 + ret float %ret +} + +; Test a <2 x f64> -> <4 x i32> pack in which only individual elements are +; needed. +define i32 @f9(double %scalar0, double %scalar1, double %scalar2, + double %scalar3) { +; CHECK-LABEL: f9: +; CHECK-NOT: vperm +; CHECK-NOT: vpk +; CHECK-NOT: vmrh +; CHECK: ar {{%r[0-5]}}, +; CHECK: ar {{%r[0-5]}}, +; CHECK: or %r2, +; CHECK: br %r14 + %vec0 = insertelement <2 x double> undef, double %scalar0, i32 0 + %vec1 = insertelement <2 x double> undef, double %scalar1, i32 0 + %vec2 = insertelement <2 x double> undef, double %scalar2, i32 0 + %vec3 = insertelement <2 x double> undef, double %scalar3, i32 0 + %join0 = shufflevector <2 x double> %vec0, <2 x double> %vec1, + <2 x i32> <i32 0, i32 2> + %join1 = shufflevector <2 x double> %vec2, <2 x double> %vec3, + <2 x i32> <i32 0, i32 2> + %bitcast0 = bitcast <2 x double> %join0 to <4 x i32> + %bitcast1 = bitcast <2 x double> %join1 to <4 x i32> + %pack = shufflevector <4 x i32> %bitcast0, <4 x i32> %bitcast1, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + %elt0 = extractelement <4 x i32> %pack, i32 0 + %elt1 = extractelement <4 x i32> %pack, i32 1 + %elt2 = extractelement <4 x i32> %pack, i32 2 + %elt3 = extractelement <4 x i32> %pack, i32 3 + %add0 = add i32 %elt0, %elt2 + %add1 = add i32 %elt1, %elt3 + %ret = or i32 %add0, %add1 + ret i32 %ret +} diff --git a/test/CodeGen/SystemZ/vec-const-01.ll b/test/CodeGen/SystemZ/vec-const-01.ll new file mode 100644 index 000000000000..4cdcbf7c2dcb --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-01.ll @@ -0,0 +1,103 @@ +; Test vector byte masks, v16i8 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test an all-zeros vector. +define <16 x i8> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <16 x i8> zeroinitializer +} + +; Test an all-ones vector. +define <16 x i8> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgbm %v24, 65535 +; CHECK: br %r14 + ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> +} + +; Test a mixed vector (mask 0x8c75). +define <16 x i8> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgbm %v24, 35957 +; CHECK: br %r14 + ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0, + i8 -1, i8 -1, i8 0, i8 0, + i8 0, i8 -1, i8 -1, i8 -1, + i8 0, i8 -1, i8 0, i8 -1> +} + +; Test that undefs are treated as zero. +define <16 x i8> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgbm %v24, 35957 +; CHECK: br %r14 + ret <16 x i8> <i8 -1, i8 undef, i8 undef, i8 undef, + i8 -1, i8 -1, i8 undef, i8 undef, + i8 undef, i8 -1, i8 -1, i8 -1, + i8 undef, i8 -1, i8 undef, i8 -1> +} + +; Test that we don't use VGBM if one of the bytes is not 0 or 0xff. +define <16 x i8> @f5() { +; CHECK-LABEL: f5: +; CHECK-NOT: vgbm +; CHECK: br %r14 + ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0, + i8 -1, i8 -1, i8 0, i8 1, + i8 0, i8 -1, i8 -1, i8 -1, + i8 0, i8 -1, i8 0, i8 -1> +} + +; Test an all-zeros v2i8 that gets promoted to v16i8. +define <2 x i8> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <2 x i8> zeroinitializer +} + +; Test a mixed v2i8 that gets promoted to v16i8 (mask 0x8000). +define <2 x i8> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgbm %v24, 32768 +; CHECK: br %r14 + ret <2 x i8> <i8 255, i8 0> +} + +; Test an all-zeros v4i8 that gets promoted to v16i8. +define <4 x i8> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <4 x i8> zeroinitializer +} + +; Test a mixed v4i8 that gets promoted to v16i8 (mask 0x9000). +define <4 x i8> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgbm %v24, 36864 +; CHECK: br %r14 + ret <4 x i8> <i8 255, i8 0, i8 0, i8 255> +} + +; Test an all-zeros v8i8 that gets promoted to v16i8. +define <8 x i8> @f10() { +; CHECK-LABEL: f10: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <8 x i8> zeroinitializer +} + +; Test a mixed v8i8 that gets promoted to v16i8 (mask 0xE500). +define <8 x i8> @f11() { +; CHECK-LABEL: f11: +; CHECK: vgbm %v24, 58624 +; CHECK: br %r14 + ret <8 x i8> <i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 0, i8 255> +} diff --git a/test/CodeGen/SystemZ/vec-const-02.ll b/test/CodeGen/SystemZ/vec-const-02.ll new file mode 100644 index 000000000000..73a89d4a841b --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-02.ll @@ -0,0 +1,79 @@ +; Test vector byte masks, v8i16 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test an all-zeros vector. +define <8 x i16> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <8 x i16> zeroinitializer +} + +; Test an all-ones vector. +define <8 x i16> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgbm %v24, 65535 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> +} + +; Test a mixed vector (mask 0x8c76). +define <8 x i16> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgbm %v24, 35958 +; CHECK: br %r14 + ret <8 x i16> <i16 65280, i16 0, i16 65535, i16 0, + i16 255, i16 65535, i16 255, i16 65280> +} + +; Test that undefs are treated as zero. +define <8 x i16> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgbm %v24, 35958 +; CHECK: br %r14 + ret <8 x i16> <i16 65280, i16 undef, i16 65535, i16 undef, + i16 255, i16 65535, i16 255, i16 65280> +} + +; Test that we don't use VGBM if one of the bytes is not 0 or 0xff. +define <8 x i16> @f5() { +; CHECK-LABEL: f5: +; CHECK-NOT: vgbm +; CHECK: br %r14 + ret <8 x i16> <i16 65280, i16 0, i16 65535, i16 0, + i16 255, i16 65535, i16 256, i16 65280> +} + +; Test an all-zeros v2i16 that gets promoted to v8i16. +define <2 x i16> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <2 x i16> zeroinitializer +} + +; Test a mixed v2i16 that gets promoted to v8i16 (mask 0xc000). +define <2 x i16> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgbm %v24, 49152 +; CHECK: br %r14 + ret <2 x i16> <i16 65535, i16 0> +} + +; Test an all-zeros v4i16 that gets promoted to v8i16. +define <4 x i16> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <4 x i16> zeroinitializer +} + +; Test a mixed v4i16 that gets promoted to v8i16 (mask 0x7200). +define <4 x i16> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgbm %v24, 29184 +; CHECK: br %r14 + ret <4 x i16> <i16 255, i16 65535, i16 0, i16 65280> +} diff --git a/test/CodeGen/SystemZ/vec-const-03.ll b/test/CodeGen/SystemZ/vec-const-03.ll new file mode 100644 index 000000000000..adc1105229e6 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-03.ll @@ -0,0 +1,59 @@ +; Test vector byte masks, v4i32 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test an all-zeros vector. +define <4 x i32> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <4 x i32> zeroinitializer +} + +; Test an all-ones vector. +define <4 x i32> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgbm %v24, 65535 +; CHECK: br %r14 + ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> +} + +; Test a mixed vector (mask 0x8c76). +define <4 x i32> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgbm %v24, 35958 +; CHECK: br %r14 + ret <4 x i32> <i32 4278190080, i32 4294901760, i32 16777215, i32 16776960> +} + +; Test that undefs are treated as zero (mask 0x8076). +define <4 x i32> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgbm %v24, 32886 +; CHECK: br %r14 + ret <4 x i32> <i32 4278190080, i32 undef, i32 16777215, i32 16776960> +} + +; Test that we don't use VGBM if one of the bytes is not 0 or 0xff. +define <4 x i32> @f5() { +; CHECK-LABEL: f5: +; CHECK-NOT: vgbm +; CHECK: br %r14 + ret <4 x i32> <i32 4278190080, i32 1, i32 16777215, i32 16776960> +} + +; Test an all-zeros v2i32 that gets promoted to v4i32. +define <2 x i32> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <2 x i32> zeroinitializer +} + +; Test a mixed v2i32 that gets promoted to v4i32 (mask 0xae00). +define <2 x i32> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgbm %v24, 44544 +; CHECK: br %r14 + ret <2 x i32> <i32 4278255360, i32 -256> +} diff --git a/test/CodeGen/SystemZ/vec-const-04.ll b/test/CodeGen/SystemZ/vec-const-04.ll new file mode 100644 index 000000000000..1c2fb414d25f --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-04.ll @@ -0,0 +1,43 @@ +; Test vector byte masks, v2i64 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test an all-zeros vector. +define <2 x i64> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <2 x i64> zeroinitializer +} + +; Test an all-ones vector. +define <2 x i64> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgbm %v24, 65535 +; CHECK: br %r14 + ret <2 x i64> <i64 -1, i64 -1> +} + +; Test a mixed vector (mask 0x8c76). +define <2 x i64> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgbm %v24, 35958 +; CHECK: br %r14 + ret <2 x i64> <i64 18374686483966525440, i64 72057589759737600> +} + +; Test that undefs are treated as zero (mask 0x8c00). +define <2 x i64> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgbm %v24, 35840 +; CHECK: br %r14 + ret <2 x i64> <i64 18374686483966525440, i64 undef> +} + +; Test that we don't use VGBM if one of the bytes is not 0 or 0xff. +define <2 x i64> @f5() { +; CHECK-LABEL: f5: +; CHECK-NOT: vgbm +; CHECK: br %r14 + ret <2 x i64> <i64 18374686483966525441, i64 72057589759737600> +} diff --git a/test/CodeGen/SystemZ/vec-const-05.ll b/test/CodeGen/SystemZ/vec-const-05.ll new file mode 100644 index 000000000000..55f3cdd59027 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-05.ll @@ -0,0 +1,63 @@ +; Test vector byte masks, v4f32 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test an all-zeros vector. +define <4 x float> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <4 x float> zeroinitializer +} + +; Test an all-ones vector. +define <4 x float> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgbm %v24, 65535 +; CHECK: br %r14 + ret <4 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, + float 0xffffffffe0000000, float 0xffffffffe0000000> +} + +; Test a mixed vector (mask 0xc731). +define <4 x float> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgbm %v24, 50993 +; CHECK: br %r14 + ret <4 x float> <float 0xffffe00000000000, float 0x381fffffe0000000, + float 0x379fffe000000000, float 0x371fe00000000000> +} + +; Test that undefs are treated as zero (mask 0xc031). +define <4 x float> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgbm %v24, 49201 +; CHECK: br %r14 + ret <4 x float> <float 0xffffe00000000000, float undef, + float 0x379fffe000000000, float 0x371fe00000000000> +} + +; Test that we don't use VGBM if one of the bytes is not 0 or 0xff. +define <4 x float> @f5() { +; CHECK-LABEL: f5: +; CHECK-NOT: vgbm +; CHECK: br %r14 + ret <4 x float> <float 0xffffe00000000000, float 0x381fffffc0000000, + float 0x379fffe000000000, float 0x371fe00000000000> +} + +; Test an all-zeros v2f32 that gets promoted to v4f32. +define <2 x float> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <2 x float> zeroinitializer +} + +; Test a mixed v2f32 that gets promoted to v4f32 (mask 0xc700). +define <2 x float> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgbm %v24, 50944 +; CHECK: br %r14 + ret <2 x float> <float 0xffffe00000000000, float 0x381fffffe0000000> +} diff --git a/test/CodeGen/SystemZ/vec-const-06.ll b/test/CodeGen/SystemZ/vec-const-06.ll new file mode 100644 index 000000000000..be53a0581ec2 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-06.ll @@ -0,0 +1,43 @@ +; Test vector byte masks, v2f64 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test an all-zeros vector. +define <2 x double> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgbm %v24, 0 +; CHECK: br %r14 + ret <2 x double> zeroinitializer +} + +; Test an all-ones vector. +define <2 x double> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgbm %v24, 65535 +; CHECK: br %r14 + ret <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff> +} + +; Test a mixed vector (mask 0x8c76). +define <2 x double> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgbm %v24, 35958 +; CHECK: br %r14 + ret <2 x double> <double 0xff000000ffff0000, double 0x00ffffff00ffff00> +} + +; Test that undefs are treated as zero (mask 0x8c00). +define <2 x double> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgbm %v24, 35840 +; CHECK: br %r14 + ret <2 x double> <double 0xff000000ffff0000, double undef> +} + +; Test that we don't use VGBM if one of the bytes is not 0 or 0xff. +define <2 x double> @f5() { +; CHECK-LABEL: f5: +; CHECK-NOT: vgbm +; CHECK: br %r14 + ret <2 x double> <double 0xfe000000ffff0000, double 0x00ffffff00ffff00> +} diff --git a/test/CodeGen/SystemZ/vec-const-07.ll b/test/CodeGen/SystemZ/vec-const-07.ll new file mode 100644 index 000000000000..6fcf95b69218 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-07.ll @@ -0,0 +1,229 @@ +; Test vector replicates, v16i8 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a byte-granularity replicate with the lowest useful value. +define <16 x i8> @f1() { +; CHECK-LABEL: f1: +; CHECK: vrepib %v24, 1 +; CHECK: br %r14 + ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1> +} + +; Test a byte-granularity replicate with an arbitrary value. +define <16 x i8> @f2() { +; CHECK-LABEL: f2: +; CHECK: vrepib %v24, -55 +; CHECK: br %r14 + ret <16 x i8> <i8 201, i8 201, i8 201, i8 201, + i8 201, i8 201, i8 201, i8 201, + i8 201, i8 201, i8 201, i8 201, + i8 201, i8 201, i8 201, i8 201> +} + +; Test a byte-granularity replicate with the highest useful value. +define <16 x i8> @f3() { +; CHECK-LABEL: f3: +; CHECK: vrepib %v24, -2 +; CHECK: br %r14 + ret <16 x i8> <i8 254, i8 254, i8 254, i8 254, + i8 254, i8 254, i8 254, i8 254, + i8 254, i8 254, i8 254, i8 254, + i8 254, i8 254, i8 254, i8 254> +} + +; Test a halfword-granularity replicate with the lowest useful value. +define <16 x i8> @f4() { +; CHECK-LABEL: f4: +; CHECK: vrepih %v24, 1 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 1, i8 0, i8 1, + i8 0, i8 1, i8 0, i8 1, + i8 0, i8 1, i8 0, i8 1, + i8 0, i8 1, i8 0, i8 1> +} + +; Test a halfword-granularity replicate with an arbitrary value. +define <16 x i8> @f5() { +; CHECK-LABEL: f5: +; CHECK: vrepih %v24, 25650 +; CHECK: br %r14 + ret <16 x i8> <i8 100, i8 50, i8 100, i8 50, + i8 100, i8 50, i8 100, i8 50, + i8 100, i8 50, i8 100, i8 50, + i8 100, i8 50, i8 100, i8 50> +} + +; Test a halfword-granularity replicate with the highest useful value. +define <16 x i8> @f6() { +; CHECK-LABEL: f6: +; CHECK: vrepih %v24, -2 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 254, i8 255, i8 254, + i8 255, i8 254, i8 255, i8 254, + i8 255, i8 254, i8 255, i8 254, + i8 255, i8 254, i8 255, i8 254> +} + +; Test a word-granularity replicate with the lowest useful positive value. +define <16 x i8> @f7() { +; CHECK-LABEL: f7: +; CHECK: vrepif %v24, 1 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 0, i8 1, + i8 0, i8 0, i8 0, i8 1, + i8 0, i8 0, i8 0, i8 1, + i8 0, i8 0, i8 0, i8 1> +} + +; Test a word-granularity replicate with the highest in-range value. +define <16 x i8> @f8() { +; CHECK-LABEL: f8: +; CHECK: vrepif %v24, 32767 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 127, i8 255, + i8 0, i8 0, i8 127, i8 255, + i8 0, i8 0, i8 127, i8 255, + i8 0, i8 0, i8 127, i8 255> +} + +; Test a word-granularity replicate with the next highest value. +; This cannot use VREPIF. +define <16 x i8> @f9() { +; CHECK-LABEL: f9: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 128, i8 0> +} + +; Test a word-granularity replicate with the lowest in-range value. +define <16 x i8> @f10() { +; CHECK-LABEL: f10: +; CHECK: vrepif %v24, -32768 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 128, i8 0, + i8 255, i8 255, i8 128, i8 0, + i8 255, i8 255, i8 128, i8 0, + i8 255, i8 255, i8 128, i8 0> +} + +; Test a word-granularity replicate with the next lowest value. +; This cannot use VREPIF. +define <16 x i8> @f11() { +; CHECK-LABEL: f11: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 127, i8 255, + i8 255, i8 255, i8 127, i8 255, + i8 255, i8 255, i8 127, i8 255, + i8 255, i8 255, i8 127, i8 255> +} + +; Test a word-granularity replicate with the highest useful negative value. +define <16 x i8> @f12() { +; CHECK-LABEL: f12: +; CHECK: vrepif %v24, -2 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 255, i8 254, + i8 255, i8 255, i8 255, i8 254, + i8 255, i8 255, i8 255, i8 254, + i8 255, i8 255, i8 255, i8 254> +} + +; Test a doubleword-granularity replicate with the lowest useful positive +; value. +define <16 x i8> @f13() { +; CHECK-LABEL: f13: +; CHECK: vrepig %v24, 1 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 0, i8 1, + i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 0, i8 1> +} + +; Test a doubleword-granularity replicate with the highest in-range value. +define <16 x i8> @f14() { +; CHECK-LABEL: f14: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 127, i8 255, + i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 127, i8 255> +} + +; Test a doubleword-granularity replicate with the next highest value. +; This cannot use VREPIG. +define <16 x i8> @f15() { +; CHECK-LABEL: f15: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 128, i8 0> +} + +; Test a doubleword-granularity replicate with the lowest in-range value. +define <16 x i8> @f16() { +; CHECK-LABEL: f16: +; CHECK: vrepig %v24, -32768 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 255, i8 255, + i8 255, i8 255, i8 128, i8 0, + i8 255, i8 255, i8 255, i8 255, + i8 255, i8 255, i8 128, i8 0> +} + +; Test a doubleword-granularity replicate with the next lowest value. +; This cannot use VREPIG. +define <16 x i8> @f17() { +; CHECK-LABEL: f17: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 255, i8 255, + i8 255, i8 255, i8 127, i8 255, + i8 255, i8 255, i8 255, i8 255, + i8 255, i8 255, i8 127, i8 255> +} + +; Test a doubleword-granularity replicate with the highest useful negative +; value. +define <16 x i8> @f18() { +; CHECK-LABEL: f18: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 255, i8 255, + i8 255, i8 255, i8 255, i8 254, + i8 255, i8 255, i8 255, i8 255, + i8 255, i8 255, i8 255, i8 254> +} + +; Repeat f14 with undefs optimistically treated as 0. +define <16 x i8> @f19() { +; CHECK-LABEL: f19: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 undef, i8 0, i8 0, + i8 0, i8 0, i8 127, i8 255, + i8 undef, i8 0, i8 undef, i8 0, + i8 0, i8 0, i8 127, i8 255> +} + +; Repeat f18 with undefs optimistically treated as -1. +define <16 x i8> @f20() { +; CHECK-LABEL: f20: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <16 x i8> <i8 undef, i8 255, i8 255, i8 255, + i8 255, i8 255, i8 undef, i8 254, + i8 255, i8 255, i8 255, i8 undef, + i8 255, i8 undef, i8 255, i8 254> +} diff --git a/test/CodeGen/SystemZ/vec-const-08.ll b/test/CodeGen/SystemZ/vec-const-08.ll new file mode 100644 index 000000000000..5ab6947e548e --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-08.ll @@ -0,0 +1,189 @@ +; Test vector replicates, v8i16 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a byte-granularity replicate with the lowest useful value. +define <8 x i16> @f1() { +; CHECK-LABEL: f1: +; CHECK: vrepib %v24, 1 +; CHECK: br %r14 + ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, + i16 257, i16 257, i16 257, i16 257> +} + +; Test a byte-granularity replicate with an arbitrary value. +define <8 x i16> @f2() { +; CHECK-LABEL: f2: +; CHECK: vrepib %v24, -55 +; CHECK: br %r14 + ret <8 x i16> <i16 51657, i16 51657, i16 51657, i16 51657, + i16 51657, i16 51657, i16 51657, i16 51657> +} + +; Test a byte-granularity replicate with the highest useful value. +define <8 x i16> @f3() { +; CHECK-LABEL: f3: +; CHECK: vrepib %v24, -2 +; CHECK: br %r14 + ret <8 x i16> <i16 -258, i16 -258, i16 -258, i16 -258, + i16 -258, i16 -258, i16 -258, i16 -258> +} + +; Test a halfword-granularity replicate with the lowest useful value. +define <8 x i16> @f4() { +; CHECK-LABEL: f4: +; CHECK: vrepih %v24, 1 +; CHECK: br %r14 + ret <8 x i16> <i16 1, i16 1, i16 1, i16 1, + i16 1, i16 1, i16 1, i16 1> +} + +; Test a halfword-granularity replicate with an arbitrary value. +define <8 x i16> @f5() { +; CHECK-LABEL: f5: +; CHECK: vrepih %v24, 25650 +; CHECK: br %r14 + ret <8 x i16> <i16 25650, i16 25650, i16 25650, i16 25650, + i16 25650, i16 25650, i16 25650, i16 25650> +} + +; Test a halfword-granularity replicate with the highest useful value. +define <8 x i16> @f6() { +; CHECK-LABEL: f6: +; CHECK: vrepih %v24, -2 +; CHECK: br %r14 + ret <8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, + i16 65534, i16 65534, i16 65534, i16 65534> +} + +; Test a word-granularity replicate with the lowest useful positive value. +define <8 x i16> @f7() { +; CHECK-LABEL: f7: +; CHECK: vrepif %v24, 1 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 1, i16 0, i16 1, + i16 0, i16 1, i16 0, i16 1> +} + +; Test a word-granularity replicate with the highest in-range value. +define <8 x i16> @f8() { +; CHECK-LABEL: f8: +; CHECK: vrepif %v24, 32767 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 32767, i16 0, i16 32767, + i16 0, i16 32767, i16 0, i16 32767> +} + +; Test a word-granularity replicate with the next highest value. +; This cannot use VREPIF. +define <8 x i16> @f9() { +; CHECK-LABEL: f9: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 32768, i16 0, i16 32768, + i16 0, i16 32768, i16 0, i16 32768> +} + +; Test a word-granularity replicate with the lowest in-range value. +define <8 x i16> @f10() { +; CHECK-LABEL: f10: +; CHECK: vrepif %v24, -32768 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -32768, i16 -1, i16 -32768, + i16 -1, i16 -32768, i16 -1, i16 -32768> +} + +; Test a word-granularity replicate with the next lowest value. +; This cannot use VREPIF. +define <8 x i16> @f11() { +; CHECK-LABEL: f11: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -32769, i16 -1, i16 -32769, + i16 -1, i16 -32769, i16 -1, i16 -32769> +} + +; Test a word-granularity replicate with the highest useful negative value. +define <8 x i16> @f12() { +; CHECK-LABEL: f12: +; CHECK: vrepif %v24, -2 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -2, i16 -1, i16 -2, + i16 -1, i16 -2, i16 -1, i16 -2> +} + +; Test a doubleword-granularity replicate with the lowest useful positive +; value. +define <8 x i16> @f13() { +; CHECK-LABEL: f13: +; CHECK: vrepig %v24, 1 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 0, i16 0, i16 1, + i16 0, i16 0, i16 0, i16 1> +} + +; Test a doubleword-granularity replicate with the highest in-range value. +define <8 x i16> @f14() { +; CHECK-LABEL: f14: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 0, i16 0, i16 32767, + i16 0, i16 0, i16 0, i16 32767> +} + +; Test a doubleword-granularity replicate with the next highest value. +; This cannot use VREPIG. +define <8 x i16> @f15() { +; CHECK-LABEL: f15: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 0, i16 0, i16 32768, + i16 0, i16 0, i16 0, i16 32768> +} + +; Test a doubleword-granularity replicate with the lowest in-range value. +define <8 x i16> @f16() { +; CHECK-LABEL: f16: +; CHECK: vrepig %v24, -32768 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -32768, + i16 -1, i16 -1, i16 -1, i16 -32768> +} + +; Test a doubleword-granularity replicate with the next lowest value. +; This cannot use VREPIG. +define <8 x i16> @f17() { +; CHECK-LABEL: f17: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -32769, + i16 -1, i16 -1, i16 -1, i16 -32769> +} + +; Test a doubleword-granularity replicate with the highest useful negative +; value. +define <8 x i16> @f18() { +; CHECK-LABEL: f18: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -2, + i16 -1, i16 -1, i16 -1, i16 -2> +} + +; Repeat f14 with undefs optimistically treated as 0. +define <8 x i16> @f19() { +; CHECK-LABEL: f19: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 undef, i16 0, i16 32767, + i16 undef, i16 0, i16 undef, i16 32767> +} + +; Repeat f18 with undefs optimistically treated as -1. +define <8 x i16> @f20() { +; CHECK-LABEL: f20: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -1, i16 undef, i16 -2, + i16 undef, i16 undef, i16 -1, i16 -2> +} diff --git a/test/CodeGen/SystemZ/vec-const-09.ll b/test/CodeGen/SystemZ/vec-const-09.ll new file mode 100644 index 000000000000..2cbe92594525 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-09.ll @@ -0,0 +1,169 @@ +; Test vector replicates, v4i32 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a byte-granularity replicate with the lowest useful value. +define <4 x i32> @f1() { +; CHECK-LABEL: f1: +; CHECK: vrepib %v24, 1 +; CHECK: br %r14 + ret <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009> +} + +; Test a byte-granularity replicate with an arbitrary value. +define <4 x i32> @f2() { +; CHECK-LABEL: f2: +; CHECK: vrepib %v24, -55 +; CHECK: br %r14 + ret <4 x i32> <i32 3385444809, i32 3385444809, i32 3385444809, i32 3385444809> +} + +; Test a byte-granularity replicate with the highest useful value. +define <4 x i32> @f3() { +; CHECK-LABEL: f3: +; CHECK: vrepib %v24, -2 +; CHECK: br %r14 + ret <4 x i32> <i32 4278124286, i32 4278124286, i32 4278124286, i32 4278124286> +} + +; Test a halfword-granularity replicate with the lowest useful value. +define <4 x i32> @f4() { +; CHECK-LABEL: f4: +; CHECK: vrepih %v24, 1 +; CHECK: br %r14 + ret <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537> +} + +; Test a halfword-granularity replicate with an arbitrary value. +define <4 x i32> @f5() { +; CHECK-LABEL: f5: +; CHECK: vrepih %v24, 25650 +; CHECK: br %r14 + ret <4 x i32> <i32 1681024050, i32 1681024050, i32 1681024050, i32 1681024050> +} + +; Test a halfword-granularity replicate with the highest useful value. +define <4 x i32> @f6() { +; CHECK-LABEL: f6: +; CHECK: vrepih %v24, -2 +; CHECK: br %r14 + ret <4 x i32> <i32 -65538, i32 -65538, i32 -65538, i32 -65538> +} + +; Test a word-granularity replicate with the lowest useful positive value. +define <4 x i32> @f7() { +; CHECK-LABEL: f7: +; CHECK: vrepif %v24, 1 +; CHECK: br %r14 + ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> +} + +; Test a word-granularity replicate with the highest in-range value. +define <4 x i32> @f8() { +; CHECK-LABEL: f8: +; CHECK: vrepif %v24, 32767 +; CHECK: br %r14 + ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> +} + +; Test a word-granularity replicate with the next highest value. +; This cannot use VREPIF. +define <4 x i32> @f9() { +; CHECK-LABEL: f9: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <4 x i32> <i32 32768, i32 32768, i32 32768, i32 32768> +} + +; Test a word-granularity replicate with the lowest in-range value. +define <4 x i32> @f10() { +; CHECK-LABEL: f10: +; CHECK: vrepif %v24, -32768 +; CHECK: br %r14 + ret <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768> +} + +; Test a word-granularity replicate with the next lowest value. +; This cannot use VREPIF. +define <4 x i32> @f11() { +; CHECK-LABEL: f11: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <4 x i32> <i32 -32769, i32 -32769, i32 -32769, i32 -32769> +} + +; Test a word-granularity replicate with the highest useful negative value. +define <4 x i32> @f12() { +; CHECK-LABEL: f12: +; CHECK: vrepif %v24, -2 +; CHECK: br %r14 + ret <4 x i32> <i32 -2, i32 -2, i32 -2, i32 -2> +} + +; Test a doubleword-granularity replicate with the lowest useful positive +; value. +define <4 x i32> @f13() { +; CHECK-LABEL: f13: +; CHECK: vrepig %v24, 1 +; CHECK: br %r14 + ret <4 x i32> <i32 0, i32 1, i32 0, i32 1> +} + +; Test a doubleword-granularity replicate with the highest in-range value. +define <4 x i32> @f14() { +; CHECK-LABEL: f14: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <4 x i32> <i32 0, i32 32767, i32 0, i32 32767> +} + +; Test a doubleword-granularity replicate with the next highest value. +; This cannot use VREPIG. +define <4 x i32> @f15() { +; CHECK-LABEL: f15: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <4 x i32> <i32 0, i32 32768, i32 0, i32 32768> +} + +; Test a doubleword-granularity replicate with the lowest in-range value. +define <4 x i32> @f16() { +; CHECK-LABEL: f16: +; CHECK: vrepig %v24, -32768 +; CHECK: br %r14 + ret <4 x i32> <i32 -1, i32 -32768, i32 -1, i32 -32768> +} + +; Test a doubleword-granularity replicate with the next lowest value. +; This cannot use VREPIG. +define <4 x i32> @f17() { +; CHECK-LABEL: f17: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <4 x i32> <i32 -1, i32 -32769, i32 -1, i32 -32769> +} + +; Test a doubleword-granularity replicate with the highest useful negative +; value. +define <4 x i32> @f18() { +; CHECK-LABEL: f18: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <4 x i32> <i32 -1, i32 -2, i32 -1, i32 -2> +} + +; Repeat f14 with undefs optimistically treated as 0, 32767. +define <4 x i32> @f19() { +; CHECK-LABEL: f19: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <4 x i32> <i32 undef, i32 undef, i32 0, i32 32767> +} + +; Repeat f18 with undefs optimistically treated as -2, -1. +define <4 x i32> @f20() { +; CHECK-LABEL: f20: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <4 x i32> <i32 -1, i32 undef, i32 undef, i32 -2> +} diff --git a/test/CodeGen/SystemZ/vec-const-10.ll b/test/CodeGen/SystemZ/vec-const-10.ll new file mode 100644 index 000000000000..0613b69a2777 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-10.ll @@ -0,0 +1,169 @@ +; Test vector replicates, v2i64 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a byte-granularity replicate with the lowest useful value. +define <2 x i64> @f1() { +; CHECK-LABEL: f1: +; CHECK: vrepib %v24, 1 +; CHECK: br %r14 + ret <2 x i64> <i64 72340172838076673, i64 72340172838076673> +} + +; Test a byte-granularity replicate with an arbitrary value. +define <2 x i64> @f2() { +; CHECK-LABEL: f2: +; CHECK: vrepib %v24, -55 +; CHECK: br %r14 + ret <2 x i64> <i64 -3906369333256140343, i64 -3906369333256140343> +} + +; Test a byte-granularity replicate with the highest useful value. +define <2 x i64> @f3() { +; CHECK-LABEL: f3: +; CHECK: vrepib %v24, -2 +; CHECK: br %r14 + ret <2 x i64> <i64 -72340172838076674, i64 -72340172838076674> +} + +; Test a halfword-granularity replicate with the lowest useful value. +define <2 x i64> @f4() { +; CHECK-LABEL: f4: +; CHECK: vrepih %v24, 1 +; CHECK: br %r14 + ret <2 x i64> <i64 281479271743489, i64 281479271743489> +} + +; Test a halfword-granularity replicate with an arbitrary value. +define <2 x i64> @f5() { +; CHECK-LABEL: f5: +; CHECK: vrepih %v24, 25650 +; CHECK: br %r14 + ret <2 x i64> <i64 7219943320220492850, i64 7219943320220492850> +} + +; Test a halfword-granularity replicate with the highest useful value. +define <2 x i64> @f6() { +; CHECK-LABEL: f6: +; CHECK: vrepih %v24, -2 +; CHECK: br %r14 + ret <2 x i64> <i64 -281479271743490, i64 -281479271743490> +} + +; Test a word-granularity replicate with the lowest useful positive value. +define <2 x i64> @f7() { +; CHECK-LABEL: f7: +; CHECK: vrepif %v24, 1 +; CHECK: br %r14 + ret <2 x i64> <i64 4294967297, i64 4294967297> +} + +; Test a word-granularity replicate with the highest in-range value. +define <2 x i64> @f8() { +; CHECK-LABEL: f8: +; CHECK: vrepif %v24, 32767 +; CHECK: br %r14 + ret <2 x i64> <i64 140733193420799, i64 140733193420799> +} + +; Test a word-granularity replicate with the next highest value. +; This cannot use VREPIF. +define <2 x i64> @f9() { +; CHECK-LABEL: f9: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <2 x i64> <i64 140737488388096, i64 140737488388096> +} + +; Test a word-granularity replicate with the lowest in-range value. +define <2 x i64> @f10() { +; CHECK-LABEL: f10: +; CHECK: vrepif %v24, -32768 +; CHECK: br %r14 + ret <2 x i64> <i64 -140733193420800, i64 -140733193420800> +} + +; Test a word-granularity replicate with the next lowest value. +; This cannot use VREPIF. +define <2 x i64> @f11() { +; CHECK-LABEL: f11: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <2 x i64> <i64 -140737488388097, i64 -140737488388097> +} + +; Test a word-granularity replicate with the highest useful negative value. +define <2 x i64> @f12() { +; CHECK-LABEL: f12: +; CHECK: vrepif %v24, -2 +; CHECK: br %r14 + ret <2 x i64> <i64 -4294967298, i64 -4294967298> +} + +; Test a doubleword-granularity replicate with the lowest useful positive +; value. +define <2 x i64> @f13() { +; CHECK-LABEL: f13: +; CHECK: vrepig %v24, 1 +; CHECK: br %r14 + ret <2 x i64> <i64 1, i64 1> +} + +; Test a doubleword-granularity replicate with the highest in-range value. +define <2 x i64> @f14() { +; CHECK-LABEL: f14: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <2 x i64> <i64 32767, i64 32767> +} + +; Test a doubleword-granularity replicate with the next highest value. +; This cannot use VREPIG. +define <2 x i64> @f15() { +; CHECK-LABEL: f15: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <2 x i64> <i64 32768, i64 32768> +} + +; Test a doubleword-granularity replicate with the lowest in-range value. +define <2 x i64> @f16() { +; CHECK-LABEL: f16: +; CHECK: vrepig %v24, -32768 +; CHECK: br %r14 + ret <2 x i64> <i64 -32768, i64 -32768> +} + +; Test a doubleword-granularity replicate with the next lowest value. +; This cannot use VREPIG. +define <2 x i64> @f17() { +; CHECK-LABEL: f17: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <2 x i64> <i64 -32769, i64 -32769> +} + +; Test a doubleword-granularity replicate with the highest useful negative +; value. +define <2 x i64> @f18() { +; CHECK-LABEL: f18: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <2 x i64> <i64 -2, i64 -2> +} + +; Repeat f14 with undefs optimistically treated as 32767. +define <2 x i64> @f19() { +; CHECK-LABEL: f19: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <2 x i64> <i64 undef, i64 32767> +} + +; Repeat f18 with undefs optimistically treated as -2. +define <2 x i64> @f20() { +; CHECK-LABEL: f20: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <2 x i64> <i64 undef, i64 -2> +} diff --git a/test/CodeGen/SystemZ/vec-const-11.ll b/test/CodeGen/SystemZ/vec-const-11.ll new file mode 100644 index 000000000000..0c69b8803b2f --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-11.ll @@ -0,0 +1,189 @@ +; Test vector replicates, v4f32 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a byte-granularity replicate with the lowest useful value. +define <4 x float> @f1() { +; CHECK-LABEL: f1: +; CHECK: vrepib %v24, 1 +; CHECK: br %r14 + ret <4 x float> <float 0x3820202020000000, float 0x3820202020000000, + float 0x3820202020000000, float 0x3820202020000000> +} + +; Test a byte-granularity replicate with an arbitrary value. +define <4 x float> @f2() { +; CHECK-LABEL: f2: +; CHECK: vrepib %v24, -55 +; CHECK: br %r14 + ret <4 x float> <float 0xc139393920000000, float 0xc139393920000000, + float 0xc139393920000000, float 0xc139393920000000> +} + +; Test a byte-granularity replicate with the highest useful value. +define <4 x float> @f3() { +; CHECK-LABEL: f3: +; CHECK: vrepib %v24, -2 +; CHECK: br %r14 + ret <4 x float> <float 0xc7dfdfdfc0000000, float 0xc7dfdfdfc0000000, + float 0xc7dfdfdfc0000000, float 0xc7dfdfdfc0000000> +} + +; Test a halfword-granularity replicate with the lowest useful value. +define <4 x float> @f4() { +; CHECK-LABEL: f4: +; CHECK: vrepih %v24, 1 +; CHECK: br %r14 + ret <4 x float> <float 0x37a0001000000000, float 0x37a0001000000000, + float 0x37a0001000000000, float 0x37a0001000000000> +} + +; Test a halfword-granularity replicate with an arbitrary value. +define <4 x float> @f5() { +; CHECK-LABEL: f5: +; CHECK: vrepih %v24, 25650 +; CHECK: br %r14 + ret <4 x float> <float 0x44864c8640000000, float 0x44864c8640000000, + float 0x44864c8640000000, float 0x44864c8640000000> +} + +; Test a halfword-granularity replicate with the highest useful value. +define <4 x float> @f6() { +; CHECK-LABEL: f6: +; CHECK: vrepih %v24, -2 +; CHECK: br %r14 + ret <4 x float> <float 0xffffdfffc0000000, float 0xffffdfffc0000000, + float 0xffffdfffc0000000, float 0xffffdfffc0000000> +} + +; Test a word-granularity replicate with the lowest useful positive value. +define <4 x float> @f7() { +; CHECK-LABEL: f7: +; CHECK: vrepif %v24, 1 +; CHECK: br %r14 + ret <4 x float> <float 0x36a0000000000000, float 0x36a0000000000000, + float 0x36a0000000000000, float 0x36a0000000000000> +} + +; Test a word-granularity replicate with the highest in-range value. +define <4 x float> @f8() { +; CHECK-LABEL: f8: +; CHECK: vrepif %v24, 32767 +; CHECK: br %r14 + ret <4 x float> <float 0x378fffc000000000, float 0x378fffc000000000, + float 0x378fffc000000000, float 0x378fffc000000000> +} + +; Test a word-granularity replicate with the next highest value. +; This cannot use VREPIF. +define <4 x float> @f9() { +; CHECK-LABEL: f9: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <4 x float> <float 0x3790000000000000, float 0x3790000000000000, + float 0x3790000000000000, float 0x3790000000000000> +} + +; Test a word-granularity replicate with the lowest in-range value. +define <4 x float> @f10() { +; CHECK-LABEL: f10: +; CHECK: vrepif %v24, -32768 +; CHECK: br %r14 + ret <4 x float> <float 0xfffff00000000000, float 0xfffff00000000000, + float 0xfffff00000000000, float 0xfffff00000000000> +} + +; Test a word-granularity replicate with the next lowest value. +; This cannot use VREPIF. +define <4 x float> @f11() { +; CHECK-LABEL: f11: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <4 x float> <float 0xffffefffe0000000, float 0xffffefffe0000000, + float 0xffffefffe0000000, float 0xffffefffe0000000> +} + +; Test a word-granularity replicate with the highest useful negative value. +define <4 x float> @f12() { +; CHECK-LABEL: f12: +; CHECK: vrepif %v24, -2 +; CHECK: br %r14 + ret <4 x float> <float 0xffffffffc0000000, float 0xffffffffc0000000, + float 0xffffffffc0000000, float 0xffffffffc0000000> +} + +; Test a doubleword-granularity replicate with the lowest useful positive +; value. +define <4 x float> @f13() { +; CHECK-LABEL: f13: +; CHECK: vrepig %v24, 1 +; CHECK: br %r14 + ret <4 x float> <float 0.0, float 0x36a0000000000000, + float 0.0, float 0x36a0000000000000> +} + +; Test a doubleword-granularity replicate with the highest in-range value. +define <4 x float> @f14() { +; CHECK-LABEL: f14: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <4 x float> <float 0.0, float 0x378fffc000000000, + float 0.0, float 0x378fffc000000000> +} + +; Test a doubleword-granularity replicate with the next highest value. +; This cannot use VREPIG. +define <4 x float> @f15() { +; CHECK-LABEL: f15: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <4 x float> <float 0.0, float 0x3790000000000000, + float 0.0, float 0x3790000000000000> +} + +; Test a doubleword-granularity replicate with the lowest in-range value. +define <4 x float> @f16() { +; CHECK-LABEL: f16: +; CHECK: vrepig %v24, -32768 +; CHECK: br %r14 + ret <4 x float> <float 0xffffffffe0000000, float 0xfffff00000000000, + float 0xffffffffe0000000, float 0xfffff00000000000> +} + +; Test a doubleword-granularity replicate with the next lowest value. +; This cannot use VREPIG. +define <4 x float> @f17() { +; CHECK-LABEL: f17: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <4 x float> <float 0xffffffffe0000000, float 0xffffefffe0000000, + float 0xffffffffe0000000, float 0xffffefffe0000000> +} + +; Test a doubleword-granularity replicate with the highest useful negative +; value. +define <4 x float> @f18() { +; CHECK-LABEL: f18: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <4 x float> <float 0xffffffffe0000000, float 0xffffffffc0000000, + float 0xffffffffe0000000, float 0xffffffffc0000000> +} + +; Repeat f14 with undefs optimistically treated as 0, 32767. +define <4 x float> @f19() { +; CHECK-LABEL: f19: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <4 x float> <float undef, float undef, + float 0.0, float 0x378fffc000000000> +} + +; Repeat f18 with undefs optimistically treated as -2, -1. +define <4 x float> @f20() { +; CHECK-LABEL: f20: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <4 x float> <float 0xffffffffe0000000, float undef, + float undef, float 0xffffffffc0000000> +} diff --git a/test/CodeGen/SystemZ/vec-const-12.ll b/test/CodeGen/SystemZ/vec-const-12.ll new file mode 100644 index 000000000000..ca66a3d173eb --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-12.ll @@ -0,0 +1,169 @@ +; Test vector replicates, v2f64 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a byte-granularity replicate with the lowest useful value. +define <2 x double> @f1() { +; CHECK-LABEL: f1: +; CHECK: vrepib %v24, 1 +; CHECK: br %r14 + ret <2 x double> <double 0x0101010101010101, double 0x0101010101010101> +} + +; Test a byte-granularity replicate with an arbitrary value. +define <2 x double> @f2() { +; CHECK-LABEL: f2: +; CHECK: vrepib %v24, -55 +; CHECK: br %r14 + ret <2 x double> <double 0xc9c9c9c9c9c9c9c9, double 0xc9c9c9c9c9c9c9c9> +} + +; Test a byte-granularity replicate with the highest useful value. +define <2 x double> @f3() { +; CHECK-LABEL: f3: +; CHECK: vrepib %v24, -2 +; CHECK: br %r14 + ret <2 x double> <double 0xfefefefefefefefe, double 0xfefefefefefefefe> +} + +; Test a halfword-granularity replicate with the lowest useful value. +define <2 x double> @f4() { +; CHECK-LABEL: f4: +; CHECK: vrepih %v24, 1 +; CHECK: br %r14 + ret <2 x double> <double 0x0001000100010001, double 0x0001000100010001> +} + +; Test a halfword-granularity replicate with an arbitrary value. +define <2 x double> @f5() { +; CHECK-LABEL: f5: +; CHECK: vrepih %v24, 25650 +; CHECK: br %r14 + ret <2 x double> <double 0x6432643264326432, double 0x6432643264326432> +} + +; Test a halfword-granularity replicate with the highest useful value. +define <2 x double> @f6() { +; CHECK-LABEL: f6: +; CHECK: vrepih %v24, -2 +; CHECK: br %r14 + ret <2 x double> <double 0xfffefffefffefffe, double 0xfffefffefffefffe> +} + +; Test a word-granularity replicate with the lowest useful positive value. +define <2 x double> @f7() { +; CHECK-LABEL: f7: +; CHECK: vrepif %v24, 1 +; CHECK: br %r14 + ret <2 x double> <double 0x0000000100000001, double 0x0000000100000001> +} + +; Test a word-granularity replicate with the highest in-range value. +define <2 x double> @f8() { +; CHECK-LABEL: f8: +; CHECK: vrepif %v24, 32767 +; CHECK: br %r14 + ret <2 x double> <double 0x00007fff00007fff, double 0x00007fff00007fff> +} + +; Test a word-granularity replicate with the next highest value. +; This cannot use VREPIF. +define <2 x double> @f9() { +; CHECK-LABEL: f9: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <2 x double> <double 0x0000800000008000, double 0x0000800000008000> +} + +; Test a word-granularity replicate with the lowest in-range value. +define <2 x double> @f10() { +; CHECK-LABEL: f10: +; CHECK: vrepif %v24, -32768 +; CHECK: br %r14 + ret <2 x double> <double 0xffff8000ffff8000, double 0xffff8000ffff8000> +} + +; Test a word-granularity replicate with the next lowest value. +; This cannot use VREPIF. +define <2 x double> @f11() { +; CHECK-LABEL: f11: +; CHECK-NOT: vrepif +; CHECK: br %r14 + ret <2 x double> <double 0xffff7fffffff7fff, double 0xffff7fffffff7fff> +} + +; Test a word-granularity replicate with the highest useful negative value. +define <2 x double> @f12() { +; CHECK-LABEL: f12: +; CHECK: vrepif %v24, -2 +; CHECK: br %r14 + ret <2 x double> <double 0xfffffffefffffffe, double 0xfffffffefffffffe> +} + +; Test a doubleword-granularity replicate with the lowest useful positive +; value. +define <2 x double> @f13() { +; CHECK-LABEL: f13: +; CHECK: vrepig %v24, 1 +; CHECK: br %r14 + ret <2 x double> <double 0x0000000000000001, double 0x0000000000000001> +} + +; Test a doubleword-granularity replicate with the highest in-range value. +define <2 x double> @f14() { +; CHECK-LABEL: f14: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <2 x double> <double 0x0000000000007fff, double 0x0000000000007fff> +} + +; Test a doubleword-granularity replicate with the next highest value. +; This cannot use VREPIG. +define <2 x double> @f15() { +; CHECK-LABEL: f15: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <2 x double> <double 0x0000000000008000, double 0x0000000000008000> +} + +; Test a doubleword-granularity replicate with the lowest in-range value. +define <2 x double> @f16() { +; CHECK-LABEL: f16: +; CHECK: vrepig %v24, -32768 +; CHECK: br %r14 + ret <2 x double> <double 0xffffffffffff8000, double 0xffffffffffff8000> +} + +; Test a doubleword-granularity replicate with the next lowest value. +; This cannot use VREPIG. +define <2 x double> @f17() { +; CHECK-LABEL: f17: +; CHECK-NOT: vrepig +; CHECK: br %r14 + ret <2 x double> <double 0xffffffffffff7fff, double 0xffffffffffff7fff> +} + +; Test a doubleword-granularity replicate with the highest useful negative +; value. +define <2 x double> @f18() { +; CHECK-LABEL: f18: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <2 x double> <double 0xfffffffffffffffe, double 0xfffffffffffffffe> +} + +; Repeat f14 with undefs optimistically treated as 32767. +define <2 x double> @f19() { +; CHECK-LABEL: f19: +; CHECK: vrepig %v24, 32767 +; CHECK: br %r14 + ret <2 x double> <double undef, double 0x0000000000007fff> +} + +; Repeat f18 with undefs optimistically treated as -2. +define <2 x double> @f20() { +; CHECK-LABEL: f20: +; CHECK: vrepig %v24, -2 +; CHECK: br %r14 + ret <2 x double> <double undef, double 0xfffffffffffffffe> +} diff --git a/test/CodeGen/SystemZ/vec-const-13.ll b/test/CodeGen/SystemZ/vec-const-13.ll new file mode 100644 index 000000000000..2cc425252c21 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-13.ll @@ -0,0 +1,193 @@ +; Test vector replicates that use VECTOR GENERATE MASK, v16i8 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a word-granularity replicate with the lowest value that cannot use +; VREPIF. +define <16 x i8> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 128, i8 0> +} + +; Test a word-granularity replicate that has the lower 17 bits set. +define <16 x i8> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgmf %v24, 15, 31 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 1, i8 255, i8 255, + i8 0, i8 1, i8 255, i8 255, + i8 0, i8 1, i8 255, i8 255, + i8 0, i8 1, i8 255, i8 255> +} + +; Test a word-granularity replicate that has the upper 15 bits set. +define <16 x i8> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgmf %v24, 0, 14 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 254, i8 0, i8 0, + i8 255, i8 254, i8 0, i8 0, + i8 255, i8 254, i8 0, i8 0, + i8 255, i8 254, i8 0, i8 0> +} + +; Test a word-granularity replicate that has middle bits set. +define <16 x i8> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgmf %v24, 12, 17 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 15, i8 192, i8 0, + i8 0, i8 15, i8 192, i8 0, + i8 0, i8 15, i8 192, i8 0, + i8 0, i8 15, i8 192, i8 0> +} + +; Test a word-granularity replicate with a wrap-around mask. +define <16 x i8> @f5() { +; CHECK-LABEL: f5: +; CHECK: vgmf %v24, 17, 15 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 127, i8 255, + i8 255, i8 255, i8 127, i8 255, + i8 255, i8 255, i8 127, i8 255, + i8 255, i8 255, i8 127, i8 255> +} + +; Test a doubleword-granularity replicate with the lowest value that cannot +; use VREPIG. +define <16 x i8> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgmg %v24, 48, 48 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 128, i8 0, + i8 0, i8 0, i8 0, i8 0, + i8 0, i8 0, i8 128, i8 0> +} + +; Test a doubleword-granularity replicate that has the lower 22 bits set. +define <16 x i8> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgmg %v24, 42, 63 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, + i8 0, i8 63, i8 255, i8 255, + i8 0, i8 0, i8 0, i8 0, + i8 0, i8 63, i8 255, i8 255> +} + +; Test a doubleword-granularity replicate that has the upper 45 bits set. +define <16 x i8> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgmg %v24, 0, 44 +; CHECK: br %r14 + ret <16 x i8> <i8 255, i8 255, i8 255, i8 255, + i8 255, i8 248, i8 0, i8 0, + i8 255, i8 255, i8 255, i8 255, + i8 255, i8 248, i8 0, i8 0> +} + +; Test a doubleword-granularity replicate that has middle bits set. +define <16 x i8> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgmg %v24, 31, 42 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 0, i8 0, i8 1, + i8 255, i8 224, i8 0, i8 0, + i8 0, i8 0, i8 0, i8 1, + i8 255, i8 224, i8 0, i8 0> +} + +; Test a doubleword-granularity replicate with a wrap-around mask. +define <16 x i8> @f10() { +; CHECK-LABEL: f10: +; CHECK: vgmg %v24, 18, 0 +; CHECK: br %r14 + ret <16 x i8> <i8 128, i8 0, i8 63, i8 255, + i8 255, i8 255, i8 255, i8 255, + i8 128, i8 0, i8 63, i8 255, + i8 255, i8 255, i8 255, i8 255> +} + +; Retest f1 with arbitrary undefs instead of 0s. +define <16 x i8> @f11() { +; CHECK-LABEL: f11: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 undef, i8 128, i8 0, + i8 0, i8 0, i8 128, i8 undef, + i8 undef, i8 0, i8 128, i8 0, + i8 undef, i8 undef, i8 128, i8 0> +} + +; Try a case where we want consistent undefs to be treated as 0. +define <16 x i8> @f12() { +; CHECK-LABEL: f12: +; CHECK: vgmf %v24, 15, 23 +; CHECK: br %r14 + ret <16 x i8> <i8 undef, i8 1, i8 255, i8 0, + i8 undef, i8 1, i8 255, i8 0, + i8 undef, i8 1, i8 255, i8 0, + i8 undef, i8 1, i8 255, i8 0> +} + +; ...and again with the lower bits of the replicated constant. +define <16 x i8> @f13() { +; CHECK-LABEL: f13: +; CHECK: vgmf %v24, 15, 22 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 1, i8 254, i8 undef, + i8 0, i8 1, i8 254, i8 undef, + i8 0, i8 1, i8 254, i8 undef, + i8 0, i8 1, i8 254, i8 undef> +} + +; Try a case where we want consistent undefs to be treated as -1. +define <16 x i8> @f14() { +; CHECK-LABEL: f14: +; CHECK: vgmf %v24, 28, 8 +; CHECK: br %r14 + ret <16 x i8> <i8 undef, i8 128, i8 0, i8 15, + i8 undef, i8 128, i8 0, i8 15, + i8 undef, i8 128, i8 0, i8 15, + i8 undef, i8 128, i8 0, i8 15> +} + +; ...and again with the lower bits of the replicated constant. +define <16 x i8> @f15() { +; CHECK-LABEL: f15: +; CHECK: vgmf %v24, 18, 3 +; CHECK: br %r14 + ret <16 x i8> <i8 240, i8 0, i8 63, i8 undef, + i8 240, i8 0, i8 63, i8 undef, + i8 240, i8 0, i8 63, i8 undef, + i8 240, i8 0, i8 63, i8 undef> +} + +; Repeat f9 with arbitrary undefs. +define <16 x i8> @f16() { +; CHECK-LABEL: f16: +; CHECK: vgmg %v24, 31, 42 +; CHECK: br %r14 + ret <16 x i8> <i8 undef, i8 0, i8 undef, i8 1, + i8 255, i8 undef, i8 0, i8 0, + i8 0, i8 0, i8 0, i8 1, + i8 undef, i8 224, i8 undef, i8 undef> +} + +; Try a case where we want some consistent undefs to be treated as 0 +; and some to be treated as 255. +define <16 x i8> @f17() { +; CHECK-LABEL: f17: +; CHECK: vgmg %v24, 23, 35 +; CHECK: br %r14 + ret <16 x i8> <i8 0, i8 undef, i8 1, i8 undef, + i8 240, i8 undef, i8 0, i8 0, + i8 0, i8 undef, i8 1, i8 undef, + i8 240, i8 undef, i8 0, i8 0> +} diff --git a/test/CodeGen/SystemZ/vec-const-14.ll b/test/CodeGen/SystemZ/vec-const-14.ll new file mode 100644 index 000000000000..0e3f124dbf6a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-14.ll @@ -0,0 +1,113 @@ +; Test vector replicates that use VECTOR GENERATE MASK, v8i16 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a word-granularity replicate with the lowest value that cannot use +; VREPIF. +define <8 x i16> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 32768, i16 0, i16 32768, + i16 0, i16 32768, i16 0, i16 32768> +} + +; Test a word-granularity replicate that has the lower 17 bits set. +define <8 x i16> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgmf %v24, 15, 31 +; CHECK: br %r14 + ret <8 x i16> <i16 1, i16 -1, i16 1, i16 -1, + i16 1, i16 -1, i16 1, i16 -1> +} + +; Test a word-granularity replicate that has the upper 15 bits set. +define <8 x i16> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgmf %v24, 0, 14 +; CHECK: br %r14 + ret <8 x i16> <i16 -2, i16 0, i16 -2, i16 0, + i16 -2, i16 0, i16 -2, i16 0> +} + +; Test a word-granularity replicate that has middle bits set. +define <8 x i16> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgmf %v24, 12, 17 +; CHECK: br %r14 + ret <8 x i16> <i16 15, i16 49152, i16 15, i16 49152, + i16 15, i16 49152, i16 15, i16 49152> +} + +; Test a word-granularity replicate with a wrap-around mask. +define <8 x i16> @f5() { +; CHECK-LABEL: f5: +; CHECK: vgmf %v24, 17, 15 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 32767, i16 -1, i16 32767, + i16 -1, i16 32767, i16 -1, i16 32767> +} + +; Test a doubleword-granularity replicate with the lowest value that cannot +; use VREPIG. +define <8 x i16> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgmg %v24, 48, 48 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 0, i16 0, i16 32768, + i16 0, i16 0, i16 0, i16 32768> +} + +; Test a doubleword-granularity replicate that has the lower 22 bits set. +define <8 x i16> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgmg %v24, 42, 63 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 0, i16 63, i16 -1, + i16 0, i16 0, i16 63, i16 -1> +} + +; Test a doubleword-granularity replicate that has the upper 45 bits set. +define <8 x i16> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgmg %v24, 0, 44 +; CHECK: br %r14 + ret <8 x i16> <i16 -1, i16 -1, i16 -8, i16 0, + i16 -1, i16 -1, i16 -8, i16 0> +} + +; Test a doubleword-granularity replicate that has middle bits set. +define <8 x i16> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgmg %v24, 31, 42 +; CHECK: br %r14 + ret <8 x i16> <i16 0, i16 1, i16 -32, i16 0, + i16 0, i16 1, i16 -32, i16 0> +} + +; Test a doubleword-granularity replicate with a wrap-around mask. +define <8 x i16> @f10() { +; CHECK-LABEL: f10: +; CHECK: vgmg %v24, 18, 0 +; CHECK: br %r14 + ret <8 x i16> <i16 32768, i16 16383, i16 -1, i16 -1, + i16 32768, i16 16383, i16 -1, i16 -1> +} + +; Retest f1 with arbitrary undefs instead of 0s. +define <8 x i16> @f11() { +; CHECK-LABEL: f11: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <8 x i16> <i16 undef, i16 32768, i16 0, i16 32768, + i16 0, i16 32768, i16 undef, i16 32768> +} + +; ...likewise f9. +define <8 x i16> @f12() { +; CHECK-LABEL: f12: +; CHECK: vgmg %v24, 31, 42 +; CHECK: br %r14 + ret <8 x i16> <i16 undef, i16 1, i16 -32, i16 0, + i16 0, i16 1, i16 -32, i16 undef> +} diff --git a/test/CodeGen/SystemZ/vec-const-15.ll b/test/CodeGen/SystemZ/vec-const-15.ll new file mode 100644 index 000000000000..cec445efe893 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-15.ll @@ -0,0 +1,85 @@ +; Test vector replicates that use VECTOR GENERATE MASK, v4i32 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a word-granularity replicate with the lowest value that cannot use +; VREPIF. +define <4 x i32> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <4 x i32> <i32 32768, i32 32768, i32 32768, i32 32768> +} + +; Test a word-granularity replicate that has the lower 17 bits set. +define <4 x i32> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgmf %v24, 15, 31 +; CHECK: br %r14 + ret <4 x i32> <i32 131071, i32 131071, i32 131071, i32 131071> +} + +; Test a word-granularity replicate that has the upper 15 bits set. +define <4 x i32> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgmf %v24, 0, 14 +; CHECK: br %r14 + ret <4 x i32> <i32 -131072, i32 -131072, i32 -131072, i32 -131072> +} + +; Test a word-granularity replicate that has middle bits set. +define <4 x i32> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgmf %v24, 12, 17 +; CHECK: br %r14 + ret <4 x i32> <i32 1032192, i32 1032192, i32 1032192, i32 1032192> +} + +; Test a word-granularity replicate with a wrap-around mask. +define <4 x i32> @f5() { +; CHECK-LABEL: f5: +; CHECK: vgmf %v24, 17, 15 +; CHECK: br %r14 + ret <4 x i32> <i32 -32769, i32 -32769, i32 -32769, i32 -32769> +} + +; Test a doubleword-granularity replicate with the lowest value that cannot +; use VREPIG. +define <4 x i32> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgmg %v24, 48, 48 +; CHECK: br %r14 + ret <4 x i32> <i32 0, i32 32768, i32 0, i32 32768> +} + +; Test a doubleword-granularity replicate that has the lower 22 bits set. +define <4 x i32> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgmg %v24, 42, 63 +; CHECK: br %r14 + ret <4 x i32> <i32 0, i32 4194303, i32 0, i32 4194303> +} + +; Test a doubleword-granularity replicate that has the upper 45 bits set. +define <4 x i32> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgmg %v24, 0, 44 +; CHECK: br %r14 + ret <4 x i32> <i32 -1, i32 -524288, i32 -1, i32 -524288> +} + +; Test a doubleword-granularity replicate that has middle bits set. +define <4 x i32> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgmg %v24, 31, 42 +; CHECK: br %r14 + ret <4 x i32> <i32 1, i32 -2097152, i32 1, i32 -2097152> +} + +; Test a doubleword-granularity replicate with a wrap-around mask. +define <4 x i32> @f10() { +; CHECK-LABEL: f10: +; CHECK: vgmg %v24, 18, 0 +; CHECK: br %r14 + ret <4 x i32> <i32 -2147467265, i32 -1, i32 -2147467265, i32 -1> +} diff --git a/test/CodeGen/SystemZ/vec-const-16.ll b/test/CodeGen/SystemZ/vec-const-16.ll new file mode 100644 index 000000000000..1ab7de2761cf --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-16.ll @@ -0,0 +1,85 @@ +; Test vector replicates that use VECTOR GENERATE MASK, v2i64 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a word-granularity replicate with the lowest value that cannot use +; VREPIF. +define <2 x i64> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <2 x i64> <i64 140737488388096, i64 140737488388096> +} + +; Test a word-granularity replicate that has the lower 17 bits set. +define <2 x i64> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgmf %v24, 15, 31 +; CHECK: br %r14 + ret <2 x i64> <i64 562945658585087, i64 562945658585087> +} + +; Test a word-granularity replicate that has the upper 15 bits set. +define <2 x i64> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgmf %v24, 0, 14 +; CHECK: br %r14 + ret <2 x i64> <i64 -562945658585088, i64 -562945658585088> +} + +; Test a word-granularity replicate that has middle bits set. +define <2 x i64> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgmf %v24, 12, 17 +; CHECK: br %r14 + ret <2 x i64> <i64 4433230884225024, i64 4433230884225024> +} + +; Test a word-granularity replicate with a wrap-around mask. +define <2 x i64> @f5() { +; CHECK-LABEL: f5: +; CHECK: vgmf %v24, 17, 15 +; CHECK: br %r14 + ret <2 x i64> <i64 -140737488388097, i64 -140737488388097> +} + +; Test a doubleword-granularity replicate with the lowest value that cannot +; use VREPIG. +define <2 x i64> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgmg %v24, 48, 48 +; CHECK: br %r14 + ret <2 x i64> <i64 32768, i64 32768> +} + +; Test a doubleword-granularity replicate that has the lower 22 bits set. +define <2 x i64> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgmg %v24, 42, 63 +; CHECK: br %r14 + ret <2 x i64> <i64 4194303, i64 4194303> +} + +; Test a doubleword-granularity replicate that has the upper 45 bits set. +define <2 x i64> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgmg %v24, 0, 44 +; CHECK: br %r14 + ret <2 x i64> <i64 -524288, i64 -524288> +} + +; Test a doubleword-granularity replicate that has middle bits set. +define <2 x i64> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgmg %v24, 31, 42 +; CHECK: br %r14 + ret <2 x i64> <i64 8587837440, i64 8587837440> +} + +; Test a doubleword-granularity replicate with a wrap-around mask. +define <2 x i64> @f10() { +; CHECK-LABEL: f10: +; CHECK: vgmg %v24, 18, 0 +; CHECK: br %r14 + ret <2 x i64> <i64 -9223301668110598145, i64 -9223301668110598145> +} diff --git a/test/CodeGen/SystemZ/vec-const-17.ll b/test/CodeGen/SystemZ/vec-const-17.ll new file mode 100644 index 000000000000..1306eab556e9 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-17.ll @@ -0,0 +1,95 @@ +; Test vector replicates that use VECTOR GENERATE MASK, v4f32 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a word-granularity replicate with the lowest value that cannot use +; VREPIF. +define <4 x float> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <4 x float> <float 0x3790000000000000, float 0x3790000000000000, + float 0x3790000000000000, float 0x3790000000000000> +} + +; Test a word-granularity replicate that has the lower 17 bits set. +define <4 x float> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgmf %v24, 15, 31 +; CHECK: br %r14 + ret <4 x float> <float 0x37affff000000000, float 0x37affff000000000, + float 0x37affff000000000, float 0x37affff000000000> +} + +; Test a word-granularity replicate that has the upper 15 bits set. +define <4 x float> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgmf %v24, 0, 14 +; CHECK: br %r14 + ret <4 x float> <float 0xffffc00000000000, float 0xffffc00000000000, + float 0xffffc00000000000, float 0xffffc00000000000> +} + +; Test a word-granularity replicate that has middle bits set. +define <4 x float> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgmf %v24, 2, 8 +; CHECK: br %r14 + ret <4 x float> <float 0x3ff0000000000000, float 0x3ff0000000000000, + float 0x3ff0000000000000, float 0x3ff0000000000000> +} + +; Test a word-granularity replicate with a wrap-around mask. +define <4 x float> @f5() { +; CHECK-LABEL: f5: +; CHECK: vgmf %v24, 9, 1 +; CHECK: br %r14 + ret <4 x float> <float 0xc00fffffe0000000, float 0xc00fffffe0000000, + float 0xc00fffffe0000000, float 0xc00fffffe0000000> +} + +; Test a doubleword-granularity replicate with the lowest value that cannot +; use VREPIG. +define <4 x float> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgmg %v24, 48, 48 +; CHECK: br %r14 + ret <4 x float> <float 0.0, float 0x3790000000000000, + float 0.0, float 0x3790000000000000> +} + +; Test a doubleword-granularity replicate that has the lower 22 bits set. +define <4 x float> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgmg %v24, 42, 63 +; CHECK: br %r14 + ret <4 x float> <float 0.0, float 0x37ffffff80000000, + float 0.0, float 0x37ffffff80000000> +} + +; Test a doubleword-granularity replicate that has the upper 45 bits set. +define <4 x float> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgmg %v24, 0, 44 +; CHECK: br %r14 + ret <4 x float> <float 0xffffffffe0000000, float 0xffff000000000000, + float 0xffffffffe0000000, float 0xffff000000000000> +} + +; Test a doubleword-granularity replicate that has middle bits set. +define <4 x float> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgmg %v24, 34, 41 +; CHECK: br %r14 + ret <4 x float> <float 0.0, float 0x3ff8000000000000, + float 0.0, float 0x3ff8000000000000> +} + +; Test a doubleword-granularity replicate with a wrap-around mask. +define <4 x float> @f10() { +; CHECK-LABEL: f10: +; CHECK: vgmg %v24, 32, 0 +; CHECK: br %r14 + ret <4 x float> <float 0x8000000000000000, float 0xffffffffe0000000, + float 0x8000000000000000, float 0xffffffffe0000000> +} diff --git a/test/CodeGen/SystemZ/vec-const-18.ll b/test/CodeGen/SystemZ/vec-const-18.ll new file mode 100644 index 000000000000..c6c20c2a0037 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-const-18.ll @@ -0,0 +1,85 @@ +; Test vector replicates that use VECTOR GENERATE MASK, v2f64 version. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a word-granularity replicate with the lowest value that cannot use +; VREPIF. +define <2 x double> @f1() { +; CHECK-LABEL: f1: +; CHECK: vgmf %v24, 16, 16 +; CHECK: br %r14 + ret <2 x double> <double 0x0000800000008000, double 0x0000800000008000> +} + +; Test a word-granularity replicate that has the lower 17 bits set. +define <2 x double> @f2() { +; CHECK-LABEL: f2: +; CHECK: vgmf %v24, 15, 31 +; CHECK: br %r14 + ret <2 x double> <double 0x0001ffff0001ffff, double 0x0001ffff0001ffff> +} + +; Test a word-granularity replicate that has the upper 15 bits set. +define <2 x double> @f3() { +; CHECK-LABEL: f3: +; CHECK: vgmf %v24, 0, 14 +; CHECK: br %r14 + ret <2 x double> <double 0xfffe0000fffe0000, double 0xfffe0000fffe0000> +} + +; Test a word-granularity replicate that has middle bits set. +define <2 x double> @f4() { +; CHECK-LABEL: f4: +; CHECK: vgmf %v24, 2, 11 +; CHECK: br %r14 + ret <2 x double> <double 0x3ff000003ff00000, double 0x3ff000003ff00000> +} + +; Test a word-granularity replicate with a wrap-around mask. +define <2 x double> @f5() { +; CHECK-LABEL: f5: +; CHECK: vgmf %v24, 17, 15 +; CHECK: br %r14 + ret <2 x double> <double 0xffff7fffffff7fff, double 0xffff7fffffff7fff> +} + +; Test a doubleword-granularity replicate with the lowest value that cannot +; use VREPIG. +define <2 x double> @f6() { +; CHECK-LABEL: f6: +; CHECK: vgmg %v24, 48, 48 +; CHECK: br %r14 + ret <2 x double> <double 0x0000000000008000, double 0x0000000000008000> +} + +; Test a doubleword-granularity replicate that has the lower 22 bits set. +define <2 x double> @f7() { +; CHECK-LABEL: f7: +; CHECK: vgmg %v24, 42, 63 +; CHECK: br %r14 + ret <2 x double> <double 0x000000000003fffff, double 0x000000000003fffff> +} + +; Test a doubleword-granularity replicate that has the upper 45 bits set. +define <2 x double> @f8() { +; CHECK-LABEL: f8: +; CHECK: vgmg %v24, 0, 44 +; CHECK: br %r14 + ret <2 x double> <double 0xfffffffffff80000, double 0xfffffffffff80000> +} + +; Test a doubleword-granularity replicate that has middle bits set. +define <2 x double> @f9() { +; CHECK-LABEL: f9: +; CHECK: vgmg %v24, 2, 11 +; CHECK: br %r14 + ret <2 x double> <double 0x3ff0000000000000, double 0x3ff0000000000000> +} + +; Test a doubleword-granularity replicate with a wrap-around mask. +define <2 x double> @f10() { +; CHECK-LABEL: f10: +; CHECK: vgmg %v24, 10, 0 +; CHECK: br %r14 + ret <2 x double> <double 0x803fffffffffffff, double 0x803fffffffffffff> +} diff --git a/test/CodeGen/SystemZ/vec-conv-01.ll b/test/CodeGen/SystemZ/vec-conv-01.ll new file mode 100644 index 000000000000..cbf42c0f533e --- /dev/null +++ b/test/CodeGen/SystemZ/vec-conv-01.ll @@ -0,0 +1,95 @@ +; Test conversions between integer and float elements. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test conversion of f64s to signed i64s. +define <2 x i64> @f1(<2 x double> %doubles) { +; CHECK-LABEL: f1: +; CHECK: vcgdb %v24, %v24, 0, 5 +; CHECK: br %r14 + %dwords = fptosi <2 x double> %doubles to <2 x i64> + ret <2 x i64> %dwords +} + +; Test conversion of f64s to unsigned i64s. +define <2 x i64> @f2(<2 x double> %doubles) { +; CHECK-LABEL: f2: +; CHECK: vclgdb %v24, %v24, 0, 5 +; CHECK: br %r14 + %dwords = fptoui <2 x double> %doubles to <2 x i64> + ret <2 x i64> %dwords +} + +; Test conversion of signed i64s to f64s. +define <2 x double> @f3(<2 x i64> %dwords) { +; CHECK-LABEL: f3: +; CHECK: vcdgb %v24, %v24, 0, 0 +; CHECK: br %r14 + %doubles = sitofp <2 x i64> %dwords to <2 x double> + ret <2 x double> %doubles +} + +; Test conversion of unsigned i64s to f64s. +define <2 x double> @f4(<2 x i64> %dwords) { +; CHECK-LABEL: f4: +; CHECK: vcdlgb %v24, %v24, 0, 0 +; CHECK: br %r14 + %doubles = uitofp <2 x i64> %dwords to <2 x double> + ret <2 x double> %doubles +} + +; Test conversion of f64s to signed i32s, which must compile. +define void @f5(<2 x double> %doubles, <2 x i32> *%ptr) { + %words = fptosi <2 x double> %doubles to <2 x i32> + store <2 x i32> %words, <2 x i32> *%ptr + ret void +} + +; Test conversion of f64s to unsigned i32s, which must compile. +define void @f6(<2 x double> %doubles, <2 x i32> *%ptr) { + %words = fptoui <2 x double> %doubles to <2 x i32> + store <2 x i32> %words, <2 x i32> *%ptr + ret void +} + +; Test conversion of signed i32s to f64s, which must compile. +define <2 x double> @f7(<2 x i32> *%ptr) { + %words = load <2 x i32>, <2 x i32> *%ptr + %doubles = sitofp <2 x i32> %words to <2 x double> + ret <2 x double> %doubles +} + +; Test conversion of unsigned i32s to f64s, which must compile. +define <2 x double> @f8(<2 x i32> *%ptr) { + %words = load <2 x i32>, <2 x i32> *%ptr + %doubles = uitofp <2 x i32> %words to <2 x double> + ret <2 x double> %doubles +} + +; Test conversion of f32s to signed i64s, which must compile. +define <2 x i64> @f9(<2 x float> *%ptr) { + %floats = load <2 x float>, <2 x float> *%ptr + %dwords = fptosi <2 x float> %floats to <2 x i64> + ret <2 x i64> %dwords +} + +; Test conversion of f32s to unsigned i64s, which must compile. +define <2 x i64> @f10(<2 x float> *%ptr) { + %floats = load <2 x float>, <2 x float> *%ptr + %dwords = fptoui <2 x float> %floats to <2 x i64> + ret <2 x i64> %dwords +} + +; Test conversion of signed i64s to f32, which must compile. +define void @f11(<2 x i64> %dwords, <2 x float> *%ptr) { + %floats = sitofp <2 x i64> %dwords to <2 x float> + store <2 x float> %floats, <2 x float> *%ptr + ret void +} + +; Test conversion of unsigned i64s to f32, which must compile. +define void @f12(<2 x i64> %dwords, <2 x float> *%ptr) { + %floats = uitofp <2 x i64> %dwords to <2 x float> + store <2 x float> %floats, <2 x float> *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/vec-conv-02.ll b/test/CodeGen/SystemZ/vec-conv-02.ll new file mode 100644 index 000000000000..ab84389f3c8e --- /dev/null +++ b/test/CodeGen/SystemZ/vec-conv-02.ll @@ -0,0 +1,33 @@ +; Test conversions between different-sized float elements. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test cases where both elements of a v2f64 are converted to f32s. +define void @f1(<2 x double> %val, <2 x float> *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vledb {{%v[0-9]+}}, %v24, 0, 0 +; CHECK: br %r14 + %res = fptrunc <2 x double> %val to <2 x float> + store <2 x float> %res, <2 x float> *%ptr + ret void +} + +; Test conversion of an f64 in a vector register to an f32. +define float @f2(<2 x double> %vec) { +; CHECK-LABEL: f2: +; CHECK: wledb %f0, %v24 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %vec, i32 0 + %ret = fptrunc double %scalar to float + ret float %ret +} + +; Test conversion of an f32 in a vector register to an f64. +define double @f3(<4 x float> %vec) { +; CHECK-LABEL: f3: +; CHECK: wldeb %f0, %v24 +; CHECK: br %r14 + %scalar = extractelement <4 x float> %vec, i32 0 + %ret = fpext float %scalar to double + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-ctlz-01.ll b/test/CodeGen/SystemZ/vec-ctlz-01.ll new file mode 100644 index 000000000000..f6502202ef58 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-ctlz-01.ll @@ -0,0 +1,81 @@ +; Test vector count leading zeros +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 %is_zero_undef) +declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 %is_zero_undef) +declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 %is_zero_undef) +declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 %is_zero_undef) + +define <16 x i8> @f1(<16 x i8> %a) { +; CHECK-LABEL: f1: +; CHECK: vclzb %v24, %v24 +; CHECK: br %r14 + + %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) + ret <16 x i8> %res +} + +define <16 x i8> @f2(<16 x i8> %a) { +; CHECK-LABEL: f2: +; CHECK: vclzb %v24, %v24 +; CHECK: br %r14 + + %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 true) + ret <16 x i8> %res +} + +define <8 x i16> @f3(<8 x i16> %a) { +; CHECK-LABEL: f3: +; CHECK: vclzh %v24, %v24 +; CHECK: br %r14 + + %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) + ret <8 x i16> %res +} + +define <8 x i16> @f4(<8 x i16> %a) { +; CHECK-LABEL: f4: +; CHECK: vclzh %v24, %v24 +; CHECK: br %r14 + + %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 true) + ret <8 x i16> %res +} + +define <4 x i32> @f5(<4 x i32> %a) { +; CHECK-LABEL: f5: +; CHECK: vclzf %v24, %v24 +; CHECK: br %r14 + + %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) + ret <4 x i32> %res +} + +define <4 x i32> @f6(<4 x i32> %a) { +; CHECK-LABEL: f6: +; CHECK: vclzf %v24, %v24 +; CHECK: br %r14 + + %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 true) + ret <4 x i32> %res +} + +define <2 x i64> @f7(<2 x i64> %a) { +; CHECK-LABEL: f7: +; CHECK: vclzg %v24, %v24 +; CHECK: br %r14 + + %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) + ret <2 x i64> %res +} + +define <2 x i64> @f8(<2 x i64> %a) { +; CHECK-LABEL: f8: +; CHECK: vclzg %v24, %v24 +; CHECK: br %r14 + + %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 true) + ret <2 x i64> %res +} + diff --git a/test/CodeGen/SystemZ/vec-ctpop-01.ll b/test/CodeGen/SystemZ/vec-ctpop-01.ll new file mode 100644 index 000000000000..0056af73a2e1 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-ctpop-01.ll @@ -0,0 +1,53 @@ +; Test vector population-count instruction +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) +declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a) +declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a) +declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a) + +define <16 x i8> @f1(<16 x i8> %a) { +; CHECK-LABEL: f1: +; CHECK: vpopct %v24, %v24, 0 +; CHECK: br %r14 + + %popcnt = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) + ret <16 x i8> %popcnt +} + +define <8 x i16> @f2(<8 x i16> %a) { +; CHECK-LABEL: f2: +; CHECK: vpopct [[T1:%v[0-9]+]], %v24, 0 +; CHECK: veslh [[T2:%v[0-9]+]], [[T1]], 8 +; CHECK: vah [[T3:%v[0-9]+]], [[T1]], [[T2]] +; CHECK: vesrlh %v24, [[T3]], 8 +; CHECK: br %r14 + + %popcnt = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a) + ret <8 x i16> %popcnt +} + +define <4 x i32> @f3(<4 x i32> %a) { +; CHECK-LABEL: f3: +; CHECK: vpopct [[T1:%v[0-9]+]], %v24, 0 +; CHECK: vgbm [[T2:%v[0-9]+]], 0 +; CHECK: vsumb %v24, [[T1]], [[T2]] +; CHECK: br %r14 + + %popcnt = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a) + ret <4 x i32> %popcnt +} + +define <2 x i64> @f4(<2 x i64> %a) { +; CHECK-LABEL: f4: +; CHECK: vpopct [[T1:%v[0-9]+]], %v24, 0 +; CHECK: vgbm [[T2:%v[0-9]+]], 0 +; CHECK: vsumb [[T3:%v[0-9]+]], [[T1]], [[T2]] +; CHECK: vsumgf %v24, [[T3]], [[T2]] +; CHECK: br %r14 + + %popcnt = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a) + ret <2 x i64> %popcnt +} + diff --git a/test/CodeGen/SystemZ/vec-cttz-01.ll b/test/CodeGen/SystemZ/vec-cttz-01.ll new file mode 100644 index 000000000000..00a0d21b42fe --- /dev/null +++ b/test/CodeGen/SystemZ/vec-cttz-01.ll @@ -0,0 +1,81 @@ +; Test vector count trailing zeros +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 %is_zero_undef) +declare <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 %is_zero_undef) +declare <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 %is_zero_undef) +declare <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 %is_zero_undef) + +define <16 x i8> @f1(<16 x i8> %a) { +; CHECK-LABEL: f1: +; CHECK: vctzb %v24, %v24 +; CHECK: br %r14 + + %res = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false) + ret <16 x i8> %res +} + +define <16 x i8> @f2(<16 x i8> %a) { +; CHECK-LABEL: f2: +; CHECK: vctzb %v24, %v24 +; CHECK: br %r14 + + %res = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 true) + ret <16 x i8> %res +} + +define <8 x i16> @f3(<8 x i16> %a) { +; CHECK-LABEL: f3: +; CHECK: vctzh %v24, %v24 +; CHECK: br %r14 + + %res = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false) + ret <8 x i16> %res +} + +define <8 x i16> @f4(<8 x i16> %a) { +; CHECK-LABEL: f4: +; CHECK: vctzh %v24, %v24 +; CHECK: br %r14 + + %res = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 true) + ret <8 x i16> %res +} + +define <4 x i32> @f5(<4 x i32> %a) { +; CHECK-LABEL: f5: +; CHECK: vctzf %v24, %v24 +; CHECK: br %r14 + + %res = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false) + ret <4 x i32> %res +} + +define <4 x i32> @f6(<4 x i32> %a) { +; CHECK-LABEL: f6: +; CHECK: vctzf %v24, %v24 +; CHECK: br %r14 + + %res = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true) + ret <4 x i32> %res +} + +define <2 x i64> @f7(<2 x i64> %a) { +; CHECK-LABEL: f7: +; CHECK: vctzg %v24, %v24 +; CHECK: br %r14 + + %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false) + ret <2 x i64> %res +} + +define <2 x i64> @f8(<2 x i64> %a) { +; CHECK-LABEL: f8: +; CHECK: vctzg %v24, %v24 +; CHECK: br %r14 + + %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true) + ret <2 x i64> %res +} + diff --git a/test/CodeGen/SystemZ/vec-div-01.ll b/test/CodeGen/SystemZ/vec-div-01.ll new file mode 100644 index 000000000000..506d40861d35 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-div-01.ll @@ -0,0 +1,83 @@ +; Test vector division. There is no native integer support for this, +; so the integer cases are really a test of the operation legalization code. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 division. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vlvgp [[REG:%v[0-9]+]], +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 0 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 1 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 2 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 3 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 4 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 5 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 6 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 8 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 9 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 10 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 11 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 12 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 13 +; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 14 +; CHECK: br %r14 + %ret = sdiv <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 division. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vlvgp [[REG:%v[0-9]+]], +; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 0 +; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 1 +; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 2 +; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 4 +; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 5 +; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 6 +; CHECK: br %r14 + %ret = sdiv <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 division. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vlvgp [[REG:%v[0-9]+]], +; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 0 +; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 2 +; CHECK: br %r14 + %ret = sdiv <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 division. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vlvgp %v24, +; CHECK: br %r14 + %ret = sdiv <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} + +; Test a v2f64 division. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfddb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = fdiv <2 x double> %val1, %val2 + ret <2 x double> %ret +} + +; Test an f64 division that uses vector registers. +define double @f6(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f6: +; CHECK: wfddb %f0, %v24, %v26 +; CHECK: br %r14 + %scalar1 = extractelement <2 x double> %val1, i32 0 + %scalar2 = extractelement <2 x double> %val2, i32 0 + %ret = fdiv double %scalar1, %scalar2 + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-extract-01.ll b/test/CodeGen/SystemZ/vec-extract-01.ll new file mode 100644 index 000000000000..549392ffd64d --- /dev/null +++ b/test/CodeGen/SystemZ/vec-extract-01.ll @@ -0,0 +1,13 @@ +; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a memory copy of a v2i32 (via the constant pool). +define void @f1(<2 x i32> *%dest) { +; CHECK-LABEL: f1: +; CHECK: lgrl [[REG:%r[0-5]]], {{[._A-Za-z0-9]}} +; CHECK: stg [[REG]], 0(%r2) +; CHECK: br %r14 + store <2 x i32> <i32 1000000, i32 99999>, <2 x i32> *%dest + ret void +} diff --git a/test/CodeGen/SystemZ/vec-extract-02.ll b/test/CodeGen/SystemZ/vec-extract-02.ll new file mode 100644 index 000000000000..c91e852fcf45 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-extract-02.ll @@ -0,0 +1,15 @@ +; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a case where a vector extraction can be simplified to a scalar load. +; The index must be extended from i32 to i64. +define i32 @f1(<4 x i32> *%ptr, i32 %index) { +; CHECK-LABEL: f1: +; CHECK: risbg {{%r[0-5]}}, %r3, 30, 189, 2 +; CHECK: l %r2, +; CHECK: br %r14 + %vec = load <4 x i32>, <4 x i32> *%ptr + %res = extractelement <4 x i32> %vec, i32 %index + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/vec-intrinsics.ll b/test/CodeGen/SystemZ/vec-intrinsics.ll new file mode 100644 index 000000000000..55527787da4c --- /dev/null +++ b/test/CodeGen/SystemZ/vec-intrinsics.ll @@ -0,0 +1,3335 @@ +; Test vector intrinsics. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare i32 @llvm.s390.lcbb(i8 *, i32) +declare <16 x i8> @llvm.s390.vlbb(i8 *, i32) +declare <16 x i8> @llvm.s390.vll(i32, i8 *) +declare <2 x i64> @llvm.s390.vpdi(<2 x i64>, <2 x i64>, i32) +declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vpksh(<8 x i16>, <8 x i16>) +declare <8 x i16> @llvm.s390.vpksf(<4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.s390.vpksg(<2 x i64>, <2 x i64>) +declare {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16>, <8 x i16>) +declare {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32>, <4 x i32>) +declare {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64>, <2 x i64>) +declare <16 x i8> @llvm.s390.vpklsh(<8 x i16>, <8 x i16>) +declare <8 x i16> @llvm.s390.vpklsf(<4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.s390.vpklsg(<2 x i64>, <2 x i64>) +declare {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16>, <8 x i16>) +declare {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32>, <4 x i32>) +declare {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64>, <2 x i64>) +declare void @llvm.s390.vstl(<16 x i8>, i32, i8 *) +declare <8 x i16> @llvm.s390.vuphb(<16 x i8>) +declare <4 x i32> @llvm.s390.vuphh(<8 x i16>) +declare <2 x i64> @llvm.s390.vuphf(<4 x i32>) +declare <8 x i16> @llvm.s390.vuplhb(<16 x i8>) +declare <4 x i32> @llvm.s390.vuplhh(<8 x i16>) +declare <2 x i64> @llvm.s390.vuplhf(<4 x i32>) +declare <8 x i16> @llvm.s390.vuplb(<16 x i8>) +declare <4 x i32> @llvm.s390.vuplhw(<8 x i16>) +declare <2 x i64> @llvm.s390.vuplf(<4 x i32>) +declare <8 x i16> @llvm.s390.vupllb(<16 x i8>) +declare <4 x i32> @llvm.s390.vupllh(<8 x i16>) +declare <2 x i64> @llvm.s390.vupllf(<4 x i32>) +declare <16 x i8> @llvm.s390.vaccb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vacch(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vaccf(<4 x i32>, <4 x i32>) +declare <2 x i64> @llvm.s390.vaccg(<2 x i64>, <2 x i64>) +declare <16 x i8> @llvm.s390.vaq(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vacq(<16 x i8>, <16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vaccq(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vacccq(<16 x i8>, <16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vavgb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vavgh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vavgf(<4 x i32>, <4 x i32>) +declare <2 x i64> @llvm.s390.vavgg(<2 x i64>, <2 x i64>) +declare <16 x i8> @llvm.s390.vavglb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vavglh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vavglf(<4 x i32>, <4 x i32>) +declare <2 x i64> @llvm.s390.vavglg(<2 x i64>, <2 x i64>) +declare <4 x i32> @llvm.s390.vcksm(<4 x i32>, <4 x i32>) +declare <8 x i16> @llvm.s390.vgfmb(<16 x i8>, <16 x i8>) +declare <4 x i32> @llvm.s390.vgfmh(<8 x i16>, <8 x i16>) +declare <2 x i64> @llvm.s390.vgfmf(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vgfmg(<2 x i64>, <2 x i64>) +declare <8 x i16> @llvm.s390.vgfmab(<16 x i8>, <16 x i8>, <8 x i16>) +declare <4 x i32> @llvm.s390.vgfmah(<8 x i16>, <8 x i16>, <4 x i32>) +declare <2 x i64> @llvm.s390.vgfmaf(<4 x i32>, <4 x i32>, <2 x i64>) +declare <16 x i8> @llvm.s390.vgfmag(<2 x i64>, <2 x i64>, <16 x i8>) +declare <16 x i8> @llvm.s390.vmahb(<16 x i8>, <16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vmahh(<8 x i16>, <8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmahf(<4 x i32>, <4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vmalhb(<16 x i8>, <16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vmalhh(<8 x i16>, <8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmalhf(<4 x i32>, <4 x i32>, <4 x i32>) +declare <8 x i16> @llvm.s390.vmaeb(<16 x i8>, <16 x i8>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmaeh(<8 x i16>, <8 x i16>, <4 x i32>) +declare <2 x i64> @llvm.s390.vmaef(<4 x i32>, <4 x i32>, <2 x i64>) +declare <8 x i16> @llvm.s390.vmaleb(<16 x i8>, <16 x i8>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmaleh(<8 x i16>, <8 x i16>, <4 x i32>) +declare <2 x i64> @llvm.s390.vmalef(<4 x i32>, <4 x i32>, <2 x i64>) +declare <8 x i16> @llvm.s390.vmaob(<16 x i8>, <16 x i8>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmaoh(<8 x i16>, <8 x i16>, <4 x i32>) +declare <2 x i64> @llvm.s390.vmaof(<4 x i32>, <4 x i32>, <2 x i64>) +declare <8 x i16> @llvm.s390.vmalob(<16 x i8>, <16 x i8>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmaloh(<8 x i16>, <8 x i16>, <4 x i32>) +declare <2 x i64> @llvm.s390.vmalof(<4 x i32>, <4 x i32>, <2 x i64>) +declare <16 x i8> @llvm.s390.vmhb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vmhh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmhf(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vmlhb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vmlhh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vmlhf(<4 x i32>, <4 x i32>) +declare <8 x i16> @llvm.s390.vmeb(<16 x i8>, <16 x i8>) +declare <4 x i32> @llvm.s390.vmeh(<8 x i16>, <8 x i16>) +declare <2 x i64> @llvm.s390.vmef(<4 x i32>, <4 x i32>) +declare <8 x i16> @llvm.s390.vmleb(<16 x i8>, <16 x i8>) +declare <4 x i32> @llvm.s390.vmleh(<8 x i16>, <8 x i16>) +declare <2 x i64> @llvm.s390.vmlef(<4 x i32>, <4 x i32>) +declare <8 x i16> @llvm.s390.vmob(<16 x i8>, <16 x i8>) +declare <4 x i32> @llvm.s390.vmoh(<8 x i16>, <8 x i16>) +declare <2 x i64> @llvm.s390.vmof(<4 x i32>, <4 x i32>) +declare <8 x i16> @llvm.s390.vmlob(<16 x i8>, <16 x i8>) +declare <4 x i32> @llvm.s390.vmloh(<8 x i16>, <8 x i16>) +declare <2 x i64> @llvm.s390.vmlof(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.verllvb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.verllvh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.verllvf(<4 x i32>, <4 x i32>) +declare <2 x i64> @llvm.s390.verllvg(<2 x i64>, <2 x i64>) +declare <16 x i8> @llvm.s390.verllb(<16 x i8>, i32) +declare <8 x i16> @llvm.s390.verllh(<8 x i16>, i32) +declare <4 x i32> @llvm.s390.verllf(<4 x i32>, i32) +declare <2 x i64> @llvm.s390.verllg(<2 x i64>, i32) +declare <16 x i8> @llvm.s390.verimb(<16 x i8>, <16 x i8>, <16 x i8>, i32) +declare <8 x i16> @llvm.s390.verimh(<8 x i16>, <8 x i16>, <8 x i16>, i32) +declare <4 x i32> @llvm.s390.verimf(<4 x i32>, <4 x i32>, <4 x i32>, i32) +declare <2 x i64> @llvm.s390.verimg(<2 x i64>, <2 x i64>, <2 x i64>, i32) +declare <16 x i8> @llvm.s390.vsl(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vslb(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vsra(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vsrab(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vsrl(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vsrlb(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vsldb(<16 x i8>, <16 x i8>, i32) +declare <16 x i8> @llvm.s390.vscbib(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vscbih(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vscbif(<4 x i32>, <4 x i32>) +declare <2 x i64> @llvm.s390.vscbig(<2 x i64>, <2 x i64>) +declare <16 x i8> @llvm.s390.vsq(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vsbiq(<16 x i8>, <16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vscbiq(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vsbcbiq(<16 x i8>, <16 x i8>, <16 x i8>) +declare <4 x i32> @llvm.s390.vsumb(<16 x i8>, <16 x i8>) +declare <4 x i32> @llvm.s390.vsumh(<8 x i16>, <8 x i16>) +declare <2 x i64> @llvm.s390.vsumgh(<8 x i16>, <8 x i16>) +declare <2 x i64> @llvm.s390.vsumgf(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vsumqf(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vsumqg(<2 x i64>, <2 x i64>) +declare i32 @llvm.s390.vtm(<16 x i8>, <16 x i8>) +declare {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8>, <16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16>, <8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32>, <4 x i32>) +declare {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64>, <2 x i64>) +declare {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8>, <16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16>, <8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32>, <4 x i32>) +declare {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64>, <2 x i64>) +declare {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8>, <16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16>, <8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32>, <4 x i32>) +declare {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64>, <2 x i64>) +declare <16 x i8> @llvm.s390.vfaeb(<16 x i8>, <16 x i8>, i32) +declare <8 x i16> @llvm.s390.vfaeh(<8 x i16>, <8 x i16>, i32) +declare <4 x i32> @llvm.s390.vfaef(<4 x i32>, <4 x i32>, i32) +declare {<16 x i8>, i32} @llvm.s390.vfaebs(<16 x i8>, <16 x i8>, i32) +declare {<8 x i16>, i32} @llvm.s390.vfaehs(<8 x i16>, <8 x i16>, i32) +declare {<4 x i32>, i32} @llvm.s390.vfaefs(<4 x i32>, <4 x i32>, i32) +declare <16 x i8> @llvm.s390.vfaezb(<16 x i8>, <16 x i8>, i32) +declare <8 x i16> @llvm.s390.vfaezh(<8 x i16>, <8 x i16>, i32) +declare <4 x i32> @llvm.s390.vfaezf(<4 x i32>, <4 x i32>, i32) +declare {<16 x i8>, i32} @llvm.s390.vfaezbs(<16 x i8>, <16 x i8>, i32) +declare {<8 x i16>, i32} @llvm.s390.vfaezhs(<8 x i16>, <8 x i16>, i32) +declare {<4 x i32>, i32} @llvm.s390.vfaezfs(<4 x i32>, <4 x i32>, i32) +declare <16 x i8> @llvm.s390.vfeeb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vfeeh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vfeef(<4 x i32>, <4 x i32>) +declare {<16 x i8>, i32} @llvm.s390.vfeebs(<16 x i8>, <16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vfeehs(<8 x i16>, <8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vfeefs(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vfeezb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vfeezh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vfeezf(<4 x i32>, <4 x i32>) +declare {<16 x i8>, i32} @llvm.s390.vfeezbs(<16 x i8>, <16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vfeezhs(<8 x i16>, <8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vfeezfs(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vfeneb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vfeneh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vfenef(<4 x i32>, <4 x i32>) +declare {<16 x i8>, i32} @llvm.s390.vfenebs(<16 x i8>, <16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vfenehs(<8 x i16>, <8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vfenefs(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vfenezb(<16 x i8>, <16 x i8>) +declare <8 x i16> @llvm.s390.vfenezh(<8 x i16>, <8 x i16>) +declare <4 x i32> @llvm.s390.vfenezf(<4 x i32>, <4 x i32>) +declare {<16 x i8>, i32} @llvm.s390.vfenezbs(<16 x i8>, <16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vfenezhs(<8 x i16>, <8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vfenezfs(<4 x i32>, <4 x i32>) +declare <16 x i8> @llvm.s390.vistrb(<16 x i8>) +declare <8 x i16> @llvm.s390.vistrh(<8 x i16>) +declare <4 x i32> @llvm.s390.vistrf(<4 x i32>) +declare {<16 x i8>, i32} @llvm.s390.vistrbs(<16 x i8>) +declare {<8 x i16>, i32} @llvm.s390.vistrhs(<8 x i16>) +declare {<4 x i32>, i32} @llvm.s390.vistrfs(<4 x i32>) +declare <16 x i8> @llvm.s390.vstrcb(<16 x i8>, <16 x i8>, <16 x i8>, i32) +declare <8 x i16> @llvm.s390.vstrch(<8 x i16>, <8 x i16>, <8 x i16>, i32) +declare <4 x i32> @llvm.s390.vstrcf(<4 x i32>, <4 x i32>, <4 x i32>, i32) +declare {<16 x i8>, i32} @llvm.s390.vstrcbs(<16 x i8>, <16 x i8>, <16 x i8>, + i32) +declare {<8 x i16>, i32} @llvm.s390.vstrchs(<8 x i16>, <8 x i16>, <8 x i16>, + i32) +declare {<4 x i32>, i32} @llvm.s390.vstrcfs(<4 x i32>, <4 x i32>, <4 x i32>, + i32) +declare <16 x i8> @llvm.s390.vstrczb(<16 x i8>, <16 x i8>, <16 x i8>, i32) +declare <8 x i16> @llvm.s390.vstrczh(<8 x i16>, <8 x i16>, <8 x i16>, i32) +declare <4 x i32> @llvm.s390.vstrczf(<4 x i32>, <4 x i32>, <4 x i32>, i32) +declare {<16 x i8>, i32} @llvm.s390.vstrczbs(<16 x i8>, <16 x i8>, <16 x i8>, + i32) +declare {<8 x i16>, i32} @llvm.s390.vstrczhs(<8 x i16>, <8 x i16>, <8 x i16>, + i32) +declare {<4 x i32>, i32} @llvm.s390.vstrczfs(<4 x i32>, <4 x i32>, <4 x i32>, + i32) +declare {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double>, <2 x double>) +declare {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double>, <2 x double>) +declare {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double>, <2 x double>) +declare {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double>, i32) +declare <2 x double> @llvm.s390.vfidb(<2 x double>, i32, i32) + +; LCBB with the lowest M3 operand. +define i32 @test_lcbb1(i8 *%ptr) { +; CHECK-LABEL: test_lcbb1: +; CHECK: lcbb %r2, 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 0) + ret i32 %res +} + +; LCBB with the highest M3 operand. +define i32 @test_lcbb2(i8 *%ptr) { +; CHECK-LABEL: test_lcbb2: +; CHECK: lcbb %r2, 0(%r2), 15 +; CHECK: br %r14 + %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 15) + ret i32 %res +} + +; LCBB with a displacement and index. +define i32 @test_lcbb3(i8 *%base, i64 %index) { +; CHECK-LABEL: test_lcbb3: +; CHECK: lcbb %r2, 4095({{%r2,%r3|%r3,%r2}}), 4 +; CHECK: br %r14 + %add = add i64 %index, 4095 + %ptr = getelementptr i8, i8 *%base, i64 %add + %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 4) + ret i32 %res +} + +; LCBB with an out-of-range displacement. +define i32 @test_lcbb4(i8 *%base) { +; CHECK-LABEL: test_lcbb4: +; CHECK: lcbb %r2, 0({{%r[1-5]}}), 5 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 5) + ret i32 %res +} + +; VLBB with the lowest M3 operand. +define <16 x i8> @test_vlbb1(i8 *%ptr) { +; CHECK-LABEL: test_vlbb1: +; CHECK: vlbb %v24, 0(%r2), 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 0) + ret <16 x i8> %res +} + +; VLBB with the highest M3 operand. +define <16 x i8> @test_vlbb2(i8 *%ptr) { +; CHECK-LABEL: test_vlbb2: +; CHECK: vlbb %v24, 0(%r2), 15 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 15) + ret <16 x i8> %res +} + +; VLBB with a displacement and index. +define <16 x i8> @test_vlbb3(i8 *%base, i64 %index) { +; CHECK-LABEL: test_vlbb3: +; CHECK: vlbb %v24, 4095({{%r2,%r3|%r3,%r2}}), 4 +; CHECK: br %r14 + %add = add i64 %index, 4095 + %ptr = getelementptr i8, i8 *%base, i64 %add + %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 4) + ret <16 x i8> %res +} + +; VLBB with an out-of-range displacement. +define <16 x i8> @test_vlbb4(i8 *%base) { +; CHECK-LABEL: test_vlbb4: +; CHECK: vlbb %v24, 0({{%r[1-5]}}), 5 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 5) + ret <16 x i8> %res +} + +; VLL with the lowest in-range displacement. +define <16 x i8> @test_vll1(i8 *%ptr, i32 %length) { +; CHECK-LABEL: test_vll1: +; CHECK: vll %v24, %r3, 0(%r2) +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLL with the highest in-range displacement. +define <16 x i8> @test_vll2(i8 *%base, i32 %length) { +; CHECK-LABEL: test_vll2: +; CHECK: vll %v24, %r3, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLL with an out-of-range displacementa. +define <16 x i8> @test_vll3(i8 *%base, i32 %length) { +; CHECK-LABEL: test_vll3: +; CHECK: vll %v24, %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; Check that VLL doesn't allow an index. +define <16 x i8> @test_vll4(i8 *%base, i64 %index, i32 %length) { +; CHECK-LABEL: test_vll4: +; CHECK: vll %v24, %r4, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VPDI taking element 0 from each half. +define <2 x i64> @test_vpdi1(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vpdi1: +; CHECK: vpdi %v24, %v24, %v26, 0 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 0) + ret <2 x i64> %res +} + +; VPDI taking element 1 from each half. +define <2 x i64> @test_vpdi2(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vpdi2: +; CHECK: vpdi %v24, %v24, %v26, 10 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 10) + ret <2 x i64> %res +} + +; VPERM. +define <16 x i8> @test_vperm(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vperm: +; CHECK: vperm %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vperm(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VPKSH. +define <16 x i8> @test_vpksh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vpksh: +; CHECK: vpksh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vpksh(<8 x i16> %a, <8 x i16> %b) + ret <16 x i8> %res +} + +; VPKSF. +define <8 x i16> @test_vpksf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vpksf: +; CHECK: vpksf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vpksf(<4 x i32> %a, <4 x i32> %b) + ret <8 x i16> %res +} + +; VPKSG. +define <4 x i32> @test_vpksg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vpksg: +; CHECK: vpksg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vpksg(<2 x i64> %a, <2 x i64> %b) + ret <4 x i32> %res +} + +; VPKSHS with no processing of the result. +define <16 x i8> @test_vpkshs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vpkshs: +; CHECK: vpkshs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VPKSHS, storing to %ptr if all values were saturated. +define <16 x i8> @test_vpkshs_all_store(<8 x i16> %a, <8 x i16> %b, i32 *%ptr) { +; CHECK-LABEL: test_vpkshs_all_store: +; CHECK: vpkshs %v24, %v24, %v26 +; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp uge i32 %cc, 3 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <16 x i8> %res +} + +; VPKSFS with no processing of the result. +define <8 x i16> @test_vpksfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vpksfs: +; CHECK: vpksfs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VPKSFS, storing to %ptr if any values were saturated. +define <8 x i16> @test_vpksfs_any_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) { +; CHECK-LABEL: test_vpksfs_any_store: +; CHECK: vpksfs %v24, %v24, %v26 +; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp ugt i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <8 x i16> %res +} + +; VPKSGS with no processing of the result. +define <4 x i32> @test_vpksgs(<2 x i64> %a, <2 x i64> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vpksgs: +; CHECK: vpksgs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VPKSGS, storing to %ptr if no elements were saturated +define <4 x i32> @test_vpksgs_none_store(<2 x i64> %a, <2 x i64> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vpksgs_none_store: +; CHECK: vpksgs %v24, %v24, %v26 +; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp sle i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <4 x i32> %res +} + +; VPKLSH. +define <16 x i8> @test_vpklsh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vpklsh: +; CHECK: vpklsh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vpklsh(<8 x i16> %a, <8 x i16> %b) + ret <16 x i8> %res +} + +; VPKLSF. +define <8 x i16> @test_vpklsf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vpklsf: +; CHECK: vpklsf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vpklsf(<4 x i32> %a, <4 x i32> %b) + ret <8 x i16> %res +} + +; VPKLSG. +define <4 x i32> @test_vpklsg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vpklsg: +; CHECK: vpklsg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> %a, <2 x i64> %b) + ret <4 x i32> %res +} + +; VPKLSHS with no processing of the result. +define <16 x i8> @test_vpklshs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vpklshs: +; CHECK: vpklshs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VPKLSHS, storing to %ptr if all values were saturated. +define <16 x i8> @test_vpklshs_all_store(<8 x i16> %a, <8 x i16> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vpklshs_all_store: +; CHECK: vpklshs %v24, %v24, %v26 +; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp eq i32 %cc, 3 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <16 x i8> %res +} + +; VPKLSFS with no processing of the result. +define <8 x i16> @test_vpklsfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vpklsfs: +; CHECK: vpklsfs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VPKLSFS, storing to %ptr if any values were saturated. +define <8 x i16> @test_vpklsfs_any_store(<4 x i32> %a, <4 x i32> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vpklsfs_any_store: +; CHECK: vpklsfs %v24, %v24, %v26 +; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp ne i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <8 x i16> %res +} + +; VPKLSGS with no processing of the result. +define <4 x i32> @test_vpklsgs(<2 x i64> %a, <2 x i64> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vpklsgs: +; CHECK: vpklsgs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VPKLSGS, storing to %ptr if no elements were saturated +define <4 x i32> @test_vpklsgs_none_store(<2 x i64> %a, <2 x i64> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vpklsgs_none_store: +; CHECK: vpklsgs %v24, %v24, %v26 +; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp eq i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <4 x i32> %res +} + +; VSTL with the lowest in-range displacement. +define void @test_vstl1(<16 x i8> %vec, i8 *%ptr, i32 %length) { +; CHECK-LABEL: test_vstl1: +; CHECK: vstl %v24, %r3, 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTL with the highest in-range displacement. +define void @test_vstl2(<16 x i8> %vec, i8 *%base, i32 %length) { +; CHECK-LABEL: test_vstl2: +; CHECK: vstl %v24, %r3, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTL with an out-of-range displacement. +define void @test_vstl3(<16 x i8> %vec, i8 *%base, i32 %length) { +; CHECK-LABEL: test_vstl3: +; CHECK: vstl %v24, %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; Check that VSTL doesn't allow an index. +define void @test_vstl4(<16 x i8> %vec, i8 *%base, i64 %index, i32 %length) { +; CHECK-LABEL: test_vstl4: +; CHECK: vstl %v24, %r4, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VUPHB. +define <8 x i16> @test_vuphb(<16 x i8> %a) { +; CHECK-LABEL: test_vuphb: +; CHECK: vuphb %v24, %v24 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vuphb(<16 x i8> %a) + ret <8 x i16> %res +} + +; VUPHH. +define <4 x i32> @test_vuphh(<8 x i16> %a) { +; CHECK-LABEL: test_vuphh: +; CHECK: vuphh %v24, %v24 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vuphh(<8 x i16> %a) + ret <4 x i32> %res +} + +; VUPHF. +define <2 x i64> @test_vuphf(<4 x i32> %a) { +; CHECK-LABEL: test_vuphf: +; CHECK: vuphf %v24, %v24 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vuphf(<4 x i32> %a) + ret <2 x i64> %res +} + +; VUPLHB. +define <8 x i16> @test_vuplhb(<16 x i8> %a) { +; CHECK-LABEL: test_vuplhb: +; CHECK: vuplhb %v24, %v24 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vuplhb(<16 x i8> %a) + ret <8 x i16> %res +} + +; VUPLHH. +define <4 x i32> @test_vuplhh(<8 x i16> %a) { +; CHECK-LABEL: test_vuplhh: +; CHECK: vuplhh %v24, %v24 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vuplhh(<8 x i16> %a) + ret <4 x i32> %res +} + +; VUPLHF. +define <2 x i64> @test_vuplhf(<4 x i32> %a) { +; CHECK-LABEL: test_vuplhf: +; CHECK: vuplhf %v24, %v24 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vuplhf(<4 x i32> %a) + ret <2 x i64> %res +} + +; VUPLB. +define <8 x i16> @test_vuplb(<16 x i8> %a) { +; CHECK-LABEL: test_vuplb: +; CHECK: vuplb %v24, %v24 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vuplb(<16 x i8> %a) + ret <8 x i16> %res +} + +; VUPLHW. +define <4 x i32> @test_vuplhw(<8 x i16> %a) { +; CHECK-LABEL: test_vuplhw: +; CHECK: vuplhw %v24, %v24 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vuplhw(<8 x i16> %a) + ret <4 x i32> %res +} + +; VUPLF. +define <2 x i64> @test_vuplf(<4 x i32> %a) { +; CHECK-LABEL: test_vuplf: +; CHECK: vuplf %v24, %v24 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vuplf(<4 x i32> %a) + ret <2 x i64> %res +} + +; VUPLLB. +define <8 x i16> @test_vupllb(<16 x i8> %a) { +; CHECK-LABEL: test_vupllb: +; CHECK: vupllb %v24, %v24 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vupllb(<16 x i8> %a) + ret <8 x i16> %res +} + +; VUPLLH. +define <4 x i32> @test_vupllh(<8 x i16> %a) { +; CHECK-LABEL: test_vupllh: +; CHECK: vupllh %v24, %v24 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vupllh(<8 x i16> %a) + ret <4 x i32> %res +} + +; VUPLLF. +define <2 x i64> @test_vupllf(<4 x i32> %a) { +; CHECK-LABEL: test_vupllf: +; CHECK: vupllf %v24, %v24 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vupllf(<4 x i32> %a) + ret <2 x i64> %res +} + +; VACCB. +define <16 x i8> @test_vaccb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vaccb: +; CHECK: vaccb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vaccb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VACCH. +define <8 x i16> @test_vacch(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vacch: +; CHECK: vacch %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vacch(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VACCF. +define <4 x i32> @test_vaccf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vaccf: +; CHECK: vaccf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vaccf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VACCG. +define <2 x i64> @test_vaccg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vaccg: +; CHECK: vaccg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vaccg(<2 x i64> %a, <2 x i64> %b) + ret <2 x i64> %res +} + +; VAQ. +define <16 x i8> @test_vaq(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vaq: +; CHECK: vaq %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vaq(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VACQ. +define <16 x i8> @test_vacq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vacq: +; CHECK: vacq %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vacq(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VACCQ. +define <16 x i8> @test_vaccq(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vaccq: +; CHECK: vaccq %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vaccq(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VACCCQ. +define <16 x i8> @test_vacccq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vacccq: +; CHECK: vacccq %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vacccq(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VAVGB. +define <16 x i8> @test_vavgb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vavgb: +; CHECK: vavgb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vavgb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VAVGH. +define <8 x i16> @test_vavgh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vavgh: +; CHECK: vavgh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vavgh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VAVGF. +define <4 x i32> @test_vavgf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vavgf: +; CHECK: vavgf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vavgf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VAVGG. +define <2 x i64> @test_vavgg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vavgg: +; CHECK: vavgg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vavgg(<2 x i64> %a, <2 x i64> %b) + ret <2 x i64> %res +} + +; VAVGLB. +define <16 x i8> @test_vavglb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vavglb: +; CHECK: vavglb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vavglb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VAVGLH. +define <8 x i16> @test_vavglh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vavglh: +; CHECK: vavglh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vavglh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VAVGLF. +define <4 x i32> @test_vavglf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vavglf: +; CHECK: vavglf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vavglf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VAVGLG. +define <2 x i64> @test_vavglg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vavglg: +; CHECK: vavglg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vavglg(<2 x i64> %a, <2 x i64> %b) + ret <2 x i64> %res +} + +; VCKSM. +define <4 x i32> @test_vcksm(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vcksm: +; CHECK: vcksm %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vcksm(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VGFMB. +define <8 x i16> @test_vgfmb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vgfmb: +; CHECK: vgfmb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vgfmb(<16 x i8> %a, <16 x i8> %b) + ret <8 x i16> %res +} + +; VGFMH. +define <4 x i32> @test_vgfmh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vgfmh: +; CHECK: vgfmh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vgfmh(<8 x i16> %a, <8 x i16> %b) + ret <4 x i32> %res +} + +; VGFMF. +define <2 x i64> @test_vgfmf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vgfmf: +; CHECK: vgfmf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vgfmf(<4 x i32> %a, <4 x i32> %b) + ret <2 x i64> %res +} + +; VGFMG. +define <16 x i8> @test_vgfmg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vgfmg: +; CHECK: vgfmg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vgfmg(<2 x i64> %a, <2 x i64> %b) + ret <16 x i8> %res +} + +; VGFMAB. +define <8 x i16> @test_vgfmab(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vgfmab: +; CHECK: vgfmab %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vgfmab(<16 x i8> %a, <16 x i8> %b, + <8 x i16> %c) + ret <8 x i16> %res +} + +; VGFMAH. +define <4 x i32> @test_vgfmah(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vgfmah: +; CHECK: vgfmah %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vgfmah(<8 x i16> %a, <8 x i16> %b, + <4 x i32> %c) + ret <4 x i32> %res +} + +; VGFMAF. +define <2 x i64> @test_vgfmaf(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { +; CHECK-LABEL: test_vgfmaf: +; CHECK: vgfmaf %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vgfmaf(<4 x i32> %a, <4 x i32> %b, + <2 x i64> %c) + ret <2 x i64> %res +} + +; VGFMAG. +define <16 x i8> @test_vgfmag(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vgfmag: +; CHECK: vgfmag %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vgfmag(<2 x i64> %a, <2 x i64> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VMAHB. +define <16 x i8> @test_vmahb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vmahb: +; CHECK: vmahb %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmahb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VMAHH. +define <8 x i16> @test_vmahh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vmahh: +; CHECK: vmahh %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmahh(<8 x i16> %a, <8 x i16> %b, + <8 x i16> %c) + ret <8 x i16> %res +} + +; VMAHF. +define <4 x i32> @test_vmahf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vmahf: +; CHECK: vmahf %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmahf(<4 x i32> %a, <4 x i32> %b, + <4 x i32> %c) + ret <4 x i32> %res +} + +; VMALHB. +define <16 x i8> @test_vmalhb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vmalhb: +; CHECK: vmalhb %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmalhb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VMALHH. +define <8 x i16> @test_vmalhh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vmalhh: +; CHECK: vmalhh %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmalhh(<8 x i16> %a, <8 x i16> %b, + <8 x i16> %c) + ret <8 x i16> %res +} + +; VMALHF. +define <4 x i32> @test_vmalhf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vmalhf: +; CHECK: vmalhf %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmalhf(<4 x i32> %a, <4 x i32> %b, + <4 x i32> %c) + ret <4 x i32> %res +} + +; VMAEB. +define <8 x i16> @test_vmaeb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vmaeb: +; CHECK: vmaeb %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmaeb(<16 x i8> %a, <16 x i8> %b, + <8 x i16> %c) + ret <8 x i16> %res +} + +; VMAEH. +define <4 x i32> @test_vmaeh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vmaeh: +; CHECK: vmaeh %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmaeh(<8 x i16> %a, <8 x i16> %b, + <4 x i32> %c) + ret <4 x i32> %res +} + +; VMAEF. +define <2 x i64> @test_vmaef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { +; CHECK-LABEL: test_vmaef: +; CHECK: vmaef %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmaef(<4 x i32> %a, <4 x i32> %b, + <2 x i64> %c) + ret <2 x i64> %res +} + +; VMALEB. +define <8 x i16> @test_vmaleb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vmaleb: +; CHECK: vmaleb %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmaleb(<16 x i8> %a, <16 x i8> %b, + <8 x i16> %c) + ret <8 x i16> %res +} + +; VMALEH. +define <4 x i32> @test_vmaleh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vmaleh: +; CHECK: vmaleh %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmaleh(<8 x i16> %a, <8 x i16> %b, + <4 x i32> %c) + ret <4 x i32> %res +} + +; VMALEF. +define <2 x i64> @test_vmalef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { +; CHECK-LABEL: test_vmalef: +; CHECK: vmalef %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmalef(<4 x i32> %a, <4 x i32> %b, + <2 x i64> %c) + ret <2 x i64> %res +} + +; VMAOB. +define <8 x i16> @test_vmaob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vmaob: +; CHECK: vmaob %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmaob(<16 x i8> %a, <16 x i8> %b, + <8 x i16> %c) + ret <8 x i16> %res +} + +; VMAOH. +define <4 x i32> @test_vmaoh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vmaoh: +; CHECK: vmaoh %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmaoh(<8 x i16> %a, <8 x i16> %b, + <4 x i32> %c) + ret <4 x i32> %res +} + +; VMAOF. +define <2 x i64> @test_vmaof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { +; CHECK-LABEL: test_vmaof: +; CHECK: vmaof %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmaof(<4 x i32> %a, <4 x i32> %b, + <2 x i64> %c) + ret <2 x i64> %res +} + +; VMALOB. +define <8 x i16> @test_vmalob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vmalob: +; CHECK: vmalob %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmalob(<16 x i8> %a, <16 x i8> %b, + <8 x i16> %c) + ret <8 x i16> %res +} + +; VMALOH. +define <4 x i32> @test_vmaloh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vmaloh: +; CHECK: vmaloh %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmaloh(<8 x i16> %a, <8 x i16> %b, + <4 x i32> %c) + ret <4 x i32> %res +} + +; VMALOF. +define <2 x i64> @test_vmalof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { +; CHECK-LABEL: test_vmalof: +; CHECK: vmalof %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmalof(<4 x i32> %a, <4 x i32> %b, + <2 x i64> %c) + ret <2 x i64> %res +} + +; VMHB. +define <16 x i8> @test_vmhb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vmhb: +; CHECK: vmhb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmhb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VMHH. +define <8 x i16> @test_vmhh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vmhh: +; CHECK: vmhh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmhh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VMHF. +define <4 x i32> @test_vmhf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vmhf: +; CHECK: vmhf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmhf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VMLHB. +define <16 x i8> @test_vmlhb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vmlhb: +; CHECK: vmlhb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmlhb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VMLHH. +define <8 x i16> @test_vmlhh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vmlhh: +; CHECK: vmlhh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmlhh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VMLHF. +define <4 x i32> @test_vmlhf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vmlhf: +; CHECK: vmlhf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmlhf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VMEB. +define <8 x i16> @test_vmeb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vmeb: +; CHECK: vmeb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmeb(<16 x i8> %a, <16 x i8> %b) + ret <8 x i16> %res +} + +; VMEH. +define <4 x i32> @test_vmeh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vmeh: +; CHECK: vmeh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmeh(<8 x i16> %a, <8 x i16> %b) + ret <4 x i32> %res +} + +; VMEF. +define <2 x i64> @test_vmef(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vmef: +; CHECK: vmef %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmef(<4 x i32> %a, <4 x i32> %b) + ret <2 x i64> %res +} + +; VMLEB. +define <8 x i16> @test_vmleb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vmleb: +; CHECK: vmleb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmleb(<16 x i8> %a, <16 x i8> %b) + ret <8 x i16> %res +} + +; VMLEH. +define <4 x i32> @test_vmleh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vmleh: +; CHECK: vmleh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmleh(<8 x i16> %a, <8 x i16> %b) + ret <4 x i32> %res +} + +; VMLEF. +define <2 x i64> @test_vmlef(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vmlef: +; CHECK: vmlef %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmlef(<4 x i32> %a, <4 x i32> %b) + ret <2 x i64> %res +} + +; VMOB. +define <8 x i16> @test_vmob(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vmob: +; CHECK: vmob %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmob(<16 x i8> %a, <16 x i8> %b) + ret <8 x i16> %res +} + +; VMOH. +define <4 x i32> @test_vmoh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vmoh: +; CHECK: vmoh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmoh(<8 x i16> %a, <8 x i16> %b) + ret <4 x i32> %res +} + +; VMOF. +define <2 x i64> @test_vmof(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vmof: +; CHECK: vmof %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmof(<4 x i32> %a, <4 x i32> %b) + ret <2 x i64> %res +} + +; VMLOB. +define <8 x i16> @test_vmlob(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vmlob: +; CHECK: vmlob %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vmlob(<16 x i8> %a, <16 x i8> %b) + ret <8 x i16> %res +} + +; VMLOH. +define <4 x i32> @test_vmloh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vmloh: +; CHECK: vmloh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vmloh(<8 x i16> %a, <8 x i16> %b) + ret <4 x i32> %res +} + +; VMLOF. +define <2 x i64> @test_vmlof(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vmlof: +; CHECK: vmlof %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vmlof(<4 x i32> %a, <4 x i32> %b) + ret <2 x i64> %res +} + +; VERLLVB. +define <16 x i8> @test_verllvb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_verllvb: +; CHECK: verllvb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.verllvb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VERLLVH. +define <8 x i16> @test_verllvh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_verllvh: +; CHECK: verllvh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.verllvh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VERLLVF. +define <4 x i32> @test_verllvf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_verllvf: +; CHECK: verllvf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.verllvf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VERLLVG. +define <2 x i64> @test_verllvg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_verllvg: +; CHECK: verllvg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.verllvg(<2 x i64> %a, <2 x i64> %b) + ret <2 x i64> %res +} + +; VERLLB. +define <16 x i8> @test_verllb(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_verllb: +; CHECK: verllb %v24, %v24, 0(%r2) +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 %b) + ret <16 x i8> %res +} + +; VERLLH. +define <8 x i16> @test_verllh(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_verllh: +; CHECK: verllh %v24, %v24, 0(%r2) +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.verllh(<8 x i16> %a, i32 %b) + ret <8 x i16> %res +} + +; VERLLF. +define <4 x i32> @test_verllf(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_verllf: +; CHECK: verllf %v24, %v24, 0(%r2) +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.verllf(<4 x i32> %a, i32 %b) + ret <4 x i32> %res +} + +; VERLLG. +define <2 x i64> @test_verllg(<2 x i64> %a, i32 %b) { +; CHECK-LABEL: test_verllg: +; CHECK: verllg %v24, %v24, 0(%r2) +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.verllg(<2 x i64> %a, i32 %b) + ret <2 x i64> %res +} + +; VERLLB with the smallest count. +define <16 x i8> @test_verllb_1(<16 x i8> %a) { +; CHECK-LABEL: test_verllb_1: +; CHECK: verllb %v24, %v24, 1 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 1) + ret <16 x i8> %res +} + +; VERLLB with the largest count. +define <16 x i8> @test_verllb_4095(<16 x i8> %a) { +; CHECK-LABEL: test_verllb_4095: +; CHECK: verllb %v24, %v24, 4095 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4095) + ret <16 x i8> %res +} + +; VERLLB with the largest count + 1. +define <16 x i8> @test_verllb_4096(<16 x i8> %a) { +; CHECK-LABEL: test_verllb_4096: +; CHECK: lhi [[REG:%r[1-5]]], 4096 +; CHECK: verllb %v24, %v24, 0([[REG]]) +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4096) + ret <16 x i8> %res +} + +; VERIMB. +define <16 x i8> @test_verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_verimb: +; CHECK: verimb %v24, %v26, %v28, 1 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1) + ret <16 x i8> %res +} + +; VERIMH. +define <8 x i16> @test_verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { +; CHECK-LABEL: test_verimh: +; CHECK: verimh %v24, %v26, %v28, 1 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, i32 1) + ret <8 x i16> %res +} + +; VERIMF. +define <4 x i32> @test_verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { +; CHECK-LABEL: test_verimf: +; CHECK: verimf %v24, %v26, %v28, 1 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i32 1) + ret <4 x i32> %res +} + +; VERIMG. +define <2 x i64> @test_verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { +; CHECK-LABEL: test_verimg: +; CHECK: verimg %v24, %v26, %v28, 1 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, i32 1) + ret <2 x i64> %res +} + +; VERIMB with a different mask. +define <16 x i8> @test_verimb_254(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_verimb_254: +; CHECK: verimb %v24, %v26, %v28, 254 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 254) + ret <16 x i8> %res +} + +; VSL. +define <16 x i8> @test_vsl(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsl: +; CHECK: vsl %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsl(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSLB. +define <16 x i8> @test_vslb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vslb: +; CHECK: vslb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vslb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSRA. +define <16 x i8> @test_vsra(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsra: +; CHECK: vsra %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsra(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSRAB. +define <16 x i8> @test_vsrab(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsrab: +; CHECK: vsrab %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsrab(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSRL. +define <16 x i8> @test_vsrl(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsrl: +; CHECK: vsrl %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsrl(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSRLB. +define <16 x i8> @test_vsrlb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsrlb: +; CHECK: vsrlb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsrlb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSLDB with the minimum useful value. +define <16 x i8> @test_vsldb_1(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsldb_1: +; CHECK: vsldb %v24, %v24, %v26, 1 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 1) + ret <16 x i8> %res +} + +; VSLDB with the maximum value. +define <16 x i8> @test_vsldb_15(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsldb_15: +; CHECK: vsldb %v24, %v24, %v26, 15 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 15) + ret <16 x i8> %res +} + +; VSCBIB. +define <16 x i8> @test_vscbib(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vscbib: +; CHECK: vscbib %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vscbib(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSCBIH. +define <8 x i16> @test_vscbih(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vscbih: +; CHECK: vscbih %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vscbih(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VSCBIF. +define <4 x i32> @test_vscbif(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vscbif: +; CHECK: vscbif %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vscbif(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VSCBIG. +define <2 x i64> @test_vscbig(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vscbig: +; CHECK: vscbig %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vscbig(<2 x i64> %a, <2 x i64> %b) + ret <2 x i64> %res +} + +; VSQ. +define <16 x i8> @test_vsq(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsq: +; CHECK: vsq %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsq(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSBIQ. +define <16 x i8> @test_vsbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vsbiq: +; CHECK: vsbiq %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsbiq(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VSCBIQ. +define <16 x i8> @test_vscbiq(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vscbiq: +; CHECK: vscbiq %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vscbiq(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VSBCBIQ. +define <16 x i8> @test_vsbcbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vsbcbiq: +; CHECK: vsbcbiq %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsbcbiq(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c) + ret <16 x i8> %res +} + +; VSUMB. +define <4 x i32> @test_vsumb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vsumb: +; CHECK: vsumb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vsumb(<16 x i8> %a, <16 x i8> %b) + ret <4 x i32> %res +} + +; VSUMH. +define <4 x i32> @test_vsumh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vsumh: +; CHECK: vsumh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vsumh(<8 x i16> %a, <8 x i16> %b) + ret <4 x i32> %res +} + +; VSUMGH. +define <2 x i64> @test_vsumgh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vsumgh: +; CHECK: vsumgh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vsumgh(<8 x i16> %a, <8 x i16> %b) + ret <2 x i64> %res +} + +; VSUMGF. +define <2 x i64> @test_vsumgf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vsumgf: +; CHECK: vsumgf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vsumgf(<4 x i32> %a, <4 x i32> %b) + ret <2 x i64> %res +} + +; VSUMQF. +define <16 x i8> @test_vsumqf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vsumqf: +; CHECK: vsumqf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsumqf(<4 x i32> %a, <4 x i32> %b) + ret <16 x i8> %res +} + +; VSUMQG. +define <16 x i8> @test_vsumqg(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vsumqg: +; CHECK: vsumqg %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vsumqg(<2 x i64> %a, <2 x i64> %b) + ret <16 x i8> %res +} + +; VTM with no processing of the result. +define i32 @test_vtm(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vtm: +; CHECK: vtm %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b) + ret i32 %res +} + +; VTM, storing to %ptr if all bits are set. +define void @test_vtm_all_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { +; CHECK-LABEL: test_vtm_all_store: +; CHECK-NOT: %r +; CHECK: vtm %v24, %v26 +; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b) + %cmp = icmp sge i32 %res, 3 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret void +} + +; VCEQBS with no processing of the result. +define i32 @test_vceqbs(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vceqbs: +; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 1 + ret i32 %res +} + +; VCEQBS, returning 1 if any elements are equal (CC != 3). +define i32 @test_vceqbs_any_bool(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vceqbs_any_bool: +; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: afi %r2, -536870912 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp ne i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCEQBS, storing to %ptr if any elements are equal. +define <16 x i8> @test_vceqbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { +; CHECK-LABEL: test_vceqbs_any_store: +; CHECK-NOT: %r +; CHECK: vceqbs %v24, %v24, %v26 +; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp ule i32 %cc, 2 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <16 x i8> %res +} + +; VCEQHS with no processing of the result. +define i32 @test_vceqhs(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vceqhs: +; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 1 + ret i32 %res +} + +; VCEQHS, returning 1 if not all elements are equal. +define i32 @test_vceqhs_notall_bool(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vceqhs_notall_bool: +; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 36 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp sge i32 %res, 1 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCEQHS, storing to %ptr if not all elements are equal. +define <8 x i16> @test_vceqhs_notall_store(<8 x i16> %a, <8 x i16> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vceqhs_notall_store: +; CHECK-NOT: %r +; CHECK: vceqhs %v24, %v24, %v26 +; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp ugt i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <8 x i16> %res +} + +; VCEQFS with no processing of the result. +define i32 @test_vceqfs(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vceqfs: +; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 1 + ret i32 %res +} + +; VCEQFS, returning 1 if no elements are equal. +define i32 @test_vceqfs_none_bool(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vceqfs_none_bool: +; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 35 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp eq i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCEQFS, storing to %ptr if no elements are equal. +define <4 x i32> @test_vceqfs_none_store(<4 x i32> %a, <4 x i32> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vceqfs_none_store: +; CHECK-NOT: %r +; CHECK: vceqfs %v24, %v24, %v26 +; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp uge i32 %cc, 3 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <4 x i32> %res +} + +; VCEQGS with no processing of the result. +define i32 @test_vceqgs(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vceqgs: +; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + ret i32 %res +} + +; VCEQGS returning 1 if all elements are equal (CC == 0). +define i32 @test_vceqgs_all_bool(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vceqgs_all_bool: +; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: afi %r2, -268435456 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp ult i32 %res, 1 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCEQGS, storing to %ptr if all elements are equal. +define <2 x i64> @test_vceqgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { +; CHECK-LABEL: test_vceqgs_all_store: +; CHECK-NOT: %r +; CHECK: vceqgs %v24, %v24, %v26 +; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 0 + %cc = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp sle i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <2 x i64> %res +} + +; VCHBS with no processing of the result. +define i32 @test_vchbs(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vchbs: +; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 1 + ret i32 %res +} + +; VCHBS, returning 1 if any elements are higher (CC != 3). +define i32 @test_vchbs_any_bool(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vchbs_any_bool: +; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: afi %r2, -536870912 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp ne i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHBS, storing to %ptr if any elements are higher. +define <16 x i8> @test_vchbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { +; CHECK-LABEL: test_vchbs_any_store: +; CHECK-NOT: %r +; CHECK: vchbs %v24, %v24, %v26 +; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp ule i32 %cc, 2 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <16 x i8> %res +} + +; VCHHS with no processing of the result. +define i32 @test_vchhs(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vchhs: +; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 1 + ret i32 %res +} + +; VCHHS, returning 1 if not all elements are higher. +define i32 @test_vchhs_notall_bool(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vchhs_notall_bool: +; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 36 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp sge i32 %res, 1 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHHS, storing to %ptr if not all elements are higher. +define <8 x i16> @test_vchhs_notall_store(<8 x i16> %a, <8 x i16> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vchhs_notall_store: +; CHECK-NOT: %r +; CHECK: vchhs %v24, %v24, %v26 +; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp ugt i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <8 x i16> %res +} + +; VCHFS with no processing of the result. +define i32 @test_vchfs(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vchfs: +; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 1 + ret i32 %res +} + +; VCHFS, returning 1 if no elements are higher. +define i32 @test_vchfs_none_bool(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vchfs_none_bool: +; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 35 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp eq i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHFS, storing to %ptr if no elements are higher. +define <4 x i32> @test_vchfs_none_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) { +; CHECK-LABEL: test_vchfs_none_store: +; CHECK-NOT: %r +; CHECK: vchfs %v24, %v24, %v26 +; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp uge i32 %cc, 3 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <4 x i32> %res +} + +; VCHGS with no processing of the result. +define i32 @test_vchgs(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vchgs: +; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + ret i32 %res +} + +; VCHGS returning 1 if all elements are higher (CC == 0). +define i32 @test_vchgs_all_bool(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vchgs_all_bool: +; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: afi %r2, -268435456 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp ult i32 %res, 1 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHGS, storing to %ptr if all elements are higher. +define <2 x i64> @test_vchgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { +; CHECK-LABEL: test_vchgs_all_store: +; CHECK-NOT: %r +; CHECK: vchgs %v24, %v24, %v26 +; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 0 + %cc = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp sle i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <2 x i64> %res +} + +; VCHLBS with no processing of the result. +define i32 @test_vchlbs(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vchlbs: +; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 1 + ret i32 %res +} + +; VCHLBS, returning 1 if any elements are higher (CC != 3). +define i32 @test_vchlbs_any_bool(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vchlbs_any_bool: +; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: afi %r2, -536870912 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp ne i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHLBS, storing to %ptr if any elements are higher. +define <16 x i8> @test_vchlbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { +; CHECK-LABEL: test_vchlbs_any_store: +; CHECK-NOT: %r +; CHECK: vchlbs %v24, %v24, %v26 +; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + %cmp = icmp sle i32 %cc, 2 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <16 x i8> %res +} + +; VCHLHS with no processing of the result. +define i32 @test_vchlhs(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vchlhs: +; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 1 + ret i32 %res +} + +; VCHLHS, returning 1 if not all elements are higher. +define i32 @test_vchlhs_notall_bool(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vchlhs_notall_bool: +; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 36 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp uge i32 %res, 1 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHLHS, storing to %ptr if not all elements are higher. +define <8 x i16> @test_vchlhs_notall_store(<8 x i16> %a, <8 x i16> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vchlhs_notall_store: +; CHECK-NOT: %r +; CHECK: vchlhs %v24, %v24, %v26 +; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + %cmp = icmp sgt i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <8 x i16> %res +} + +; VCHLFS with no processing of the result. +define i32 @test_vchlfs(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vchlfs: +; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 1 + ret i32 %res +} + +; VCHLFS, returning 1 if no elements are higher. +define i32 @test_vchlfs_none_bool(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vchlfs_none_bool: +; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 35 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp eq i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHLFS, storing to %ptr if no elements are higher. +define <4 x i32> @test_vchlfs_none_store(<4 x i32> %a, <4 x i32> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vchlfs_none_store: +; CHECK-NOT: %r +; CHECK: vchlfs %v24, %v24, %v26 +; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + %cmp = icmp sge i32 %cc, 3 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <4 x i32> %res +} + +; VCHLGS with no processing of the result. +define i32 @test_vchlgs(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vchlgs: +; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + ret i32 %res +} + +; VCHLGS returning 1 if all elements are higher (CC == 0). +define i32 @test_vchlgs_all_bool(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: test_vchlgs_all_bool: +; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: afi %r2, -268435456 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp slt i32 %res, 1 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VCHLGS, storing to %ptr if all elements are higher. +define <2 x i64> @test_vchlgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { +; CHECK-LABEL: test_vchlgs_all_store: +; CHECK-NOT: %r +; CHECK: vchlgs %v24, %v24, %v26 +; CHECK-NEXT: {{jnhe|jne}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b) + %res = extractvalue {<2 x i64>, i32} %call, 0 + %cc = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp ule i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <2 x i64> %res +} + +; VFAEB with !IN !RT. +define <16 x i8> @test_vfaeb_0(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaeb_0: +; CHECK: vfaeb %v24, %v24, %v26, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 0) + ret <16 x i8> %res +} + +; VFAEB with !IN RT. +define <16 x i8> @test_vfaeb_4(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaeb_4: +; CHECK: vfaeb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 4) + ret <16 x i8> %res +} + +; VFAEB with IN !RT. +define <16 x i8> @test_vfaeb_8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaeb_8: +; CHECK: vfaeb %v24, %v24, %v26, 8 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 8) + ret <16 x i8> %res +} + +; VFAEB with IN RT. +define <16 x i8> @test_vfaeb_12(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaeb_12: +; CHECK: vfaeb %v24, %v24, %v26, 12 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 12) + ret <16 x i8> %res +} + +; VFAEB with CS -- should be ignored. +define <16 x i8> @test_vfaeb_1(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaeb_1: +; CHECK: vfaeb %v24, %v24, %v26, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 1) + ret <16 x i8> %res +} + +; VFAEH. +define <8 x i16> @test_vfaeh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vfaeh: +; CHECK: vfaeh %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vfaeh(<8 x i16> %a, <8 x i16> %b, i32 4) + ret <8 x i16> %res +} + +; VFAEF. +define <4 x i32> @test_vfaef(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vfaef: +; CHECK: vfaef %v24, %v24, %v26, 8 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vfaef(<4 x i32> %a, <4 x i32> %b, i32 8) + ret <4 x i32> %res +} + +; VFAEBS. +define <16 x i8> @test_vfaebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfaebs: +; CHECK: vfaebs %v24, %v24, %v26, 0 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vfaebs(<16 x i8> %a, <16 x i8> %b, + i32 0) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VFAEHS. +define <8 x i16> @test_vfaehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfaehs: +; CHECK: vfaehs %v24, %v24, %v26, 4 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vfaehs(<8 x i16> %a, <8 x i16> %b, + i32 4) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VFAEFS. +define <4 x i32> @test_vfaefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfaefs: +; CHECK: vfaefs %v24, %v24, %v26, 8 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vfaefs(<4 x i32> %a, <4 x i32> %b, + i32 8) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VFAEZB with !IN !RT. +define <16 x i8> @test_vfaezb_0(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaezb_0: +; CHECK: vfaezb %v24, %v24, %v26, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 0) + ret <16 x i8> %res +} + +; VFAEZB with !IN RT. +define <16 x i8> @test_vfaezb_4(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaezb_4: +; CHECK: vfaezb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 4) + ret <16 x i8> %res +} + +; VFAEZB with IN !RT. +define <16 x i8> @test_vfaezb_8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaezb_8: +; CHECK: vfaezb %v24, %v24, %v26, 8 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 8) + ret <16 x i8> %res +} + +; VFAEZB with IN RT. +define <16 x i8> @test_vfaezb_12(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaezb_12: +; CHECK: vfaezb %v24, %v24, %v26, 12 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 12) + ret <16 x i8> %res +} + +; VFAEZB with CS -- should be ignored. +define <16 x i8> @test_vfaezb_1(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfaezb_1: +; CHECK: vfaezb %v24, %v24, %v26, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 1) + ret <16 x i8> %res +} + +; VFAEZH. +define <8 x i16> @test_vfaezh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vfaezh: +; CHECK: vfaezh %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vfaezh(<8 x i16> %a, <8 x i16> %b, i32 4) + ret <8 x i16> %res +} + +; VFAEZF. +define <4 x i32> @test_vfaezf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vfaezf: +; CHECK: vfaezf %v24, %v24, %v26, 8 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vfaezf(<4 x i32> %a, <4 x i32> %b, i32 8) + ret <4 x i32> %res +} + +; VFAEZBS. +define <16 x i8> @test_vfaezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfaezbs: +; CHECK: vfaezbs %v24, %v24, %v26, 0 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vfaezbs(<16 x i8> %a, <16 x i8> %b, + i32 0) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VFAEZHS. +define <8 x i16> @test_vfaezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfaezhs: +; CHECK: vfaezhs %v24, %v24, %v26, 4 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vfaezhs(<8 x i16> %a, <8 x i16> %b, + i32 4) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VFAEZFS. +define <4 x i32> @test_vfaezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfaezfs: +; CHECK: vfaezfs %v24, %v24, %v26, 8 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vfaezfs(<4 x i32> %a, <4 x i32> %b, + i32 8) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VFEEB. +define <16 x i8> @test_vfeeb_0(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfeeb_0: +; CHECK: vfeeb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfeeb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VFEEH. +define <8 x i16> @test_vfeeh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vfeeh: +; CHECK: vfeeh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vfeeh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VFEEF. +define <4 x i32> @test_vfeef(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vfeef: +; CHECK: vfeef %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vfeef(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VFEEBS. +define <16 x i8> @test_vfeebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfeebs: +; CHECK: vfeebs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vfeebs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VFEEHS. +define <8 x i16> @test_vfeehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfeehs: +; CHECK: vfeehs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vfeehs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VFEEFS. +define <4 x i32> @test_vfeefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfeefs: +; CHECK: vfeefs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vfeefs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VFEEZB. +define <16 x i8> @test_vfeezb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfeezb: +; CHECK: vfeezb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfeezb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VFEEZH. +define <8 x i16> @test_vfeezh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vfeezh: +; CHECK: vfeezh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vfeezh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VFEEZF. +define <4 x i32> @test_vfeezf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vfeezf: +; CHECK: vfeezf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vfeezf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VFEEZBS. +define <16 x i8> @test_vfeezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfeezbs: +; CHECK: vfeezbs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vfeezbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VFEEZHS. +define <8 x i16> @test_vfeezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfeezhs: +; CHECK: vfeezhs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vfeezhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VFEEZFS. +define <4 x i32> @test_vfeezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfeezfs: +; CHECK: vfeezfs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vfeezfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VFENEB. +define <16 x i8> @test_vfeneb_0(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfeneb_0: +; CHECK: vfeneb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfeneb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VFENEH. +define <8 x i16> @test_vfeneh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vfeneh: +; CHECK: vfeneh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vfeneh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VFENEF. +define <4 x i32> @test_vfenef(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vfenef: +; CHECK: vfenef %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vfenef(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VFENEBS. +define <16 x i8> @test_vfenebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfenebs: +; CHECK: vfenebs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vfenebs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VFENEHS. +define <8 x i16> @test_vfenehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfenehs: +; CHECK: vfenehs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vfenehs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VFENEFS. +define <4 x i32> @test_vfenefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfenefs: +; CHECK: vfenefs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vfenefs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VFENEZB. +define <16 x i8> @test_vfenezb(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vfenezb: +; CHECK: vfenezb %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vfenezb(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %res +} + +; VFENEZH. +define <8 x i16> @test_vfenezh(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vfenezh: +; CHECK: vfenezh %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vfenezh(<8 x i16> %a, <8 x i16> %b) + ret <8 x i16> %res +} + +; VFENEZF. +define <4 x i32> @test_vfenezf(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vfenezf: +; CHECK: vfenezf %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vfenezf(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + +; VFENEZBS. +define <16 x i8> @test_vfenezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfenezbs: +; CHECK: vfenezbs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vfenezbs(<16 x i8> %a, <16 x i8> %b) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VFENEZHS. +define <8 x i16> @test_vfenezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfenezhs: +; CHECK: vfenezhs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vfenezhs(<8 x i16> %a, <8 x i16> %b) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VFENEZFS. +define <4 x i32> @test_vfenezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { +; CHECK-LABEL: test_vfenezfs: +; CHECK: vfenezfs %v24, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vfenezfs(<4 x i32> %a, <4 x i32> %b) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VISTRB. +define <16 x i8> @test_vistrb(<16 x i8> %a) { +; CHECK-LABEL: test_vistrb: +; CHECK: vistrb %v24, %v24 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vistrb(<16 x i8> %a) + ret <16 x i8> %res +} + +; VISTRH. +define <8 x i16> @test_vistrh(<8 x i16> %a) { +; CHECK-LABEL: test_vistrh: +; CHECK: vistrh %v24, %v24 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vistrh(<8 x i16> %a) + ret <8 x i16> %res +} + +; VISTRF. +define <4 x i32> @test_vistrf(<4 x i32> %a) { +; CHECK-LABEL: test_vistrf: +; CHECK: vistrf %v24, %v24 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vistrf(<4 x i32> %a) + ret <4 x i32> %res +} + +; VISTRBS. +define <16 x i8> @test_vistrbs(<16 x i8> %a, i32 *%ccptr) { +; CHECK-LABEL: test_vistrbs: +; CHECK: vistrbs %v24, %v24 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vistrbs(<16 x i8> %a) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VISTRHS. +define <8 x i16> @test_vistrhs(<8 x i16> %a, i32 *%ccptr) { +; CHECK-LABEL: test_vistrhs: +; CHECK: vistrhs %v24, %v24 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vistrhs(<8 x i16> %a) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VISTRFS. +define <4 x i32> @test_vistrfs(<4 x i32> %a, i32 *%ccptr) { +; CHECK-LABEL: test_vistrfs: +; CHECK: vistrfs %v24, %v24 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vistrfs(<4 x i32> %a) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VSTRCB with !IN !RT. +define <16 x i8> @test_vstrcb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrcb_0: +; CHECK: vstrcb %v24, %v24, %v26, %v28, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 0) + ret <16 x i8> %res +} + +; VSTRCB with !IN RT. +define <16 x i8> @test_vstrcb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrcb_4: +; CHECK: vstrcb %v24, %v24, %v26, %v28, 4 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 4) + ret <16 x i8> %res +} + +; VSTRCB with IN !RT. +define <16 x i8> @test_vstrcb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrcb_8: +; CHECK: vstrcb %v24, %v24, %v26, %v28, 8 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 8) + ret <16 x i8> %res +} + +; VSTRCB with IN RT. +define <16 x i8> @test_vstrcb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrcb_12: +; CHECK: vstrcb %v24, %v24, %v26, %v28, 12 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 12) + ret <16 x i8> %res +} + +; VSTRCB with CS -- should be ignored. +define <16 x i8> @test_vstrcb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrcb_1: +; CHECK: vstrcb %v24, %v24, %v26, %v28, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 1) + ret <16 x i8> %res +} + +; VSTRCH. +define <8 x i16> @test_vstrch(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vstrch: +; CHECK: vstrch %v24, %v24, %v26, %v28, 4 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vstrch(<8 x i16> %a, <8 x i16> %b, + <8 x i16> %c, i32 4) + ret <8 x i16> %res +} + +; VSTRCF. +define <4 x i32> @test_vstrcf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vstrcf: +; CHECK: vstrcf %v24, %v24, %v26, %v28, 8 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vstrcf(<4 x i32> %a, <4 x i32> %b, + <4 x i32> %c, i32 8) + ret <4 x i32> %res +} + +; VSTRCBS. +define <16 x i8> @test_vstrcbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, + i32 *%ccptr) { +; CHECK-LABEL: test_vstrcbs: +; CHECK: vstrcbs %v24, %v24, %v26, %v28, 0 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vstrcbs(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 0) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VSTRCHS. +define <8 x i16> @test_vstrchs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, + i32 *%ccptr) { +; CHECK-LABEL: test_vstrchs: +; CHECK: vstrchs %v24, %v24, %v26, %v28, 4 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vstrchs(<8 x i16> %a, <8 x i16> %b, + <8 x i16> %c, i32 4) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VSTRCFS. +define <4 x i32> @test_vstrcfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, + i32 *%ccptr) { +; CHECK-LABEL: test_vstrcfs: +; CHECK: vstrcfs %v24, %v24, %v26, %v28, 8 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vstrcfs(<4 x i32> %a, <4 x i32> %b, + <4 x i32> %c, i32 8) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VSTRCZB with !IN !RT. +define <16 x i8> @test_vstrczb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrczb_0: +; CHECK: vstrczb %v24, %v24, %v26, %v28, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 0) + ret <16 x i8> %res +} + +; VSTRCZB with !IN RT. +define <16 x i8> @test_vstrczb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrczb_4: +; CHECK: vstrczb %v24, %v24, %v26, %v28, 4 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 4) + ret <16 x i8> %res +} + +; VSTRCZB with IN !RT. +define <16 x i8> @test_vstrczb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrczb_8: +; CHECK: vstrczb %v24, %v24, %v26, %v28, 8 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 8) + ret <16 x i8> %res +} + +; VSTRCZB with IN RT. +define <16 x i8> @test_vstrczb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrczb_12: +; CHECK: vstrczb %v24, %v24, %v26, %v28, 12 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 12) + ret <16 x i8> %res +} + +; VSTRCZB with CS -- should be ignored. +define <16 x i8> @test_vstrczb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vstrczb_1: +; CHECK: vstrczb %v24, %v24, %v26, %v28, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 1) + ret <16 x i8> %res +} + +; VSTRCZH. +define <8 x i16> @test_vstrczh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { +; CHECK-LABEL: test_vstrczh: +; CHECK: vstrczh %v24, %v24, %v26, %v28, 4 +; CHECK: br %r14 + %res = call <8 x i16> @llvm.s390.vstrczh(<8 x i16> %a, <8 x i16> %b, + <8 x i16> %c, i32 4) + ret <8 x i16> %res +} + +; VSTRCZF. +define <4 x i32> @test_vstrczf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { +; CHECK-LABEL: test_vstrczf: +; CHECK: vstrczf %v24, %v24, %v26, %v28, 8 +; CHECK: br %r14 + %res = call <4 x i32> @llvm.s390.vstrczf(<4 x i32> %a, <4 x i32> %b, + <4 x i32> %c, i32 8) + ret <4 x i32> %res +} + +; VSTRCZBS. +define <16 x i8> @test_vstrczbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, + i32 *%ccptr) { +; CHECK-LABEL: test_vstrczbs: +; CHECK: vstrczbs %v24, %v24, %v26, %v28, 0 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<16 x i8>, i32} @llvm.s390.vstrczbs(<16 x i8> %a, <16 x i8> %b, + <16 x i8> %c, i32 0) + %res = extractvalue {<16 x i8>, i32} %call, 0 + %cc = extractvalue {<16 x i8>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <16 x i8> %res +} + +; VSTRCZHS. +define <8 x i16> @test_vstrczhs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, + i32 *%ccptr) { +; CHECK-LABEL: test_vstrczhs: +; CHECK: vstrczhs %v24, %v24, %v26, %v28, 4 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<8 x i16>, i32} @llvm.s390.vstrczhs(<8 x i16> %a, <8 x i16> %b, + <8 x i16> %c, i32 4) + %res = extractvalue {<8 x i16>, i32} %call, 0 + %cc = extractvalue {<8 x i16>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <8 x i16> %res +} + +; VSTRCZFS. +define <4 x i32> @test_vstrczfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, + i32 *%ccptr) { +; CHECK-LABEL: test_vstrczfs: +; CHECK: vstrczfs %v24, %v24, %v26, %v28, 8 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: srl [[REG]], 28 +; CHECK: st [[REG]], 0(%r2) +; CHECK: br %r14 + %call = call {<4 x i32>, i32} @llvm.s390.vstrczfs(<4 x i32> %a, <4 x i32> %b, + <4 x i32> %c, i32 8) + %res = extractvalue {<4 x i32>, i32} %call, 0 + %cc = extractvalue {<4 x i32>, i32} %call, 1 + store i32 %cc, i32 *%ccptr + ret <4 x i32> %res +} + +; VFCEDBS with no processing of the result. +define i32 @test_vfcedbs(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfcedbs: +; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + ret i32 %res +} + +; VFCEDBS, returning 1 if any elements are equal (CC != 3). +define i32 @test_vfcedbs_any_bool(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfcedbs_any_bool: +; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: afi %r2, -536870912 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp ne i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VFCEDBS, storing to %ptr if any elements are equal. +define <2 x i64> @test_vfcedbs_any_store(<2 x double> %a, <2 x double> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vfcedbs_any_store: +; CHECK-NOT: %r +; CHECK: vfcedbs %v24, %v24, %v26 +; CHECK-NEXT: {{jo|jnle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 0 + %cc = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp ule i32 %cc, 2 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <2 x i64> %res +} + +; VFCHDBS with no processing of the result. +define i32 @test_vfchdbs(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfchdbs: +; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + ret i32 %res +} + +; VFCHDBS, returning 1 if not all elements are higher. +define i32 @test_vfchdbs_notall_bool(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfchdbs_notall_bool: +; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 36 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp sge i32 %res, 1 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VFCHDBS, storing to %ptr if not all elements are higher. +define <2 x i64> @test_vfchdbs_notall_store(<2 x double> %a, <2 x double> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vfchdbs_notall_store: +; CHECK-NOT: %r +; CHECK: vfchdbs %v24, %v24, %v26 +; CHECK-NEXT: {{jhe|je}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 0 + %cc = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp ugt i32 %cc, 0 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <2 x i64> %res +} + +; VFCHEDBS with no processing of the result. +define i32 @test_vfchedbs(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfchedbs: +; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + ret i32 %res +} + +; VFCHEDBS, returning 1 if neither element is higher or equal. +define i32 @test_vfchedbs_none_bool(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfchedbs_none_bool: +; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26 +; CHECK: ipm [[REG:%r[0-5]]] +; CHECK: risblg %r2, [[REG]], 31, 159, 35 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp eq i32 %res, 3 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VFCHEDBS, storing to %ptr if neither element is higher or equal. +define <2 x i64> @test_vfchedbs_none_store(<2 x double> %a, <2 x double> %b, + i32 *%ptr) { +; CHECK-LABEL: test_vfchedbs_none_store: +; CHECK-NOT: %r +; CHECK: vfchedbs %v24, %v24, %v26 +; CHECK-NEXT: {{jno|jle}} {{\.L*}} +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a, + <2 x double> %b) + %res = extractvalue {<2 x i64>, i32} %call, 0 + %cc = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp uge i32 %cc, 3 + br i1 %cmp, label %store, label %exit + +store: + store i32 0, i32 *%ptr + br label %exit + +exit: + ret <2 x i64> %res +} + +; VFTCIDB with the lowest useful class selector and no processing of the result. +define i32 @test_vftcidb(<2 x double> %a) { +; CHECK-LABEL: test_vftcidb: +; CHECK: vftcidb {{%v[0-9]+}}, %v24, 1 +; CHECK: ipm %r2 +; CHECK: srl %r2, 28 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 1) + %res = extractvalue {<2 x i64>, i32} %call, 1 + ret i32 %res +} + +; VFTCIDB with the highest useful class selector, returning 1 if all elements +; have the right class (CC == 0). +define i32 @test_vftcidb_all_bool(<2 x double> %a) { +; CHECK-LABEL: test_vftcidb_all_bool: +; CHECK: vftcidb {{%v[0-9]+}}, %v24, 4094 +; CHECK: afi %r2, -268435456 +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 4094) + %res = extractvalue {<2 x i64>, i32} %call, 1 + %cmp = icmp eq i32 %res, 0 + %ext = zext i1 %cmp to i32 + ret i32 %ext +} + +; VFIDB with a rounding mode not usable via standard intrinsics. +define <2 x double> @test_vfidb_0_4(<2 x double> %a) { +; CHECK-LABEL: test_vfidb_0_4: +; CHECK: vfidb %v24, %v24, 0, 4 +; CHECK: br %r14 + %res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 0, i32 4) + ret <2 x double> %res +} + +; VFIDB with IEEE-inexact exception suppressed. +define <2 x double> @test_vfidb_4_0(<2 x double> %a) { +; CHECK-LABEL: test_vfidb_4_0: +; CHECK: vfidb %v24, %v24, 4, 0 +; CHECK: br %r14 + %res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 4, i32 0) + ret <2 x double> %res +} + diff --git a/test/CodeGen/SystemZ/vec-log-01.ll b/test/CodeGen/SystemZ/vec-log-01.ll new file mode 100644 index 000000000000..f9b7402f08e7 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-log-01.ll @@ -0,0 +1,15 @@ +; Test v2f64 logarithm. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare <2 x double> @llvm.log.v2f64(<2 x double>) + +define <2 x double> @f1(<2 x double> %val) { +; CHECK-LABEL: f1: +; CHECK: brasl %r14, log@PLT +; CHECK: brasl %r14, log@PLT +; CHECK: vmrhg %v24, +; CHECK: br %r14 + %ret = call <2 x double> @llvm.log.v2f64(<2 x double> %val) + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-max-01.ll b/test/CodeGen/SystemZ/vec-max-01.ll new file mode 100644 index 000000000000..ca6f08aa493f --- /dev/null +++ b/test/CodeGen/SystemZ/vec-max-01.ll @@ -0,0 +1,83 @@ +; Test v16i8 maximum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with sle. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with sgt. +define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} + +; Test with sge. +define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmxb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} + +; Test with ult. +define <16 x i8> @f5(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with ule. +define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with ugt. +define <16 x i8> @f7(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} + +; Test with uge. +define <16 x i8> @f8(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmxlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <16 x i8> %val1, %val2 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} diff --git a/test/CodeGen/SystemZ/vec-max-02.ll b/test/CodeGen/SystemZ/vec-max-02.ll new file mode 100644 index 000000000000..2c61603b6f3b --- /dev/null +++ b/test/CodeGen/SystemZ/vec-max-02.ll @@ -0,0 +1,83 @@ +; Test v8i16 maximum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with sle. +define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with sgt. +define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} + +; Test with sge. +define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmxh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} + +; Test with ult. +define <8 x i16> @f5(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with ule. +define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with ugt. +define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} + +; Test with uge. +define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmxlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <8 x i16> %val1, %val2 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} diff --git a/test/CodeGen/SystemZ/vec-max-03.ll b/test/CodeGen/SystemZ/vec-max-03.ll new file mode 100644 index 000000000000..a43879483997 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-max-03.ll @@ -0,0 +1,83 @@ +; Test v4i32 maximum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with sle. +define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with sgt. +define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} + +; Test with sge. +define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmxf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} + +; Test with ult. +define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with ule. +define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with ugt. +define <4 x i32> @f7(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} + +; Test with uge. +define <4 x i32> @f8(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmxlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <4 x i32> %val1, %val2 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} diff --git a/test/CodeGen/SystemZ/vec-max-04.ll b/test/CodeGen/SystemZ/vec-max-04.ll new file mode 100644 index 000000000000..ab7c62391277 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-max-04.ll @@ -0,0 +1,83 @@ +; Test v2i64 maximum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with sle. +define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with sgt. +define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} + +; Test with sge. +define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmxg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} + +; Test with ult. +define <2 x i64> @f5(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with ule. +define <2 x i64> @f6(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with ugt. +define <2 x i64> @f7(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} + +; Test with uge. +define <2 x i64> @f8(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmxlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <2 x i64> %val1, %val2 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-min-01.ll b/test/CodeGen/SystemZ/vec-min-01.ll new file mode 100644 index 000000000000..255dc57e1134 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-min-01.ll @@ -0,0 +1,83 @@ +; Test v16i8 minimum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with sle. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with sgt. +define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} + +; Test with sge. +define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmnb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} + +; Test with ult. +define <16 x i8> @f5(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with ule. +define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1 + ret <16 x i8> %ret +} + +; Test with ugt. +define <16 x i8> @f7(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} + +; Test with uge. +define <16 x i8> @f8(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmnlb %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <16 x i8> %val2, %val1 + %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2 + ret <16 x i8> %ret +} diff --git a/test/CodeGen/SystemZ/vec-min-02.ll b/test/CodeGen/SystemZ/vec-min-02.ll new file mode 100644 index 000000000000..cad8a61506c8 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-min-02.ll @@ -0,0 +1,83 @@ +; Test v8i16 minimum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with sle. +define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with sgt. +define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} + +; Test with sge. +define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmnh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} + +; Test with ult. +define <8 x i16> @f5(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with ule. +define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1 + ret <8 x i16> %ret +} + +; Test with ugt. +define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} + +; Test with uge. +define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmnlh %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <8 x i16> %val2, %val1 + %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2 + ret <8 x i16> %ret +} diff --git a/test/CodeGen/SystemZ/vec-min-03.ll b/test/CodeGen/SystemZ/vec-min-03.ll new file mode 100644 index 000000000000..febac50aa462 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-min-03.ll @@ -0,0 +1,83 @@ +; Test v4i32 minimum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with sle. +define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with sgt. +define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} + +; Test with sge. +define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmnf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} + +; Test with ult. +define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with ule. +define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1 + ret <4 x i32> %ret +} + +; Test with ugt. +define <4 x i32> @f7(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} + +; Test with uge. +define <4 x i32> @f8(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmnlf %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <4 x i32> %val2, %val1 + %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2 + ret <4 x i32> %ret +} diff --git a/test/CodeGen/SystemZ/vec-min-04.ll b/test/CodeGen/SystemZ/vec-min-04.ll new file mode 100644 index 000000000000..765ce1956b5d --- /dev/null +++ b/test/CodeGen/SystemZ/vec-min-04.ll @@ -0,0 +1,83 @@ +; Test v2i64 minimum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test with slt. +define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp slt <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with sle. +define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sle <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with sgt. +define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sgt <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} + +; Test with sge. +define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmng %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp sge <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} + +; Test with ult. +define <2 x i64> @f5(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f5: +; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ult <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with ule. +define <2 x i64> @f6(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ule <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1 + ret <2 x i64> %ret +} + +; Test with ugt. +define <2 x i64> @f7(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f7: +; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp ugt <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} + +; Test with uge. +define <2 x i64> @f8(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmnlg %v24, {{%v24, %v26|%v26, %v24}} +; CHECK: br %r14 + %cmp = icmp uge <2 x i64> %val2, %val1 + %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-01.ll b/test/CodeGen/SystemZ/vec-move-01.ll new file mode 100644 index 000000000000..3ef98b7eda03 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-01.ll @@ -0,0 +1,107 @@ +; Test vector register moves. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 moves. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <16 x i8> %val2 +} + +; Test v8i16 moves. +define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <8 x i16> %val2 +} + +; Test v4i32 moves. +define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <4 x i32> %val2 +} + +; Test v2i64 moves. +define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <2 x i64> %val2 +} + +; Test v4f32 moves. +define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f5: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <4 x float> %val2 +} + +; Test v2f64 moves. +define <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f6: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <2 x double> %val2 +} + +; Test v2i8 moves. +define <2 x i8> @f7(<2 x i8> %val1, <2 x i8> %val2) { +; CHECK-LABEL: f7: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <2 x i8> %val2 +} + +; Test v4i8 moves. +define <4 x i8> @f8(<4 x i8> %val1, <4 x i8> %val2) { +; CHECK-LABEL: f8: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <4 x i8> %val2 +} + +; Test v8i8 moves. +define <8 x i8> @f9(<8 x i8> %val1, <8 x i8> %val2) { +; CHECK-LABEL: f9: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <8 x i8> %val2 +} + +; Test v2i16 moves. +define <2 x i16> @f10(<2 x i16> %val1, <2 x i16> %val2) { +; CHECK-LABEL: f10: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <2 x i16> %val2 +} + +; Test v4i16 moves. +define <4 x i16> @f11(<4 x i16> %val1, <4 x i16> %val2) { +; CHECK-LABEL: f11: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <4 x i16> %val2 +} + +; Test v2i32 moves. +define <2 x i32> @f12(<2 x i32> %val1, <2 x i32> %val2) { +; CHECK-LABEL: f12: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <2 x i32> %val2 +} + +; Test v2f32 moves. +define <2 x float> @f13(<2 x float> %val1, <2 x float> %val2) { +; CHECK-LABEL: f13: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <2 x float> %val2 +} diff --git a/test/CodeGen/SystemZ/vec-move-02.ll b/test/CodeGen/SystemZ/vec-move-02.ll new file mode 100644 index 000000000000..dcaf0acccb2f --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-02.ll @@ -0,0 +1,174 @@ +; Test vector loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 loads. +define <16 x i8> @f1(<16 x i8> *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <16 x i8>, <16 x i8> *%ptr + ret <16 x i8> %ret +} + +; Test v8i16 loads. +define <8 x i16> @f2(<8 x i16> *%ptr) { +; CHECK-LABEL: f2: +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <8 x i16>, <8 x i16> *%ptr + ret <8 x i16> %ret +} + +; Test v4i32 loads. +define <4 x i32> @f3(<4 x i32> *%ptr) { +; CHECK-LABEL: f3: +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <4 x i32>, <4 x i32> *%ptr + ret <4 x i32> %ret +} + +; Test v2i64 loads. +define <2 x i64> @f4(<2 x i64> *%ptr) { +; CHECK-LABEL: f4: +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <2 x i64>, <2 x i64> *%ptr + ret <2 x i64> %ret +} + +; Test v4f32 loads. +define <4 x float> @f5(<4 x float> *%ptr) { +; CHECK-LABEL: f5: +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <4 x float>, <4 x float> *%ptr + ret <4 x float> %ret +} + +; Test v2f64 loads. +define <2 x double> @f6(<2 x double> *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <2 x double>, <2 x double> *%ptr + ret <2 x double> %ret +} + +; Test the highest aligned in-range offset. +define <16 x i8> @f7(<16 x i8> *%base) { +; CHECK-LABEL: f7: +; CHECK: vl %v24, 4080(%r2) +; CHECK: br %r14 + %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255 + %ret = load <16 x i8>, <16 x i8> *%ptr + ret <16 x i8> %ret +} + +; Test the highest unaligned in-range offset. +define <16 x i8> @f8(i8 *%base) { +; CHECK-LABEL: f8: +; CHECK: vl %v24, 4095(%r2) +; CHECK: br %r14 + %addr = getelementptr i8, i8 *%base, i64 4095 + %ptr = bitcast i8 *%addr to <16 x i8> * + %ret = load <16 x i8>, <16 x i8> *%ptr, align 1 + ret <16 x i8> %ret +} + +; Test the next offset up, which requires separate address logic, +define <16 x i8> @f9(<16 x i8> *%base) { +; CHECK-LABEL: f9: +; CHECK: aghi %r2, 4096 +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256 + %ret = load <16 x i8>, <16 x i8> *%ptr + ret <16 x i8> %ret +} + +; Test negative offsets, which also require separate address logic, +define <16 x i8> @f10(<16 x i8> *%base) { +; CHECK-LABEL: f10: +; CHECK: aghi %r2, -16 +; CHECK: vl %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1 + %ret = load <16 x i8>, <16 x i8> *%ptr + ret <16 x i8> %ret +} + +; Check that indexes are allowed. +define <16 x i8> @f11(i8 *%base, i64 %index) { +; CHECK-LABEL: f11: +; CHECK: vl %v24, 0(%r3,%r2) +; CHECK: br %r14 + %addr = getelementptr i8, i8 *%base, i64 %index + %ptr = bitcast i8 *%addr to <16 x i8> * + %ret = load <16 x i8>, <16 x i8> *%ptr, align 1 + ret <16 x i8> %ret +} + +; Test v2i8 loads. +define <2 x i8> @f12(<2 x i8> *%ptr) { +; CHECK-LABEL: f12: +; CHECK: vlreph %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <2 x i8>, <2 x i8> *%ptr + ret <2 x i8> %ret +} + +; Test v4i8 loads. +define <4 x i8> @f13(<4 x i8> *%ptr) { +; CHECK-LABEL: f13: +; CHECK: vlrepf %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <4 x i8>, <4 x i8> *%ptr + ret <4 x i8> %ret +} + +; Test v8i8 loads. +define <8 x i8> @f14(<8 x i8> *%ptr) { +; CHECK-LABEL: f14: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <8 x i8>, <8 x i8> *%ptr + ret <8 x i8> %ret +} + +; Test v2i16 loads. +define <2 x i16> @f15(<2 x i16> *%ptr) { +; CHECK-LABEL: f15: +; CHECK: vlrepf %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <2 x i16>, <2 x i16> *%ptr + ret <2 x i16> %ret +} + +; Test v4i16 loads. +define <4 x i16> @f16(<4 x i16> *%ptr) { +; CHECK-LABEL: f16: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <4 x i16>, <4 x i16> *%ptr + ret <4 x i16> %ret +} + +; Test v2i32 loads. +define <2 x i32> @f17(<2 x i32> *%ptr) { +; CHECK-LABEL: f17: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <2 x i32>, <2 x i32> *%ptr + ret <2 x i32> %ret +} + +; Test v2f32 loads. +define <2 x float> @f18(<2 x float> *%ptr) { +; CHECK-LABEL: f18: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %ret = load <2 x float>, <2 x float> *%ptr + ret <2 x float> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-03.ll b/test/CodeGen/SystemZ/vec-move-03.ll new file mode 100644 index 000000000000..f40e2cb2bf28 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-03.ll @@ -0,0 +1,174 @@ +; Test vector stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 stores. +define void @f1(<16 x i8> %val, <16 x i8> *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + store <16 x i8> %val, <16 x i8> *%ptr + ret void +} + +; Test v8i16 stores. +define void @f2(<8 x i16> %val, <8 x i16> *%ptr) { +; CHECK-LABEL: f2: +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + store <8 x i16> %val, <8 x i16> *%ptr + ret void +} + +; Test v4i32 stores. +define void @f3(<4 x i32> %val, <4 x i32> *%ptr) { +; CHECK-LABEL: f3: +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + store <4 x i32> %val, <4 x i32> *%ptr + ret void +} + +; Test v2i64 stores. +define void @f4(<2 x i64> %val, <2 x i64> *%ptr) { +; CHECK-LABEL: f4: +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + store <2 x i64> %val, <2 x i64> *%ptr + ret void +} + +; Test v4f32 stores. +define void @f5(<4 x float> %val, <4 x float> *%ptr) { +; CHECK-LABEL: f5: +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + store <4 x float> %val, <4 x float> *%ptr + ret void +} + +; Test v2f64 stores. +define void @f6(<2 x double> %val, <2 x double> *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + store <2 x double> %val, <2 x double> *%ptr + ret void +} + +; Test the highest aligned in-range offset. +define void @f7(<16 x i8> %val, <16 x i8> *%base) { +; CHECK-LABEL: f7: +; CHECK: vst %v24, 4080(%r2) +; CHECK: br %r14 + %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255 + store <16 x i8> %val, <16 x i8> *%ptr + ret void +} + +; Test the highest unaligned in-range offset. +define void @f8(<16 x i8> %val, i8 *%base) { +; CHECK-LABEL: f8: +; CHECK: vst %v24, 4095(%r2) +; CHECK: br %r14 + %addr = getelementptr i8, i8 *%base, i64 4095 + %ptr = bitcast i8 *%addr to <16 x i8> * + store <16 x i8> %val, <16 x i8> *%ptr, align 1 + ret void +} + +; Test the next offset up, which requires separate address logic, +define void @f9(<16 x i8> %val, <16 x i8> *%base) { +; CHECK-LABEL: f9: +; CHECK: aghi %r2, 4096 +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256 + store <16 x i8> %val, <16 x i8> *%ptr + ret void +} + +; Test negative offsets, which also require separate address logic, +define void @f10(<16 x i8> %val, <16 x i8> *%base) { +; CHECK-LABEL: f10: +; CHECK: aghi %r2, -16 +; CHECK: vst %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1 + store <16 x i8> %val, <16 x i8> *%ptr + ret void +} + +; Check that indexes are allowed. +define void @f11(<16 x i8> %val, i8 *%base, i64 %index) { +; CHECK-LABEL: f11: +; CHECK: vst %v24, 0(%r3,%r2) +; CHECK: br %r14 + %addr = getelementptr i8, i8 *%base, i64 %index + %ptr = bitcast i8 *%addr to <16 x i8> * + store <16 x i8> %val, <16 x i8> *%ptr, align 1 + ret void +} + +; Test v2i8 stores. +define void @f12(<2 x i8> %val, <2 x i8> *%ptr) { +; CHECK-LABEL: f12: +; CHECK: vsteh %v24, 0(%r2), 0 +; CHECK: br %r14 + store <2 x i8> %val, <2 x i8> *%ptr + ret void +} + +; Test v4i8 stores. +define void @f13(<4 x i8> %val, <4 x i8> *%ptr) { +; CHECK-LABEL: f13: +; CHECK: vstef %v24, 0(%r2) +; CHECK: br %r14 + store <4 x i8> %val, <4 x i8> *%ptr + ret void +} + +; Test v8i8 stores. +define void @f14(<8 x i8> %val, <8 x i8> *%ptr) { +; CHECK-LABEL: f14: +; CHECK: vsteg %v24, 0(%r2) +; CHECK: br %r14 + store <8 x i8> %val, <8 x i8> *%ptr + ret void +} + +; Test v2i16 stores. +define void @f15(<2 x i16> %val, <2 x i16> *%ptr) { +; CHECK-LABEL: f15: +; CHECK: vstef %v24, 0(%r2), 0 +; CHECK: br %r14 + store <2 x i16> %val, <2 x i16> *%ptr + ret void +} + +; Test v4i16 stores. +define void @f16(<4 x i16> %val, <4 x i16> *%ptr) { +; CHECK-LABEL: f16: +; CHECK: vsteg %v24, 0(%r2) +; CHECK: br %r14 + store <4 x i16> %val, <4 x i16> *%ptr + ret void +} + +; Test v2i32 stores. +define void @f17(<2 x i32> %val, <2 x i32> *%ptr) { +; CHECK-LABEL: f17: +; CHECK: vsteg %v24, 0(%r2), 0 +; CHECK: br %r14 + store <2 x i32> %val, <2 x i32> *%ptr + ret void +} + +; Test v2f32 stores. +define void @f18(<2 x float> %val, <2 x float> *%ptr) { +; CHECK-LABEL: f18: +; CHECK: vsteg %v24, 0(%r2), 0 +; CHECK: br %r14 + store <2 x float> %val, <2 x float> *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/vec-move-04.ll b/test/CodeGen/SystemZ/vec-move-04.ll new file mode 100644 index 000000000000..27c9e5f71f40 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-04.ll @@ -0,0 +1,179 @@ +; Test vector insertion of register variables. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 insertion into the first element. +define <16 x i8> @f1(<16 x i8> %val, i8 %element) { +; CHECK-LABEL: f1: +; CHECK: vlvgb %v24, %r2, 0 +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 %element, i32 0 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into the last element. +define <16 x i8> @f2(<16 x i8> %val, i8 %element) { +; CHECK-LABEL: f2: +; CHECK: vlvgb %v24, %r2, 15 +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 %element, i32 15 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into a variable element. +define <16 x i8> @f3(<16 x i8> %val, i8 %element, i32 %index) { +; CHECK-LABEL: f3: +; CHECK: vlvgb %v24, %r2, 0(%r3) +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 %element, i32 %index + ret <16 x i8> %ret +} + +; Test v8i16 insertion into the first element. +define <8 x i16> @f4(<8 x i16> %val, i16 %element) { +; CHECK-LABEL: f4: +; CHECK: vlvgh %v24, %r2, 0 +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 %element, i32 0 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into the last element. +define <8 x i16> @f5(<8 x i16> %val, i16 %element) { +; CHECK-LABEL: f5: +; CHECK: vlvgh %v24, %r2, 7 +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 %element, i32 7 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into a variable element. +define <8 x i16> @f6(<8 x i16> %val, i16 %element, i32 %index) { +; CHECK-LABEL: f6: +; CHECK: vlvgh %v24, %r2, 0(%r3) +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 %element, i32 %index + ret <8 x i16> %ret +} + +; Test v4i32 insertion into the first element. +define <4 x i32> @f7(<4 x i32> %val, i32 %element) { +; CHECK-LABEL: f7: +; CHECK: vlvgf %v24, %r2, 0 +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 %element, i32 0 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into the last element. +define <4 x i32> @f8(<4 x i32> %val, i32 %element) { +; CHECK-LABEL: f8: +; CHECK: vlvgf %v24, %r2, 3 +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 %element, i32 3 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into a variable element. +define <4 x i32> @f9(<4 x i32> %val, i32 %element, i32 %index) { +; CHECK-LABEL: f9: +; CHECK: vlvgf %v24, %r2, 0(%r3) +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 %element, i32 %index + ret <4 x i32> %ret +} + +; Test v2i64 insertion into the first element. +define <2 x i64> @f10(<2 x i64> %val, i64 %element) { +; CHECK-LABEL: f10: +; CHECK: vlvgg %v24, %r2, 0 +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 %element, i32 0 + ret <2 x i64> %ret +} + +; Test v2i64 insertion into the last element. +define <2 x i64> @f11(<2 x i64> %val, i64 %element) { +; CHECK-LABEL: f11: +; CHECK: vlvgg %v24, %r2, 1 +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 %element, i32 1 + ret <2 x i64> %ret +} + +; Test v2i64 insertion into a variable element. +define <2 x i64> @f12(<2 x i64> %val, i64 %element, i32 %index) { +; CHECK-LABEL: f12: +; CHECK: vlvgg %v24, %r2, 0(%r3) +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 %element, i32 %index + ret <2 x i64> %ret +} + +; Test v4f32 insertion into the first element. +define <4 x float> @f13(<4 x float> %val, float %element) { +; CHECK-LABEL: f13: +; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0 +; CHECK: vlvgf %v24, [[REG]], 0 +; CHECK: br %r14 + %ret = insertelement <4 x float> %val, float %element, i32 0 + ret <4 x float> %ret +} + +; Test v4f32 insertion into the last element. +define <4 x float> @f14(<4 x float> %val, float %element) { +; CHECK-LABEL: f14: +; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0 +; CHECK: vlvgf %v24, [[REG]], 3 +; CHECK: br %r14 + %ret = insertelement <4 x float> %val, float %element, i32 3 + ret <4 x float> %ret +} + +; Test v4f32 insertion into a variable element. +define <4 x float> @f15(<4 x float> %val, float %element, i32 %index) { +; CHECK-LABEL: f15: +; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0 +; CHECK: vlvgf %v24, [[REG]], 0(%r2) +; CHECK: br %r14 + %ret = insertelement <4 x float> %val, float %element, i32 %index + ret <4 x float> %ret +} + +; Test v2f64 insertion into the first element. +define <2 x double> @f16(<2 x double> %val, double %element) { +; CHECK-LABEL: f16: +; CHECK: vpdi %v24, %v0, %v24, 1 +; CHECK: br %r14 + %ret = insertelement <2 x double> %val, double %element, i32 0 + ret <2 x double> %ret +} + +; Test v2f64 insertion into the last element. +define <2 x double> @f17(<2 x double> %val, double %element) { +; CHECK-LABEL: f17: +; CHECK: vpdi %v24, %v24, %v0, 0 +; CHECK: br %r14 + %ret = insertelement <2 x double> %val, double %element, i32 1 + ret <2 x double> %ret +} + +; Test v2f64 insertion into a variable element. +define <2 x double> @f18(<2 x double> %val, double %element, i32 %index) { +; CHECK-LABEL: f18: +; CHECK: lgdr [[REG:%r[0-5]]], %f0 +; CHECK: vlvgg %v24, [[REG]], 0(%r2) +; CHECK: br %r14 + %ret = insertelement <2 x double> %val, double %element, i32 %index + ret <2 x double> %ret +} + +; Test v16i8 insertion into a variable element plus one. +define <16 x i8> @f19(<16 x i8> %val, i8 %element, i32 %index) { +; CHECK-LABEL: f19: +; CHECK: vlvgb %v24, %r2, 1(%r3) +; CHECK: br %r14 + %add = add i32 %index, 1 + %ret = insertelement <16 x i8> %val, i8 %element, i32 %add + ret <16 x i8> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-05.ll b/test/CodeGen/SystemZ/vec-move-05.ll new file mode 100644 index 000000000000..99871196d685 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-05.ll @@ -0,0 +1,249 @@ +; Test vector extraction. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 extraction of the first element. +define i8 @f1(<16 x i8> %val) { +; CHECK-LABEL: f1: +; CHECK: vlgvb %r2, %v24, 0 +; CHECK: br %r14 + %ret = extractelement <16 x i8> %val, i32 0 + ret i8 %ret +} + +; Test v16i8 extraction of the last element. +define i8 @f2(<16 x i8> %val) { +; CHECK-LABEL: f2: +; CHECK: vlgvb %r2, %v24, 15 +; CHECK: br %r14 + %ret = extractelement <16 x i8> %val, i32 15 + ret i8 %ret +} + +; Test v16i8 extractions of an absurd element number. This must compile +; but we don't care what it does. +define i8 @f3(<16 x i8> %val) { +; CHECK-LABEL: f3: +; CHECK-NOT: vlgvb %r2, %v24, 100000 +; CHECK: br %r14 + %ret = extractelement <16 x i8> %val, i32 100000 + ret i8 %ret +} + +; Test v16i8 extraction of a variable element. +define i8 @f4(<16 x i8> %val, i32 %index) { +; CHECK-LABEL: f4: +; CHECK: vlgvb %r2, %v24, 0(%r2) +; CHECK: br %r14 + %ret = extractelement <16 x i8> %val, i32 %index + ret i8 %ret +} + +; Test v8i16 extraction of the first element. +define i16 @f5(<8 x i16> %val) { +; CHECK-LABEL: f5: +; CHECK: vlgvh %r2, %v24, 0 +; CHECK: br %r14 + %ret = extractelement <8 x i16> %val, i32 0 + ret i16 %ret +} + +; Test v8i16 extraction of the last element. +define i16 @f6(<8 x i16> %val) { +; CHECK-LABEL: f6: +; CHECK: vlgvh %r2, %v24, 7 +; CHECK: br %r14 + %ret = extractelement <8 x i16> %val, i32 7 + ret i16 %ret +} + +; Test v8i16 extractions of an absurd element number. This must compile +; but we don't care what it does. +define i16 @f7(<8 x i16> %val) { +; CHECK-LABEL: f7: +; CHECK-NOT: vlgvh %r2, %v24, 100000 +; CHECK: br %r14 + %ret = extractelement <8 x i16> %val, i32 100000 + ret i16 %ret +} + +; Test v8i16 extraction of a variable element. +define i16 @f8(<8 x i16> %val, i32 %index) { +; CHECK-LABEL: f8: +; CHECK: vlgvh %r2, %v24, 0(%r2) +; CHECK: br %r14 + %ret = extractelement <8 x i16> %val, i32 %index + ret i16 %ret +} + +; Test v4i32 extraction of the first element. +define i32 @f9(<4 x i32> %val) { +; CHECK-LABEL: f9: +; CHECK: vlgvf %r2, %v24, 0 +; CHECK: br %r14 + %ret = extractelement <4 x i32> %val, i32 0 + ret i32 %ret +} + +; Test v4i32 extraction of the last element. +define i32 @f10(<4 x i32> %val) { +; CHECK-LABEL: f10: +; CHECK: vlgvf %r2, %v24, 3 +; CHECK: br %r14 + %ret = extractelement <4 x i32> %val, i32 3 + ret i32 %ret +} + +; Test v4i32 extractions of an absurd element number. This must compile +; but we don't care what it does. +define i32 @f11(<4 x i32> %val) { +; CHECK-LABEL: f11: +; CHECK-NOT: vlgvf %r2, %v24, 100000 +; CHECK: br %r14 + %ret = extractelement <4 x i32> %val, i32 100000 + ret i32 %ret +} + +; Test v4i32 extraction of a variable element. +define i32 @f12(<4 x i32> %val, i32 %index) { +; CHECK-LABEL: f12: +; CHECK: vlgvf %r2, %v24, 0(%r2) +; CHECK: br %r14 + %ret = extractelement <4 x i32> %val, i32 %index + ret i32 %ret +} + +; Test v2i64 extraction of the first element. +define i64 @f13(<2 x i64> %val) { +; CHECK-LABEL: f13: +; CHECK: vlgvg %r2, %v24, 0 +; CHECK: br %r14 + %ret = extractelement <2 x i64> %val, i32 0 + ret i64 %ret +} + +; Test v2i64 extraction of the last element. +define i64 @f14(<2 x i64> %val) { +; CHECK-LABEL: f14: +; CHECK: vlgvg %r2, %v24, 1 +; CHECK: br %r14 + %ret = extractelement <2 x i64> %val, i32 1 + ret i64 %ret +} + +; Test v2i64 extractions of an absurd element number. This must compile +; but we don't care what it does. +define i64 @f15(<2 x i64> %val) { +; CHECK-LABEL: f15: +; CHECK-NOT: vlgvg %r2, %v24, 100000 +; CHECK: br %r14 + %ret = extractelement <2 x i64> %val, i32 100000 + ret i64 %ret +} + +; Test v2i64 extraction of a variable element. +define i64 @f16(<2 x i64> %val, i32 %index) { +; CHECK-LABEL: f16: +; CHECK: vlgvg %r2, %v24, 0(%r2) +; CHECK: br %r14 + %ret = extractelement <2 x i64> %val, i32 %index + ret i64 %ret +} + +; Test v4f32 extraction of element 0. +define float @f17(<4 x float> %val) { +; CHECK-LABEL: f17: +; CHECK: vlr %v0, %v24 +; CHECK: br %r14 + %ret = extractelement <4 x float> %val, i32 0 + ret float %ret +} + +; Test v4f32 extraction of element 1. +define float @f18(<4 x float> %val) { +; CHECK-LABEL: f18: +; CHECK: vrepf %v0, %v24, 1 +; CHECK: br %r14 + %ret = extractelement <4 x float> %val, i32 1 + ret float %ret +} + +; Test v4f32 extraction of element 2. +define float @f19(<4 x float> %val) { +; CHECK-LABEL: f19: +; CHECK: vrepf %v0, %v24, 2 +; CHECK: br %r14 + %ret = extractelement <4 x float> %val, i32 2 + ret float %ret +} + +; Test v4f32 extraction of element 3. +define float @f20(<4 x float> %val) { +; CHECK-LABEL: f20: +; CHECK: vrepf %v0, %v24, 3 +; CHECK: br %r14 + %ret = extractelement <4 x float> %val, i32 3 + ret float %ret +} + +; Test v4f32 extractions of an absurd element number. This must compile +; but we don't care what it does. +define float @f21(<4 x float> %val) { + %ret = extractelement <4 x float> %val, i32 100000 + ret float %ret +} + +; Test v4f32 extraction of a variable element. +define float @f22(<4 x float> %val, i32 %index) { +; CHECK-LABEL: f22: +; CHECK: vlgvf [[REG:%r[0-5]]], %v24, 0(%r2) +; CHECK: vlvgf %v0, [[REG]], 0 +; CHECK: br %r14 + %ret = extractelement <4 x float> %val, i32 %index + ret float %ret +} + +; Test v2f64 extraction of the first element. +define double @f23(<2 x double> %val) { +; CHECK-LABEL: f23: +; CHECK: vlr %v0, %v24 +; CHECK: br %r14 + %ret = extractelement <2 x double> %val, i32 0 + ret double %ret +} + +; Test v2f64 extraction of the last element. +define double @f24(<2 x double> %val) { +; CHECK-LABEL: f24: +; CHECK: vrepg %v0, %v24, 1 +; CHECK: br %r14 + %ret = extractelement <2 x double> %val, i32 1 + ret double %ret +} + +; Test v2f64 extractions of an absurd element number. This must compile +; but we don't care what it does. +define double @f25(<2 x double> %val) { + %ret = extractelement <2 x double> %val, i32 100000 + ret double %ret +} + +; Test v2f64 extraction of a variable element. +define double @f26(<2 x double> %val, i32 %index) { +; CHECK-LABEL: f26: +; CHECK: vlgvg [[REG:%r[0-5]]], %v24, 0(%r2) +; CHECK: ldgr %f0, [[REG]] +; CHECK: br %r14 + %ret = extractelement <2 x double> %val, i32 %index + ret double %ret +} + +; Test v16i8 extraction of a variable element with an offset. +define i8 @f27(<16 x i8> %val, i32 %index) { +; CHECK-LABEL: f27: +; CHECK: vlgvb %r2, %v24, 1(%r2) +; CHECK: br %r14 + %add = add i32 %index, 1 + %ret = extractelement <16 x i8> %val, i32 %add + ret i8 %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-06.ll b/test/CodeGen/SystemZ/vec-move-06.ll new file mode 100644 index 000000000000..de3960cad956 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-06.ll @@ -0,0 +1,13 @@ +; Test vector builds using VLVGP. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test the basic v2i64 usage. +define <2 x i64> @f1(i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK: vlvgp %v24, %r2, %r3 +; CHECK: br %r14 + %veca = insertelement <2 x i64> undef, i64 %a, i32 0 + %vecb = insertelement <2 x i64> %veca, i64 %b, i32 1 + ret <2 x i64> %vecb +} diff --git a/test/CodeGen/SystemZ/vec-move-07.ll b/test/CodeGen/SystemZ/vec-move-07.ll new file mode 100644 index 000000000000..b0d06f782dee --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-07.ll @@ -0,0 +1,57 @@ +; Test scalar_to_vector expansion. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8. +define <16 x i8> @f1(i8 %val) { +; CHECK-LABEL: f1: +; CHECK: vlvgb %v24, %r2, 0 +; CHECK: br %r14 + %ret = insertelement <16 x i8> undef, i8 %val, i32 0 + ret <16 x i8> %ret +} + +; Test v8i16. +define <8 x i16> @f2(i16 %val) { +; CHECK-LABEL: f2: +; CHECK: vlvgh %v24, %r2, 0 +; CHECK: br %r14 + %ret = insertelement <8 x i16> undef, i16 %val, i32 0 + ret <8 x i16> %ret +} + +; Test v4i32. +define <4 x i32> @f3(i32 %val) { +; CHECK-LABEL: f3: +; CHECK: vlvgf %v24, %r2, 0 +; CHECK: br %r14 + %ret = insertelement <4 x i32> undef, i32 %val, i32 0 + ret <4 x i32> %ret +} + +; Test v2i64. Here we load %val into both halves. +define <2 x i64> @f4(i64 %val) { +; CHECK-LABEL: f4: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK: br %r14 + %ret = insertelement <2 x i64> undef, i64 %val, i32 0 + ret <2 x i64> %ret +} + +; Test v4f32, which is just a move. +define <4 x float> @f5(float %val) { +; CHECK-LABEL: f5: +; CHECK: vlr %v24, %v0 +; CHECK: br %r14 + %ret = insertelement <4 x float> undef, float %val, i32 0 + ret <4 x float> %ret +} + +; Likewise v2f64. +define <2 x double> @f6(double %val) { +; CHECK-LABEL: f6: +; CHECK: vlr %v24, %v0 +; CHECK: br %r14 + %ret = insertelement <2 x double> undef, double %val, i32 0 + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-08.ll b/test/CodeGen/SystemZ/vec-move-08.ll new file mode 100644 index 000000000000..5396a1edec6a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-08.ll @@ -0,0 +1,444 @@ +; Test vector insertion of memory values. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 insertion into the first element. +define <16 x i8> @f1(<16 x i8> %val, i8 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vleb %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = load i8, i8 *%ptr + %ret = insertelement <16 x i8> %val, i8 %element, i32 0 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into the last element. +define <16 x i8> @f2(<16 x i8> %val, i8 *%ptr) { +; CHECK-LABEL: f2: +; CHECK: vleb %v24, 0(%r2), 15 +; CHECK: br %r14 + %element = load i8, i8 *%ptr + %ret = insertelement <16 x i8> %val, i8 %element, i32 15 + ret <16 x i8> %ret +} + +; Test v16i8 insertion with the highest in-range offset. +define <16 x i8> @f3(<16 x i8> %val, i8 *%base) { +; CHECK-LABEL: f3: +; CHECK: vleb %v24, 4095(%r2), 10 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i32 4095 + %element = load i8, i8 *%ptr + %ret = insertelement <16 x i8> %val, i8 %element, i32 10 + ret <16 x i8> %ret +} + +; Test v16i8 insertion with the first ouf-of-range offset. +define <16 x i8> @f4(<16 x i8> %val, i8 *%base) { +; CHECK-LABEL: f4: +; CHECK: aghi %r2, 4096 +; CHECK: vleb %v24, 0(%r2), 5 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i32 4096 + %element = load i8, i8 *%ptr + %ret = insertelement <16 x i8> %val, i8 %element, i32 5 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into a variable element. +define <16 x i8> @f5(<16 x i8> %val, i8 *%ptr, i32 %index) { +; CHECK-LABEL: f5: +; CHECK-NOT: vleb +; CHECK: br %r14 + %element = load i8, i8 *%ptr + %ret = insertelement <16 x i8> %val, i8 %element, i32 %index + ret <16 x i8> %ret +} + +; Test v8i16 insertion into the first element. +define <8 x i16> @f6(<8 x i16> %val, i16 *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vleh %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = load i16, i16 *%ptr + %ret = insertelement <8 x i16> %val, i16 %element, i32 0 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into the last element. +define <8 x i16> @f7(<8 x i16> %val, i16 *%ptr) { +; CHECK-LABEL: f7: +; CHECK: vleh %v24, 0(%r2), 7 +; CHECK: br %r14 + %element = load i16, i16 *%ptr + %ret = insertelement <8 x i16> %val, i16 %element, i32 7 + ret <8 x i16> %ret +} + +; Test v8i16 insertion with the highest in-range offset. +define <8 x i16> @f8(<8 x i16> %val, i16 *%base) { +; CHECK-LABEL: f8: +; CHECK: vleh %v24, 4094(%r2), 5 +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%base, i32 2047 + %element = load i16, i16 *%ptr + %ret = insertelement <8 x i16> %val, i16 %element, i32 5 + ret <8 x i16> %ret +} + +; Test v8i16 insertion with the first ouf-of-range offset. +define <8 x i16> @f9(<8 x i16> %val, i16 *%base) { +; CHECK-LABEL: f9: +; CHECK: aghi %r2, 4096 +; CHECK: vleh %v24, 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%base, i32 2048 + %element = load i16, i16 *%ptr + %ret = insertelement <8 x i16> %val, i16 %element, i32 1 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into a variable element. +define <8 x i16> @f10(<8 x i16> %val, i16 *%ptr, i32 %index) { +; CHECK-LABEL: f10: +; CHECK-NOT: vleh +; CHECK: br %r14 + %element = load i16, i16 *%ptr + %ret = insertelement <8 x i16> %val, i16 %element, i32 %index + ret <8 x i16> %ret +} + +; Test v4i32 insertion into the first element. +define <4 x i32> @f11(<4 x i32> %val, i32 *%ptr) { +; CHECK-LABEL: f11: +; CHECK: vlef %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 0 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into the last element. +define <4 x i32> @f12(<4 x i32> %val, i32 *%ptr) { +; CHECK-LABEL: f12: +; CHECK: vlef %v24, 0(%r2), 3 +; CHECK: br %r14 + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 3 + ret <4 x i32> %ret +} + +; Test v4i32 insertion with the highest in-range offset. +define <4 x i32> @f13(<4 x i32> %val, i32 *%base) { +; CHECK-LABEL: f13: +; CHECK: vlef %v24, 4092(%r2), 2 +; CHECK: br %r14 + %ptr = getelementptr i32, i32 *%base, i32 1023 + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 2 + ret <4 x i32> %ret +} + +; Test v4i32 insertion with the first ouf-of-range offset. +define <4 x i32> @f14(<4 x i32> %val, i32 *%base) { +; CHECK-LABEL: f14: +; CHECK: aghi %r2, 4096 +; CHECK: vlef %v24, 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i32, i32 *%base, i32 1024 + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 1 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into a variable element. +define <4 x i32> @f15(<4 x i32> %val, i32 *%ptr, i32 %index) { +; CHECK-LABEL: f15: +; CHECK-NOT: vlef +; CHECK: br %r14 + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 %index + ret <4 x i32> %ret +} + +; Test v2i64 insertion into the first element. +define <2 x i64> @f16(<2 x i64> %val, i64 *%ptr) { +; CHECK-LABEL: f16: +; CHECK: vleg %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = load i64, i64 *%ptr + %ret = insertelement <2 x i64> %val, i64 %element, i32 0 + ret <2 x i64> %ret +} + +; Test v2i64 insertion into the last element. +define <2 x i64> @f17(<2 x i64> %val, i64 *%ptr) { +; CHECK-LABEL: f17: +; CHECK: vleg %v24, 0(%r2), 1 +; CHECK: br %r14 + %element = load i64, i64 *%ptr + %ret = insertelement <2 x i64> %val, i64 %element, i32 1 + ret <2 x i64> %ret +} + +; Test v2i64 insertion with the highest in-range offset. +define <2 x i64> @f18(<2 x i64> %val, i64 *%base) { +; CHECK-LABEL: f18: +; CHECK: vleg %v24, 4088(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i32 511 + %element = load i64, i64 *%ptr + %ret = insertelement <2 x i64> %val, i64 %element, i32 1 + ret <2 x i64> %ret +} + +; Test v2i64 insertion with the first ouf-of-range offset. +define <2 x i64> @f19(<2 x i64> %val, i64 *%base) { +; CHECK-LABEL: f19: +; CHECK: aghi %r2, 4096 +; CHECK: vleg %v24, 0(%r2), 0 +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i32 512 + %element = load i64, i64 *%ptr + %ret = insertelement <2 x i64> %val, i64 %element, i32 0 + ret <2 x i64> %ret +} + +; Test v2i64 insertion into a variable element. +define <2 x i64> @f20(<2 x i64> %val, i64 *%ptr, i32 %index) { +; CHECK-LABEL: f20: +; CHECK-NOT: vleg +; CHECK: br %r14 + %element = load i64, i64 *%ptr + %ret = insertelement <2 x i64> %val, i64 %element, i32 %index + ret <2 x i64> %ret +} + +; Test v4f32 insertion into the first element. +define <4 x float> @f21(<4 x float> %val, float *%ptr) { +; CHECK-LABEL: f21: +; CHECK: vlef %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = load float, float *%ptr + %ret = insertelement <4 x float> %val, float %element, i32 0 + ret <4 x float> %ret +} + +; Test v4f32 insertion into the last element. +define <4 x float> @f22(<4 x float> %val, float *%ptr) { +; CHECK-LABEL: f22: +; CHECK: vlef %v24, 0(%r2), 3 +; CHECK: br %r14 + %element = load float, float *%ptr + %ret = insertelement <4 x float> %val, float %element, i32 3 + ret <4 x float> %ret +} + +; Test v4f32 insertion with the highest in-range offset. +define <4 x float> @f23(<4 x float> %val, float *%base) { +; CHECK-LABEL: f23: +; CHECK: vlef %v24, 4092(%r2), 2 +; CHECK: br %r14 + %ptr = getelementptr float, float *%base, i32 1023 + %element = load float, float *%ptr + %ret = insertelement <4 x float> %val, float %element, i32 2 + ret <4 x float> %ret +} + +; Test v4f32 insertion with the first ouf-of-range offset. +define <4 x float> @f24(<4 x float> %val, float *%base) { +; CHECK-LABEL: f24: +; CHECK: aghi %r2, 4096 +; CHECK: vlef %v24, 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr float, float *%base, i32 1024 + %element = load float, float *%ptr + %ret = insertelement <4 x float> %val, float %element, i32 1 + ret <4 x float> %ret +} + +; Test v4f32 insertion into a variable element. +define <4 x float> @f25(<4 x float> %val, float *%ptr, i32 %index) { +; CHECK-LABEL: f25: +; CHECK-NOT: vlef +; CHECK: br %r14 + %element = load float, float *%ptr + %ret = insertelement <4 x float> %val, float %element, i32 %index + ret <4 x float> %ret +} + +; Test v2f64 insertion into the first element. +define <2 x double> @f26(<2 x double> %val, double *%ptr) { +; CHECK-LABEL: f26: +; CHECK: vleg %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = load double, double *%ptr + %ret = insertelement <2 x double> %val, double %element, i32 0 + ret <2 x double> %ret +} + +; Test v2f64 insertion into the last element. +define <2 x double> @f27(<2 x double> %val, double *%ptr) { +; CHECK-LABEL: f27: +; CHECK: vleg %v24, 0(%r2), 1 +; CHECK: br %r14 + %element = load double, double *%ptr + %ret = insertelement <2 x double> %val, double %element, i32 1 + ret <2 x double> %ret +} + +; Test v2f64 insertion with the highest in-range offset. +define <2 x double> @f28(<2 x double> %val, double *%base) { +; CHECK-LABEL: f28: +; CHECK: vleg %v24, 4088(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr double, double *%base, i32 511 + %element = load double, double *%ptr + %ret = insertelement <2 x double> %val, double %element, i32 1 + ret <2 x double> %ret +} + +; Test v2f64 insertion with the first ouf-of-range offset. +define <2 x double> @f29(<2 x double> %val, double *%base) { +; CHECK-LABEL: f29: +; CHECK: aghi %r2, 4096 +; CHECK: vleg %v24, 0(%r2), 0 +; CHECK: br %r14 + %ptr = getelementptr double, double *%base, i32 512 + %element = load double, double *%ptr + %ret = insertelement <2 x double> %val, double %element, i32 0 + ret <2 x double> %ret +} + +; Test v2f64 insertion into a variable element. +define <2 x double> @f30(<2 x double> %val, double *%ptr, i32 %index) { +; CHECK-LABEL: f30: +; CHECK-NOT: vleg +; CHECK: br %r14 + %element = load double, double *%ptr + %ret = insertelement <2 x double> %val, double %element, i32 %index + ret <2 x double> %ret +} + +; Test a v4i32 gather of the first element. +define <4 x i32> @f31(<4 x i32> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f31: +; CHECK: vgef %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 0 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to i32 * + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 0 + ret <4 x i32> %ret +} + +; Test a v4i32 gather of the last element. +define <4 x i32> @f32(<4 x i32> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f32: +; CHECK: vgef %v24, 0(%v26,%r2), 3 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 3 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to i32 * + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 3 + ret <4 x i32> %ret +} + +; Test a v4i32 gather with the highest in-range offset. +define <4 x i32> @f33(<4 x i32> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f33: +; CHECK: vgef %v24, 4095(%v26,%r2), 1 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 1 + %ext = zext i32 %elem to i64 + %add1 = add i64 %base, %ext + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i32 * + %element = load i32, i32 *%ptr + %ret = insertelement <4 x i32> %val, i32 %element, i32 1 + ret <4 x i32> %ret +} + +; Test a v2i64 gather of the first element. +define <2 x i64> @f34(<2 x i64> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f34: +; CHECK: vgeg %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 0 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to i64 * + %element = load i64, i64 *%ptr + %ret = insertelement <2 x i64> %val, i64 %element, i32 0 + ret <2 x i64> %ret +} + +; Test a v2i64 gather of the last element. +define <2 x i64> @f35(<2 x i64> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f35: +; CHECK: vgeg %v24, 0(%v26,%r2), 1 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 1 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to i64 * + %element = load i64, i64 *%ptr + %ret = insertelement <2 x i64> %val, i64 %element, i32 1 + ret <2 x i64> %ret +} + +; Test a v4f32 gather of the first element. +define <4 x float> @f36(<4 x float> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f36: +; CHECK: vgef %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 0 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to float * + %element = load float, float *%ptr + %ret = insertelement <4 x float> %val, float %element, i32 0 + ret <4 x float> %ret +} + +; Test a v4f32 gather of the last element. +define <4 x float> @f37(<4 x float> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f37: +; CHECK: vgef %v24, 0(%v26,%r2), 3 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 3 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to float * + %element = load float, float *%ptr + %ret = insertelement <4 x float> %val, float %element, i32 3 + ret <4 x float> %ret +} + +; Test a v2f64 gather of the first element. +define <2 x double> @f38(<2 x double> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f38: +; CHECK: vgeg %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 0 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to double * + %element = load double, double *%ptr + %ret = insertelement <2 x double> %val, double %element, i32 0 + ret <2 x double> %ret +} + +; Test a v2f64 gather of the last element. +define <2 x double> @f39(<2 x double> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f39: +; CHECK: vgeg %v24, 0(%v26,%r2), 1 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 1 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to double * + %element = load double, double *%ptr + %ret = insertelement <2 x double> %val, double %element, i32 1 + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-09.ll b/test/CodeGen/SystemZ/vec-move-09.ll new file mode 100644 index 000000000000..5a53a2d6a198 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-09.ll @@ -0,0 +1,291 @@ +; Test vector insertion of constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 insertion into the first element. +define <16 x i8> @f1(<16 x i8> %val) { +; CHECK-LABEL: f1: +; CHECK: vleib %v24, 0, 0 +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 0, i32 0 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into the last element. +define <16 x i8> @f2(<16 x i8> %val) { +; CHECK-LABEL: f2: +; CHECK: vleib %v24, 100, 15 +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 100, i32 15 + ret <16 x i8> %ret +} + +; Test v16i8 insertion with the maximum signed value. +define <16 x i8> @f3(<16 x i8> %val) { +; CHECK-LABEL: f3: +; CHECK: vleib %v24, 127, 10 +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 127, i32 10 + ret <16 x i8> %ret +} + +; Test v16i8 insertion with the minimum signed value. +define <16 x i8> @f4(<16 x i8> %val) { +; CHECK-LABEL: f4: +; CHECK: vleib %v24, -128, 11 +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 128, i32 11 + ret <16 x i8> %ret +} + +; Test v16i8 insertion with the maximum unsigned value. +define <16 x i8> @f5(<16 x i8> %val) { +; CHECK-LABEL: f5: +; CHECK: vleib %v24, -1, 12 +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 255, i32 12 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into a variable element. +define <16 x i8> @f6(<16 x i8> %val, i32 %index) { +; CHECK-LABEL: f6: +; CHECK-NOT: vleib +; CHECK: br %r14 + %ret = insertelement <16 x i8> %val, i8 0, i32 %index + ret <16 x i8> %ret +} + +; Test v8i16 insertion into the first element. +define <8 x i16> @f7(<8 x i16> %val) { +; CHECK-LABEL: f7: +; CHECK: vleih %v24, 0, 0 +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 0, i32 0 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into the last element. +define <8 x i16> @f8(<8 x i16> %val) { +; CHECK-LABEL: f8: +; CHECK: vleih %v24, 0, 7 +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 0, i32 7 + ret <8 x i16> %ret +} + +; Test v8i16 insertion with the maximum signed value. +define <8 x i16> @f9(<8 x i16> %val) { +; CHECK-LABEL: f9: +; CHECK: vleih %v24, 32767, 4 +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 32767, i32 4 + ret <8 x i16> %ret +} + +; Test v8i16 insertion with the minimum signed value. +define <8 x i16> @f10(<8 x i16> %val) { +; CHECK-LABEL: f10: +; CHECK: vleih %v24, -32768, 5 +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 32768, i32 5 + ret <8 x i16> %ret +} + +; Test v8i16 insertion with the maximum unsigned value. +define <8 x i16> @f11(<8 x i16> %val) { +; CHECK-LABEL: f11: +; CHECK: vleih %v24, -1, 6 +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 65535, i32 6 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into a variable element. +define <8 x i16> @f12(<8 x i16> %val, i32 %index) { +; CHECK-LABEL: f12: +; CHECK-NOT: vleih +; CHECK: br %r14 + %ret = insertelement <8 x i16> %val, i16 0, i32 %index + ret <8 x i16> %ret +} + +; Test v4i32 insertion into the first element. +define <4 x i32> @f13(<4 x i32> %val) { +; CHECK-LABEL: f13: +; CHECK: vleif %v24, 0, 0 +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 0, i32 0 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into the last element. +define <4 x i32> @f14(<4 x i32> %val) { +; CHECK-LABEL: f14: +; CHECK: vleif %v24, 0, 3 +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 0, i32 3 + ret <4 x i32> %ret +} + +; Test v4i32 insertion with the maximum value allowed by VLEIF. +define <4 x i32> @f15(<4 x i32> %val) { +; CHECK-LABEL: f15: +; CHECK: vleif %v24, 32767, 1 +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 32767, i32 1 + ret <4 x i32> %ret +} + +; Test v4i32 insertion with the next value up. +define <4 x i32> @f16(<4 x i32> %val) { +; CHECK-LABEL: f16: +; CHECK-NOT: vleif +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 32768, i32 1 + ret <4 x i32> %ret +} + +; Test v4i32 insertion with the minimum value allowed by VLEIF. +define <4 x i32> @f17(<4 x i32> %val) { +; CHECK-LABEL: f17: +; CHECK: vleif %v24, -32768, 2 +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 -32768, i32 2 + ret <4 x i32> %ret +} + +; Test v4i32 insertion with the next value down. +define <4 x i32> @f18(<4 x i32> %val) { +; CHECK-LABEL: f18: +; CHECK-NOT: vleif +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 -32769, i32 2 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into a variable element. +define <4 x i32> @f19(<4 x i32> %val, i32 %index) { +; CHECK-LABEL: f19: +; CHECK-NOT: vleif +; CHECK: br %r14 + %ret = insertelement <4 x i32> %val, i32 0, i32 %index + ret <4 x i32> %ret +} + +; Test v2i64 insertion into the first element. +define <2 x i64> @f20(<2 x i64> %val) { +; CHECK-LABEL: f20: +; CHECK: vleig %v24, 0, 0 +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 0, i32 0 + ret <2 x i64> %ret +} + +; Test v2i64 insertion into the last element. +define <2 x i64> @f21(<2 x i64> %val) { +; CHECK-LABEL: f21: +; CHECK: vleig %v24, 0, 1 +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 0, i32 1 + ret <2 x i64> %ret +} + +; Test v2i64 insertion with the maximum value allowed by VLEIG. +define <2 x i64> @f22(<2 x i64> %val) { +; CHECK-LABEL: f22: +; CHECK: vleig %v24, 32767, 1 +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 32767, i32 1 + ret <2 x i64> %ret +} + +; Test v2i64 insertion with the next value up. +define <2 x i64> @f23(<2 x i64> %val) { +; CHECK-LABEL: f23: +; CHECK-NOT: vleig +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 32768, i32 1 + ret <2 x i64> %ret +} + +; Test v2i64 insertion with the minimum value allowed by VLEIG. +define <2 x i64> @f24(<2 x i64> %val) { +; CHECK-LABEL: f24: +; CHECK: vleig %v24, -32768, 0 +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 -32768, i32 0 + ret <2 x i64> %ret +} + +; Test v2i64 insertion with the next value down. +define <2 x i64> @f25(<2 x i64> %val) { +; CHECK-LABEL: f25: +; CHECK-NOT: vleig +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 -32769, i32 0 + ret <2 x i64> %ret +} + +; Test v2i64 insertion into a variable element. +define <2 x i64> @f26(<2 x i64> %val, i32 %index) { +; CHECK-LABEL: f26: +; CHECK-NOT: vleig +; CHECK: br %r14 + %ret = insertelement <2 x i64> %val, i64 0, i32 %index + ret <2 x i64> %ret +} + +; Test v4f32 insertion of 0 into the first element. +define <4 x float> @f27(<4 x float> %val) { +; CHECK-LABEL: f27: +; CHECK: vleif %v24, 0, 0 +; CHECK: br %r14 + %ret = insertelement <4 x float> %val, float 0.0, i32 0 + ret <4 x float> %ret +} + +; Test v4f32 insertion of 0 into the last element. +define <4 x float> @f28(<4 x float> %val) { +; CHECK-LABEL: f28: +; CHECK: vleif %v24, 0, 3 +; CHECK: br %r14 + %ret = insertelement <4 x float> %val, float 0.0, i32 3 + ret <4 x float> %ret +} + +; Test v4f32 insertion of a nonzero value. +define <4 x float> @f29(<4 x float> %val) { +; CHECK-LABEL: f29: +; CHECK-NOT: vleif +; CHECK: br %r14 + %ret = insertelement <4 x float> %val, float 1.0, i32 1 + ret <4 x float> %ret +} + +; Test v2f64 insertion of 0 into the first element. +define <2 x double> @f30(<2 x double> %val) { +; CHECK-LABEL: f30: +; CHECK: vleig %v24, 0, 0 +; CHECK: br %r14 + %ret = insertelement <2 x double> %val, double 0.0, i32 0 + ret <2 x double> %ret +} + +; Test v2f64 insertion of 0 into the last element. +define <2 x double> @f31(<2 x double> %val) { +; CHECK-LABEL: f31: +; CHECK: vleig %v24, 0, 1 +; CHECK: br %r14 + %ret = insertelement <2 x double> %val, double 0.0, i32 1 + ret <2 x double> %ret +} + +; Test v2f64 insertion of a nonzero value. +define <2 x double> @f32(<2 x double> %val) { +; CHECK-LABEL: f32: +; CHECK-NOT: vleig +; CHECK: br %r14 + %ret = insertelement <2 x double> %val, double 1.0, i32 1 + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-10.ll b/test/CodeGen/SystemZ/vec-move-10.ll new file mode 100644 index 000000000000..894d0c2b41fa --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-10.ll @@ -0,0 +1,499 @@ +; Test vector extraction to memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 extraction from the first element. +define void @f1(<16 x i8> %val, i8 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vsteb %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = extractelement <16 x i8> %val, i32 0 + store i8 %element, i8 *%ptr + ret void +} + +; Test v16i8 extraction from the last element. +define void @f2(<16 x i8> %val, i8 *%ptr) { +; CHECK-LABEL: f2: +; CHECK: vsteb %v24, 0(%r2), 15 +; CHECK: br %r14 + %element = extractelement <16 x i8> %val, i32 15 + store i8 %element, i8 *%ptr + ret void +} + +; Test v16i8 extraction of an invalid element. This must compile, +; but we don't care what it does. +define void @f3(<16 x i8> %val, i8 *%ptr) { +; CHECK-LABEL: f3: +; CHECK-NOT: vsteb %v24, 0(%r2), 16 +; CHECK: br %r14 + %element = extractelement <16 x i8> %val, i32 16 + store i8 %element, i8 *%ptr + ret void +} + +; Test v16i8 extraction with the highest in-range offset. +define void @f4(<16 x i8> %val, i8 *%base) { +; CHECK-LABEL: f4: +; CHECK: vsteb %v24, 4095(%r2), 10 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i32 4095 + %element = extractelement <16 x i8> %val, i32 10 + store i8 %element, i8 *%ptr + ret void +} + +; Test v16i8 extraction with the first ouf-of-range offset. +define void @f5(<16 x i8> %val, i8 *%base) { +; CHECK-LABEL: f5: +; CHECK: aghi %r2, 4096 +; CHECK: vsteb %v24, 0(%r2), 5 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i32 4096 + %element = extractelement <16 x i8> %val, i32 5 + store i8 %element, i8 *%ptr + ret void +} + +; Test v16i8 extraction from a variable element. +define void @f6(<16 x i8> %val, i8 *%ptr, i32 %index) { +; CHECK-LABEL: f6: +; CHECK-NOT: vsteb +; CHECK: br %r14 + %element = extractelement <16 x i8> %val, i32 %index + store i8 %element, i8 *%ptr + ret void +} + +; Test v8i16 extraction from the first element. +define void @f7(<8 x i16> %val, i16 *%ptr) { +; CHECK-LABEL: f7: +; CHECK: vsteh %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = extractelement <8 x i16> %val, i32 0 + store i16 %element, i16 *%ptr + ret void +} + +; Test v8i16 extraction from the last element. +define void @f8(<8 x i16> %val, i16 *%ptr) { +; CHECK-LABEL: f8: +; CHECK: vsteh %v24, 0(%r2), 7 +; CHECK: br %r14 + %element = extractelement <8 x i16> %val, i32 7 + store i16 %element, i16 *%ptr + ret void +} + +; Test v8i16 extraction of an invalid element. This must compile, +; but we don't care what it does. +define void @f9(<8 x i16> %val, i16 *%ptr) { +; CHECK-LABEL: f9: +; CHECK-NOT: vsteh %v24, 0(%r2), 8 +; CHECK: br %r14 + %element = extractelement <8 x i16> %val, i32 8 + store i16 %element, i16 *%ptr + ret void +} + +; Test v8i16 extraction with the highest in-range offset. +define void @f10(<8 x i16> %val, i16 *%base) { +; CHECK-LABEL: f10: +; CHECK: vsteh %v24, 4094(%r2), 5 +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%base, i32 2047 + %element = extractelement <8 x i16> %val, i32 5 + store i16 %element, i16 *%ptr + ret void +} + +; Test v8i16 extraction with the first ouf-of-range offset. +define void @f11(<8 x i16> %val, i16 *%base) { +; CHECK-LABEL: f11: +; CHECK: aghi %r2, 4096 +; CHECK: vsteh %v24, 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%base, i32 2048 + %element = extractelement <8 x i16> %val, i32 1 + store i16 %element, i16 *%ptr + ret void +} + +; Test v8i16 extraction from a variable element. +define void @f12(<8 x i16> %val, i16 *%ptr, i32 %index) { +; CHECK-LABEL: f12: +; CHECK-NOT: vsteh +; CHECK: br %r14 + %element = extractelement <8 x i16> %val, i32 %index + store i16 %element, i16 *%ptr + ret void +} + +; Test v4i32 extraction from the first element. +define void @f13(<4 x i32> %val, i32 *%ptr) { +; CHECK-LABEL: f13: +; CHECK: vstef %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = extractelement <4 x i32> %val, i32 0 + store i32 %element, i32 *%ptr + ret void +} + +; Test v4i32 extraction from the last element. +define void @f14(<4 x i32> %val, i32 *%ptr) { +; CHECK-LABEL: f14: +; CHECK: vstef %v24, 0(%r2), 3 +; CHECK: br %r14 + %element = extractelement <4 x i32> %val, i32 3 + store i32 %element, i32 *%ptr + ret void +} + +; Test v4i32 extraction of an invalid element. This must compile, +; but we don't care what it does. +define void @f15(<4 x i32> %val, i32 *%ptr) { +; CHECK-LABEL: f15: +; CHECK-NOT: vstef %v24, 0(%r2), 4 +; CHECK: br %r14 + %element = extractelement <4 x i32> %val, i32 4 + store i32 %element, i32 *%ptr + ret void +} + +; Test v4i32 extraction with the highest in-range offset. +define void @f16(<4 x i32> %val, i32 *%base) { +; CHECK-LABEL: f16: +; CHECK: vstef %v24, 4092(%r2), 2 +; CHECK: br %r14 + %ptr = getelementptr i32, i32 *%base, i32 1023 + %element = extractelement <4 x i32> %val, i32 2 + store i32 %element, i32 *%ptr + ret void +} + +; Test v4i32 extraction with the first ouf-of-range offset. +define void @f17(<4 x i32> %val, i32 *%base) { +; CHECK-LABEL: f17: +; CHECK: aghi %r2, 4096 +; CHECK: vstef %v24, 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i32, i32 *%base, i32 1024 + %element = extractelement <4 x i32> %val, i32 1 + store i32 %element, i32 *%ptr + ret void +} + +; Test v4i32 extraction from a variable element. +define void @f18(<4 x i32> %val, i32 *%ptr, i32 %index) { +; CHECK-LABEL: f18: +; CHECK-NOT: vstef +; CHECK: br %r14 + %element = extractelement <4 x i32> %val, i32 %index + store i32 %element, i32 *%ptr + ret void +} + +; Test v2i64 extraction from the first element. +define void @f19(<2 x i64> %val, i64 *%ptr) { +; CHECK-LABEL: f19: +; CHECK: vsteg %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = extractelement <2 x i64> %val, i32 0 + store i64 %element, i64 *%ptr + ret void +} + +; Test v2i64 extraction from the last element. +define void @f20(<2 x i64> %val, i64 *%ptr) { +; CHECK-LABEL: f20: +; CHECK: vsteg %v24, 0(%r2), 1 +; CHECK: br %r14 + %element = extractelement <2 x i64> %val, i32 1 + store i64 %element, i64 *%ptr + ret void +} + +; Test v2i64 extraction of an invalid element. This must compile, +; but we don't care what it does. +define void @f21(<2 x i64> %val, i64 *%ptr) { +; CHECK-LABEL: f21: +; CHECK-NOT: vsteg %v24, 0(%r2), 2 +; CHECK: br %r14 + %element = extractelement <2 x i64> %val, i32 2 + store i64 %element, i64 *%ptr + ret void +} + +; Test v2i64 extraction with the highest in-range offset. +define void @f22(<2 x i64> %val, i64 *%base) { +; CHECK-LABEL: f22: +; CHECK: vsteg %v24, 4088(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i32 511 + %element = extractelement <2 x i64> %val, i32 1 + store i64 %element, i64 *%ptr + ret void +} + +; Test v2i64 extraction with the first ouf-of-range offset. +define void @f23(<2 x i64> %val, i64 *%base) { +; CHECK-LABEL: f23: +; CHECK: aghi %r2, 4096 +; CHECK: vsteg %v24, 0(%r2), 0 +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i32 512 + %element = extractelement <2 x i64> %val, i32 0 + store i64 %element, i64 *%ptr + ret void +} + +; Test v2i64 extraction from a variable element. +define void @f24(<2 x i64> %val, i64 *%ptr, i32 %index) { +; CHECK-LABEL: f24: +; CHECK-NOT: vsteg +; CHECK: br %r14 + %element = extractelement <2 x i64> %val, i32 %index + store i64 %element, i64 *%ptr + ret void +} + +; Test v4f32 extraction from the first element. +define void @f25(<4 x float> %val, float *%ptr) { +; CHECK-LABEL: f25: +; CHECK: vstef %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = extractelement <4 x float> %val, i32 0 + store float %element, float *%ptr + ret void +} + +; Test v4f32 extraction from the last element. +define void @f26(<4 x float> %val, float *%ptr) { +; CHECK-LABEL: f26: +; CHECK: vstef %v24, 0(%r2), 3 +; CHECK: br %r14 + %element = extractelement <4 x float> %val, i32 3 + store float %element, float *%ptr + ret void +} + +; Test v4f32 extraction of an invalid element. This must compile, +; but we don't care what it does. +define void @f27(<4 x float> %val, float *%ptr) { +; CHECK-LABEL: f27: +; CHECK-NOT: vstef %v24, 0(%r2), 4 +; CHECK: br %r14 + %element = extractelement <4 x float> %val, i32 4 + store float %element, float *%ptr + ret void +} + +; Test v4f32 extraction with the highest in-range offset. +define void @f28(<4 x float> %val, float *%base) { +; CHECK-LABEL: f28: +; CHECK: vstef %v24, 4092(%r2), 2 +; CHECK: br %r14 + %ptr = getelementptr float, float *%base, i32 1023 + %element = extractelement <4 x float> %val, i32 2 + store float %element, float *%ptr + ret void +} + +; Test v4f32 extraction with the first ouf-of-range offset. +define void @f29(<4 x float> %val, float *%base) { +; CHECK-LABEL: f29: +; CHECK: aghi %r2, 4096 +; CHECK: vstef %v24, 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr float, float *%base, i32 1024 + %element = extractelement <4 x float> %val, i32 1 + store float %element, float *%ptr + ret void +} + +; Test v4f32 extraction from a variable element. +define void @f30(<4 x float> %val, float *%ptr, i32 %index) { +; CHECK-LABEL: f30: +; CHECK-NOT: vstef +; CHECK: br %r14 + %element = extractelement <4 x float> %val, i32 %index + store float %element, float *%ptr + ret void +} + +; Test v2f64 extraction from the first element. +define void @f32(<2 x double> %val, double *%ptr) { +; CHECK-LABEL: f32: +; CHECK: vsteg %v24, 0(%r2), 0 +; CHECK: br %r14 + %element = extractelement <2 x double> %val, i32 0 + store double %element, double *%ptr + ret void +} + +; Test v2f64 extraction from the last element. +define void @f33(<2 x double> %val, double *%ptr) { +; CHECK-LABEL: f33: +; CHECK: vsteg %v24, 0(%r2), 1 +; CHECK: br %r14 + %element = extractelement <2 x double> %val, i32 1 + store double %element, double *%ptr + ret void +} + +; Test v2f64 extraction with the highest in-range offset. +define void @f34(<2 x double> %val, double *%base) { +; CHECK-LABEL: f34: +; CHECK: vsteg %v24, 4088(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr double, double *%base, i32 511 + %element = extractelement <2 x double> %val, i32 1 + store double %element, double *%ptr + ret void +} + +; Test v2f64 extraction with the first ouf-of-range offset. +define void @f35(<2 x double> %val, double *%base) { +; CHECK-LABEL: f35: +; CHECK: aghi %r2, 4096 +; CHECK: vsteg %v24, 0(%r2), 0 +; CHECK: br %r14 + %ptr = getelementptr double, double *%base, i32 512 + %element = extractelement <2 x double> %val, i32 0 + store double %element, double *%ptr + ret void +} + +; Test v2f64 extraction from a variable element. +define void @f36(<2 x double> %val, double *%ptr, i32 %index) { +; CHECK-LABEL: f36: +; CHECK-NOT: vsteg +; CHECK: br %r14 + %element = extractelement <2 x double> %val, i32 %index + store double %element, double *%ptr + ret void +} + +; Test a v4i32 scatter of the first element. +define void @f37(<4 x i32> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f37: +; CHECK: vscef %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 0 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to i32 * + %element = extractelement <4 x i32> %val, i32 0 + store i32 %element, i32 *%ptr + ret void +} + +; Test a v4i32 scatter of the last element. +define void @f38(<4 x i32> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f38: +; CHECK: vscef %v24, 0(%v26,%r2), 3 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 3 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to i32 * + %element = extractelement <4 x i32> %val, i32 3 + store i32 %element, i32 *%ptr + ret void +} + +; Test a v4i32 scatter with the highest in-range offset. +define void @f39(<4 x i32> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f39: +; CHECK: vscef %v24, 4095(%v26,%r2), 1 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 1 + %ext = zext i32 %elem to i64 + %add1 = add i64 %base, %ext + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i32 * + %element = extractelement <4 x i32> %val, i32 1 + store i32 %element, i32 *%ptr + ret void +} + +; Test a v2i64 scatter of the first element. +define void @f40(<2 x i64> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f40: +; CHECK: vsceg %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 0 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to i64 * + %element = extractelement <2 x i64> %val, i32 0 + store i64 %element, i64 *%ptr + ret void +} + +; Test a v2i64 scatter of the last element. +define void @f41(<2 x i64> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f41: +; CHECK: vsceg %v24, 0(%v26,%r2), 1 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 1 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to i64 * + %element = extractelement <2 x i64> %val, i32 1 + store i64 %element, i64 *%ptr + ret void +} + +; Test a v4f32 scatter of the first element. +define void @f42(<4 x float> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f42: +; CHECK: vscef %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 0 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to float * + %element = extractelement <4 x float> %val, i32 0 + store float %element, float *%ptr + ret void +} + +; Test a v4f32 scatter of the last element. +define void @f43(<4 x float> %val, <4 x i32> %index, i64 %base) { +; CHECK-LABEL: f43: +; CHECK: vscef %v24, 0(%v26,%r2), 3 +; CHECK: br %r14 + %elem = extractelement <4 x i32> %index, i32 3 + %ext = zext i32 %elem to i64 + %add = add i64 %base, %ext + %ptr = inttoptr i64 %add to float * + %element = extractelement <4 x float> %val, i32 3 + store float %element, float *%ptr + ret void +} + +; Test a v2f64 scatter of the first element. +define void @f44(<2 x double> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f44: +; CHECK: vsceg %v24, 0(%v26,%r2), 0 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 0 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to double * + %element = extractelement <2 x double> %val, i32 0 + store double %element, double *%ptr + ret void +} + +; Test a v2f64 scatter of the last element. +define void @f45(<2 x double> %val, <2 x i64> %index, i64 %base) { +; CHECK-LABEL: f45: +; CHECK: vsceg %v24, 0(%v26,%r2), 1 +; CHECK: br %r14 + %elem = extractelement <2 x i64> %index, i32 1 + %add = add i64 %base, %elem + %ptr = inttoptr i64 %add to double * + %element = extractelement <2 x double> %val, i32 1 + store double %element, double *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/vec-move-11.ll b/test/CodeGen/SystemZ/vec-move-11.ll new file mode 100644 index 000000000000..fd9c3d3559f0 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-11.ll @@ -0,0 +1,111 @@ +; Test insertions of register values into a nonzero index of an undef. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 insertion into an undef, with an arbitrary index. +define <16 x i8> @f1(i8 %val) { +; CHECK-LABEL: f1: +; CHECK: vlvgb %v24, %r2, 12 +; CHECK-NEXT: br %r14 + %ret = insertelement <16 x i8> undef, i8 %val, i32 12 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into an undef, with the first good index for VLVGP. +define <16 x i8> @f2(i8 %val) { +; CHECK-LABEL: f2: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK-NEXT: br %r14 + %ret = insertelement <16 x i8> undef, i8 %val, i32 7 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into an undef, with the second good index for VLVGP. +define <16 x i8> @f3(i8 %val) { +; CHECK-LABEL: f3: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK-NEXT: br %r14 + %ret = insertelement <16 x i8> undef, i8 %val, i32 15 + ret <16 x i8> %ret +} + +; Test v8i16 insertion into an undef, with an arbitrary index. +define <8 x i16> @f4(i16 %val) { +; CHECK-LABEL: f4: +; CHECK: vlvgh %v24, %r2, 5 +; CHECK-NEXT: br %r14 + %ret = insertelement <8 x i16> undef, i16 %val, i32 5 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into an undef, with the first good index for VLVGP. +define <8 x i16> @f5(i16 %val) { +; CHECK-LABEL: f5: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK-NEXT: br %r14 + %ret = insertelement <8 x i16> undef, i16 %val, i32 3 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into an undef, with the second good index for VLVGP. +define <8 x i16> @f6(i16 %val) { +; CHECK-LABEL: f6: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK-NEXT: br %r14 + %ret = insertelement <8 x i16> undef, i16 %val, i32 7 + ret <8 x i16> %ret +} + +; Test v4i32 insertion into an undef, with an arbitrary index. +define <4 x i32> @f7(i32 %val) { +; CHECK-LABEL: f7: +; CHECK: vlvgf %v24, %r2, 2 +; CHECK-NEXT: br %r14 + %ret = insertelement <4 x i32> undef, i32 %val, i32 2 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into an undef, with the first good index for VLVGP. +define <4 x i32> @f8(i32 %val) { +; CHECK-LABEL: f8: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK-NEXT: br %r14 + %ret = insertelement <4 x i32> undef, i32 %val, i32 1 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into an undef, with the second good index for VLVGP. +define <4 x i32> @f9(i32 %val) { +; CHECK-LABEL: f9: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK-NEXT: br %r14 + %ret = insertelement <4 x i32> undef, i32 %val, i32 3 + ret <4 x i32> %ret +} + +; Test v2i64 insertion into an undef. +define <2 x i64> @f10(i64 %val) { +; CHECK-LABEL: f10: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK-NEXT: br %r14 + %ret = insertelement <2 x i64> undef, i64 %val, i32 1 + ret <2 x i64> %ret +} + +; Test v4f32 insertion into an undef. +define <4 x float> @f11(float %val) { +; CHECK-LABEL: f11: +; CHECK: vrepf %v24, %v0, 0 +; CHECK: br %r14 + %ret = insertelement <4 x float> undef, float %val, i32 2 + ret <4 x float> %ret +} + +; Test v2f64 insertion into an undef. +define <2 x double> @f12(double %val) { +; CHECK-LABEL: f12: +; CHECK: vrepg %v24, %v0, 0 +; CHECK: br %r14 + %ret = insertelement <2 x double> undef, double %val, i32 1 + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-12.ll b/test/CodeGen/SystemZ/vec-move-12.ll new file mode 100644 index 000000000000..bc8ff97f8057 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-12.ll @@ -0,0 +1,123 @@ +; Test insertions of memory values into a nonzero index of an undef. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 insertion into an undef, with an arbitrary index. +define <16 x i8> @f1(i8 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vlrepb %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i8, i8 *%ptr + %ret = insertelement <16 x i8> undef, i8 %val, i32 12 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into an undef, with the first good index for VLVGP. +define <16 x i8> @f2(i8 *%ptr) { +; CHECK-LABEL: f2: +; CHECK: {{vlrepb|vllezb}} %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i8, i8 *%ptr + %ret = insertelement <16 x i8> undef, i8 %val, i32 7 + ret <16 x i8> %ret +} + +; Test v16i8 insertion into an undef, with the second good index for VLVGP. +define <16 x i8> @f3(i8 *%ptr) { +; CHECK-LABEL: f3: +; CHECK: vlrepb %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i8, i8 *%ptr + %ret = insertelement <16 x i8> undef, i8 %val, i32 15 + ret <16 x i8> %ret +} + +; Test v8i16 insertion into an undef, with an arbitrary index. +define <8 x i16> @f4(i16 *%ptr) { +; CHECK-LABEL: f4: +; CHECK: vlreph %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i16, i16 *%ptr + %ret = insertelement <8 x i16> undef, i16 %val, i32 5 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into an undef, with the first good index for VLVGP. +define <8 x i16> @f5(i16 *%ptr) { +; CHECK-LABEL: f5: +; CHECK: {{vlreph|vllezh}} %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i16, i16 *%ptr + %ret = insertelement <8 x i16> undef, i16 %val, i32 3 + ret <8 x i16> %ret +} + +; Test v8i16 insertion into an undef, with the second good index for VLVGP. +define <8 x i16> @f6(i16 *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vlreph %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i16, i16 *%ptr + %ret = insertelement <8 x i16> undef, i16 %val, i32 7 + ret <8 x i16> %ret +} + +; Test v4i32 insertion into an undef, with an arbitrary index. +define <4 x i32> @f7(i32 *%ptr) { +; CHECK-LABEL: f7: +; CHECK: vlrepf %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i32, i32 *%ptr + %ret = insertelement <4 x i32> undef, i32 %val, i32 2 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into an undef, with the first good index for VLVGP. +define <4 x i32> @f8(i32 *%ptr) { +; CHECK-LABEL: f8: +; CHECK: {{vlrepf|vllezf}} %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i32, i32 *%ptr + %ret = insertelement <4 x i32> undef, i32 %val, i32 1 + ret <4 x i32> %ret +} + +; Test v4i32 insertion into an undef, with the second good index for VLVGP. +define <4 x i32> @f9(i32 *%ptr) { +; CHECK-LABEL: f9: +; CHECK: vlrepf %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i32, i32 *%ptr + %ret = insertelement <4 x i32> undef, i32 %val, i32 3 + ret <4 x i32> %ret +} + +; Test v2i64 insertion into an undef. +define <2 x i64> @f10(i64 *%ptr) { +; CHECK-LABEL: f10: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK-NEXT: br %r14 + %val = load i64, i64 *%ptr + %ret = insertelement <2 x i64> undef, i64 %val, i32 1 + ret <2 x i64> %ret +} + +; Test v4f32 insertion into an undef. +define <4 x float> @f11(float *%ptr) { +; CHECK-LABEL: f11: +; CHECK: vlrepf %v24, 0(%r2) +; CHECK: br %r14 + %val = load float, float *%ptr + %ret = insertelement <4 x float> undef, float %val, i32 2 + ret <4 x float> %ret +} + +; Test v2f64 insertion into an undef. +define <2 x double> @f12(double *%ptr) { +; CHECK-LABEL: f12: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %val = load double, double *%ptr + %ret = insertelement <2 x double> undef, double %val, i32 1 + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-13.ll b/test/CodeGen/SystemZ/vec-move-13.ll new file mode 100644 index 000000000000..165c3498702f --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-13.ll @@ -0,0 +1,69 @@ +; Test insertions of register values into 0. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 insertion into 0. +define <16 x i8> @f1(i8 %val1, i8 %val2) { +; CHECK-LABEL: f1: +; CHECK: vgbm %v24, 0 +; CHECK-DAG: vlvgb %v24, %r2, 2 +; CHECK-DAG: vlvgb %v24, %r3, 12 +; CHECK: br %r14 + %vec1 = insertelement <16 x i8> zeroinitializer, i8 %val1, i32 2 + %vec2 = insertelement <16 x i8> %vec1, i8 %val2, i32 12 + ret <16 x i8> %vec2 +} + +; Test v8i16 insertion into 0. +define <8 x i16> @f2(i16 %val1, i16 %val2) { +; CHECK-LABEL: f2: +; CHECK: vgbm %v24, 0 +; CHECK-DAG: vlvgh %v24, %r2, 3 +; CHECK-DAG: vlvgh %v24, %r3, 5 +; CHECK: br %r14 + %vec1 = insertelement <8 x i16> zeroinitializer, i16 %val1, i32 3 + %vec2 = insertelement <8 x i16> %vec1, i16 %val2, i32 5 + ret <8 x i16> %vec2 +} + +; Test v4i32 insertion into 0. +define <4 x i32> @f3(i32 %val) { +; CHECK-LABEL: f3: +; CHECK: vgbm %v24, 0 +; CHECK: vlvgf %v24, %r2, 3 +; CHECK: br %r14 + %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 3 + ret <4 x i32> %ret +} + +; Test v2i64 insertion into 0. +define <2 x i64> @f4(i64 %val) { +; CHECK-LABEL: f4: +; CHECK: lghi [[REG:%r[0-5]]], 0 +; CHECK: vlvgp %v24, [[REG]], %r2 +; CHECK: br %r14 + %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 1 + ret <2 x i64> %ret +} + +; Test v4f32 insertion into 0. +define <4 x float> @f5(float %val) { +; CHECK-LABEL: f5: +; CHECK-DAG: vuplhf [[REG:%v[0-9]+]], %v0 +; CHECK-DAG: vgbm [[ZERO:%v[0-9]+]], 0 +; CHECK: vmrhg %v24, [[ZERO]], [[REG]] +; CHECK: br %r14 + %ret = insertelement <4 x float> zeroinitializer, float %val, i32 3 + ret <4 x float> %ret +} + +; Test v2f64 insertion into 0. +define <2 x double> @f6(double %val) { +; CHECK-LABEL: f6: +; CHECK: vgbm [[REG:%v[0-9]+]], 0 +; CHECK: vmrhg %v24, [[REG]], %v0 +; CHECK: br %r14 + %ret = insertelement <2 x double> zeroinitializer, double %val, i32 1 + ret <2 x double> %ret +} + diff --git a/test/CodeGen/SystemZ/vec-move-14.ll b/test/CodeGen/SystemZ/vec-move-14.ll new file mode 100644 index 000000000000..e41eb9da0346 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-14.ll @@ -0,0 +1,96 @@ +; Test insertions of memory values into 0. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test VLLEZB. +define <16 x i8> @f1(i8 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vllezb %v24, 0(%r2) +; CHECK: br %r14 + %val = load i8, i8 *%ptr + %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7 + ret <16 x i8> %ret +} + +; Test VLLEZB with the highest in-range offset. +define <16 x i8> @f2(i8 *%base) { +; CHECK-LABEL: f2: +; CHECK: vllezb %v24, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + %val = load i8, i8 *%ptr + %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7 + ret <16 x i8> %ret +} + +; Test VLLEZB with the next highest offset. +define <16 x i8> @f3(i8 *%base) { +; CHECK-LABEL: f3: +; CHECK-NOT: vllezb %v24, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %val = load i8, i8 *%ptr + %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7 + ret <16 x i8> %ret +} + +; Test that VLLEZB allows an index. +define <16 x i8> @f4(i8 *%base, i64 %index) { +; CHECK-LABEL: f4: +; CHECK: vllezb %v24, 0({{%r2,%r3|%r3,%r2}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + %val = load i8, i8 *%ptr + %ret = insertelement <16 x i8> zeroinitializer, i8 %val, i32 7 + ret <16 x i8> %ret +} + +; Test VLLEZH. +define <8 x i16> @f5(i16 *%ptr) { +; CHECK-LABEL: f5: +; CHECK: vllezh %v24, 0(%r2) +; CHECK: br %r14 + %val = load i16, i16 *%ptr + %ret = insertelement <8 x i16> zeroinitializer, i16 %val, i32 3 + ret <8 x i16> %ret +} + +; Test VLLEZF. +define <4 x i32> @f6(i32 *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vllezf %v24, 0(%r2) +; CHECK: br %r14 + %val = load i32, i32 *%ptr + %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 1 + ret <4 x i32> %ret +} + +; Test VLLEZG. +define <2 x i64> @f7(i64 *%ptr) { +; CHECK-LABEL: f7: +; CHECK: vllezg %v24, 0(%r2) +; CHECK: br %r14 + %val = load i64, i64 *%ptr + %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 0 + ret <2 x i64> %ret +} + +; Test VLLEZF with a float. +define <4 x float> @f8(float *%ptr) { +; CHECK-LABEL: f8: +; CHECK: vllezf %v24, 0(%r2) +; CHECK: br %r14 + %val = load float, float *%ptr + %ret = insertelement <4 x float> zeroinitializer, float %val, i32 1 + ret <4 x float> %ret +} + +; Test VLLEZG with a double. +define <2 x double> @f9(double *%ptr) { +; CHECK-LABEL: f9: +; CHECK: vllezg %v24, 0(%r2) +; CHECK: br %r14 + %val = load double, double *%ptr + %ret = insertelement <2 x double> zeroinitializer, double %val, i32 0 + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-15.ll b/test/CodeGen/SystemZ/vec-move-15.ll new file mode 100644 index 000000000000..503627c163c6 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-15.ll @@ -0,0 +1,105 @@ +; Test vector sign-extending loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i1->v16i8 extension. +define <16 x i8> @f1(<16 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <16 x i1>, <16 x i1> *%ptr + %ret = sext <16 x i1> %val to <16 x i8> + ret <16 x i8> %ret +} + +; Test a v8i1->v8i16 extension. +define <8 x i16> @f2(<8 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <8 x i1>, <8 x i1> *%ptr + %ret = sext <8 x i1> %val to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v8i8->v8i16 extension. +define <8 x i16> @f3(<8 x i8> *%ptr) { +; CHECK-LABEL: f3: +; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuphb %v24, [[REG1]] +; CHECK: br %r14 + %val = load <8 x i8>, <8 x i8> *%ptr + %ret = sext <8 x i8> %val to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v4i1->v4i32 extension. +define <4 x i32> @f4(<4 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <4 x i1>, <4 x i1> *%ptr + %ret = sext <4 x i1> %val to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i8->v4i32 extension. +define <4 x i32> @f5(<4 x i8> *%ptr) { +; CHECK-LABEL: f5: +; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]] +; CHECK: vuphh %v24, [[REG2]] +; CHECK: br %r14 + %val = load <4 x i8>, <4 x i8> *%ptr + %ret = sext <4 x i8> %val to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i16->v4i32 extension. +define <4 x i32> @f6(<4 x i16> *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuphh %v24, [[REG1]] +; CHECK: br %r14 + %val = load <4 x i16>, <4 x i16> *%ptr + %ret = sext <4 x i16> %val to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v2i1->v2i64 extension. +define <2 x i64> @f7(<2 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <2 x i1>, <2 x i1> *%ptr + %ret = sext <2 x i1> %val to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i8->v2i64 extension. +define <2 x i64> @f8(<2 x i8> *%ptr) { +; CHECK-LABEL: f8: +; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]] +; CHECK: vuphh [[REG3:%v[0-9]+]], [[REG2]] +; CHECK: vuphf %v24, [[REG3]] +; CHECK: br %r14 + %val = load <2 x i8>, <2 x i8> *%ptr + %ret = sext <2 x i8> %val to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i16->v2i64 extension. +define <2 x i64> @f9(<2 x i16> *%ptr) { +; CHECK-LABEL: f9: +; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuphh [[REG2:%v[0-9]+]], [[REG1]] +; CHECK: vuphf %v24, [[REG2]] +; CHECK: br %r14 + %val = load <2 x i16>, <2 x i16> *%ptr + %ret = sext <2 x i16> %val to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i32->v2i64 extension. +define <2 x i64> @f10(<2 x i32> *%ptr) { +; CHECK-LABEL: f10: +; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuphf %v24, [[REG1]] +; CHECK: br %r14 + %val = load <2 x i32>, <2 x i32> *%ptr + %ret = sext <2 x i32> %val to <2 x i64> + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-16.ll b/test/CodeGen/SystemZ/vec-move-16.ll new file mode 100644 index 000000000000..cd2577396800 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-16.ll @@ -0,0 +1,105 @@ +; Test vector zero-extending loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i1->v16i8 extension. +define <16 x i8> @f1(<16 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <16 x i1>, <16 x i1> *%ptr + %ret = zext <16 x i1> %val to <16 x i8> + ret <16 x i8> %ret +} + +; Test a v8i1->v8i16 extension. +define <8 x i16> @f2(<8 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <8 x i1>, <8 x i1> *%ptr + %ret = zext <8 x i1> %val to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v8i8->v8i16 extension. +define <8 x i16> @f3(<8 x i8> *%ptr) { +; CHECK-LABEL: f3: +; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuplhb %v24, [[REG1]] +; CHECK: br %r14 + %val = load <8 x i8>, <8 x i8> *%ptr + %ret = zext <8 x i8> %val to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v4i1->v4i32 extension. +define <4 x i32> @f4(<4 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <4 x i1>, <4 x i1> *%ptr + %ret = zext <4 x i1> %val to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i8->v4i32 extension. +define <4 x i32> @f5(<4 x i8> *%ptr) { +; CHECK-LABEL: f5: +; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]] +; CHECK: vuplhh %v24, [[REG2]] +; CHECK: br %r14 + %val = load <4 x i8>, <4 x i8> *%ptr + %ret = zext <4 x i8> %val to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i16->v4i32 extension. +define <4 x i32> @f6(<4 x i16> *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuplhh %v24, [[REG1]] +; CHECK: br %r14 + %val = load <4 x i16>, <4 x i16> *%ptr + %ret = zext <4 x i16> %val to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v2i1->v2i64 extension. +define <2 x i64> @f7(<2 x i1> *%ptr) { +; No expected output, but must compile. + %val = load <2 x i1>, <2 x i1> *%ptr + %ret = zext <2 x i1> %val to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i8->v2i64 extension. +define <2 x i64> @f8(<2 x i8> *%ptr) { +; CHECK-LABEL: f8: +; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]] +; CHECK: vuplhh [[REG3:%v[0-9]+]], [[REG2]] +; CHECK: vuplhf %v24, [[REG3]] +; CHECK: br %r14 + %val = load <2 x i8>, <2 x i8> *%ptr + %ret = zext <2 x i8> %val to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i16->v2i64 extension. +define <2 x i64> @f9(<2 x i16> *%ptr) { +; CHECK-LABEL: f9: +; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuplhh [[REG2:%v[0-9]+]], [[REG1]] +; CHECK: vuplhf %v24, [[REG2]] +; CHECK: br %r14 + %val = load <2 x i16>, <2 x i16> *%ptr + %ret = zext <2 x i16> %val to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i32->v2i64 extension. +define <2 x i64> @f10(<2 x i32> *%ptr) { +; CHECK-LABEL: f10: +; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2) +; CHECK: vuplhf %v24, [[REG1]] +; CHECK: br %r14 + %val = load <2 x i32>, <2 x i32> *%ptr + %ret = zext <2 x i32> %val to <2 x i64> + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-move-17.ll b/test/CodeGen/SystemZ/vec-move-17.ll new file mode 100644 index 000000000000..e7fc06c9260c --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-17.ll @@ -0,0 +1,104 @@ +; Test vector truncating stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8->v16i1 truncation. +define void @f1(<16 x i8> %val, <16 x i1> *%ptr) { +; No expected output, but must compile. + %trunc = trunc <16 x i8> %val to <16 x i1> + store <16 x i1> %trunc, <16 x i1> *%ptr + ret void +} + +; Test a v8i16->v8i1 truncation. +define void @f2(<8 x i16> %val, <8 x i1> *%ptr) { +; No expected output, but must compile. + %trunc = trunc <8 x i16> %val to <8 x i1> + store <8 x i1> %trunc, <8 x i1> *%ptr + ret void +} + +; Test a v8i16->v8i8 truncation. +define void @f3(<8 x i16> %val, <8 x i8> *%ptr) { +; CHECK-LABEL: f3: +; CHECK: vpkh [[REG1:%v[0-9]+]], %v24, %v24 +; CHECK: vsteg [[REG1]], 0(%r2) +; CHECK: br %r14 + %trunc = trunc <8 x i16> %val to <8 x i8> + store <8 x i8> %trunc, <8 x i8> *%ptr + ret void +} + +; Test a v4i32->v4i1 truncation. +define void @f4(<4 x i32> %val, <4 x i1> *%ptr) { +; No expected output, but must compile. + %trunc = trunc <4 x i32> %val to <4 x i1> + store <4 x i1> %trunc, <4 x i1> *%ptr + ret void +} + +; Test a v4i32->v4i8 truncation. At the moment we use a VPERM rather than +; a chain of packs. +define void @f5(<4 x i32> %val, <4 x i8> *%ptr) { +; CHECK-LABEL: f5: +; CHECK: vperm [[REG:%v[0-9]+]], +; CHECK: vstef [[REG]], 0(%r2) +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i8> + store <4 x i8> %trunc, <4 x i8> *%ptr + ret void +} + +; Test a v4i32->v4i16 truncation. +define void @f6(<4 x i32> %val, <4 x i16> *%ptr) { +; CHECK-LABEL: f6: +; CHECK: vpkf [[REG1:%v[0-9]+]], %v24, %v24 +; CHECK: vsteg [[REG1]], 0(%r2) +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i16> + store <4 x i16> %trunc, <4 x i16> *%ptr + ret void +} + +; Test a v2i64->v2i1 truncation. +define void @f7(<2 x i64> %val, <2 x i1> *%ptr) { +; No expected output, but must compile. + %trunc = trunc <2 x i64> %val to <2 x i1> + store <2 x i1> %trunc, <2 x i1> *%ptr + ret void +} + +; Test a v2i64->v2i8 truncation. At the moment we use a VPERM rather than +; a chain of packs. +define void @f8(<2 x i64> %val, <2 x i8> *%ptr) { +; CHECK-LABEL: f8: +; CHECK: vperm [[REG:%v[0-9]+]], +; CHECK: vsteh [[REG]], 0(%r2) +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i8> + store <2 x i8> %trunc, <2 x i8> *%ptr + ret void +} + +; Test a v2i64->v2i16 truncation. At the moment we use a VPERM rather than +; a chain of packs. +define void @f9(<2 x i64> %val, <2 x i16> *%ptr) { +; CHECK-LABEL: f9: +; CHECK: vperm [[REG:%v[0-9]+]], +; CHECK: vstef [[REG]], 0(%r2) +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i16> + store <2 x i16> %trunc, <2 x i16> *%ptr + ret void +} + +; Test a v2i64->v2i32 truncation. +define void @f10(<2 x i64> %val, <2 x i32> *%ptr) { +; CHECK-LABEL: f10: +; CHECK: vpkg [[REG1:%v[0-9]+]], %v24, %v24 +; CHECK: vsteg [[REG1]], 0(%r2) +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i32> + store <2 x i32> %trunc, <2 x i32> *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/vec-mul-01.ll b/test/CodeGen/SystemZ/vec-mul-01.ll new file mode 100644 index 000000000000..5ecc30d4427a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-mul-01.ll @@ -0,0 +1,60 @@ +; Test vector multiplication. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 multiplication. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmlb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = mul <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 multiplication. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmlhw %v24, %v26, %v28 +; CHECK: br %r14 + %ret = mul <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 multiplication. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmlf %v24, %v26, %v28 +; CHECK: br %r14 + %ret = mul <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 multiplication. There's no vector equivalent. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK-NOT: vmlg +; CHECK: br %r14 + %ret = mul <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} + +; Test a v2f64 multiplication. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfmdb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = fmul <2 x double> %val1, %val2 + ret <2 x double> %ret +} + +; Test an f64 multiplication that uses vector registers. +define double @f6(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f6: +; CHECK: wfmdb %f0, %v24, %v26 +; CHECK: br %r14 + %scalar1 = extractelement <2 x double> %val1, i32 0 + %scalar2 = extractelement <2 x double> %val2, i32 0 + %ret = fmul double %scalar1, %scalar2 + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-mul-02.ll b/test/CodeGen/SystemZ/vec-mul-02.ll new file mode 100644 index 000000000000..11a651e49975 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-mul-02.ll @@ -0,0 +1,63 @@ +; Test vector multiply-and-add. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) + +; Test a v16i8 multiply-and-add. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2, + <16 x i8> %val3) { +; CHECK-LABEL: f1: +; CHECK: vmalb %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %mul = mul <16 x i8> %val1, %val2 + %ret = add <16 x i8> %mul, %val3 + ret <16 x i8> %ret +} + +; Test a v8i16 multiply-and-add. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2, + <8 x i16> %val3) { +; CHECK-LABEL: f2: +; CHECK: vmalhw %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %mul = mul <8 x i16> %val1, %val2 + %ret = add <8 x i16> %mul, %val3 + ret <8 x i16> %ret +} + +; Test a v4i32 multiply-and-add. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> %val3) { +; CHECK-LABEL: f3: +; CHECK: vmalf %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %mul = mul <4 x i32> %val1, %val2 + %ret = add <4 x i32> %mul, %val3 + ret <4 x i32> %ret +} + +; Test a v2f64 multiply-and-add. +define <2 x double> @f4(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2, <2 x double> %val3) { +; CHECK-LABEL: f4: +; CHECK: vfmadb %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1, + <2 x double> %val2, + <2 x double> %val3) + ret <2 x double> %ret +} + +; Test a v2f64 multiply-and-subtract. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2, <2 x double> %val3) { +; CHECK-LABEL: f5: +; CHECK: vfmsdb %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %negval3 = fsub <2 x double> <double -0.0, double -0.0>, %val3 + %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1, + <2 x double> %val2, + <2 x double> %negval3) + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-neg-01.ll b/test/CodeGen/SystemZ/vec-neg-01.ll new file mode 100644 index 000000000000..b1389ce4d6d0 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-neg-01.ll @@ -0,0 +1,58 @@ +; Test vector negation. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 negation. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val) { +; CHECK-LABEL: f1: +; CHECK: vlcb %v24, %v26 +; CHECK: br %r14 + %ret = sub <16 x i8> zeroinitializer, %val + ret <16 x i8> %ret +} + +; Test a v8i16 negation. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val) { +; CHECK-LABEL: f2: +; CHECK: vlch %v24, %v26 +; CHECK: br %r14 + %ret = sub <8 x i16> zeroinitializer, %val + ret <8 x i16> %ret +} + +; Test a v4i32 negation. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val) { +; CHECK-LABEL: f3: +; CHECK: vlcf %v24, %v26 +; CHECK: br %r14 + %ret = sub <4 x i32> zeroinitializer, %val + ret <4 x i32> %ret +} + +; Test a v2i64 negation. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val) { +; CHECK-LABEL: f4: +; CHECK: vlcg %v24, %v26 +; CHECK: br %r14 + %ret = sub <2 x i64> zeroinitializer, %val + ret <2 x i64> %ret +} + +; Test a v2f64 negation. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val) { +; CHECK-LABEL: f5: +; CHECK: vflcdb %v24, %v26 +; CHECK: br %r14 + %ret = fsub <2 x double> <double -0.0, double -0.0>, %val + ret <2 x double> %ret +} + +; Test an f64 negation that uses vector registers. +define double @f6(<2 x double> %val) { +; CHECK-LABEL: f6: +; CHECK: wflcdb %f0, %v24 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %ret = fsub double -0.0, %scalar + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-or-01.ll b/test/CodeGen/SystemZ/vec-or-01.ll new file mode 100644 index 000000000000..789150ad2d1b --- /dev/null +++ b/test/CodeGen/SystemZ/vec-or-01.ll @@ -0,0 +1,39 @@ +; Test vector OR. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 OR. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vo %v24, %v26, %v28 +; CHECK: br %r14 + %ret = or <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 OR. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vo %v24, %v26, %v28 +; CHECK: br %r14 + %ret = or <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 OR. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vo %v24, %v26, %v28 +; CHECK: br %r14 + %ret = or <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 OR. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vo %v24, %v26, %v28 +; CHECK: br %r14 + %ret = or <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-or-02.ll b/test/CodeGen/SystemZ/vec-or-02.ll new file mode 100644 index 000000000000..eeb86e36ff00 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-or-02.ll @@ -0,0 +1,107 @@ +; Test vector (or (and X, Z), (and Y, (not Z))) patterns. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) { +; CHECK-LABEL: f1: +; CHECK: vsel %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <16 x i8> %val3, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + %and1 = and <16 x i8> %val1, %val3 + %and2 = and <16 x i8> %val2, %not + %ret = or <16 x i8> %and1, %and2 + ret <16 x i8> %ret +} + +; ...and again with the XOR applied to the other operand of the AND. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) { +; CHECK-LABEL: f2: +; CHECK: vsel %v24, %v26, %v24, %v28 +; CHECK: br %r14 + %not = xor <16 x i8> %val3, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + %and1 = and <16 x i8> %val1, %not + %and2 = and <16 x i8> %val2, %val3 + %ret = or <16 x i8> %and1, %and2 + ret <16 x i8> %ret +} + +; Test v8i16. +define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) { +; CHECK-LABEL: f3: +; CHECK: vsel %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <8 x i16> %val3, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + %and1 = and <8 x i16> %val1, %val3 + %and2 = and <8 x i16> %val2, %not + %ret = or <8 x i16> %and1, %and2 + ret <8 x i16> %ret +} + +; ...and again with the XOR applied to the other operand of the AND. +define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) { +; CHECK-LABEL: f4: +; CHECK: vsel %v24, %v26, %v24, %v28 +; CHECK: br %r14 + %not = xor <8 x i16> %val3, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + %and1 = and <8 x i16> %val1, %not + %and2 = and <8 x i16> %val2, %val3 + %ret = or <8 x i16> %and1, %and2 + ret <8 x i16> %ret +} + +; Test v4i32. +define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) { +; CHECK-LABEL: f5: +; CHECK: vsel %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <4 x i32> %val3, <i32 -1, i32 -1, i32 -1, i32 -1> + %and1 = and <4 x i32> %val1, %val3 + %and2 = and <4 x i32> %val2, %not + %ret = or <4 x i32> %and1, %and2 + ret <4 x i32> %ret +} + +; ...and again with the XOR applied to the other operand of the AND. +define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) { +; CHECK-LABEL: f6: +; CHECK: vsel %v24, %v26, %v24, %v28 +; CHECK: br %r14 + %not = xor <4 x i32> %val3, <i32 -1, i32 -1, i32 -1, i32 -1> + %and1 = and <4 x i32> %val1, %not + %and2 = and <4 x i32> %val2, %val3 + %ret = or <4 x i32> %and1, %and2 + ret <4 x i32> %ret +} + +; Test v2i64. +define <2 x i64> @f7(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) { +; CHECK-LABEL: f7: +; CHECK: vsel %v24, %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <2 x i64> %val3, <i64 -1, i64 -1> + %and1 = and <2 x i64> %val1, %val3 + %and2 = and <2 x i64> %val2, %not + %ret = or <2 x i64> %and1, %and2 + ret <2 x i64> %ret +} + +; ...and again with the XOR applied to the other operand of the AND. +define <2 x i64> @f8(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) { +; CHECK-LABEL: f8: +; CHECK: vsel %v24, %v26, %v24, %v28 +; CHECK: br %r14 + %not = xor <2 x i64> %val3, <i64 -1, i64 -1> + %and1 = and <2 x i64> %val1, %not + %and2 = and <2 x i64> %val2, %val3 + %ret = or <2 x i64> %and1, %and2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-01.ll b/test/CodeGen/SystemZ/vec-perm-01.ll new file mode 100644 index 000000000000..4beec05eaece --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-01.ll @@ -0,0 +1,175 @@ +; Test vector splat. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 splat of the first element. +define <16 x i8> @f1(<16 x i8> %val) { +; CHECK-LABEL: f1: +; CHECK: vrepb %v24, %v24, 0 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> zeroinitializer + ret <16 x i8> %ret +} + +; Test v16i8 splat of the last element. +define <16 x i8> @f2(<16 x i8> %val) { +; CHECK-LABEL: f2: +; CHECK: vrepb %v24, %v24, 15 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> <i32 15, i32 15, i32 15, i32 15, + i32 15, i32 15, i32 15, i32 15, + i32 15, i32 15, i32 15, i32 15, + i32 15, i32 15, i32 15, i32 15> + ret <16 x i8> %ret +} + +; Test v16i8 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <16 x i8> @f3(<16 x i8> %val) { +; CHECK-LABEL: f3: +; CHECK: vrepb %v24, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> undef, <16 x i8> %val, + <16 x i32> <i32 20, i32 20, i32 20, i32 20, + i32 20, i32 20, i32 20, i32 20, + i32 20, i32 20, i32 20, i32 20, + i32 20, i32 20, i32 20, i32 20> + ret <16 x i8> %ret +} + +; Test v8i16 splat of the first element. +define <8 x i16> @f4(<8 x i16> %val) { +; CHECK-LABEL: f4: +; CHECK: vreph %v24, %v24, 0 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val, <8 x i16> undef, + <8 x i32> zeroinitializer + ret <8 x i16> %ret +} + +; Test v8i16 splat of the last element. +define <8 x i16> @f5(<8 x i16> %val) { +; CHECK-LABEL: f5: +; CHECK: vreph %v24, %v24, 7 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val, <8 x i16> undef, + <8 x i32> <i32 7, i32 7, i32 7, i32 7, + i32 7, i32 7, i32 7, i32 7> + ret <8 x i16> %ret +} + +; Test v8i16 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <8 x i16> @f6(<8 x i16> %val) { +; CHECK-LABEL: f6: +; CHECK: vreph %v24, %v24, 2 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> undef, <8 x i16> %val, + <8 x i32> <i32 10, i32 10, i32 10, i32 10, + i32 10, i32 10, i32 10, i32 10> + ret <8 x i16> %ret +} + +; Test v4i32 splat of the first element. +define <4 x i32> @f7(<4 x i32> %val) { +; CHECK-LABEL: f7: +; CHECK: vrepf %v24, %v24, 0 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val, <4 x i32> undef, + <4 x i32> zeroinitializer + ret <4 x i32> %ret +} + +; Test v4i32 splat of the last element. +define <4 x i32> @f8(<4 x i32> %val) { +; CHECK-LABEL: f8: +; CHECK: vrepf %v24, %v24, 3 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val, <4 x i32> undef, + <4 x i32> <i32 3, i32 3, i32 3, i32 3> + ret <4 x i32> %ret +} + +; Test v4i32 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <4 x i32> @f9(<4 x i32> %val) { +; CHECK-LABEL: f9: +; CHECK: vrepf %v24, %v24, 1 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> undef, <4 x i32> %val, + <4 x i32> <i32 5, i32 5, i32 5, i32 5> + ret <4 x i32> %ret +} + +; Test v2i64 splat of the first element. +define <2 x i64> @f10(<2 x i64> %val) { +; CHECK-LABEL: f10: +; CHECK: vrepg %v24, %v24, 0 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val, <2 x i64> undef, + <2 x i32> zeroinitializer + ret <2 x i64> %ret +} + +; Test v2i64 splat of the last element. +define <2 x i64> @f11(<2 x i64> %val) { +; CHECK-LABEL: f11: +; CHECK: vrepg %v24, %v24, 1 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val, <2 x i64> undef, + <2 x i32> <i32 1, i32 1> + ret <2 x i64> %ret +} + +; Test v4f32 splat of the first element. +define <4 x float> @f12(<4 x float> %val) { +; CHECK-LABEL: f12: +; CHECK: vrepf %v24, %v24, 0 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val, <4 x float> undef, + <4 x i32> zeroinitializer + ret <4 x float> %ret +} + +; Test v4f32 splat of the last element. +define <4 x float> @f13(<4 x float> %val) { +; CHECK-LABEL: f13: +; CHECK: vrepf %v24, %v24, 3 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val, <4 x float> undef, + <4 x i32> <i32 3, i32 3, i32 3, i32 3> + ret <4 x float> %ret +} + +; Test v4f32 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <4 x float> @f14(<4 x float> %val) { +; CHECK-LABEL: f14: +; CHECK: vrepf %v24, %v24, 1 +; CHECK: br %r14 + %ret = shufflevector <4 x float> undef, <4 x float> %val, + <4 x i32> <i32 5, i32 5, i32 5, i32 5> + ret <4 x float> %ret +} + +; Test v2f64 splat of the first element. +define <2 x double> @f15(<2 x double> %val) { +; CHECK-LABEL: f15: +; CHECK: vrepg %v24, %v24, 0 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val, <2 x double> undef, + <2 x i32> zeroinitializer + ret <2 x double> %ret +} + +; Test v2f64 splat of the last element. +define <2 x double> @f16(<2 x double> %val) { +; CHECK-LABEL: f16: +; CHECK: vrepg %v24, %v24, 1 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val, <2 x double> undef, + <2 x i32> <i32 1, i32 1> + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-02.ll b/test/CodeGen/SystemZ/vec-perm-02.ll new file mode 100644 index 000000000000..e5c6df8e955a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-02.ll @@ -0,0 +1,200 @@ +; Test replications of a scalar register value, represented as splats. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test v16i8 splat of the first element. +define <16 x i8> @f1(i8 %scalar) { +; CHECK-LABEL: f1: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vrepb %v24, [[REG]], 7 +; CHECK: br %r14 + %val = insertelement <16 x i8> undef, i8 %scalar, i32 0 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> zeroinitializer + ret <16 x i8> %ret +} + +; Test v16i8 splat of the last element. +define <16 x i8> @f2(i8 %scalar) { +; CHECK-LABEL: f2: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vrepb %v24, [[REG]], 7 +; CHECK: br %r14 + %val = insertelement <16 x i8> undef, i8 %scalar, i32 15 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> <i32 15, i32 15, i32 15, i32 15, + i32 15, i32 15, i32 15, i32 15, + i32 15, i32 15, i32 15, i32 15, + i32 15, i32 15, i32 15, i32 15> + ret <16 x i8> %ret +} + +; Test v16i8 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <16 x i8> @f3(i8 %scalar) { +; CHECK-LABEL: f3: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vrepb %v24, [[REG]], 7 +; CHECK: br %r14 + %val = insertelement <16 x i8> undef, i8 %scalar, i32 4 + %ret = shufflevector <16 x i8> undef, <16 x i8> %val, + <16 x i32> <i32 20, i32 20, i32 20, i32 20, + i32 20, i32 20, i32 20, i32 20, + i32 20, i32 20, i32 20, i32 20, + i32 20, i32 20, i32 20, i32 20> + ret <16 x i8> %ret +} + +; Test v8i16 splat of the first element. +define <8 x i16> @f4(i16 %scalar) { +; CHECK-LABEL: f4: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vreph %v24, [[REG]], 3 +; CHECK: br %r14 + %val = insertelement <8 x i16> undef, i16 %scalar, i32 0 + %ret = shufflevector <8 x i16> %val, <8 x i16> undef, + <8 x i32> zeroinitializer + ret <8 x i16> %ret +} + +; Test v8i16 splat of the last element. +define <8 x i16> @f5(i16 %scalar) { +; CHECK-LABEL: f5: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vreph %v24, [[REG]], 3 +; CHECK: br %r14 + %val = insertelement <8 x i16> undef, i16 %scalar, i32 7 + %ret = shufflevector <8 x i16> %val, <8 x i16> undef, + <8 x i32> <i32 7, i32 7, i32 7, i32 7, + i32 7, i32 7, i32 7, i32 7> + ret <8 x i16> %ret +} + +; Test v8i16 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <8 x i16> @f6(i16 %scalar) { +; CHECK-LABEL: f6: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vreph %v24, [[REG]], 3 +; CHECK: br %r14 + %val = insertelement <8 x i16> undef, i16 %scalar, i32 2 + %ret = shufflevector <8 x i16> undef, <8 x i16> %val, + <8 x i32> <i32 10, i32 10, i32 10, i32 10, + i32 10, i32 10, i32 10, i32 10> + ret <8 x i16> %ret +} + +; Test v4i32 splat of the first element. +define <4 x i32> @f7(i32 %scalar) { +; CHECK-LABEL: f7: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vrepf %v24, [[REG]], 1 +; CHECK: br %r14 + %val = insertelement <4 x i32> undef, i32 %scalar, i32 0 + %ret = shufflevector <4 x i32> %val, <4 x i32> undef, + <4 x i32> zeroinitializer + ret <4 x i32> %ret +} + +; Test v4i32 splat of the last element. +define <4 x i32> @f8(i32 %scalar) { +; CHECK-LABEL: f8: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vrepf %v24, [[REG]], 1 +; CHECK: br %r14 + %val = insertelement <4 x i32> undef, i32 %scalar, i32 3 + %ret = shufflevector <4 x i32> %val, <4 x i32> undef, + <4 x i32> <i32 3, i32 3, i32 3, i32 3> + ret <4 x i32> %ret +} + +; Test v4i32 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <4 x i32> @f9(i32 %scalar) { +; CHECK-LABEL: f9: +; CHECK: vlvgp [[REG:%v[0-9]+]], %r2, %r2 +; CHECK: vrepf %v24, [[REG]], 1 +; CHECK: br %r14 + %val = insertelement <4 x i32> undef, i32 %scalar, i32 1 + %ret = shufflevector <4 x i32> undef, <4 x i32> %val, + <4 x i32> <i32 5, i32 5, i32 5, i32 5> + ret <4 x i32> %ret +} + +; Test v2i64 splat of the first element. +define <2 x i64> @f10(i64 %scalar) { +; CHECK-LABEL: f10: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK: br %r14 + %val = insertelement <2 x i64> undef, i64 %scalar, i32 0 + %ret = shufflevector <2 x i64> %val, <2 x i64> undef, + <2 x i32> zeroinitializer + ret <2 x i64> %ret +} + +; Test v2i64 splat of the last element. +define <2 x i64> @f11(i64 %scalar) { +; CHECK-LABEL: f11: +; CHECK: vlvgp %v24, %r2, %r2 +; CHECK: br %r14 + %val = insertelement <2 x i64> undef, i64 %scalar, i32 1 + %ret = shufflevector <2 x i64> %val, <2 x i64> undef, + <2 x i32> <i32 1, i32 1> + ret <2 x i64> %ret +} + +; Test v4f32 splat of the first element. +define <4 x float> @f12(float %scalar) { +; CHECK-LABEL: f12: +; CHECK: vrepf %v24, %v0, 0 +; CHECK: br %r14 + %val = insertelement <4 x float> undef, float %scalar, i32 0 + %ret = shufflevector <4 x float> %val, <4 x float> undef, + <4 x i32> zeroinitializer + ret <4 x float> %ret +} + +; Test v4f32 splat of the last element. +define <4 x float> @f13(float %scalar) { +; CHECK-LABEL: f13: +; CHECK: vrepf %v24, %v0, 0 +; CHECK: br %r14 + %val = insertelement <4 x float> undef, float %scalar, i32 3 + %ret = shufflevector <4 x float> %val, <4 x float> undef, + <4 x i32> <i32 3, i32 3, i32 3, i32 3> + ret <4 x float> %ret +} + +; Test v4f32 splat of an arbitrary element, using the second operand of +; the shufflevector. +define <4 x float> @f14(float %scalar) { +; CHECK-LABEL: f14: +; CHECK: vrepf %v24, %v0, 0 +; CHECK: br %r14 + %val = insertelement <4 x float> undef, float %scalar, i32 1 + %ret = shufflevector <4 x float> undef, <4 x float> %val, + <4 x i32> <i32 5, i32 5, i32 5, i32 5> + ret <4 x float> %ret +} + +; Test v2f64 splat of the first element. +define <2 x double> @f15(double %scalar) { +; CHECK-LABEL: f15: +; CHECK: vrepg %v24, %v0, 0 +; CHECK: br %r14 + %val = insertelement <2 x double> undef, double %scalar, i32 0 + %ret = shufflevector <2 x double> %val, <2 x double> undef, + <2 x i32> zeroinitializer + ret <2 x double> %ret +} + +; Test v2f64 splat of the last element. +define <2 x double> @f16(double %scalar) { +; CHECK-LABEL: f16: +; CHECK: vrepg %v24, %v0, 0 +; CHECK: br %r14 + %val = insertelement <2 x double> undef, double %scalar, i32 1 + %ret = shufflevector <2 x double> %val, <2 x double> undef, + <2 x i32> <i32 1, i32 1> + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-03.ll b/test/CodeGen/SystemZ/vec-perm-03.ll new file mode 100644 index 000000000000..663815549c33 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-03.ll @@ -0,0 +1,251 @@ +; Test replications of a scalar memory value, represented as splats. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 replicating load with no offset. +define <16 x i8> @f1(i8 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vlrepb %v24, 0(%r2) +; CHECK: br %r14 + %scalar = load i8, i8 *%ptr + %val = insertelement <16 x i8> undef, i8 %scalar, i32 0 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> zeroinitializer + ret <16 x i8> %ret +} + +; Test a v16i8 replicating load with the maximum in-range offset. +define <16 x i8> @f2(i8 *%base) { +; CHECK-LABEL: f2: +; CHECK: vlrepb %v24, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + %scalar = load i8, i8 *%ptr + %val = insertelement <16 x i8> undef, i8 %scalar, i32 0 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> zeroinitializer + ret <16 x i8> %ret +} + +; Test a v16i8 replicating load with the first out-of-range offset. +define <16 x i8> @f3(i8 *%base) { +; CHECK-LABEL: f3: +; CHECK: aghi %r2, 4096 +; CHECK: vlrepb %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %scalar = load i8, i8 *%ptr + %val = insertelement <16 x i8> undef, i8 %scalar, i32 0 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> zeroinitializer + ret <16 x i8> %ret +} + +; Test a v8i16 replicating load with no offset. +define <8 x i16> @f4(i16 *%ptr) { +; CHECK-LABEL: f4: +; CHECK: vlreph %v24, 0(%r2) +; CHECK: br %r14 + %scalar = load i16, i16 *%ptr + %val = insertelement <8 x i16> undef, i16 %scalar, i32 0 + %ret = shufflevector <8 x i16> %val, <8 x i16> undef, + <8 x i32> zeroinitializer + ret <8 x i16> %ret +} + +; Test a v8i16 replicating load with the maximum in-range offset. +define <8 x i16> @f5(i16 *%base) { +; CHECK-LABEL: f5: +; CHECK: vlreph %v24, 4094(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%base, i64 2047 + %scalar = load i16, i16 *%ptr + %val = insertelement <8 x i16> undef, i16 %scalar, i32 0 + %ret = shufflevector <8 x i16> %val, <8 x i16> undef, + <8 x i32> zeroinitializer + ret <8 x i16> %ret +} + +; Test a v8i16 replicating load with the first out-of-range offset. +define <8 x i16> @f6(i16 *%base) { +; CHECK-LABEL: f6: +; CHECK: aghi %r2, 4096 +; CHECK: vlreph %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%base, i64 2048 + %scalar = load i16, i16 *%ptr + %val = insertelement <8 x i16> undef, i16 %scalar, i32 0 + %ret = shufflevector <8 x i16> %val, <8 x i16> undef, + <8 x i32> zeroinitializer + ret <8 x i16> %ret +} + +; Test a v4i32 replicating load with no offset. +define <4 x i32> @f7(i32 *%ptr) { +; CHECK-LABEL: f7: +; CHECK: vlrepf %v24, 0(%r2) +; CHECK: br %r14 + %scalar = load i32, i32 *%ptr + %val = insertelement <4 x i32> undef, i32 %scalar, i32 0 + %ret = shufflevector <4 x i32> %val, <4 x i32> undef, + <4 x i32> zeroinitializer + ret <4 x i32> %ret +} + +; Test a v4i32 replicating load with the maximum in-range offset. +define <4 x i32> @f8(i32 *%base) { +; CHECK-LABEL: f8: +; CHECK: vlrepf %v24, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32, i32 *%base, i64 1023 + %scalar = load i32, i32 *%ptr + %val = insertelement <4 x i32> undef, i32 %scalar, i32 0 + %ret = shufflevector <4 x i32> %val, <4 x i32> undef, + <4 x i32> zeroinitializer + ret <4 x i32> %ret +} + +; Test a v4i32 replicating load with the first out-of-range offset. +define <4 x i32> @f9(i32 *%base) { +; CHECK-LABEL: f9: +; CHECK: aghi %r2, 4096 +; CHECK: vlrepf %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32, i32 *%base, i64 1024 + %scalar = load i32, i32 *%ptr + %val = insertelement <4 x i32> undef, i32 %scalar, i32 0 + %ret = shufflevector <4 x i32> %val, <4 x i32> undef, + <4 x i32> zeroinitializer + ret <4 x i32> %ret +} + +; Test a v2i64 replicating load with no offset. +define <2 x i64> @f10(i64 *%ptr) { +; CHECK-LABEL: f10: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %scalar = load i64, i64 *%ptr + %val = insertelement <2 x i64> undef, i64 %scalar, i32 0 + %ret = shufflevector <2 x i64> %val, <2 x i64> undef, + <2 x i32> zeroinitializer + ret <2 x i64> %ret +} + +; Test a v2i64 replicating load with the maximum in-range offset. +define <2 x i64> @f11(i64 *%base) { +; CHECK-LABEL: f11: +; CHECK: vlrepg %v24, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i32 511 + %scalar = load i64, i64 *%ptr + %val = insertelement <2 x i64> undef, i64 %scalar, i32 0 + %ret = shufflevector <2 x i64> %val, <2 x i64> undef, + <2 x i32> zeroinitializer + ret <2 x i64> %ret +} + +; Test a v2i64 replicating load with the first out-of-range offset. +define <2 x i64> @f12(i64 *%base) { +; CHECK-LABEL: f12: +; CHECK: aghi %r2, 4096 +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%base, i32 512 + %scalar = load i64, i64 *%ptr + %val = insertelement <2 x i64> undef, i64 %scalar, i32 0 + %ret = shufflevector <2 x i64> %val, <2 x i64> undef, + <2 x i32> zeroinitializer + ret <2 x i64> %ret +} + +; Test a v4f32 replicating load with no offset. +define <4 x float> @f13(float *%ptr) { +; CHECK-LABEL: f13: +; CHECK: vlrepf %v24, 0(%r2) +; CHECK: br %r14 + %scalar = load float, float *%ptr + %val = insertelement <4 x float> undef, float %scalar, i32 0 + %ret = shufflevector <4 x float> %val, <4 x float> undef, + <4 x i32> zeroinitializer + ret <4 x float> %ret +} + +; Test a v4f32 replicating load with the maximum in-range offset. +define <4 x float> @f14(float *%base) { +; CHECK-LABEL: f14: +; CHECK: vlrepf %v24, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%base, i64 1023 + %scalar = load float, float *%ptr + %val = insertelement <4 x float> undef, float %scalar, i32 0 + %ret = shufflevector <4 x float> %val, <4 x float> undef, + <4 x i32> zeroinitializer + ret <4 x float> %ret +} + +; Test a v4f32 replicating load with the first out-of-range offset. +define <4 x float> @f15(float *%base) { +; CHECK-LABEL: f15: +; CHECK: aghi %r2, 4096 +; CHECK: vlrepf %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float, float *%base, i64 1024 + %scalar = load float, float *%ptr + %val = insertelement <4 x float> undef, float %scalar, i32 0 + %ret = shufflevector <4 x float> %val, <4 x float> undef, + <4 x i32> zeroinitializer + ret <4 x float> %ret +} + +; Test a v2f64 replicating load with no offset. +define <2 x double> @f16(double *%ptr) { +; CHECK-LABEL: f16: +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %scalar = load double, double *%ptr + %val = insertelement <2 x double> undef, double %scalar, i32 0 + %ret = shufflevector <2 x double> %val, <2 x double> undef, + <2 x i32> zeroinitializer + ret <2 x double> %ret +} + +; Test a v2f64 replicating load with the maximum in-range offset. +define <2 x double> @f17(double *%base) { +; CHECK-LABEL: f17: +; CHECK: vlrepg %v24, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double, double *%base, i32 511 + %scalar = load double, double *%ptr + %val = insertelement <2 x double> undef, double %scalar, i32 0 + %ret = shufflevector <2 x double> %val, <2 x double> undef, + <2 x i32> zeroinitializer + ret <2 x double> %ret +} + +; Test a v2f64 replicating load with the first out-of-range offset. +define <2 x double> @f18(double *%base) { +; CHECK-LABEL: f18: +; CHECK: aghi %r2, 4096 +; CHECK: vlrepg %v24, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double, double *%base, i32 512 + %scalar = load double, double *%ptr + %val = insertelement <2 x double> undef, double %scalar, i32 0 + %ret = shufflevector <2 x double> %val, <2 x double> undef, + <2 x i32> zeroinitializer + ret <2 x double> %ret +} + +; Test a v16i8 replicating load with an index. +define <16 x i8> @f19(i8 *%base, i64 %index) { +; CHECK-LABEL: f19: +; CHECK: vlrepb %v24, 1023(%r3,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr i8, i8 *%base, i64 %index + %ptr = getelementptr i8, i8 *%ptr1, i64 1023 + %scalar = load i8, i8 *%ptr + %val = insertelement <16 x i8> undef, i8 %scalar, i32 0 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> zeroinitializer + ret <16 x i8> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-04.ll b/test/CodeGen/SystemZ/vec-perm-04.ll new file mode 100644 index 000000000000..0df6f4fbb012 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-04.ll @@ -0,0 +1,200 @@ +; Test vector merge high. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a canonical v16i8 merge high. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmrhb %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 0, i32 16, i32 1, i32 17, + i32 2, i32 18, i32 3, i32 19, + i32 4, i32 20, i32 5, i32 21, + i32 6, i32 22, i32 7, i32 23> + ret <16 x i8> %ret +} + +; Test a reversed v16i8 merge high. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmrhb %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 16, i32 0, i32 17, i32 1, + i32 18, i32 2, i32 19, i32 3, + i32 20, i32 4, i32 21, i32 5, + i32 22, i32 6, i32 23, i32 7> + ret <16 x i8> %ret +} + +; Test a v16i8 merge high with only the first operand being used. +define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmrhb %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 0, i32 0, i32 1, i32 1, + i32 2, i32 2, i32 3, i32 3, + i32 4, i32 4, i32 5, i32 5, + i32 6, i32 6, i32 7, i32 7> + ret <16 x i8> %ret +} + +; Test a v16i8 merge high with only the second operand being used. +; This is converted into @f3 by target-independent code. +define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmrhb %v24, %v26, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 16, i32 16, i32 17, i32 17, + i32 18, i32 18, i32 19, i32 19, + i32 20, i32 20, i32 21, i32 21, + i32 22, i32 22, i32 23, i32 23> + ret <16 x i8> %ret +} + +; Test a v16i8 merge with both operands being the same. This too is +; converted into @f3 by target-independent code. +define <16 x i8> @f5(<16 x i8> %val) { +; CHECK-LABEL: f5: +; CHECK: vmrhb %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val, <16 x i8> %val, + <16 x i32> <i32 0, i32 16, i32 17, i32 17, + i32 18, i32 2, i32 3, i32 3, + i32 20, i32 20, i32 5, i32 5, + i32 6, i32 22, i32 23, i32 7> + ret <16 x i8> %ret +} + +; Test a v16i8 merge in which some of the indices are don't care. +define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmrhb %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 0, i32 undef, i32 1, i32 17, + i32 undef, i32 18, i32 undef, i32 undef, + i32 undef, i32 20, i32 5, i32 21, + i32 undef, i32 22, i32 7, i32 undef> + ret <16 x i8> %ret +} + +; Test a v16i8 merge in which one of the operands is undefined and where +; indices for that operand are "don't care". Target-independent code +; converts the indices themselves into "undef"s. +define <16 x i8> @f7(<16 x i8> %val) { +; CHECK-LABEL: f7: +; CHECK: vmrhb %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> undef, <16 x i8> %val, + <16 x i32> <i32 11, i32 16, i32 17, i32 5, + i32 18, i32 10, i32 19, i32 19, + i32 20, i32 20, i32 21, i32 3, + i32 2, i32 22, i32 9, i32 23> + ret <16 x i8> %ret +} + +; Test a canonical v8i16 merge high. +define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmrhh %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 0, i32 8, i32 1, i32 9, + i32 2, i32 10, i32 3, i32 11> + ret <8 x i16> %ret +} + +; Test a reversed v8i16 merge high. +define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f9: +; CHECK: vmrhh %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 8, i32 0, i32 9, i32 1, + i32 10, i32 2, i32 11, i32 3> + ret <8 x i16> %ret +} + +; Test a canonical v4i32 merge high. +define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f10: +; CHECK: vmrhf %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 0, i32 4, i32 1, i32 5> + ret <4 x i32> %ret +} + +; Test a reversed v4i32 merge high. +define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f11: +; CHECK: vmrhf %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 4, i32 0, i32 5, i32 1> + ret <4 x i32> %ret +} + +; Test a canonical v2i64 merge high. +define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f12: +; CHECK: vmrhg %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2, + <2 x i32> <i32 0, i32 2> + ret <2 x i64> %ret +} + +; Test a reversed v2i64 merge high. +define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f13: +; CHECK: vmrhg %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2, + <2 x i32> <i32 2, i32 0> + ret <2 x i64> %ret +} + +; Test a canonical v4f32 merge high. +define <4 x float> @f14(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f14: +; CHECK: vmrhf %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 0, i32 4, i32 1, i32 5> + ret <4 x float> %ret +} + +; Test a reversed v4f32 merge high. +define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f15: +; CHECK: vmrhf %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 4, i32 0, i32 5, i32 1> + ret <4 x float> %ret +} + +; Test a canonical v2f64 merge high. +define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f16: +; CHECK: vmrhg %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val1, <2 x double> %val2, + <2 x i32> <i32 0, i32 2> + ret <2 x double> %ret +} + +; Test a reversed v2f64 merge high. +define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f17: +; CHECK: vmrhg %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val1, <2 x double> %val2, + <2 x i32> <i32 2, i32 0> + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-05.ll b/test/CodeGen/SystemZ/vec-perm-05.ll new file mode 100644 index 000000000000..b585cefbf845 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-05.ll @@ -0,0 +1,200 @@ +; Test vector merge low. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a canonical v16i8 merge low. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vmrlb %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 8, i32 24, i32 9, i32 25, + i32 10, i32 26, i32 11, i32 27, + i32 12, i32 28, i32 13, i32 29, + i32 14, i32 30, i32 15, i32 31> + ret <16 x i8> %ret +} + +; Test a reversed v16i8 merge low. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vmrlb %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 24, i32 8, i32 25, i32 9, + i32 26, i32 10, i32 27, i32 11, + i32 28, i32 12, i32 29, i32 13, + i32 30, i32 14, i32 31, i32 15> + ret <16 x i8> %ret +} + +; Test a v16i8 merge low with only the first operand being used. +define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vmrlb %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 8, i32 8, i32 9, i32 9, + i32 10, i32 10, i32 11, i32 11, + i32 12, i32 12, i32 13, i32 13, + i32 14, i32 14, i32 15, i32 15> + ret <16 x i8> %ret +} + +; Test a v16i8 merge low with only the second operand being used. +; This is converted into @f3 by target-independent code. +define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f4: +; CHECK: vmrlb %v24, %v26, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 24, i32 24, i32 25, i32 25, + i32 26, i32 26, i32 27, i32 27, + i32 28, i32 28, i32 29, i32 29, + i32 30, i32 30, i32 31, i32 31> + ret <16 x i8> %ret +} + +; Test a v16i8 merge with both operands being the same. This too is +; converted into @f3 by target-independent code. +define <16 x i8> @f5(<16 x i8> %val) { +; CHECK-LABEL: f5: +; CHECK: vmrlb %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val, <16 x i8> %val, + <16 x i32> <i32 8, i32 24, i32 25, i32 25, + i32 26, i32 10, i32 11, i32 11, + i32 28, i32 28, i32 13, i32 13, + i32 14, i32 30, i32 31, i32 15> + ret <16 x i8> %ret +} + +; Test a v16i8 merge in which some of the indices are don't care. +define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f6: +; CHECK: vmrlb %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 8, i32 undef, i32 9, i32 25, + i32 undef, i32 26, i32 undef, i32 undef, + i32 undef, i32 28, i32 13, i32 29, + i32 undef, i32 30, i32 15, i32 undef> + ret <16 x i8> %ret +} + +; Test a v16i8 merge in which one of the operands is undefined and where +; indices for that operand are "don't care". Target-independent code +; converts the indices themselves into "undef"s. +define <16 x i8> @f7(<16 x i8> %val) { +; CHECK-LABEL: f7: +; CHECK: vmrlb %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> undef, <16 x i8> %val, + <16 x i32> <i32 11, i32 24, i32 25, i32 5, + i32 26, i32 10, i32 27, i32 27, + i32 28, i32 28, i32 29, i32 3, + i32 2, i32 30, i32 9, i32 31> + ret <16 x i8> %ret +} + +; Test a canonical v8i16 merge low. +define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f8: +; CHECK: vmrlh %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 4, i32 12, i32 5, i32 13, + i32 6, i32 14, i32 7, i32 15> + ret <8 x i16> %ret +} + +; Test a reversed v8i16 merge low. +define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f9: +; CHECK: vmrlh %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 12, i32 4, i32 13, i32 5, + i32 14, i32 6, i32 15, i32 7> + ret <8 x i16> %ret +} + +; Test a canonical v4i32 merge low. +define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f10: +; CHECK: vmrlf %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 2, i32 6, i32 3, i32 7> + ret <4 x i32> %ret +} + +; Test a reversed v4i32 merge low. +define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f11: +; CHECK: vmrlf %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 6, i32 2, i32 7, i32 3> + ret <4 x i32> %ret +} + +; Test a canonical v2i64 merge low. +define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f12: +; CHECK: vmrlg %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2, + <2 x i32> <i32 1, i32 3> + ret <2 x i64> %ret +} + +; Test a reversed v2i64 merge low. +define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f13: +; CHECK: vmrlg %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2, + <2 x i32> <i32 3, i32 1> + ret <2 x i64> %ret +} + +; Test a canonical v4f32 merge low. +define <4 x float> @f14(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f14: +; CHECK: vmrlf %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 2, i32 6, i32 3, i32 7> + ret <4 x float> %ret +} + +; Test a reversed v4f32 merge low. +define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f15: +; CHECK: vmrlf %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 6, i32 2, i32 7, i32 3> + ret <4 x float> %ret +} + +; Test a canonical v2f64 merge low. +define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f16: +; CHECK: vmrlg %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val1, <2 x double> %val2, + <2 x i32> <i32 1, i32 3> + ret <2 x double> %ret +} + +; Test a reversed v2f64 merge low. +define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f17: +; CHECK: vmrlg %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val1, <2 x double> %val2, + <2 x i32> <i32 3, i32 1> + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-06.ll b/test/CodeGen/SystemZ/vec-perm-06.ll new file mode 100644 index 000000000000..835276a36725 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-06.ll @@ -0,0 +1,160 @@ +; Test vector pack. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a canonical v16i8 pack. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vpkh %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15, + i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31> + ret <16 x i8> %ret +} + +; Test a reversed v16i8 pack. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vpkh %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31, + i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + ret <16 x i8> %ret +} + +; Test a v16i8 pack with only the first operand being used. +define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vpkh %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15, + i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + ret <16 x i8> %ret +} + +; Test a v16i8 pack with only the second operand being used. +; This is converted into @f3 by target-independent code. +define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f4: +; CHECK: vpkh %v24, %v26, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31, + i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31> + ret <16 x i8> %ret +} + +; Test a v16i8 pack with both operands being the same. This too is +; converted into @f3 by target-independent code. +define <16 x i8> @f5(<16 x i8> %val) { +; CHECK-LABEL: f5: +; CHECK: vpkh %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val, <16 x i8> %val, + <16 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15, + i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31> + ret <16 x i8> %ret +} + +; Test a v16i8 pack in which some of the indices are don't care. +define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f6: +; CHECK: vpkh %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 1, i32 undef, i32 5, i32 7, + i32 undef, i32 11, i32 undef, i32 undef, + i32 undef, i32 19, i32 21, i32 23, + i32 undef, i32 27, i32 29, i32 undef> + ret <16 x i8> %ret +} + +; Test a v16i8 pack in which one of the operands is undefined and where +; indices for that operand are "don't care". Target-independent code +; converts the indices themselves into "undef"s. +define <16 x i8> @f7(<16 x i8> %val) { +; CHECK-LABEL: f7: +; CHECK: vpkh %v24, %v24, %v24 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> undef, <16 x i8> %val, + <16 x i32> <i32 7, i32 1, i32 9, i32 15, + i32 15, i32 3, i32 5, i32 1, + i32 17, i32 19, i32 21, i32 23, + i32 25, i32 27, i32 29, i32 31> + ret <16 x i8> %ret +} + +; Test a canonical v8i16 pack. +define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f8: +; CHECK: vpkf %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 1, i32 3, i32 5, i32 7, + i32 9, i32 11, i32 13, i32 15> + ret <8 x i16> %ret +} + +; Test a reversed v8i16 pack. +define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f9: +; CHECK: vpkf %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 9, i32 11, i32 13, i32 15, + i32 1, i32 3, i32 5, i32 7> + ret <8 x i16> %ret +} + +; Test a canonical v4i32 pack. +define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f10: +; CHECK: vpkg %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + ret <4 x i32> %ret +} + +; Test a reversed v4i32 pack. +define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f11: +; CHECK: vpkg %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 5, i32 7, i32 1, i32 3> + ret <4 x i32> %ret +} + +; Test a canonical v4f32 pack. +define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f12: +; CHECK: vpkg %v24, %v24, %v26 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 1, i32 3, i32 5, i32 7> + ret <4 x float> %ret +} + +; Test a reversed v4f32 pack. +define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f13: +; CHECK: vpkg %v24, %v26, %v24 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 5, i32 7, i32 1, i32 3> + ret <4 x float> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-07.ll b/test/CodeGen/SystemZ/vec-perm-07.ll new file mode 100644 index 000000000000..9a370af2c0e7 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-07.ll @@ -0,0 +1,145 @@ +; Test vector shift left double immediate. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 shift with the lowest useful shift amount. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vsldb %v24, %v24, %v26, 1 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 1, i32 2, i32 3, i32 4, + i32 5, i32 6, i32 7, i32 8, + i32 9, i32 10, i32 11, i32 12, + i32 13, i32 14, i32 15, i32 16> + ret <16 x i8> %ret +} + +; Test a v16i8 shift with the highest shift amount. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vsldb %v24, %v24, %v26, 15 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 15, i32 16, i32 17, i32 18, + i32 19, i32 20, i32 21, i32 22, + i32 23, i32 24, i32 25, i32 26, + i32 27, i32 28, i32 29, i32 30> + ret <16 x i8> %ret +} + +; Test a v16i8 shift in which the operands need to be reversed. +define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vsldb %v24, %v26, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 20, i32 21, i32 22, i32 23, + i32 24, i32 25, i32 26, i32 27, + i32 28, i32 29, i32 30, i32 31, + i32 0, i32 1, i32 2, i32 3> + ret <16 x i8> %ret +} + +; Test a v16i8 shift in which the operands need to be duplicated. +define <16 x i8> @f4(<16 x i8> %val) { +; CHECK-LABEL: f4: +; CHECK: vsldb %v24, %v24, %v24, 7 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> <i32 7, i32 8, i32 9, i32 10, + i32 11, i32 12, i32 13, i32 14, + i32 15, i32 0, i32 1, i32 2, + i32 3, i32 4, i32 5, i32 6> + ret <16 x i8> %ret +} + +; Test a v16i8 shift in which some of the indices are undefs. +define <16 x i8> @f5(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f5: +; CHECK: vsldb %v24, %v24, %v26, 11 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, + i32 15, i32 16, i32 undef, i32 18, + i32 19, i32 20, i32 21, i32 22, + i32 23, i32 24, i32 25, i32 26> + ret <16 x i8> %ret +} + +; ...and again with reversed operands. +define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f6: +; CHECK: vsldb %v24, %v26, %v24, 13 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 undef, i32 undef, i32 31, i32 0, + i32 1, i32 2, i32 3, i32 4, + i32 5, i32 6, i32 7, i32 8, + i32 9, i32 10, i32 11, i32 12> + ret <16 x i8> %ret +} + +; Test a v8i16 shift with the lowest useful shift amount. +define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f7: +; CHECK: vsldb %v24, %v24, %v26, 2 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 1, i32 2, i32 3, i32 4, + i32 5, i32 6, i32 7, i32 8> + ret <8 x i16> %ret +} + +; Test a v8i16 shift with the highest useful shift amount. +define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f8: +; CHECK: vsldb %v24, %v24, %v26, 14 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 7, i32 8, i32 9, i32 10, + i32 11, i32 12, i32 13, i32 14> + ret <8 x i16> %ret +} + +; Test a v4i32 shift with the lowest useful shift amount. +define <4 x i32> @f9(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f9: +; CHECK: vsldb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x i32> %ret +} + +; Test a v4i32 shift with the highest useful shift amount. +define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f10: +; CHECK: vsldb %v24, %v24, %v26, 12 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 3, i32 4, i32 5, i32 6> + ret <4 x i32> %ret +} + +; Test a v4f32 shift with the lowest useful shift amount. +define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f12: +; CHECK: vsldb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x float> %ret +} + +; Test a v4f32 shift with the highest useful shift amount. +define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f13: +; CHECK: vsldb %v24, %v24, %v26, 12 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 3, i32 4, i32 5, i32 6> + ret <4 x float> %ret +} + +; We use VPDI for v2i64 shuffles. diff --git a/test/CodeGen/SystemZ/vec-perm-08.ll b/test/CodeGen/SystemZ/vec-perm-08.ll new file mode 100644 index 000000000000..a18ca7b73975 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-08.ll @@ -0,0 +1,170 @@ +; Test vector permutes using VPDI. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a high1/low2 permute for v16i8. +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vpdi %v24, %v24, %v26, 1 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7, + i32 24, i32 25, i32 26, i32 27, + i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %ret +} + +; Test a low2/high1 permute for v16i8. +define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: vpdi %v24, %v26, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 24, i32 25, i32 26, i32 27, + i32 28, i32 29, i32 30, i32 31, + i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7> + ret <16 x i8> %ret +} + +; Test a low1/high2 permute for v16i8. +define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f3: +; CHECK: vpdi %v24, %v24, %v26, 4 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 8, i32 9, i32 10, i32 undef, + i32 12, i32 undef, i32 14, i32 15, + i32 16, i32 17, i32 undef, i32 19, + i32 20, i32 21, i32 22, i32 undef> + ret <16 x i8> %ret +} + +; Test a high2/low1 permute for v16i8. +define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f4: +; CHECK: vpdi %v24, %v26, %v24, 1 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 16, i32 17, i32 18, i32 19, + i32 20, i32 21, i32 22, i32 23, + i32 8, i32 9, i32 10, i32 11, + i32 12, i32 13, i32 14, i32 15> + ret <16 x i8> %ret +} + +; Test reversing two doublewords in a v16i8. +define <16 x i8> @f5(<16 x i8> %val) { +; CHECK-LABEL: f5: +; CHECK: vpdi %v24, %v24, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <16 x i8> %val, <16 x i8> undef, + <16 x i32> <i32 8, i32 9, i32 10, i32 11, + i32 12, i32 13, i32 14, i32 15, + i32 0, i32 1, i32 2, i32 3, + i32 4, i32 5, i32 6, i32 7> + ret <16 x i8> %ret +} + +; Test a high1/low2 permute for v8i16. +define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f6: +; CHECK: vpdi %v24, %v24, %v26, 1 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 0, i32 1, i32 2, i32 3, + i32 12, i32 13, i32 14, i32 15> + ret <8 x i16> %ret +} + +; Test a low2/high1 permute for v8i16. +define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f7: +; CHECK: vpdi %v24, %v26, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 12, i32 13, i32 14, i32 15, + i32 0, i32 1, i32 2, i32 3> + ret <8 x i16> %ret +} + +; Test a high1/low2 permute for v4i32. +define <4 x i32> @f8(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f8: +; CHECK: vpdi %v24, %v24, %v26, 1 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 0, i32 1, i32 6, i32 7> + ret <4 x i32> %ret +} + +; Test a low2/high1 permute for v4i32. +define <4 x i32> @f9(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f9: +; CHECK: vpdi %v24, %v26, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 6, i32 7, i32 0, i32 1> + ret <4 x i32> %ret +} + +; Test a high1/low2 permute for v2i64. +define <2 x i64> @f10(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f10: +; CHECK: vpdi %v24, %v24, %v26, 1 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2, + <2 x i32> <i32 0, i32 3> + ret <2 x i64> %ret +} + +; Test low2/high1 permute for v2i64. +define <2 x i64> @f11(<2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f11: +; CHECK: vpdi %v24, %v26, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2, + <2 x i32> <i32 3, i32 0> + ret <2 x i64> %ret +} + +; Test a high1/low2 permute for v4f32. +define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f12: +; CHECK: vpdi %v24, %v24, %v26, 1 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 0, i32 1, i32 6, i32 7> + ret <4 x float> %ret +} + +; Test a low2/high1 permute for v4f32. +define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f13: +; CHECK: vpdi %v24, %v26, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <4 x float> %val1, <4 x float> %val2, + <4 x i32> <i32 6, i32 7, i32 0, i32 1> + ret <4 x float> %ret +} + +; Test a high1/low2 permute for v2f64. +define <2 x double> @f14(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f14: +; CHECK: vpdi %v24, %v24, %v26, 1 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val1, <2 x double> %val2, + <2 x i32> <i32 0, i32 3> + ret <2 x double> %ret +} + +; Test a low2/high1 permute for v2f64. +define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f15: +; CHECK: vpdi %v24, %v26, %v24, 4 +; CHECK: br %r14 + %ret = shufflevector <2 x double> %val1, <2 x double> %val2, + <2 x i32> <i32 3, i32 0> + ret <2 x double> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-09.ll b/test/CodeGen/SystemZ/vec-perm-09.ll new file mode 100644 index 000000000000..9c9632cf0305 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-09.ll @@ -0,0 +1,38 @@ +; Test general vector permute of a v16i8. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \ +; RUN: FileCheck -check-prefix=CHECK-CODE %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s + +define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) { +; CHECK-CODE-LABEL: f1: +; CHECK-CODE: larl [[REG:%r[0-5]]], +; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]]) +; CHECK-CODE: vperm %v24, %v24, %v26, [[MASK]] +; CHECK-CODE: br %r14 +; +; CHECK-VECTOR: .byte 1 +; CHECK-VECTOR-NEXT: .byte 19 +; CHECK-VECTOR-NEXT: .byte 6 +; CHECK-VECTOR-NEXT: .byte 5 +; CHECK-VECTOR-NEXT: .byte 20 +; CHECK-VECTOR-NEXT: .byte 22 +; CHECK-VECTOR-NEXT: .byte 1 +; CHECK-VECTOR-NEXT: .byte 1 +; CHECK-VECTOR-NEXT: .byte 25 +; CHECK-VECTOR-NEXT: .byte 29 +; CHECK-VECTOR-NEXT: .byte 11 +; Any byte would be OK here +; CHECK-VECTOR-NEXT: .space 1 +; CHECK-VECTOR-NEXT: .byte 31 +; CHECK-VECTOR-NEXT: .byte 4 +; CHECK-VECTOR-NEXT: .byte 15 +; CHECK-VECTOR-NEXT: .byte 19 + %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2, + <16 x i32> <i32 1, i32 19, i32 6, i32 5, + i32 20, i32 22, i32 1, i32 1, + i32 25, i32 29, i32 11, i32 undef, + i32 31, i32 4, i32 15, i32 19> + ret <16 x i8> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-10.ll b/test/CodeGen/SystemZ/vec-perm-10.ll new file mode 100644 index 000000000000..382e6dc4c3fb --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-10.ll @@ -0,0 +1,36 @@ +; Test general vector permute of a v8i16. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \ +; RUN: FileCheck -check-prefix=CHECK-CODE %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s + +define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) { +; CHECK-CODE-LABEL: f1: +; CHECK-CODE: larl [[REG:%r[0-5]]], +; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]]) +; CHECK-CODE: vperm %v24, %v26, %v24, [[MASK]] +; CHECK-CODE: br %r14 +; +; CHECK-VECTOR: .byte 0 +; CHECK-VECTOR-NEXT: .byte 1 +; CHECK-VECTOR-NEXT: .byte 26 +; CHECK-VECTOR-NEXT: .byte 27 +; Any 2 bytes would be OK here +; CHECK-VECTOR-NEXT: .space 1 +; CHECK-VECTOR-NEXT: .space 1 +; CHECK-VECTOR-NEXT: .byte 28 +; CHECK-VECTOR-NEXT: .byte 29 +; CHECK-VECTOR-NEXT: .byte 6 +; CHECK-VECTOR-NEXT: .byte 7 +; CHECK-VECTOR-NEXT: .byte 14 +; CHECK-VECTOR-NEXT: .byte 15 +; CHECK-VECTOR-NEXT: .byte 8 +; CHECK-VECTOR-NEXT: .byte 9 +; CHECK-VECTOR-NEXT: .byte 16 +; CHECK-VECTOR-NEXT: .byte 17 + %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2, + <8 x i32> <i32 8, i32 5, i32 undef, i32 6, + i32 11, i32 15, i32 12, i32 0> + ret <8 x i16> %ret +} diff --git a/test/CodeGen/SystemZ/vec-perm-11.ll b/test/CodeGen/SystemZ/vec-perm-11.ll new file mode 100644 index 000000000000..c9e29880fe07 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-perm-11.ll @@ -0,0 +1,35 @@ +; Test general vector permute of a v4i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \ +; RUN: FileCheck -check-prefix=CHECK-CODE %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \ +; RUN: FileCheck -check-prefix=CHECK-VECTOR %s + +define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) { +; CHECK-CODE-LABEL: f1: +; CHECK-CODE: larl [[REG:%r[0-5]]], +; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]]) +; CHECK-CODE: vperm %v24, %v26, %v24, [[MASK]] +; CHECK-CODE: br %r14 +; +; CHECK-VECTOR: .byte 4 +; CHECK-VECTOR-NEXT: .byte 5 +; CHECK-VECTOR-NEXT: .byte 6 +; CHECK-VECTOR-NEXT: .byte 7 +; CHECK-VECTOR-NEXT: .byte 20 +; CHECK-VECTOR-NEXT: .byte 21 +; CHECK-VECTOR-NEXT: .byte 22 +; CHECK-VECTOR-NEXT: .byte 23 +; Any 4 bytes would be OK here +; CHECK-VECTOR-NEXT: .space 1 +; CHECK-VECTOR-NEXT: .space 1 +; CHECK-VECTOR-NEXT: .space 1 +; CHECK-VECTOR-NEXT: .space 1 +; CHECK-VECTOR-NEXT: .byte 12 +; CHECK-VECTOR-NEXT: .byte 13 +; CHECK-VECTOR-NEXT: .byte 14 +; CHECK-VECTOR-NEXT: .byte 15 + %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2, + <4 x i32> <i32 5, i32 1, i32 undef, i32 7> + ret <4 x i32> %ret +} diff --git a/test/CodeGen/SystemZ/vec-round-01.ll b/test/CodeGen/SystemZ/vec-round-01.ll new file mode 100644 index 000000000000..82718276bb08 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-round-01.ll @@ -0,0 +1,118 @@ +; Test v2f64 rounding. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare double @llvm.rint.f64(double) +declare double @llvm.nearbyint.f64(double) +declare double @llvm.floor.f64(double) +declare double @llvm.ceil.f64(double) +declare double @llvm.trunc.f64(double) +declare double @llvm.round.f64(double) +declare <2 x double> @llvm.rint.v2f64(<2 x double>) +declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) +declare <2 x double> @llvm.floor.v2f64(<2 x double>) +declare <2 x double> @llvm.ceil.v2f64(<2 x double>) +declare <2 x double> @llvm.trunc.v2f64(<2 x double>) +declare <2 x double> @llvm.round.v2f64(<2 x double>) + +define <2 x double> @f1(<2 x double> %val) { +; CHECK-LABEL: f1: +; CHECK: vfidb %v24, %v24, 0, 0 +; CHECK: br %r14 + %res = call <2 x double> @llvm.rint.v2f64(<2 x double> %val) + ret <2 x double> %res +} + +define <2 x double> @f2(<2 x double> %val) { +; CHECK-LABEL: f2: +; CHECK: vfidb %v24, %v24, 4, 0 +; CHECK: br %r14 + %res = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %val) + ret <2 x double> %res +} + +define <2 x double> @f3(<2 x double> %val) { +; CHECK-LABEL: f3: +; CHECK: vfidb %v24, %v24, 4, 7 +; CHECK: br %r14 + %res = call <2 x double> @llvm.floor.v2f64(<2 x double> %val) + ret <2 x double> %res +} + +define <2 x double> @f4(<2 x double> %val) { +; CHECK-LABEL: f4: +; CHECK: vfidb %v24, %v24, 4, 6 +; CHECK: br %r14 + %res = call <2 x double> @llvm.ceil.v2f64(<2 x double> %val) + ret <2 x double> %res +} + +define <2 x double> @f5(<2 x double> %val) { +; CHECK-LABEL: f5: +; CHECK: vfidb %v24, %v24, 4, 5 +; CHECK: br %r14 + %res = call <2 x double> @llvm.trunc.v2f64(<2 x double> %val) + ret <2 x double> %res +} + +define <2 x double> @f6(<2 x double> %val) { +; CHECK-LABEL: f6: +; CHECK: vfidb %v24, %v24, 4, 1 +; CHECK: br %r14 + %res = call <2 x double> @llvm.round.v2f64(<2 x double> %val) + ret <2 x double> %res +} + +define double @f7(<2 x double> %val) { +; CHECK-LABEL: f7: +; CHECK: wfidb %f0, %v24, 0, 0 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %res = call double @llvm.rint.f64(double %scalar) + ret double %res +} + +define double @f8(<2 x double> %val) { +; CHECK-LABEL: f8: +; CHECK: wfidb %f0, %v24, 4, 0 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %res = call double @llvm.nearbyint.f64(double %scalar) + ret double %res +} + +define double @f9(<2 x double> %val) { +; CHECK-LABEL: f9: +; CHECK: wfidb %f0, %v24, 4, 7 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %res = call double @llvm.floor.f64(double %scalar) + ret double %res +} + +define double @f10(<2 x double> %val) { +; CHECK-LABEL: f10: +; CHECK: wfidb %f0, %v24, 4, 6 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %res = call double @llvm.ceil.f64(double %scalar) + ret double %res +} + +define double @f11(<2 x double> %val) { +; CHECK-LABEL: f11: +; CHECK: wfidb %f0, %v24, 4, 5 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %res = call double @llvm.trunc.f64(double %scalar) + ret double %res +} + +define double @f12(<2 x double> %val) { +; CHECK-LABEL: f12: +; CHECK: wfidb %f0, %v24, 4, 1 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %res = call double @llvm.round.f64(double %scalar) + ret double %res +} diff --git a/test/CodeGen/SystemZ/vec-shift-01.ll b/test/CodeGen/SystemZ/vec-shift-01.ll new file mode 100644 index 000000000000..be8605b182c9 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-shift-01.ll @@ -0,0 +1,39 @@ +; Test vector shift left with vector shift amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 shift. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: veslvb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = shl <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 shift. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: veslvh %v24, %v26, %v28 +; CHECK: br %r14 + %ret = shl <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 shift. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: veslvf %v24, %v26, %v28 +; CHECK: br %r14 + %ret = shl <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 shift. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: veslvg %v24, %v26, %v28 +; CHECK: br %r14 + %ret = shl <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-shift-02.ll b/test/CodeGen/SystemZ/vec-shift-02.ll new file mode 100644 index 000000000000..2825872e023d --- /dev/null +++ b/test/CodeGen/SystemZ/vec-shift-02.ll @@ -0,0 +1,39 @@ +; Test vector arithmetic shift right with vector shift amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 shift. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vesravb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = ashr <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 shift. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vesravh %v24, %v26, %v28 +; CHECK: br %r14 + %ret = ashr <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 shift. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vesravf %v24, %v26, %v28 +; CHECK: br %r14 + %ret = ashr <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 shift. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vesravg %v24, %v26, %v28 +; CHECK: br %r14 + %ret = ashr <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-shift-03.ll b/test/CodeGen/SystemZ/vec-shift-03.ll new file mode 100644 index 000000000000..c923d8b5d452 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-shift-03.ll @@ -0,0 +1,39 @@ +; Test vector logical shift right with vector shift amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 shift. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vesrlvb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = lshr <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 shift. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vesrlvh %v24, %v26, %v28 +; CHECK: br %r14 + %ret = lshr <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 shift. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vesrlvf %v24, %v26, %v28 +; CHECK: br %r14 + %ret = lshr <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 shift. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vesrlvg %v24, %v26, %v28 +; CHECK: br %r14 + %ret = lshr <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-shift-04.ll b/test/CodeGen/SystemZ/vec-shift-04.ll new file mode 100644 index 000000000000..6fd12897bf5a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-shift-04.ll @@ -0,0 +1,134 @@ +; Test vector shift left with scalar shift amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 shift by a variable. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, i32 %shift) { +; CHECK-LABEL: f1: +; CHECK: veslb %v24, %v26, 0(%r2) +; CHECK: br %r14 + %truncshift = trunc i32 %shift to i8 + %shiftvec = insertelement <16 x i8> undef, i8 %truncshift, i32 0 + %val2 = shufflevector <16 x i8> %shiftvec, <16 x i8> undef, + <16 x i32> zeroinitializer + %ret = shl <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v16i8 shift by the lowest useful constant. +define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val) { +; CHECK-LABEL: f2: +; CHECK: veslb %v24, %v26, 1 +; CHECK: br %r14 + %ret = shl <16 x i8> %val, <i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1> + ret <16 x i8> %ret +} + +; Test a v16i8 shift by the highest useful constant. +define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val) { +; CHECK-LABEL: f3: +; CHECK: veslb %v24, %v26, 7 +; CHECK: br %r14 + %ret = shl <16 x i8> %val, <i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7> + ret <16 x i8> %ret +} + +; Test a v8i16 shift by a variable. +define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, i32 %shift) { +; CHECK-LABEL: f4: +; CHECK: veslh %v24, %v26, 0(%r2) +; CHECK: br %r14 + %truncshift = trunc i32 %shift to i16 + %shiftvec = insertelement <8 x i16> undef, i16 %truncshift, i32 0 + %val2 = shufflevector <8 x i16> %shiftvec, <8 x i16> undef, + <8 x i32> zeroinitializer + %ret = shl <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v8i16 shift by the lowest useful constant. +define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val) { +; CHECK-LABEL: f5: +; CHECK: veslh %v24, %v26, 1 +; CHECK: br %r14 + %ret = shl <8 x i16> %val, <i16 1, i16 1, i16 1, i16 1, + i16 1, i16 1, i16 1, i16 1> + ret <8 x i16> %ret +} + +; Test a v8i16 shift by the highest useful constant. +define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val) { +; CHECK-LABEL: f6: +; CHECK: veslh %v24, %v26, 15 +; CHECK: br %r14 + %ret = shl <8 x i16> %val, <i16 15, i16 15, i16 15, i16 15, + i16 15, i16 15, i16 15, i16 15> + ret <8 x i16> %ret +} + +; Test a v4i32 shift by a variable. +define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, i32 %shift) { +; CHECK-LABEL: f7: +; CHECK: veslf %v24, %v26, 0(%r2) +; CHECK: br %r14 + %shiftvec = insertelement <4 x i32> undef, i32 %shift, i32 0 + %val2 = shufflevector <4 x i32> %shiftvec, <4 x i32> undef, + <4 x i32> zeroinitializer + %ret = shl <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v4i32 shift by the lowest useful constant. +define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val) { +; CHECK-LABEL: f8: +; CHECK: veslf %v24, %v26, 1 +; CHECK: br %r14 + %ret = shl <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1> + ret <4 x i32> %ret +} + +; Test a v4i32 shift by the highest useful constant. +define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val) { +; CHECK-LABEL: f9: +; CHECK: veslf %v24, %v26, 31 +; CHECK: br %r14 + %ret = shl <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31> + ret <4 x i32> %ret +} + +; Test a v2i64 shift by a variable. +define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, i32 %shift) { +; CHECK-LABEL: f10: +; CHECK: veslg %v24, %v26, 0(%r2) +; CHECK: br %r14 + %extshift = sext i32 %shift to i64 + %shiftvec = insertelement <2 x i64> undef, i64 %extshift, i32 0 + %val2 = shufflevector <2 x i64> %shiftvec, <2 x i64> undef, + <2 x i32> zeroinitializer + %ret = shl <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} + +; Test a v2i64 shift by the lowest useful constant. +define <2 x i64> @f11(<2 x i64> %dummy, <2 x i64> %val) { +; CHECK-LABEL: f11: +; CHECK: veslg %v24, %v26, 1 +; CHECK: br %r14 + %ret = shl <2 x i64> %val, <i64 1, i64 1> + ret <2 x i64> %ret +} + +; Test a v2i64 shift by the highest useful constant. +define <2 x i64> @f12(<2 x i64> %dummy, <2 x i64> %val) { +; CHECK-LABEL: f12: +; CHECK: veslg %v24, %v26, 63 +; CHECK: br %r14 + %ret = shl <2 x i64> %val, <i64 63, i64 63> + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-shift-05.ll b/test/CodeGen/SystemZ/vec-shift-05.ll new file mode 100644 index 000000000000..22ce46b2d0d6 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-shift-05.ll @@ -0,0 +1,134 @@ +; Test vector arithmetic shift right with scalar shift amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 shift by a variable. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, i32 %shift) { +; CHECK-LABEL: f1: +; CHECK: vesrab %v24, %v26, 0(%r2) +; CHECK: br %r14 + %truncshift = trunc i32 %shift to i8 + %shiftvec = insertelement <16 x i8> undef, i8 %truncshift, i32 0 + %val2 = shufflevector <16 x i8> %shiftvec, <16 x i8> undef, + <16 x i32> zeroinitializer + %ret = ashr <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v16i8 shift by the lowest useful constant. +define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val) { +; CHECK-LABEL: f2: +; CHECK: vesrab %v24, %v26, 1 +; CHECK: br %r14 + %ret = ashr <16 x i8> %val, <i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1> + ret <16 x i8> %ret +} + +; Test a v16i8 shift by the highest useful constant. +define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val) { +; CHECK-LABEL: f3: +; CHECK: vesrab %v24, %v26, 7 +; CHECK: br %r14 + %ret = ashr <16 x i8> %val, <i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7> + ret <16 x i8> %ret +} + +; Test a v8i16 shift by a variable. +define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, i32 %shift) { +; CHECK-LABEL: f4: +; CHECK: vesrah %v24, %v26, 0(%r2) +; CHECK: br %r14 + %truncshift = trunc i32 %shift to i16 + %shiftvec = insertelement <8 x i16> undef, i16 %truncshift, i32 0 + %val2 = shufflevector <8 x i16> %shiftvec, <8 x i16> undef, + <8 x i32> zeroinitializer + %ret = ashr <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v8i16 shift by the lowest useful constant. +define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val) { +; CHECK-LABEL: f5: +; CHECK: vesrah %v24, %v26, 1 +; CHECK: br %r14 + %ret = ashr <8 x i16> %val, <i16 1, i16 1, i16 1, i16 1, + i16 1, i16 1, i16 1, i16 1> + ret <8 x i16> %ret +} + +; Test a v8i16 shift by the highest useful constant. +define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val) { +; CHECK-LABEL: f6: +; CHECK: vesrah %v24, %v26, 15 +; CHECK: br %r14 + %ret = ashr <8 x i16> %val, <i16 15, i16 15, i16 15, i16 15, + i16 15, i16 15, i16 15, i16 15> + ret <8 x i16> %ret +} + +; Test a v4i32 shift by a variable. +define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, i32 %shift) { +; CHECK-LABEL: f7: +; CHECK: vesraf %v24, %v26, 0(%r2) +; CHECK: br %r14 + %shiftvec = insertelement <4 x i32> undef, i32 %shift, i32 0 + %val2 = shufflevector <4 x i32> %shiftvec, <4 x i32> undef, + <4 x i32> zeroinitializer + %ret = ashr <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v4i32 shift by the lowest useful constant. +define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val) { +; CHECK-LABEL: f8: +; CHECK: vesraf %v24, %v26, 1 +; CHECK: br %r14 + %ret = ashr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1> + ret <4 x i32> %ret +} + +; Test a v4i32 shift by the highest useful constant. +define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val) { +; CHECK-LABEL: f9: +; CHECK: vesraf %v24, %v26, 31 +; CHECK: br %r14 + %ret = ashr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31> + ret <4 x i32> %ret +} + +; Test a v2i64 shift by a variable. +define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, i32 %shift) { +; CHECK-LABEL: f10: +; CHECK: vesrag %v24, %v26, 0(%r2) +; CHECK: br %r14 + %extshift = sext i32 %shift to i64 + %shiftvec = insertelement <2 x i64> undef, i64 %extshift, i32 0 + %val2 = shufflevector <2 x i64> %shiftvec, <2 x i64> undef, + <2 x i32> zeroinitializer + %ret = ashr <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} + +; Test a v2i64 shift by the lowest useful constant. +define <2 x i64> @f11(<2 x i64> %dummy, <2 x i64> %val) { +; CHECK-LABEL: f11: +; CHECK: vesrag %v24, %v26, 1 +; CHECK: br %r14 + %ret = ashr <2 x i64> %val, <i64 1, i64 1> + ret <2 x i64> %ret +} + +; Test a v2i64 shift by the highest useful constant. +define <2 x i64> @f12(<2 x i64> %dummy, <2 x i64> %val) { +; CHECK-LABEL: f12: +; CHECK: vesrag %v24, %v26, 63 +; CHECK: br %r14 + %ret = ashr <2 x i64> %val, <i64 63, i64 63> + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-shift-06.ll b/test/CodeGen/SystemZ/vec-shift-06.ll new file mode 100644 index 000000000000..8a5bb0a9a55a --- /dev/null +++ b/test/CodeGen/SystemZ/vec-shift-06.ll @@ -0,0 +1,134 @@ +; Test vector logical shift right with scalar shift amount. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 shift by a variable. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, i32 %shift) { +; CHECK-LABEL: f1: +; CHECK: vesrlb %v24, %v26, 0(%r2) +; CHECK: br %r14 + %truncshift = trunc i32 %shift to i8 + %shiftvec = insertelement <16 x i8> undef, i8 %truncshift, i32 0 + %val2 = shufflevector <16 x i8> %shiftvec, <16 x i8> undef, + <16 x i32> zeroinitializer + %ret = lshr <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v16i8 shift by the lowest useful constant. +define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val) { +; CHECK-LABEL: f2: +; CHECK: vesrlb %v24, %v26, 1 +; CHECK: br %r14 + %ret = lshr <16 x i8> %val, <i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1, + i8 1, i8 1, i8 1, i8 1> + ret <16 x i8> %ret +} + +; Test a v16i8 shift by the highest useful constant. +define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val) { +; CHECK-LABEL: f3: +; CHECK: vesrlb %v24, %v26, 7 +; CHECK: br %r14 + %ret = lshr <16 x i8> %val, <i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7, + i8 7, i8 7, i8 7, i8 7> + ret <16 x i8> %ret +} + +; Test a v8i16 shift by a variable. +define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, i32 %shift) { +; CHECK-LABEL: f4: +; CHECK: vesrlh %v24, %v26, 0(%r2) +; CHECK: br %r14 + %truncshift = trunc i32 %shift to i16 + %shiftvec = insertelement <8 x i16> undef, i16 %truncshift, i32 0 + %val2 = shufflevector <8 x i16> %shiftvec, <8 x i16> undef, + <8 x i32> zeroinitializer + %ret = lshr <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v8i16 shift by the lowest useful constant. +define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val) { +; CHECK-LABEL: f5: +; CHECK: vesrlh %v24, %v26, 1 +; CHECK: br %r14 + %ret = lshr <8 x i16> %val, <i16 1, i16 1, i16 1, i16 1, + i16 1, i16 1, i16 1, i16 1> + ret <8 x i16> %ret +} + +; Test a v8i16 shift by the highest useful constant. +define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val) { +; CHECK-LABEL: f6: +; CHECK: vesrlh %v24, %v26, 15 +; CHECK: br %r14 + %ret = lshr <8 x i16> %val, <i16 15, i16 15, i16 15, i16 15, + i16 15, i16 15, i16 15, i16 15> + ret <8 x i16> %ret +} + +; Test a v4i32 shift by a variable. +define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, i32 %shift) { +; CHECK-LABEL: f7: +; CHECK: vesrlf %v24, %v26, 0(%r2) +; CHECK: br %r14 + %shiftvec = insertelement <4 x i32> undef, i32 %shift, i32 0 + %val2 = shufflevector <4 x i32> %shiftvec, <4 x i32> undef, + <4 x i32> zeroinitializer + %ret = lshr <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v4i32 shift by the lowest useful constant. +define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val) { +; CHECK-LABEL: f8: +; CHECK: vesrlf %v24, %v26, 1 +; CHECK: br %r14 + %ret = lshr <4 x i32> %val, <i32 1, i32 1, i32 1, i32 1> + ret <4 x i32> %ret +} + +; Test a v4i32 shift by the highest useful constant. +define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val) { +; CHECK-LABEL: f9: +; CHECK: vesrlf %v24, %v26, 31 +; CHECK: br %r14 + %ret = lshr <4 x i32> %val, <i32 31, i32 31, i32 31, i32 31> + ret <4 x i32> %ret +} + +; Test a v2i64 shift by a variable. +define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, i32 %shift) { +; CHECK-LABEL: f10: +; CHECK: vesrlg %v24, %v26, 0(%r2) +; CHECK: br %r14 + %extshift = sext i32 %shift to i64 + %shiftvec = insertelement <2 x i64> undef, i64 %extshift, i32 0 + %val2 = shufflevector <2 x i64> %shiftvec, <2 x i64> undef, + <2 x i32> zeroinitializer + %ret = lshr <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} + +; Test a v2i64 shift by the lowest useful constant. +define <2 x i64> @f11(<2 x i64> %dummy, <2 x i64> %val) { +; CHECK-LABEL: f11: +; CHECK: vesrlg %v24, %v26, 1 +; CHECK: br %r14 + %ret = lshr <2 x i64> %val, <i64 1, i64 1> + ret <2 x i64> %ret +} + +; Test a v2i64 shift by the highest useful constant. +define <2 x i64> @f12(<2 x i64> %dummy, <2 x i64> %val) { +; CHECK-LABEL: f12: +; CHECK: vesrlg %v24, %v26, 63 +; CHECK: br %r14 + %ret = lshr <2 x i64> %val, <i64 63, i64 63> + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-shift-07.ll b/test/CodeGen/SystemZ/vec-shift-07.ll new file mode 100644 index 000000000000..f229c5e25a46 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-shift-07.ll @@ -0,0 +1,182 @@ +; Test vector sign extensions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i1->v16i8 extension. +define <16 x i8> @f1(<16 x i8> %val) { +; CHECK-LABEL: f1: +; CHECK: veslb [[REG:%v[0-9]+]], %v24, 7 +; CHECK: vesrab %v24, [[REG]], 7 +; CHECK: br %r14 + %trunc = trunc <16 x i8> %val to <16 x i1> + %ret = sext <16 x i1> %trunc to <16 x i8> + ret <16 x i8> %ret +} + +; Test a v8i1->v8i16 extension. +define <8 x i16> @f2(<8 x i16> %val) { +; CHECK-LABEL: f2: +; CHECK: veslh [[REG:%v[0-9]+]], %v24, 15 +; CHECK: vesrah %v24, [[REG]], 15 +; CHECK: br %r14 + %trunc = trunc <8 x i16> %val to <8 x i1> + %ret = sext <8 x i1> %trunc to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v8i8->v8i16 extension. +define <8 x i16> @f3(<8 x i16> %val) { +; CHECK-LABEL: f3: +; CHECK: veslh [[REG:%v[0-9]+]], %v24, 8 +; CHECK: vesrah %v24, [[REG]], 8 +; CHECK: br %r14 + %trunc = trunc <8 x i16> %val to <8 x i8> + %ret = sext <8 x i8> %trunc to <8 x i16> + ret <8 x i16> %ret +} + +; Test a v4i1->v4i32 extension. +define <4 x i32> @f4(<4 x i32> %val) { +; CHECK-LABEL: f4: +; CHECK: veslf [[REG:%v[0-9]+]], %v24, 31 +; CHECK: vesraf %v24, [[REG]], 31 +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i1> + %ret = sext <4 x i1> %trunc to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i8->v4i32 extension. +define <4 x i32> @f5(<4 x i32> %val) { +; CHECK-LABEL: f5: +; CHECK: veslf [[REG:%v[0-9]+]], %v24, 24 +; CHECK: vesraf %v24, [[REG]], 24 +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i8> + %ret = sext <4 x i8> %trunc to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v4i16->v4i32 extension. +define <4 x i32> @f6(<4 x i32> %val) { +; CHECK-LABEL: f6: +; CHECK: veslf [[REG:%v[0-9]+]], %v24, 16 +; CHECK: vesraf %v24, [[REG]], 16 +; CHECK: br %r14 + %trunc = trunc <4 x i32> %val to <4 x i16> + %ret = sext <4 x i16> %trunc to <4 x i32> + ret <4 x i32> %ret +} + +; Test a v2i1->v2i64 extension. +define <2 x i64> @f7(<2 x i64> %val) { +; CHECK-LABEL: f7: +; CHECK: veslg [[REG:%v[0-9]+]], %v24, 63 +; CHECK: vesrag %v24, [[REG]], 63 +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i1> + %ret = sext <2 x i1> %trunc to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i8->v2i64 extension. +define <2 x i64> @f8(<2 x i64> %val) { +; CHECK-LABEL: f8: +; CHECK: vsegb %v24, %v24 +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i8> + %ret = sext <2 x i8> %trunc to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i16->v2i64 extension. +define <2 x i64> @f9(<2 x i64> %val) { +; CHECK-LABEL: f9: +; CHECK: vsegh %v24, %v24 +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i16> + %ret = sext <2 x i16> %trunc to <2 x i64> + ret <2 x i64> %ret +} + +; Test a v2i32->v2i64 extension. +define <2 x i64> @f10(<2 x i64> %val) { +; CHECK-LABEL: f10: +; CHECK: vsegf %v24, %v24 +; CHECK: br %r14 + %trunc = trunc <2 x i64> %val to <2 x i32> + %ret = sext <2 x i32> %trunc to <2 x i64> + ret <2 x i64> %ret +} + +; Test an alternative v2i8->v2i64 extension. +define <2 x i64> @f11(<2 x i64> %val) { +; CHECK-LABEL: f11: +; CHECK: vsegb %v24, %v24 +; CHECK: br %r14 + %shl = shl <2 x i64> %val, <i64 56, i64 56> + %ret = ashr <2 x i64> %shl, <i64 56, i64 56> + ret <2 x i64> %ret +} + +; Test an alternative v2i16->v2i64 extension. +define <2 x i64> @f12(<2 x i64> %val) { +; CHECK-LABEL: f12: +; CHECK: vsegh %v24, %v24 +; CHECK: br %r14 + %shl = shl <2 x i64> %val, <i64 48, i64 48> + %ret = ashr <2 x i64> %shl, <i64 48, i64 48> + ret <2 x i64> %ret +} + +; Test an alternative v2i32->v2i64 extension. +define <2 x i64> @f13(<2 x i64> %val) { +; CHECK-LABEL: f13: +; CHECK: vsegf %v24, %v24 +; CHECK: br %r14 + %shl = shl <2 x i64> %val, <i64 32, i64 32> + %ret = ashr <2 x i64> %shl, <i64 32, i64 32> + ret <2 x i64> %ret +} + +; Test an extraction-based v2i8->v2i64 extension. +define <2 x i64> @f14(<16 x i8> %val) { +; CHECK-LABEL: f14: +; CHECK: vsegb %v24, %v24 +; CHECK: br %r14 + %elt0 = extractelement <16 x i8> %val, i32 7 + %elt1 = extractelement <16 x i8> %val, i32 15 + %ext0 = sext i8 %elt0 to i64 + %ext1 = sext i8 %elt1 to i64 + %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0 + %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1 + ret <2 x i64> %vec1 +} + +; Test an extraction-based v2i16->v2i64 extension. +define <2 x i64> @f15(<16 x i16> %val) { +; CHECK-LABEL: f15: +; CHECK: vsegh %v24, %v24 +; CHECK: br %r14 + %elt0 = extractelement <16 x i16> %val, i32 3 + %elt1 = extractelement <16 x i16> %val, i32 7 + %ext0 = sext i16 %elt0 to i64 + %ext1 = sext i16 %elt1 to i64 + %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0 + %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1 + ret <2 x i64> %vec1 +} + +; Test an extraction-based v2i32->v2i64 extension. +define <2 x i64> @f16(<16 x i32> %val) { +; CHECK-LABEL: f16: +; CHECK: vsegf %v24, %v24 +; CHECK: br %r14 + %elt0 = extractelement <16 x i32> %val, i32 1 + %elt1 = extractelement <16 x i32> %val, i32 3 + %ext0 = sext i32 %elt0 to i64 + %ext1 = sext i32 %elt1 to i64 + %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0 + %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1 + ret <2 x i64> %vec1 +} diff --git a/test/CodeGen/SystemZ/vec-sqrt-01.ll b/test/CodeGen/SystemZ/vec-sqrt-01.ll new file mode 100644 index 000000000000..5c3ffb3b0643 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-sqrt-01.ll @@ -0,0 +1,23 @@ +; Test f64 and v2f64 square root. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +declare double @llvm.sqrt.f64(double) +declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) + +define <2 x double> @f1(<2 x double> %val) { +; CHECK-LABEL: f1: +; CHECK: vfsqdb %v24, %v24 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %val) + ret <2 x double> %ret +} + +define double @f2(<2 x double> %val) { +; CHECK-LABEL: f2: +; CHECK: wfsqdb %f0, %v24 +; CHECK: br %r14 + %scalar = extractelement <2 x double> %val, i32 0 + %ret = call double @llvm.sqrt.f64(double %scalar) + ret double %ret +} diff --git a/test/CodeGen/SystemZ/vec-sub-01.ll b/test/CodeGen/SystemZ/vec-sub-01.ll new file mode 100644 index 000000000000..4afad8bef659 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-sub-01.ll @@ -0,0 +1,148 @@ +; Test vector subtraction. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 subtraction. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vsb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 subtraction. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vsh %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 subtraction. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vsf %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 subtraction. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vsg %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} + +; Test a v4f32 subtraction, as an example of an operation that needs to be +; scalarized and reassembled. At present there's an unnecessary move that +; could be avoided with smarter ordering. It also isn't important whether +; the VSLDBs use the result of the VLRs or use %v24 and %v26 directly. +define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f5: +; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24 +; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26 +; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v[[A1]], 1 +; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v[[A2]], 1 +; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v[[A1]], 2 +; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2 +; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3 +; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3 +; CHECK-DAG: ler %f[[A1copy:[0-5]]], %f[[A1]] +; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]] +; CHECK-DAG: sebr %f[[B1]], %f[[B2]] +; CHECK-DAG: sebr %f[[C1]], %f[[C2]] +; CHECK-DAG: sebr %f[[D1]], %f[[D2]] +; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1copy]], %v[[B1]] +; CHECK-DAG: vmrhf [[LOW:%v[0-9]+]], %v[[C1]], %v[[D1]] +; CHECK: vmrhg %v24, [[HIGH]], [[LOW]] +; CHECK: br %r14 + %ret = fsub <4 x float> %val1, %val2 + ret <4 x float> %ret +} + +; Test a v2f64 subtraction. +define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f6: +; CHECK: vfsdb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = fsub <2 x double> %val1, %val2 + ret <2 x double> %ret +} + +; Test an f64 subtraction that uses vector registers. +define double @f7(<2 x double> %val1, <2 x double> %val2) { +; CHECK-LABEL: f7: +; CHECK: wfsdb %f0, %v24, %v26 +; CHECK: br %r14 + %scalar1 = extractelement <2 x double> %val1, i32 0 + %scalar2 = extractelement <2 x double> %val2, i32 0 + %ret = fsub double %scalar1, %scalar2 + ret double %ret +} + +; Test a v2i8 subtraction, which gets promoted to v16i8. +define <2 x i8> @f8(<2 x i8> %dummy, <2 x i8> %val1, <2 x i8> %val2) { +; CHECK-LABEL: f8: +; CHECK: vsb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <2 x i8> %val1, %val2 + ret <2 x i8> %ret +} + +; Test a v4i8 subtraction, which gets promoted to v16i8. +define <4 x i8> @f9(<4 x i8> %dummy, <4 x i8> %val1, <4 x i8> %val2) { +; CHECK-LABEL: f9: +; CHECK: vsb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <4 x i8> %val1, %val2 + ret <4 x i8> %ret +} + +; Test a v8i8 subtraction, which gets promoted to v16i8. +define <8 x i8> @f10(<8 x i8> %dummy, <8 x i8> %val1, <8 x i8> %val2) { +; CHECK-LABEL: f10: +; CHECK: vsb %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <8 x i8> %val1, %val2 + ret <8 x i8> %ret +} + +; Test a v2i16 subtraction, which gets promoted to v8i16. +define <2 x i16> @f11(<2 x i16> %dummy, <2 x i16> %val1, <2 x i16> %val2) { +; CHECK-LABEL: f11: +; CHECK: vsh %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <2 x i16> %val1, %val2 + ret <2 x i16> %ret +} + +; Test a v4i16 subtraction, which gets promoted to v8i16. +define <4 x i16> @f12(<4 x i16> %dummy, <4 x i16> %val1, <4 x i16> %val2) { +; CHECK-LABEL: f12: +; CHECK: vsh %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <4 x i16> %val1, %val2 + ret <4 x i16> %ret +} + +; Test a v2i32 subtraction, which gets promoted to v4i32. +define <2 x i32> @f13(<2 x i32> %dummy, <2 x i32> %val1, <2 x i32> %val2) { +; CHECK-LABEL: f13: +; CHECK: vsf %v24, %v26, %v28 +; CHECK: br %r14 + %ret = sub <2 x i32> %val1, %val2 + ret <2 x i32> %ret +} + +; Test a v2f32 subtraction, which gets promoted to v4f32. +define <2 x float> @f14(<2 x float> %val1, <2 x float> %val2) { +; No particular output expected, but must compile. + %ret = fsub <2 x float> %val1, %val2 + ret <2 x float> %ret +} diff --git a/test/CodeGen/SystemZ/vec-xor-01.ll b/test/CodeGen/SystemZ/vec-xor-01.ll new file mode 100644 index 000000000000..063b768117c1 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-xor-01.ll @@ -0,0 +1,39 @@ +; Test vector XOR. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test a v16i8 XOR. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <16 x i8> %val1, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 XOR. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <8 x i16> %val1, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 XOR. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <4 x i32> %val1, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 XOR. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <2 x i64> %val1, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/xor-01.ll b/test/CodeGen/SystemZ/xor-01.ll index 185d6bb0a754..e0aaffbb257e 100644 --- a/test/CodeGen/SystemZ/xor-01.ll +++ b/test/CodeGen/SystemZ/xor-01.ll @@ -19,7 +19,7 @@ define i32 @f2(i32 %a, i32 *%src) { ; CHECK-LABEL: f2: ; CHECK: x %r2, 0(%r3) ; CHECK: br %r14 - %b = load i32 *%src + %b = load i32 , i32 *%src %xor = xor i32 %a, %b ret i32 %xor } @@ -29,8 +29,8 @@ define i32 @f3(i32 %a, i32 *%src) { ; CHECK-LABEL: f3: ; CHECK: x %r2, 4092(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1023 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1023 + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -40,8 +40,8 @@ define i32 @f4(i32 %a, i32 *%src) { ; CHECK-LABEL: f4: ; CHECK: xy %r2, 4096(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 1024 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 1024 + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -51,8 +51,8 @@ define i32 @f5(i32 %a, i32 *%src) { ; CHECK-LABEL: f5: ; CHECK: xy %r2, 524284(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131071 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131071 + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -64,8 +64,8 @@ define i32 @f6(i32 %a, i32 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: x %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 131072 + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -75,8 +75,8 @@ define i32 @f7(i32 %a, i32 *%src) { ; CHECK-LABEL: f7: ; CHECK: xy %r2, -4(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -1 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -1 + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -86,8 +86,8 @@ define i32 @f8(i32 %a, i32 *%src) { ; CHECK-LABEL: f8: ; CHECK: xy %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131072 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131072 + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -99,8 +99,8 @@ define i32 @f9(i32 %a, i32 *%src) { ; CHECK: agfi %r3, -524292 ; CHECK: x %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i32 *%src, i64 -131073 - %b = load i32 *%ptr + %ptr = getelementptr i32, i32 *%src, i64 -131073 + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -113,7 +113,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4092 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -126,7 +126,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i32 * - %b = load i32 *%ptr + %b = load i32 , i32 *%ptr %xor = xor i32 %a, %b ret i32 %xor } @@ -137,26 +137,26 @@ define i32 @f12(i32 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: x %r2, 16{{[04]}}(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i32 *%ptr0, i64 2 - %ptr2 = getelementptr i32 *%ptr0, i64 4 - %ptr3 = getelementptr i32 *%ptr0, i64 6 - %ptr4 = getelementptr i32 *%ptr0, i64 8 - %ptr5 = getelementptr i32 *%ptr0, i64 10 - %ptr6 = getelementptr i32 *%ptr0, i64 12 - %ptr7 = getelementptr i32 *%ptr0, i64 14 - %ptr8 = getelementptr i32 *%ptr0, i64 16 - %ptr9 = getelementptr i32 *%ptr0, i64 18 - - %val0 = load i32 *%ptr0 - %val1 = load i32 *%ptr1 - %val2 = load i32 *%ptr2 - %val3 = load i32 *%ptr3 - %val4 = load i32 *%ptr4 - %val5 = load i32 *%ptr5 - %val6 = load i32 *%ptr6 - %val7 = load i32 *%ptr7 - %val8 = load i32 *%ptr8 - %val9 = load i32 *%ptr9 + %ptr1 = getelementptr i32, i32 *%ptr0, i64 2 + %ptr2 = getelementptr i32, i32 *%ptr0, i64 4 + %ptr3 = getelementptr i32, i32 *%ptr0, i64 6 + %ptr4 = getelementptr i32, i32 *%ptr0, i64 8 + %ptr5 = getelementptr i32, i32 *%ptr0, i64 10 + %ptr6 = getelementptr i32, i32 *%ptr0, i64 12 + %ptr7 = getelementptr i32, i32 *%ptr0, i64 14 + %ptr8 = getelementptr i32, i32 *%ptr0, i64 16 + %ptr9 = getelementptr i32, i32 *%ptr0, i64 18 + + %val0 = load i32 , i32 *%ptr0 + %val1 = load i32 , i32 *%ptr1 + %val2 = load i32 , i32 *%ptr2 + %val3 = load i32 , i32 *%ptr3 + %val4 = load i32 , i32 *%ptr4 + %val5 = load i32 , i32 *%ptr5 + %val6 = load i32 , i32 *%ptr6 + %val7 = load i32 , i32 *%ptr7 + %val8 = load i32 , i32 *%ptr8 + %val9 = load i32 , i32 *%ptr9 %ret = call i32 @foo() diff --git a/test/CodeGen/SystemZ/xor-03.ll b/test/CodeGen/SystemZ/xor-03.ll index ab7f2584b60d..36fb1df45a84 100644 --- a/test/CodeGen/SystemZ/xor-03.ll +++ b/test/CodeGen/SystemZ/xor-03.ll @@ -19,7 +19,7 @@ define i64 @f2(i64 %a, i64 *%src) { ; CHECK-LABEL: f2: ; CHECK: xg %r2, 0(%r3) ; CHECK: br %r14 - %b = load i64 *%src + %b = load i64 , i64 *%src %xor = xor i64 %a, %b ret i64 %xor } @@ -29,8 +29,8 @@ define i64 @f3(i64 %a, i64 *%src) { ; CHECK-LABEL: f3: ; CHECK: xg %r2, 524280(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65535 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr %xor = xor i64 %a, %b ret i64 %xor } @@ -42,8 +42,8 @@ define i64 @f4(i64 %a, i64 *%src) { ; CHECK: agfi %r3, 524288 ; CHECK: xg %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr %xor = xor i64 %a, %b ret i64 %xor } @@ -53,8 +53,8 @@ define i64 @f5(i64 %a, i64 *%src) { ; CHECK-LABEL: f5: ; CHECK: xg %r2, -8(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -1 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr %xor = xor i64 %a, %b ret i64 %xor } @@ -64,8 +64,8 @@ define i64 @f6(i64 %a, i64 *%src) { ; CHECK-LABEL: f6: ; CHECK: xg %r2, -524288(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65536 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr %xor = xor i64 %a, %b ret i64 %xor } @@ -77,8 +77,8 @@ define i64 @f7(i64 %a, i64 *%src) { ; CHECK: agfi %r3, -524296 ; CHECK: xg %r2, 0(%r3) ; CHECK: br %r14 - %ptr = getelementptr i64 *%src, i64 -65537 - %b = load i64 *%ptr + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr %xor = xor i64 %a, %b ret i64 %xor } @@ -91,7 +91,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 524280 %ptr = inttoptr i64 %add2 to i64 * - %b = load i64 *%ptr + %b = load i64 , i64 *%ptr %xor = xor i64 %a, %b ret i64 %xor } @@ -102,26 +102,26 @@ define i64 @f9(i64 *%ptr0) { ; CHECK: brasl %r14, foo@PLT ; CHECK: xg %r2, 160(%r15) ; CHECK: br %r14 - %ptr1 = getelementptr i64 *%ptr0, i64 2 - %ptr2 = getelementptr i64 *%ptr0, i64 4 - %ptr3 = getelementptr i64 *%ptr0, i64 6 - %ptr4 = getelementptr i64 *%ptr0, i64 8 - %ptr5 = getelementptr i64 *%ptr0, i64 10 - %ptr6 = getelementptr i64 *%ptr0, i64 12 - %ptr7 = getelementptr i64 *%ptr0, i64 14 - %ptr8 = getelementptr i64 *%ptr0, i64 16 - %ptr9 = getelementptr i64 *%ptr0, i64 18 + %ptr1 = getelementptr i64, i64 *%ptr0, i64 2 + %ptr2 = getelementptr i64, i64 *%ptr0, i64 4 + %ptr3 = getelementptr i64, i64 *%ptr0, i64 6 + %ptr4 = getelementptr i64, i64 *%ptr0, i64 8 + %ptr5 = getelementptr i64, i64 *%ptr0, i64 10 + %ptr6 = getelementptr i64, i64 *%ptr0, i64 12 + %ptr7 = getelementptr i64, i64 *%ptr0, i64 14 + %ptr8 = getelementptr i64, i64 *%ptr0, i64 16 + %ptr9 = getelementptr i64, i64 *%ptr0, i64 18 - %val0 = load i64 *%ptr0 - %val1 = load i64 *%ptr1 - %val2 = load i64 *%ptr2 - %val3 = load i64 *%ptr3 - %val4 = load i64 *%ptr4 - %val5 = load i64 *%ptr5 - %val6 = load i64 *%ptr6 - %val7 = load i64 *%ptr7 - %val8 = load i64 *%ptr8 - %val9 = load i64 *%ptr9 + %val0 = load i64 , i64 *%ptr0 + %val1 = load i64 , i64 *%ptr1 + %val2 = load i64 , i64 *%ptr2 + %val3 = load i64 , i64 *%ptr3 + %val4 = load i64 , i64 *%ptr4 + %val5 = load i64 , i64 *%ptr5 + %val6 = load i64 , i64 *%ptr6 + %val7 = load i64 , i64 *%ptr7 + %val8 = load i64 , i64 *%ptr8 + %val9 = load i64 , i64 *%ptr9 %ret = call i64 @foo() diff --git a/test/CodeGen/SystemZ/xor-05.ll b/test/CodeGen/SystemZ/xor-05.ll index fbd5660ad058..7b79c7f544d0 100644 --- a/test/CodeGen/SystemZ/xor-05.ll +++ b/test/CodeGen/SystemZ/xor-05.ll @@ -7,7 +7,7 @@ define void @f1(i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: xi 0(%r2), 1 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %xor = xor i8 %val, -255 store i8 %xor, i8 *%ptr ret void @@ -18,7 +18,7 @@ define void @f2(i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %xor = xor i8 %val, -2 store i8 %xor, i8 *%ptr ret void @@ -29,7 +29,7 @@ define void @f3(i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: xi 0(%r2), 1 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 1 store i8 %xor, i8 *%ptr ret void @@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 254 store i8 %xor, i8 *%ptr ret void @@ -51,8 +51,8 @@ define void @f5(i8 *%src) { ; CHECK-LABEL: f5: ; CHECK: xi 4095(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4095 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4095 + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -63,8 +63,8 @@ define void @f6(i8 *%src) { ; CHECK-LABEL: f6: ; CHECK: xiy 4096(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 4096 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 4096 + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -75,8 +75,8 @@ define void @f7(i8 *%src) { ; CHECK-LABEL: f7: ; CHECK: xiy 524287(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524287 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524287 + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -89,8 +89,8 @@ define void @f8(i8 *%src) { ; CHECK: agfi %r2, 524288 ; CHECK: xi 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 524288 + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -101,8 +101,8 @@ define void @f9(i8 *%src) { ; CHECK-LABEL: f9: ; CHECK: xiy -1(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -1 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -1 + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -113,8 +113,8 @@ define void @f10(i8 *%src) { ; CHECK-LABEL: f10: ; CHECK: xiy -524288(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524288 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524288 + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -127,8 +127,8 @@ define void @f11(i8 *%src) { ; CHECK: agfi %r2, -524289 ; CHECK: xi 0(%r2), 127 ; CHECK: br %r14 - %ptr = getelementptr i8 *%src, i64 -524289 - %val = load i8 *%ptr + %ptr = getelementptr i8, i8 *%src, i64 -524289 + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -143,7 +143,7 @@ define void @f12(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4095 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void @@ -158,7 +158,7 @@ define void @f13(i64 %src, i64 %index) { %add1 = add i64 %src, %index %add2 = add i64 %add1, 4096 %ptr = inttoptr i64 %add2 to i8 * - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %xor = xor i8 %val, 127 store i8 %xor, i8 *%ptr ret void diff --git a/test/CodeGen/SystemZ/xor-06.ll b/test/CodeGen/SystemZ/xor-06.ll index f39c0fec4e40..40db3cb21a3e 100644 --- a/test/CodeGen/SystemZ/xor-06.ll +++ b/test/CodeGen/SystemZ/xor-06.ll @@ -8,7 +8,7 @@ define void @f1(i8 *%ptr) { ; CHECK-LABEL: f1: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %xor = xor i32 %ext, -2 %trunc = trunc i32 %xor to i8 @@ -21,7 +21,7 @@ define void @f2(i8 *%ptr) { ; CHECK-LABEL: f2: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %xor = xor i64 %ext, -2 %trunc = trunc i64 %xor to i8 @@ -34,7 +34,7 @@ define void @f3(i8 *%ptr) { ; CHECK-LABEL: f3: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i32 %xor = xor i32 %ext, 254 %trunc = trunc i32 %xor to i8 @@ -47,7 +47,7 @@ define void @f4(i8 *%ptr) { ; CHECK-LABEL: f4: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = zext i8 %val to i64 %xor = xor i64 %ext, 254 %trunc = trunc i64 %xor to i8 @@ -60,7 +60,7 @@ define void @f5(i8 *%ptr) { ; CHECK-LABEL: f5: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %xor = xor i32 %ext, -2 %trunc = trunc i32 %xor to i8 @@ -73,7 +73,7 @@ define void @f6(i8 *%ptr) { ; CHECK-LABEL: f6: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %xor = xor i64 %ext, -2 %trunc = trunc i64 %xor to i8 @@ -86,7 +86,7 @@ define void @f7(i8 *%ptr) { ; CHECK-LABEL: f7: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i32 %xor = xor i32 %ext, 254 %trunc = trunc i32 %xor to i8 @@ -99,7 +99,7 @@ define void @f8(i8 *%ptr) { ; CHECK-LABEL: f8: ; CHECK: xi 0(%r2), 254 ; CHECK: br %r14 - %val = load i8 *%ptr + %val = load i8 , i8 *%ptr %ext = sext i8 %val to i64 %xor = xor i64 %ext, 254 %trunc = trunc i64 %xor to i8 diff --git a/test/CodeGen/SystemZ/xor-08.ll b/test/CodeGen/SystemZ/xor-08.ll index 8cba41e742ce..9988a4cb45c2 100644 --- a/test/CodeGen/SystemZ/xor-08.ll +++ b/test/CodeGen/SystemZ/xor-08.ll @@ -7,9 +7,9 @@ define void @f1(i8 *%ptr1) { ; CHECK-LABEL: f1: ; CHECK: xc 1(1,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i8 *%ptr1, i64 1 - %val = load i8 *%ptr1 - %old = load i8 *%ptr2 + %ptr2 = getelementptr i8, i8 *%ptr1, i64 1 + %val = load i8 , i8 *%ptr1 + %old = load i8 , i8 *%ptr2 %xor = xor i8 %val, %old store i8 %xor, i8 *%ptr2 ret void @@ -20,9 +20,9 @@ define void @f2(i16 *%ptr1) { ; CHECK-LABEL: f2: ; CHECK: xc 2(2,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i16 *%ptr1, i64 1 - %val = load i16 *%ptr1 - %old = load i16 *%ptr2 + %ptr2 = getelementptr i16, i16 *%ptr1, i64 1 + %val = load i16 , i16 *%ptr1 + %old = load i16 , i16 *%ptr2 %xor = xor i16 %val, %old store i16 %xor, i16 *%ptr2 ret void @@ -33,9 +33,9 @@ define void @f3(i32 *%ptr1) { ; CHECK-LABEL: f3: ; CHECK: xc 4(4,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i32 *%ptr1, i64 1 - %val = load i32 *%ptr1 - %old = load i32 *%ptr2 + %ptr2 = getelementptr i32, i32 *%ptr1, i64 1 + %val = load i32 , i32 *%ptr1 + %old = load i32 , i32 *%ptr2 %xor = xor i32 %old, %val store i32 %xor, i32 *%ptr2 ret void @@ -46,9 +46,9 @@ define void @f4(i64 *%ptr1) { ; CHECK-LABEL: f4: ; CHECK: xc 8(8,%r2), 0(%r2) ; CHECK: br %r14 - %ptr2 = getelementptr i64 *%ptr1, i64 1 - %val = load i64 *%ptr1 - %old = load i64 *%ptr2 + %ptr2 = getelementptr i64, i64 *%ptr1, i64 1 + %val = load i64 , i64 *%ptr1 + %old = load i64 , i64 *%ptr2 %xor = xor i64 %old, %val store i64 %xor, i64 *%ptr2 ret void |