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-rw-r--r--test/CodeGen/X86/GlobalISel/legalize-ext.mir398
1 files changed, 324 insertions, 74 deletions
diff --git a/test/CodeGen/X86/GlobalISel/legalize-ext.mir b/test/CodeGen/X86/GlobalISel/legalize-ext.mir
index c86bfd9ee96d..ac5dcc0e3001 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-ext.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-ext.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
--- |
@@ -64,24 +65,53 @@
ret i32 %r
}
+ define void @test_anyext_i1toi8(i1 %a) {
+ ret void
+ }
+
+ define void @test_anyext_i1toi16(i1 %a) {
+ ret void
+ }
+
+ define void @test_anyext_i1(i8 %a) {
+ ret void
+ }
+
+ define void @test_anyext_i8toi16(i8 %val) {
+ ret void
+ }
+
+ define void @test_anyext_i8(i8 %val) {
+ ret void
+ }
+
+ define void @test_anyext_i16(i16 %val) {
+ ret void
+ }
+
...
---
name: test_zext_i1toi8
-# ALL-LABEL: name: test_zext_i1toi8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0(s1) = COPY %edi
-# ALL-NEXT: %1(s8) = G_ZEXT %0(s1)
-# ALL-NEXT: %al = COPY %1(s8)
-# ALL-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i1toi8
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[COPY]](s1)
+ ; X32: %al = COPY [[ZEXT]](s8)
+ ; X32: RET 0, implicit %al
+ ; X64-LABEL: name: test_zext_i1toi8
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[COPY]](s1)
+ ; X64: %al = COPY [[ZEXT]](s8)
+ ; X64: RET 0, implicit %al
%0(s1) = COPY %edi
%1(s8) = G_ZEXT %0(s1)
%al = COPY %1(s8)
@@ -90,21 +120,26 @@ body: |
...
---
name: test_zext_i1toi16
-# ALL-LABEL: name: test_zext_i1toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0(s1) = COPY %edi
-# ALL-NEXT: %1(s16) = G_ZEXT %0(s1)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i1toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s1)
+ ; X32: %ax = COPY [[ZEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_zext_i1toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s1)
+ ; X64: %ax = COPY [[ZEXT]](s16)
+ ; X64: RET 0, implicit %ax
%0(s1) = COPY %edi
%1(s16) = G_ZEXT %0(s1)
%ax = COPY %1(s16)
@@ -113,7 +148,6 @@ body: |
...
---
name: test_zext_i1
-# ALL-LABEL: name: test_zext_i1
alignment: 4
legalized: false
regBankSelected: false
@@ -121,16 +155,25 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(s8) = COPY %edi
-# ALL-NEXT: %1(s1) = G_TRUNC %0(s8)
-# ALL-NEXT: %2(s32) = G_ZEXT %1(s1)
-# ALL-NEXT: %eax = COPY %2(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s8) = COPY %edi
+ ; X32-LABEL: name: test_zext_i1
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; X32: %eax = COPY [[AND]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_zext_i1
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; X64: %eax = COPY [[AND]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_ZEXT %1(s1)
%eax = COPY %2(s32)
@@ -139,22 +182,27 @@ body: |
...
---
name: test_zext_i8toi16
-# ALL-LABEL: name: test_zext_i8toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0(s8) = COPY %edi
-# ALL-NEXT: %1(s16) = G_ZEXT %0(s8)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s8) = COPY %edi
+ ; X32-LABEL: name: test_zext_i8toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
+ ; X32: %ax = COPY [[ZEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_zext_i8toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
+ ; X64: %ax = COPY [[ZEXT]](s16)
+ ; X64: RET 0, implicit %ax
+ %0(s8) = COPY %dil
%1(s16) = G_ZEXT %0(s8)
%ax = COPY %1(s16)
RET 0, implicit %ax
@@ -162,22 +210,27 @@ body: |
...
---
name: test_zext_i8
-# ALL-LABEL: name: test_zext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0(s8) = COPY %edi
-# ALL-NEXT: %1(s32) = G_ZEXT %0(s8)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s8) = COPY %edi
+ ; X32-LABEL: name: test_zext_i8
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[ZEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_zext_i8
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[ZEXT]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s8) = COPY %dil
%1(s32) = G_ZEXT %0(s8)
%eax = COPY %1(s32)
RET 0, implicit %eax
@@ -185,22 +238,27 @@ body: |
...
---
name: test_zext_i16
-# ALL-LABEL: name: test_zext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0(s16) = COPY %edi
-# ALL-NEXT: %1(s32) = G_ZEXT %0(s16)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s16) = COPY %edi
+ ; X32-LABEL: name: test_zext_i16
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
+ ; X32: %eax = COPY [[ZEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_zext_i16
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
+ ; X64: %eax = COPY [[ZEXT]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s16) = COPY %di
%1(s32) = G_ZEXT %0(s16)
%eax = COPY %1(s32)
RET 0, implicit %eax
@@ -208,22 +266,25 @@ body: |
...
---
name: test_sext_i1toi8
-# ALL-LABEL: name: test_sext_i1toi8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0(s1) = COPY %edi
-# ALL-NEXT: %1(s8) = G_SEXT %0(s1)
-# ALL-NEXT: %al = COPY %1(s8)
-# ALL-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s1) = COPY %edi
+ ; X32-LABEL: name: test_sext_i1toi8
+ ; X32: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X32: %al = COPY [[DEF]](s8)
+ ; X32: RET 0, implicit %al
+ ; X64-LABEL: name: test_sext_i1toi8
+ ; X64: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X64: %al = COPY [[DEF]](s8)
+ ; X64: RET 0, implicit %al
+ %0(s1) = G_IMPLICIT_DEF
%1(s8) = G_SEXT %0(s1)
%al = COPY %1(s8)
RET 0, implicit %al
@@ -231,22 +292,25 @@ body: |
...
---
name: test_sext_i1toi16
-# ALL-LABEL: name: test_sext_i1toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0(s1) = COPY %edi
-# ALL-NEXT: %1(s16) = G_SEXT %0(s1)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s1) = COPY %edi
+ ; X32-LABEL: name: test_sext_i1toi16
+ ; X32: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; X32: %ax = COPY [[DEF]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_sext_i1toi16
+ ; X64: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; X64: %ax = COPY [[DEF]](s16)
+ ; X64: RET 0, implicit %ax
+ %0(s1) = G_IMPLICIT_DEF
%1(s16) = G_SEXT %0(s1)
%ax = COPY %1(s16)
RET 0, implicit %ax
@@ -254,7 +318,6 @@ body: |
...
---
name: test_sext_i1
-# ALL-LABEL: name: test_sext_i1
alignment: 4
legalized: false
regBankSelected: false
@@ -262,40 +325,47 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0(s8) = COPY %edi
-# ALL-NEXT: %1(s1) = G_TRUNC %0(s8)
-# ALL-NEXT: %2(s32) = G_SEXT %1(s1)
-# ALL-NEXT: %eax = COPY %2(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s8) = COPY %edi
- %1(s1) = G_TRUNC %0(s8)
- %2(s32) = G_SEXT %1(s1)
+ ; X32-LABEL: name: test_sext_i1
+ ; X32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X32: %eax = COPY [[DEF]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_sext_i1
+ ; X64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X64: %eax = COPY [[DEF]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s1) = G_IMPLICIT_DEF
+ %2(s32) = G_SEXT %0(s1)
%eax = COPY %2(s32)
RET 0, implicit %eax
...
---
name: test_sext_i8toi16
-# ALL-LABEL: name: test_sext_i8toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0(s8) = COPY %edi
-# ALL-NEXT: %1(s16) = G_SEXT %0(s8)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s8) = COPY %edi
+ ; X32-LABEL: name: test_sext_i8toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
+ ; X32: %ax = COPY [[SEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_sext_i8toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
+ ; X64: %ax = COPY [[SEXT]](s16)
+ ; X64: RET 0, implicit %ax
+ %0(s8) = COPY %dil
%1(s16) = G_SEXT %0(s8)
%ax = COPY %1(s16)
RET 0, implicit %ax
@@ -303,22 +373,27 @@ body: |
...
---
name: test_sext_i8
-# ALL-LABEL: name: test_sext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0(s8) = COPY %edi
-# ALL-NEXT: %1(s32) = G_SEXT %0(s8)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s8) = COPY %edi
+ ; X32-LABEL: name: test_sext_i8
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[SEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_sext_i8
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[SEXT]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s8) = COPY %dil
%1(s32) = G_SEXT %0(s8)
%eax = COPY %1(s32)
RET 0, implicit %eax
@@ -326,24 +401,199 @@ body: |
...
---
name: test_sext_i16
-# ALL-LABEL: name: test_sext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0(s16) = COPY %edi
-# ALL-NEXT: %1(s32) = G_SEXT %0(s16)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s16) = COPY %edi
+ ; X32-LABEL: name: test_sext_i16
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
+ ; X32: %eax = COPY [[SEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_sext_i16
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
+ ; X64: %eax = COPY [[SEXT]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s16) = COPY %di
%1(s32) = G_SEXT %0(s16)
%eax = COPY %1(s32)
RET 0, implicit %eax
...
+---
+name: test_anyext_i1toi8
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %edi
+
+ ; X32-LABEL: name: test_anyext_i1toi8
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY]](s1)
+ ; X32: %al = COPY [[ANYEXT]](s8)
+ ; X32: RET 0, implicit %al
+ ; X64-LABEL: name: test_anyext_i1toi8
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY]](s1)
+ ; X64: %al = COPY [[ANYEXT]](s8)
+ ; X64: RET 0, implicit %al
+ %0(s1) = COPY %edi
+ %1(s8) = G_ANYEXT %0(s1)
+ %al = COPY %1(s8)
+ RET 0, implicit %al
+
+...
+---
+name: test_anyext_i1toi16
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %edi
+
+ ; X32-LABEL: name: test_anyext_i1toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s1)
+ ; X32: %ax = COPY [[ANYEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_anyext_i1toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s1)
+ ; X64: %ax = COPY [[ANYEXT]](s16)
+ ; X64: RET 0, implicit %ax
+ %0(s1) = COPY %edi
+ %1(s16) = G_ANYEXT %0(s1)
+ %ax = COPY %1(s16)
+ RET 0, implicit %ax
+
+...
+---
+name: test_anyext_i1
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %edi
+
+ ; X32-LABEL: name: test_anyext_i1
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_anyext_i1
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s8) = COPY %dil
+ %1(s1) = G_TRUNC %0(s8)
+ %2(s32) = G_ANYEXT %1(s1)
+ %eax = COPY %2(s32)
+ RET 0, implicit %eax
+
+...
+---
+name: test_anyext_i8toi16
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %edi
+
+ ; X32-LABEL: name: test_anyext_i8toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; X32: %ax = COPY [[ANYEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_anyext_i8toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; X64: %ax = COPY [[ANYEXT]](s16)
+ ; X64: RET 0, implicit %ax
+ %0(s8) = COPY %dil
+ %1(s16) = G_ANYEXT %0(s8)
+ %ax = COPY %1(s16)
+ RET 0, implicit %ax
+
+...
+---
+name: test_anyext_i8
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %edi
+
+ ; X32-LABEL: name: test_anyext_i8
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_anyext_i8
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s8) = COPY %dil
+ %1(s32) = G_ANYEXT %0(s8)
+ %eax = COPY %1(s32)
+ RET 0, implicit %eax
+
+...
+---
+name: test_anyext_i16
+alignment: 4
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %edi
+
+ ; X32-LABEL: name: test_anyext_i16
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_anyext_i16
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s16) = COPY %di
+ %1(s32) = G_ANYEXT %0(s16)
+ %eax = COPY %1(s32)
+ RET 0, implicit %eax
+
+...
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 11:20:42 +0000