1 files changed, 0 insertions, 67 deletions
diff --git a/test/CodeGen/X86/combine-srem.ll b/test/CodeGen/X86/combine-srem.ll
deleted file mode 100644
index 6c1956ac77c9..000000000000
--- a/test/CodeGen/X86/combine-srem.ll
+++ /dev/null
@@ -1,67 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
-
-; fold (srem undef, x) -> 0
-define <4 x i32> @combine_vec_srem_undef0(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_srem_undef0:
-; SSE:       # BB#0:
-; SSE-NEXT:    retq
-;
-; AVX-LABEL: combine_vec_srem_undef0:
-; AVX:       # BB#0:
-; AVX-NEXT:    retq
-  %1 = srem <4 x i32> undef, %x
-  ret <4 x i32> %1
-}
-
-; fold (srem x, undef) -> undef
-define <4 x i32> @combine_vec_srem_undef1(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_srem_undef1:
-; SSE:       # BB#0:
-; SSE-NEXT:    retq
-;
-; AVX-LABEL: combine_vec_srem_undef1:
-; AVX:       # BB#0:
-; AVX-NEXT:    retq
-  %1 = srem <4 x i32> %x, undef
-  ret <4 x i32> %1
-}
-
-; fold (srem x, y) -> (urem x, y) iff x and y are positive
-define <4 x i32> @combine_vec_srem_by_pos0(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_srem_by_pos0:
-; SSE:       # BB#0:
-; SSE-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE-NEXT:    retq
-;
-; AVX1-LABEL: combine_vec_srem_by_pos0:
-; AVX1:       # BB#0:
-; AVX1-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX2-LABEL: combine_vec_srem_by_pos0:
-; AVX2:       # BB#0:
-; AVX2-NEXT:    vbroadcastss {{.*}}(%rip), %xmm1
-; AVX2-NEXT:    vandps %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    retq
-  %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
-  %2 = srem <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
-  ret <4 x i32> %2
-}
-
-define <4 x i32> @combine_vec_srem_by_pos1(<4 x i32> %x) {
-; SSE-LABEL: combine_vec_srem_by_pos1:
-; SSE:       # BB#0:
-; SSE-NEXT:    andps {{.*}}(%rip), %xmm0
-; SSE-NEXT:    retq
-;
-; AVX-LABEL: combine_vec_srem_by_pos1:
-; AVX:       # BB#0:
-; AVX-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT:    retq
-  %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
-  %2 = srem <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>
-  ret <4 x i32> %2
-}