diff options
Diffstat (limited to 'test/CodeGen/X86/lea-opt.ll')
| -rw-r--r-- | test/CodeGen/X86/lea-opt.ll | 73 |
1 files changed, 46 insertions, 27 deletions
diff --git a/test/CodeGen/X86/lea-opt.ll b/test/CodeGen/X86/lea-opt.ll index 8096bfabd6cf..9e0e34b1e09a 100644 --- a/test/CodeGen/X86/lea-opt.ll +++ b/test/CodeGen/X86/lea-opt.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-linux -enable-x86-lea-opt | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=ENABLED +; RUN: llc --disable-x86-lea-opt < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=DISABLED %struct.anon1 = type { i32, i32, i32 } %struct.anon2 = type { i32, [32 x i32], i32 } @@ -34,16 +35,18 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void ; CHECK-LABEL: test1: -; CHECK: leaq (%rdi,%rdi,2), [[REG1:%[a-z]+]] -; CHECK: movl arr1(,[[REG1]],4), {{.*}} -; CHECK: leaq arr1+4(,[[REG1]],4), [[REG2:%[a-z]+]] -; CHECK: subl arr1+4(,[[REG1]],4), {{.*}} -; CHECK: leaq arr1+8(,[[REG1]],4), [[REG3:%[a-z]+]] -; CHECK: addl arr1+8(,[[REG1]],4), {{.*}} +; CHECK: shlq $2, [[REG1:%[a-z]+]] +; CHECK: movl arr1([[REG1]],[[REG1]],2), {{.*}} +; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]] +; CHECK: subl arr1+4([[REG1]],[[REG1]],2), {{.*}} +; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]] +; CHECK: addl arr1+8([[REG1]],[[REG1]],2), {{.*}} ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, ([[REG3]]) +; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) +; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, ([[REG3]]) +; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) +; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) } define void @test2(i64 %x) nounwind optsize { @@ -74,16 +77,21 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void ; CHECK-LABEL: test2: -; CHECK: leaq (%rdi,%rdi,2), [[REG1:%[a-z]+]] -; CHECK: leaq arr1+4(,[[REG1]],4), [[REG2:%[a-z]+]] -; CHECK: movl -4([[REG2]]), {{.*}} -; CHECK: subl ([[REG2]]), {{.*}} -; CHECK: leaq arr1+8(,[[REG1]],4), [[REG3:%[a-z]+]] -; CHECK: addl ([[REG3]]), {{.*}} +; CHECK: shlq $2, [[REG1:%[a-z]+]] +; DISABLED: movl arr1([[REG1]],[[REG1]],2), {{.*}} +; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]] +; ENABLED: movl -4([[REG2]]), {{.*}} +; ENABLED: subl ([[REG2]]), {{.*}} +; ENABLED: addl 4([[REG2]]), {{.*}} +; DISABLED: subl arr1+4([[REG1]],[[REG1]],2), {{.*}} +; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]] +; DISABLED: addl arr1+8([[REG1]],[[REG1]],2), {{.*}} ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, ([[REG3]]) +; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) +; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, ([[REG3]]) +; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) +; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) } ; Check that LEA optimization pass takes into account a resultant address @@ -109,7 +117,9 @@ sw.bb.1: ; preds = %entry sw.bb.2: ; preds = %entry store i32 333, i32* %a, align 4 - store i32 444, i32* %b, align 4 + ; Make sure the REG3's definition LEA won't be removed as redundant. + %cvt = ptrtoint i32* %b to i32 + store i32 %cvt, i32* %b, align 4 br label %sw.epilog sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry @@ -122,12 +132,14 @@ sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, ; REG3's definition is closer to movl than REG2's, but the pass still chooses ; REG2 because it provides the resultant address displacement fitting 1 byte. -; CHECK: movl ([[REG2]]), {{.*}} -; CHECK: addl ([[REG3]]), {{.*}} +; ENABLED: movl ([[REG2]]), {{.*}} +; ENABLED: addl ([[REG3]]), {{.*}} +; DISABLED: movl arr2+132([[REG1]]), {{.*}} +; DISABLED: addl arr2([[REG1]]), {{.*}} ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) ; CHECK: movl ${{[1-4]+}}, ([[REG3]]) ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, ([[REG3]]) +; CHECK: movl {{.*}}, ([[REG3]]) } define void @test4(i64 %x) nounwind minsize { @@ -158,12 +170,19 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void ; CHECK-LABEL: test4: -; CHECK: leaq arr1+4({{.*}}), [[REG2:%[a-z]+]] -; CHECK: movl -4([[REG2]]), {{.*}} -; CHECK: subl ([[REG2]]), {{.*}} -; CHECK: addl 4([[REG2]]), {{.*}} +; CHECK: imulq {{.*}}, [[REG1:%[a-z]+]] +; DISABLED: movl arr1([[REG1]]), {{.*}} +; CHECK: leaq arr1+4([[REG1]]), [[REG2:%[a-z]+]] +; ENABLED: movl -4([[REG2]]), {{.*}} +; ENABLED: subl ([[REG2]]), {{.*}} +; ENABLED: addl 4([[REG2]]), {{.*}} +; DISABLED: subl arr1+4([[REG1]]), {{.*}} +; DISABLED: leaq arr1+8([[REG1]]), [[REG3:%[a-z]+]] +; DISABLED: addl arr1+8([[REG1]]), {{.*}} ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, 4([[REG2]]) +; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) +; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) ; CHECK: movl ${{[1-4]+}}, ([[REG2]]) -; CHECK: movl ${{[1-4]+}}, 4([[REG2]]) +; ENABLED: movl ${{[1-4]+}}, 4([[REG2]]) +; DISABLED: movl ${{[1-4]+}}, ([[REG3]]) } |