diff options
Diffstat (limited to 'test/CodeGen')
228 files changed, 11091 insertions, 2208 deletions
diff --git a/test/CodeGen/2004-06-17-UnorderedCompares.c b/test/CodeGen/2004-06-17-UnorderedCompares.c index 7d2ba9614741..2c80180d2c86 100644 --- a/test/CodeGen/2004-06-17-UnorderedCompares.c +++ b/test/CodeGen/2004-06-17-UnorderedCompares.c @@ -1,4 +1,6 @@ -// RUN: %clang_cc1 -std=c99 %s -emit-llvm -o - | grep -v llvm.isunordered | not grep call +// RUN: %clang_cc1 -std=c99 %s -emit-llvm -o - | FileCheck %s +// CHECK: @Test +// CHECK-NOT: call _Bool A, B, C, D, E, F; void TestF(float X, float Y) { diff --git a/test/CodeGen/2005-12-04-DeclarationLineNumbers.c b/test/CodeGen/2005-12-04-DeclarationLineNumbers.c deleted file mode 100644 index 596d3eed24fc..000000000000 --- a/test/CodeGen/2005-12-04-DeclarationLineNumbers.c +++ /dev/null @@ -1,23 +0,0 @@ -// RUN: %clang_cc1 %s -emit-llvm -g -o - | grep DW_TAG_compile_unit | count 1 -// PR664: ensure that line #'s are emitted for declarations - - -short test(short br_data_0, -short br_data_1, -short br_data_2, -short br_data_3, -short br_data_4, -short br_data_5, -short br_data_6, -short br_data_7) { - -short sm07 = br_data_0 + br_data_7; -short sm16 = br_data_1 + br_data_6; -short sm25 = br_data_2 + br_data_5; -short sm34 = br_data_3 + br_data_4; -short s0734 = sm07 + sm34; -short s1625 = sm16 + sm25; - -return s0734 + s1625; -} - diff --git a/test/CodeGen/2007-02-25-C-DotDotDot.c b/test/CodeGen/2007-02-25-C-DotDotDot.c index 1c3a3df57094..ade052ec6b52 100644 --- a/test/CodeGen/2007-02-25-C-DotDotDot.c +++ b/test/CodeGen/2007-02-25-C-DotDotDot.c @@ -3,7 +3,7 @@ // Make sure the call to foo is compiled as: // call float @foo() // not -// call float (...)* bitcast (float ()* @foo to float (...)*)( ) +// call float (...) bitcast (float ()* @foo to float (...)*)( ) static float foo() { return 0.0; } // CHECK: call float @foo diff --git a/test/CodeGen/2007-03-27-VarLengthArray.c b/test/CodeGen/2007-03-27-VarLengthArray.c index ec11f55e6725..db92dab36e33 100644 --- a/test/CodeGen/2007-03-27-VarLengthArray.c +++ b/test/CodeGen/2007-03-27-VarLengthArray.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s -// CHECK: getelementptr inbounds i32* %{{vla|[0-9]}} +// CHECK: getelementptr inbounds i32, i32* %{{vla|[0-9]}} extern void f(int *); int e(int m, int n) { int x[n]; diff --git a/test/CodeGen/2008-07-29-override-alias-decl.c b/test/CodeGen/2008-07-29-override-alias-decl.c index 0c2d0c6ca576..84fac34f3c45 100644 --- a/test/CodeGen/2008-07-29-override-alias-decl.c +++ b/test/CodeGen/2008-07-29-override-alias-decl.c @@ -14,6 +14,6 @@ int h() { return f(); } -// CHECK: [[call:%.*]] = call i32 (...)* @f() +// CHECK: [[call:%.*]] = call i32 (...) @f() // CHECK: ret i32 [[call]] diff --git a/test/CodeGen/2008-08-07-AlignPadding1.c b/test/CodeGen/2008-08-07-AlignPadding1.c index 2bb2e61be0db..74468a8acdae 100644 --- a/test/CodeGen/2008-08-07-AlignPadding1.c +++ b/test/CodeGen/2008-08-07-AlignPadding1.c @@ -22,7 +22,7 @@ struct gc_generation { // The idea is that there are 6 undefs in this structure initializer to cover // the padding between elements. -// CHECK: @generations = global [3 x %struct.gc_generation] [%struct.gc_generation { %union._gc_head { %struct.anon { %union._gc_head* getelementptr inbounds ([3 x %struct.gc_generation]* @generations, i32 0, i32 0, i32 0), %union._gc_head* getelementptr inbounds ([3 x %struct.gc_generation]* @generations, i32 0, i32 0, i32 0), i64 0 }, [8 x i8] undef }, i32 700, i32 0, [8 x i8] undef }, %struct.gc_generation { %union._gc_head { %struct.anon { %union._gc_head* bitcast (i8* getelementptr (i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 48) to %union._gc_head*), %union._gc_head* bitcast (i8* getelementptr (i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 48) to %union._gc_head*), i64 0 }, [8 x i8] undef }, i32 10, i32 0, [8 x i8] undef }, %struct.gc_generation { %union._gc_head { %struct.anon { %union._gc_head* bitcast (i8* getelementptr (i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 96) to %union._gc_head*), %union._gc_head* bitcast (i8* getelementptr (i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 96) to %union._gc_head*), i64 0 }, [8 x i8] undef }, i32 10, i32 0, [8 x i8] undef }] +// CHECK: @generations = global [3 x %struct.gc_generation] [%struct.gc_generation { %union._gc_head { %struct.anon { %union._gc_head* getelementptr inbounds ([3 x %struct.gc_generation], [3 x %struct.gc_generation]* @generations, i32 0, i32 0, i32 0), %union._gc_head* getelementptr inbounds ([3 x %struct.gc_generation], [3 x %struct.gc_generation]* @generations, i32 0, i32 0, i32 0), i64 0 }, [8 x i8] undef }, i32 700, i32 0, [8 x i8] undef }, %struct.gc_generation { %union._gc_head { %struct.anon { %union._gc_head* bitcast (i8* getelementptr (i8, i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 48) to %union._gc_head*), %union._gc_head* bitcast (i8* getelementptr (i8, i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 48) to %union._gc_head*), i64 0 }, [8 x i8] undef }, i32 10, i32 0, [8 x i8] undef }, %struct.gc_generation { %union._gc_head { %struct.anon { %union._gc_head* bitcast (i8* getelementptr (i8, i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 96) to %union._gc_head*), %union._gc_head* bitcast (i8* getelementptr (i8, i8* bitcast ([3 x %struct.gc_generation]* @generations to i8*), i64 96) to %union._gc_head*), i64 0 }, [8 x i8] undef }, i32 10, i32 0, [8 x i8] undef }] /* linked lists of container objects */ struct gc_generation generations[3] = { /* PyGC_Head, threshold, count */ diff --git a/test/CodeGen/2009-01-05-BlockInlining.c b/test/CodeGen/2009-01-05-BlockInlining.c index 2ae9b70bb8fd..300b6ca55ab4 100644 --- a/test/CodeGen/2009-01-05-BlockInlining.c +++ b/test/CodeGen/2009-01-05-BlockInlining.c @@ -1,12 +1,12 @@ -// RUN: %clang_cc1 %s -emit-llvm -fblocks -o - | FileCheck %s +// RUN: %clang_cc1 %s -triple x86_64-linux -emit-llvm -fblocks -o - | FileCheck %s // rdar://5865221 // These will be inlined by the optimizers provided the block descriptors // and block literals are internal constants. // CHECK: @__block_descriptor_tmp = internal constant // CHECK: @__block_literal_global = internal constant -// CHECK: @__block_descriptor_tmp1 = internal constant -// CHECK: @__block_literal_global2 = internal constant +// CHECK: @__block_descriptor_tmp.2 = internal constant +// CHECK: @__block_literal_global.3 = internal constant static int fun(int x) { return x+1; } diff --git a/test/CodeGen/2009-02-13-zerosize-union-field.c b/test/CodeGen/2009-02-13-zerosize-union-field.c index b39a231c65e1..e6f024770855 100644 --- a/test/CodeGen/2009-02-13-zerosize-union-field.c +++ b/test/CodeGen/2009-02-13-zerosize-union-field.c @@ -5,12 +5,12 @@ typedef union{Foo:0;}a; typedef union{int x; Foo:0;}b; extern int printf(const char*, ...); int main() { - // CHECK: getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 0 + // CHECK: getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 0 printf("%ld\n", sizeof(a)); - // CHECK: getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 1 + // CHECK: getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 1 printf("%ld\n", __alignof__(a)); - // CHECK: getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 4 + // CHECK: getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 4 printf("%ld\n", sizeof(b)); - // CHECK: getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 4 + // CHECK: getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), i32 4 printf("%ld\n", __alignof__(b)); } diff --git a/test/CodeGen/2009-10-20-GlobalDebug.c b/test/CodeGen/2009-10-20-GlobalDebug.c index e56f227d2ac6..080f02ea7ed4 100644 --- a/test/CodeGen/2009-10-20-GlobalDebug.c +++ b/test/CodeGen/2009-10-20-GlobalDebug.c @@ -6,5 +6,11 @@ int main() { return 0; } -// CHECK: !"0x34\00localstatic\00localstatic\00\005\001\001", !{{.*}}, !{{.*}}, !{{.*}}, i32* @main.localstatic, null} ; [ DW_TAG_variable ] -// CHECK: !"0x34\00global\00global\00\003\000\001", null, !{{.*}}, !{{.*}}, i32* @global, null} ; [ DW_TAG_variable ] +// CHECK: !DIGlobalVariable(name: "localstatic" +// CHECK-NOT: linkageName: +// CHECK-SAME: line: 5, +// CHECK-SAME: variable: i32* @main.localstatic +// CHECK: !DIGlobalVariable(name: "global" +// CHECK-NOT: linkageName: +// CHECK-SAME: line: 3, +// CHECK-SAME: variable: i32* @global diff --git a/test/CodeGen/2010-02-15-DbgStaticVar.c b/test/CodeGen/2010-02-15-DbgStaticVar.c index 8980b60cf68d..273385a3a942 100644 --- a/test/CodeGen/2010-02-15-DbgStaticVar.c +++ b/test/CodeGen/2010-02-15-DbgStaticVar.c @@ -11,4 +11,6 @@ int main() { int j = foo(1); return 0; } -// CHECK: !"0x34\00b\00b\00\00{{.*}}", +// CHECK: !DIGlobalVariable(name: "b", +// CHECK-NOT: linkageName: +// CHECK-SAME: ){{$}} diff --git a/test/CodeGen/2010-02-16-DbgScopes.c b/test/CodeGen/2010-02-16-DbgScopes.c index 36484a4c6372..3c33bae8b19a 100644 --- a/test/CodeGen/2010-02-16-DbgScopes.c +++ b/test/CodeGen/2010-02-16-DbgScopes.c @@ -1,9 +1,9 @@ // RUN: %clang_cc1 -emit-llvm -g < %s | FileCheck %s // Test to check number of lexical scope identified in debug info. -// CHECK: DW_TAG_lexical_block -// CHECK: DW_TAG_lexical_block -// CHECK: DW_TAG_lexical_block -// CHECK: DW_TAG_lexical_block +// CHECK: !DILexicalBlock( +// CHECK: !DILexicalBlock( +// CHECK: !DILexicalBlock( +// CHECK: !DILexicalBlock( extern int bar(); extern void foobar(); diff --git a/test/CodeGen/2010-03-09-DbgInfo.c b/test/CodeGen/2010-03-09-DbgInfo.c index 3541e5f561fd..a23250e7b70c 100644 --- a/test/CodeGen/2010-03-09-DbgInfo.c +++ b/test/CodeGen/2010-03-09-DbgInfo.c @@ -1,2 +1,3 @@ -// RUN: %clang -emit-llvm -S -O0 -g %s -o - | grep DW_TAG_variable +// RUN: %clang -emit-llvm -S -O0 -g %s -o - | FileCheck %s +// CHECK: !DIGlobalVariable( unsigned char ctable1[1] = { 0001 }; diff --git a/test/CodeGen/2010-03-5-LexicalScope.c b/test/CodeGen/2010-03-5-LexicalScope.c index 8dc68d70557f..007be7684ba3 100644 --- a/test/CodeGen/2010-03-5-LexicalScope.c +++ b/test/CodeGen/2010-03-5-LexicalScope.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -emit-llvm -g %s -o - | FileCheck %s -// CHECK: DW_TAG_lexical_block -// CHECK: DW_TAG_lexical_block +// CHECK: !DILexicalBlock( +// CHECK: !DILexicalBlock( int foo(int i) { if (i) { int j = 2; diff --git a/test/CodeGen/2010-07-08-DeclDebugLineNo.c b/test/CodeGen/2010-07-08-DeclDebugLineNo.c index 44c973acda67..386c2c333acb 100644 --- a/test/CodeGen/2010-07-08-DeclDebugLineNo.c +++ b/test/CodeGen/2010-07-08-DeclDebugLineNo.c @@ -6,5 +6,5 @@ void foo() { int p = 0; // line #5: CHECK: {{call.*llvm.dbg.declare.*%p.*\!dbg }}[[variable_p:![0-9]+]] } // Now match the line number records: -// CHECK: {{^}}[[variable_l]] = !MDLocation(line: 5, -// CHECK: {{^}}[[variable_p]] = !MDLocation(line: 6, +// CHECK: {{^}}[[variable_l]] = !DILocation(line: 5, +// CHECK: {{^}}[[variable_p]] = !DILocation(line: 6, diff --git a/test/CodeGen/2010-07-14-overconservative-align.c b/test/CodeGen/2010-07-14-overconservative-align.c index 5c8c05645178..90e694d47b3b 100644 --- a/test/CodeGen/2010-07-14-overconservative-align.c +++ b/test/CodeGen/2010-07-14-overconservative-align.c @@ -9,6 +9,6 @@ struct s { void func (struct s *s) { - // CHECK: load %struct.s**{{.*}}align 8 + // CHECK: load %struct.s*, %struct.s**{{.*}}align 8 s->word = 0; } diff --git a/test/CodeGen/2010-07-14-ref-off-end.c b/test/CodeGen/2010-07-14-ref-off-end.c index 580ae889d8f2..5ef4076af8fa 100644 --- a/test/CodeGen/2010-07-14-ref-off-end.c +++ b/test/CodeGen/2010-07-14-ref-off-end.c @@ -14,8 +14,8 @@ return(char)s->c; } main() { -// CHECK: getelementptr inbounds [1 x %struct.T]* %s, i32 0, i32 0 -// CHECK: getelementptr inbounds [1 x %struct.T]* %s, i32 0, i32 0 +// CHECK: getelementptr inbounds [1 x %struct.T], [1 x %struct.T]* %s, i32 0, i32 0 +// CHECK: getelementptr inbounds [1 x %struct.T], [1 x %struct.T]* %s, i32 0, i32 0 struct T t; t.i=0xff; t.c=0xffff11; diff --git a/test/CodeGen/2010-08-10-DbgConstant.c b/test/CodeGen/2010-08-10-DbgConstant.c index 5b8f06470c8f..04956ae0f276 100644 --- a/test/CodeGen/2010-08-10-DbgConstant.c +++ b/test/CodeGen/2010-08-10-DbgConstant.c @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -S -emit-llvm -g %s -o - | grep DW_TAG_variable +// RUN: %clang_cc1 -S -emit-llvm -g %s -o - | FileCheck %s +// CHECK: !DIGlobalVariable( static const unsigned int ro = 201; void bar(int); diff --git a/test/CodeGen/24-bit.c b/test/CodeGen/24-bit.c index 9dd0157fd3b4..ad3076a30a79 100644 --- a/test/CodeGen/24-bit.c +++ b/test/CodeGen/24-bit.c @@ -9,6 +9,6 @@ static union ibtt2 void callee_ibt0f(union ibtt2 ibtp5); void test(void) { -// CHECK: = load i32* +// CHECK: = load i32, i32* callee_ibt0f(ibt15); } diff --git a/test/CodeGen/aarch64-inline-asm.c b/test/CodeGen/aarch64-inline-asm.c index c7ce3758fefb..a1078f1bab83 100644 --- a/test/CodeGen/aarch64-inline-asm.c +++ b/test/CodeGen/aarch64-inline-asm.c @@ -8,11 +8,11 @@ long var; void test_generic_constraints(int var32, long var64) { asm("add %0, %1, %1" : "=r"(var32) : "0"(var32)); -// CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32* +// CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32* // CHECK: call i32 asm "add $0, $1, $1", "=r,0"(i32 [[R32_ARG]]) asm("add %0, %1, %1" : "=r"(var64) : "0"(var64)); -// CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i64* +// CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i64, i64* // CHECK: call i64 asm "add $0, $1, $1", "=r,0"(i64 [[R32_ARG]]) asm("ldr %0, %1" : "=r"(var32) : "m"(var)); @@ -25,11 +25,11 @@ float f; double d; void test_constraint_w() { asm("fadd %s0, %s1, %s1" : "=w"(f) : "w"(f)); -// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float* @f +// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f // CHECK: call float asm "fadd ${0:s}, ${1:s}, ${1:s}", "=w,w"(float [[FLT_ARG]]) asm("fadd %d0, %d1, %d1" : "=w"(d) : "w"(d)); -// CHECK: [[DBL_ARG:%[a-zA-Z_0-9]+]] = load double* @d +// CHECK: [[DBL_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d // CHECK: call double asm "fadd ${0:d}, ${1:d}, ${1:d}", "=w,w"(double [[DBL_ARG]]) } diff --git a/test/CodeGen/aarch64-varargs.c b/test/CodeGen/aarch64-varargs.c index 248f1c10cec4..434337173cf8 100644 --- a/test/CodeGen/aarch64-varargs.c +++ b/test/CodeGen/aarch64-varargs.c @@ -11,19 +11,19 @@ va_list the_list; int simple_int(void) { // CHECK-LABEL: define i32 @simple_int return va_arg(the_list, int); -// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32, i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[GR_OFFS]], 0 // CHECK: br i1 [[EARLY_ONSTACK]], label %[[VAARG_ON_STACK:[a-z_.0-9]+]], label %[[VAARG_MAYBE_REG:[a-z_.0-9]+]] // CHECK: [[VAARG_MAYBE_REG]] // CHECK: [[NEW_REG_OFFS:%[a-z_0-9]+]] = add i32 [[GR_OFFS]], 8 -// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[INREG:%[a-z_0-9]+]] = icmp sle i32 [[NEW_REG_OFFS]], 0 // CHECK: br i1 [[INREG]], label %[[VAARG_IN_REG:[a-z_.0-9]+]], label %[[VAARG_ON_STACK]] // CHECK: [[VAARG_IN_REG]] -// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 1) -// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[REG_TOP]], i32 [[GR_OFFS]] +// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 1) +// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[REG_TOP]], i32 [[GR_OFFS]] // CHECK-BE: [[REG_ADDR_VAL:%[0-9]+]] = ptrtoint i8* [[REG_ADDR]] to i64 // CHECK-BE: [[REG_ADDR_VAL_ALIGNED:%[a-z_0-9]*]] = add i64 [[REG_ADDR_VAL]], 4 // CHECK-BE: [[REG_ADDR:%[0-9]+]] = inttoptr i64 [[REG_ADDR_VAL_ALIGNED]] to i8* @@ -31,9 +31,9 @@ int simple_int(void) { // CHECK: br label %[[VAARG_END:[a-z._0-9]+]] // CHECK: [[VAARG_ON_STACK]] -// CHECK: [[STACK:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) -// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8* [[STACK]], i32 8 -// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[STACK:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8, i8* [[STACK]], i32 8 +// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK-BE: [[STACK_VAL:%[0-9]+]] = ptrtoint i8* [[STACK]] to i64 // CHECK-BE: [[STACK_VAL_ALIGNED:%[a-z_0-9]*]] = add i64 [[STACK_VAL]], 4 // CHECK-BE: [[STACK:%[0-9]+]] = inttoptr i64 [[STACK_VAL_ALIGNED]] to i8* @@ -42,14 +42,14 @@ int simple_int(void) { // CHECK: [[VAARG_END]] // CHECK: [[ADDR:%[a-z._0-9]+]] = phi i32* [ [[FROMREG_ADDR]], %[[VAARG_IN_REG]] ], [ [[FROMSTACK_ADDR]], %[[VAARG_ON_STACK]] ] -// CHECK: [[RESULT:%[a-z_0-9]+]] = load i32* [[ADDR]] +// CHECK: [[RESULT:%[a-z_0-9]+]] = load i32, i32* [[ADDR]] // CHECK: ret i32 [[RESULT]] } __int128 aligned_int(void) { // CHECK-LABEL: define i128 @aligned_int return va_arg(the_list, __int128); -// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32, i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[GR_OFFS]], 0 // CHECK: br i1 [[EARLY_ONSTACK]], label %[[VAARG_ON_STACK:[a-z_.0-9]+]], label %[[VAARG_MAYBE_REG:[a-z_.0-9]+]] @@ -57,30 +57,30 @@ __int128 aligned_int(void) { // CHECK: [[ALIGN_REGOFFS:%[a-z_0-9]+]] = add i32 [[GR_OFFS]], 15 // CHECK: [[ALIGNED_REGOFFS:%[a-z_0-9]+]] = and i32 [[ALIGN_REGOFFS]], -16 // CHECK: [[NEW_REG_OFFS:%[a-z_0-9]+]] = add i32 [[ALIGNED_REGOFFS]], 16 -// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[INREG:%[a-z_0-9]+]] = icmp sle i32 [[NEW_REG_OFFS]], 0 // CHECK: br i1 [[INREG]], label %[[VAARG_IN_REG:[a-z_.0-9]+]], label %[[VAARG_ON_STACK]] // CHECK: [[VAARG_IN_REG]] -// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 1) -// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[REG_TOP]], i32 [[ALIGNED_REGOFFS]] +// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 1) +// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[REG_TOP]], i32 [[ALIGNED_REGOFFS]] // CHECK: [[FROMREG_ADDR:%[a-z_0-9]+]] = bitcast i8* [[REG_ADDR]] to i128* // CHECK: br label %[[VAARG_END:[a-z._0-9]+]] // CHECK: [[VAARG_ON_STACK]] -// CHECK: [[STACK:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[STACK:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK: [[STACKINT:%[a-z_0-9]+]] = ptrtoint i8* [[STACK]] to i64 // CHECK: [[ALIGN_STACK:%[a-z_0-9]+]] = add i64 [[STACKINT]], 15 // CHECK: [[ALIGNED_STACK_INT:%[a-z_0-9]+]] = and i64 [[ALIGN_STACK]], -16 // CHECK: [[ALIGNED_STACK_PTR:%[a-z_0-9]+]] = inttoptr i64 [[ALIGNED_STACK_INT]] to i8* -// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8* [[ALIGNED_STACK_PTR]], i32 16 -// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8, i8* [[ALIGNED_STACK_PTR]], i32 16 +// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK: [[FROMSTACK_ADDR:%[a-z_0-9]+]] = bitcast i8* [[ALIGNED_STACK_PTR]] to i128* // CHECK: br label %[[VAARG_END]] // CHECK: [[VAARG_END]] // CHECK: [[ADDR:%[a-z._0-9]+]] = phi i128* [ [[FROMREG_ADDR]], %[[VAARG_IN_REG]] ], [ [[FROMSTACK_ADDR]], %[[VAARG_ON_STACK]] ] -// CHECK: [[RESULT:%[a-z_0-9]+]] = load i128* [[ADDR]] +// CHECK: [[RESULT:%[a-z_0-9]+]] = load i128, i128* [[ADDR]] // CHECK: ret i128 [[RESULT]] } @@ -91,34 +91,34 @@ struct bigstruct { struct bigstruct simple_indirect(void) { // CHECK-LABEL: define void @simple_indirect return va_arg(the_list, struct bigstruct); -// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32, i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[GR_OFFS]], 0 // CHECK: br i1 [[EARLY_ONSTACK]], label %[[VAARG_ON_STACK:[a-z_.0-9]+]], label %[[VAARG_MAYBE_REG:[a-z_.0-9]+]] // CHECK: [[VAARG_MAYBE_REG]] // CHECK-NOT: and i32 // CHECK: [[NEW_REG_OFFS:%[a-z_0-9]+]] = add i32 [[GR_OFFS]], 8 -// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[INREG:%[a-z_0-9]+]] = icmp sle i32 [[NEW_REG_OFFS]], 0 // CHECK: br i1 [[INREG]], label %[[VAARG_IN_REG:[a-z_.0-9]+]], label %[[VAARG_ON_STACK]] // CHECK: [[VAARG_IN_REG]] -// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 1) -// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[REG_TOP]], i32 [[GR_OFFS]] +// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 1) +// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[REG_TOP]], i32 [[GR_OFFS]] // CHECK: [[FROMREG_ADDR:%[a-z_0-9]+]] = bitcast i8* [[REG_ADDR]] to %struct.bigstruct** // CHECK: br label %[[VAARG_END:[a-z._0-9]+]] // CHECK: [[VAARG_ON_STACK]] -// CHECK: [[STACK:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[STACK:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK-NOT: and i64 -// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8* [[STACK]], i32 8 -// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8, i8* [[STACK]], i32 8 +// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK: [[FROMSTACK_ADDR:%[a-z_0-9]+]] = bitcast i8* [[STACK]] to %struct.bigstruct** // CHECK: br label %[[VAARG_END]] // CHECK: [[VAARG_END]] // CHECK: [[ADDR:%[a-z._0-9]+]] = phi %struct.bigstruct** [ [[FROMREG_ADDR]], %[[VAARG_IN_REG]] ], [ [[FROMSTACK_ADDR]], %[[VAARG_ON_STACK]] ] -// CHECK: load %struct.bigstruct** [[ADDR]] +// CHECK: load %struct.bigstruct*, %struct.bigstruct** [[ADDR]] } struct aligned_bigstruct { @@ -129,50 +129,50 @@ struct aligned_bigstruct { struct aligned_bigstruct simple_aligned_indirect(void) { // CHECK-LABEL: define void @simple_aligned_indirect return va_arg(the_list, struct aligned_bigstruct); -// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: [[GR_OFFS:%[a-z_0-9]+]] = load i32, i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[GR_OFFS]], 0 // CHECK: br i1 [[EARLY_ONSTACK]], label %[[VAARG_ON_STACK:[a-z_.0-9]+]], label %[[VAARG_MAYBE_REG:[a-z_.0-9]+]] // CHECK: [[VAARG_MAYBE_REG]] // CHECK: [[NEW_REG_OFFS:%[a-z_0-9]+]] = add i32 [[GR_OFFS]], 8 -// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 3) +// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 3) // CHECK: [[INREG:%[a-z_0-9]+]] = icmp sle i32 [[NEW_REG_OFFS]], 0 // CHECK: br i1 [[INREG]], label %[[VAARG_IN_REG:[a-z_.0-9]+]], label %[[VAARG_ON_STACK]] // CHECK: [[VAARG_IN_REG]] -// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 1) -// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[REG_TOP]], i32 [[GR_OFFS]] +// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 1) +// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[REG_TOP]], i32 [[GR_OFFS]] // CHECK: [[FROMREG_ADDR:%[a-z_0-9]+]] = bitcast i8* [[REG_ADDR]] to %struct.aligned_bigstruct** // CHECK: br label %[[VAARG_END:[a-z._0-9]+]] // CHECK: [[VAARG_ON_STACK]] -// CHECK: [[STACK:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) -// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8* [[STACK]], i32 8 -// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[STACK:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8, i8* [[STACK]], i32 8 +// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK: [[FROMSTACK_ADDR:%[a-z_0-9]+]] = bitcast i8* [[STACK]] to %struct.aligned_bigstruct** // CHECK: br label %[[VAARG_END]] // CHECK: [[VAARG_END]] // CHECK: [[ADDR:%[a-z._0-9]+]] = phi %struct.aligned_bigstruct** [ [[FROMREG_ADDR]], %[[VAARG_IN_REG]] ], [ [[FROMSTACK_ADDR]], %[[VAARG_ON_STACK]] ] -// CHECK: load %struct.aligned_bigstruct** [[ADDR]] +// CHECK: load %struct.aligned_bigstruct*, %struct.aligned_bigstruct** [[ADDR]] } double simple_double(void) { // CHECK-LABEL: define double @simple_double return va_arg(the_list, double); -// CHECK: [[VR_OFFS:%[a-z_0-9]+]] = load i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 4) +// CHECK: [[VR_OFFS:%[a-z_0-9]+]] = load i32, i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 4) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[VR_OFFS]], 0 // CHECK: br i1 [[EARLY_ONSTACK]], label %[[VAARG_ON_STACK:[a-z_.0-9]+]], label %[[VAARG_MAYBE_REG]] // CHECK: [[VAARG_MAYBE_REG]] // CHECK: [[NEW_REG_OFFS:%[a-z_0-9]+]] = add i32 [[VR_OFFS]], 16 -// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 4) +// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 4) // CHECK: [[INREG:%[a-z_0-9]+]] = icmp sle i32 [[NEW_REG_OFFS]], 0 // CHECK: br i1 [[INREG]], label %[[VAARG_IN_REG:[a-z_.0-9]+]], label %[[VAARG_ON_STACK]] // CHECK: [[VAARG_IN_REG]] -// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 2) -// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[REG_TOP]], i32 [[VR_OFFS]] +// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 2) +// CHECK: [[REG_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[REG_TOP]], i32 [[VR_OFFS]] // CHECK-BE: [[REG_ADDR_VAL:%[0-9]+]] = ptrtoint i8* [[REG_ADDR]] to i64 // CHECK-BE: [[REG_ADDR_VAL_ALIGNED:%[a-z_0-9]*]] = add i64 [[REG_ADDR_VAL]], 8 // CHECK-BE: [[REG_ADDR:%[0-9]+]] = inttoptr i64 [[REG_ADDR_VAL_ALIGNED]] to i8* @@ -180,15 +180,15 @@ double simple_double(void) { // CHECK: br label %[[VAARG_END:[a-z._0-9]+]] // CHECK: [[VAARG_ON_STACK]] -// CHECK: [[STACK:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) -// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8* [[STACK]], i32 8 -// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[STACK:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8, i8* [[STACK]], i32 8 +// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK: [[FROMSTACK_ADDR:%[a-z_0-9]+]] = bitcast i8* [[STACK]] to double* // CHECK: br label %[[VAARG_END]] // CHECK: [[VAARG_END]] // CHECK: [[ADDR:%[a-z._0-9]+]] = phi double* [ [[FROMREG_ADDR]], %[[VAARG_IN_REG]] ], [ [[FROMSTACK_ADDR]], %[[VAARG_ON_STACK]] ] -// CHECK: [[RESULT:%[a-z_0-9]+]] = load double* [[ADDR]] +// CHECK: [[RESULT:%[a-z_0-9]+]] = load double, double* [[ADDR]] // CHECK: ret double [[RESULT]] } @@ -199,38 +199,38 @@ struct hfa { struct hfa simple_hfa(void) { // CHECK-LABEL: define %struct.hfa @simple_hfa return va_arg(the_list, struct hfa); -// CHECK: [[VR_OFFS:%[a-z_0-9]+]] = load i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 4) +// CHECK: [[VR_OFFS:%[a-z_0-9]+]] = load i32, i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 4) // CHECK: [[EARLY_ONSTACK:%[a-z_0-9]+]] = icmp sge i32 [[VR_OFFS]], 0 // CHECK: br i1 [[EARLY_ONSTACK]], label %[[VAARG_ON_STACK:[a-z_.0-9]+]], label %[[VAARG_MAYBE_REG:[a-z_.0-9]+]] // CHECK: [[VAARG_MAYBE_REG]] // CHECK: [[NEW_REG_OFFS:%[a-z_0-9]+]] = add i32 [[VR_OFFS]], 32 -// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 4) +// CHECK: store i32 [[NEW_REG_OFFS]], i32* getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 4) // CHECK: [[INREG:%[a-z_0-9]+]] = icmp sle i32 [[NEW_REG_OFFS]], 0 // CHECK: br i1 [[INREG]], label %[[VAARG_IN_REG:[a-z_.0-9]+]], label %[[VAARG_ON_STACK]] // CHECK: [[VAARG_IN_REG]] -// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 2) -// CHECK: [[FIRST_REG:%[a-z_0-9]+]] = getelementptr i8* [[REG_TOP]], i32 [[VR_OFFS]] -// CHECK-LE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[FIRST_REG]], i32 0 -// CHECK-BE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[FIRST_REG]], i32 12 +// CHECK: [[REG_TOP:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 2) +// CHECK: [[FIRST_REG:%[a-z_0-9]+]] = getelementptr i8, i8* [[REG_TOP]], i32 [[VR_OFFS]] +// CHECK-LE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[FIRST_REG]], i32 0 +// CHECK-BE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[FIRST_REG]], i32 12 // CHECK: [[EL_TYPED:%[a-z_0-9]+]] = bitcast i8* [[EL_ADDR]] to float* -// CHECK: [[EL_TMPADDR:%[a-z_0-9]+]] = getelementptr inbounds [2 x float]* %[[TMP_HFA:[a-z_.0-9]+]], i32 0, i32 0 -// CHECK: [[EL:%[a-z_0-9]+]] = load float* [[EL_TYPED]] +// CHECK: [[EL_TMPADDR:%[a-z_0-9]+]] = getelementptr inbounds [2 x float], [2 x float]* %[[TMP_HFA:[a-z_.0-9]+]], i32 0, i32 0 +// CHECK: [[EL:%[a-z_0-9]+]] = load float, float* [[EL_TYPED]] // CHECK: store float [[EL]], float* [[EL_TMPADDR]] -// CHECK-LE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[FIRST_REG]], i32 16 -// CHECK-BE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8* [[FIRST_REG]], i32 28 +// CHECK-LE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[FIRST_REG]], i32 16 +// CHECK-BE: [[EL_ADDR:%[a-z_0-9]+]] = getelementptr i8, i8* [[FIRST_REG]], i32 28 // CHECK: [[EL_TYPED:%[a-z_0-9]+]] = bitcast i8* [[EL_ADDR]] to float* -// CHECK: [[EL_TMPADDR:%[a-z_0-9]+]] = getelementptr inbounds [2 x float]* %[[TMP_HFA]], i32 0, i32 1 -// CHECK: [[EL:%[a-z_0-9]+]] = load float* [[EL_TYPED]] +// CHECK: [[EL_TMPADDR:%[a-z_0-9]+]] = getelementptr inbounds [2 x float], [2 x float]* %[[TMP_HFA]], i32 0, i32 1 +// CHECK: [[EL:%[a-z_0-9]+]] = load float, float* [[EL_TYPED]] // CHECK: store float [[EL]], float* [[EL_TMPADDR]] // CHECK: [[FROMREG_ADDR:%[a-z_0-9]+]] = bitcast [2 x float]* %[[TMP_HFA]] to %struct.hfa* // CHECK: br label %[[VAARG_END:[a-z_.0-9]+]] // CHECK: [[VAARG_ON_STACK]] -// CHECK: [[STACK:%[a-z_0-9]+]] = load i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) -// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8* [[STACK]], i32 8 -// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[STACK:%[a-z_0-9]+]] = load i8*, i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) +// CHECK: [[NEW_STACK:%[a-z_0-9]+]] = getelementptr i8, i8* [[STACK]], i32 8 +// CHECK: store i8* [[NEW_STACK]], i8** getelementptr inbounds (%struct.__va_list, %struct.__va_list* @the_list, i32 0, i32 0) // CHECK: [[FROMSTACK_ADDR:%[a-z_0-9]+]] = bitcast i8* [[STACK]] to %struct.hfa* // CHECK: br label %[[VAARG_END]] diff --git a/test/CodeGen/address-safety-attr.cpp b/test/CodeGen/address-safety-attr.cpp index 031d013a9b50..402d6bad909d 100644 --- a/test/CodeGen/address-safety-attr.cpp +++ b/test/CodeGen/address-safety-attr.cpp @@ -3,14 +3,14 @@ int DefinedInDifferentFile(int *a); // RUN: echo "struct S { S(){} ~S(){} };" >> %t.extra-source.cpp // RUN: echo "S glob_array[5];" >> %t.extra-source.cpp -// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp | FileCheck -check-prefix=WITHOUT %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address | FileCheck -check-prefix=ASAN %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp | FileCheck -check-prefix=WITHOUT %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address | FileCheck -check-prefix=ASAN %s // RUN: echo "fun:*BlacklistedFunction*" > %t.func.blacklist -// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.func.blacklist | FileCheck -check-prefix=BLFUNC %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.func.blacklist | FileCheck -check-prefix=BLFUNC %s // RUN: echo "src:%s" > %t.file.blacklist -// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.file.blacklist | FileCheck -check-prefix=BLFILE %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.file.blacklist | FileCheck -check-prefix=BLFILE %s // FIXME: %t.file.blacklist is like "src:x:\path\to\clang\test\CodeGen\address-safety-attr.cpp" // REQUIRES: shell @@ -27,14 +27,14 @@ int DefinedInDifferentFile(int *a); // Check that functions generated for global in different source file are // not blacklisted. -// WITHOUT: @__cxx_global_var_init{{.*}}[[NOATTR_NO_TF:#[0-9]+]] -// WITHOUT: @__cxx_global_array_dtor{{.*}}[[NOATTR_NO_TF]] -// BLFILE: @__cxx_global_var_init{{.*}}[[WITH_NO_TF:#[0-9]+]] -// BLFILE: @__cxx_global_array_dtor{{.*}}[[WITH_NO_TF]] -// BLFUNC: @__cxx_global_var_init{{.*}}[[WITH_NO_TF:#[0-9]+]] -// BLFUNC: @__cxx_global_array_dtor{{.*}}[[WITH_NO_TF]] -// ASAN: @__cxx_global_var_init{{.*}}[[WITH_NO_TF:#[0-9]+]] -// ASAN: @__cxx_global_array_dtor{{.*}}[[WITH_NO_TF]] +// WITHOUT: @__cxx_global_var_init{{.*}}[[NOATTR:#[0-9]+]] +// WITHOUT: @__cxx_global_array_dtor{{.*}}[[NOATTR]] +// BLFILE: @__cxx_global_var_init{{.*}}[[WITH:#[0-9]+]] +// BLFILE: @__cxx_global_array_dtor{{.*}}[[WITH]] +// BLFUNC: @__cxx_global_var_init{{.*}}[[WITH:#[0-9]+]] +// BLFUNC: @__cxx_global_array_dtor{{.*}}[[WITH]] +// ASAN: @__cxx_global_var_init{{.*}}[[WITH:#[0-9]+]] +// ASAN: @__cxx_global_array_dtor{{.*}}[[WITH]] // WITHOUT: NoAddressSafety1{{.*}}) [[NOATTR]] @@ -52,6 +52,36 @@ __attribute__((no_sanitize_address)) int NoAddressSafety2(int *a); int NoAddressSafety2(int *a) { return *a; } +// WITHOUT: NoAddressSafety3{{.*}}) [[NOATTR]] +// BLFILE: NoAddressSafety3{{.*}}) [[NOATTR]] +// BLFUNC: NoAddressSafety3{{.*}}) [[NOATTR]] +// ASAN: NoAddressSafety3{{.*}}) [[NOATTR]] +[[gnu::no_sanitize_address]] +int NoAddressSafety3(int *a) { return *a; } + +// WITHOUT: NoAddressSafety4{{.*}}) [[NOATTR]] +// BLFILE: NoAddressSafety4{{.*}}) [[NOATTR]] +// BLFUNC: NoAddressSafety4{{.*}}) [[NOATTR]] +// ASAN: NoAddressSafety4{{.*}}) [[NOATTR]] +[[gnu::no_sanitize_address]] +int NoAddressSafety4(int *a); +int NoAddressSafety4(int *a) { return *a; } + +// WITHOUT: NoAddressSafety5{{.*}}) [[NOATTR]] +// BLFILE: NoAddressSafety5{{.*}}) [[NOATTR]] +// BLFUNC: NoAddressSafety5{{.*}}) [[NOATTR]] +// ASAN: NoAddressSafety5{{.*}}) [[NOATTR]] +__attribute__((no_sanitize("address"))) +int NoAddressSafety5(int *a) { return *a; } + +// WITHOUT: NoAddressSafety6{{.*}}) [[NOATTR]] +// BLFILE: NoAddressSafety6{{.*}}) [[NOATTR]] +// BLFUNC: NoAddressSafety6{{.*}}) [[NOATTR]] +// ASAN: NoAddressSafety6{{.*}}) [[NOATTR]] +__attribute__((no_sanitize("address"))) +int NoAddressSafety6(int *a); +int NoAddressSafety6(int *a) { return *a; } + // WITHOUT: AddressSafetyOk{{.*}}) [[NOATTR]] // BLFILE: AddressSafetyOk{{.*}}) [[NOATTR]] // BLFUNC: AddressSafetyOk{{.*}}) [[WITH]] @@ -86,37 +116,41 @@ int GENERATE_NAME(Function)(int *a) { return *a; } template<int i> int TemplateAddressSafetyOk() { return i; } -// WITHOUT: TemplateNoAddressSafety{{.*}}) [[NOATTR]] -// BLFILE: TemplateNoAddressSafety{{.*}}) [[NOATTR]] -// BLFUNC: TemplateNoAddressSafety{{.*}}) [[NOATTR]] -// ASAN: TemplateNoAddressSafety{{.*}}) [[NOATTR]] +// WITHOUT: TemplateNoAddressSafety1{{.*}}) [[NOATTR]] +// BLFILE: TemplateNoAddressSafety1{{.*}}) [[NOATTR]] +// BLFUNC: TemplateNoAddressSafety1{{.*}}) [[NOATTR]] +// ASAN: TemplateNoAddressSafety1{{.*}}) [[NOATTR]] template<int i> __attribute__((no_sanitize_address)) -int TemplateNoAddressSafety() { return i; } +int TemplateNoAddressSafety1() { return i; } + +// WITHOUT: TemplateNoAddressSafety2{{.*}}) [[NOATTR]] +// BLFILE: TemplateNoAddressSafety2{{.*}}) [[NOATTR]] +// BLFUNC: TemplateNoAddressSafety2{{.*}}) [[NOATTR]] +// ASAN: TemplateNoAddressSafety2{{.*}}) [[NOATTR]] +template<int i> +__attribute__((no_sanitize("address"))) +int TemplateNoAddressSafety2() { return i; } int force_instance = TemplateAddressSafetyOk<42>() - + TemplateNoAddressSafety<42>(); + + TemplateNoAddressSafety1<42>() + + TemplateNoAddressSafety2<42>(); // Check that __cxx_global_var_init* get the sanitize_address attribute. int global1 = 0; int global2 = *(int*)((char*)&global1+1); -// WITHOUT: @__cxx_global_var_init{{.*}}[[NOATTR_NO_TF]] -// BLFILE: @__cxx_global_var_init{{.*}}[[NOATTR_NO_TF:#[0-9]+]] -// BLFUNC: @__cxx_global_var_init{{.*}}[[WITH_NO_TF]] -// ASAN: @__cxx_global_var_init{{.*}}[[WITH_NO_TF]] +// WITHOUT: @__cxx_global_var_init{{.*}}[[NOATTR]] +// BLFILE: @__cxx_global_var_init{{.*}}[[NOATTR:#[0-9]+]] +// BLFUNC: @__cxx_global_var_init{{.*}}[[WITH]] +// ASAN: @__cxx_global_var_init{{.*}}[[WITH]] // WITHOUT: attributes [[NOATTR]] = { nounwind{{.*}} } -// WITHOUT: attributes [[NOATTR_NO_TF]] = { nounwind } // BLFILE: attributes [[WITH]] = { nounwind sanitize_address{{.*}} } -// BLFILE: attributes [[WITH_NO_TF]] = { nounwind sanitize_address } -// BLFILE: attributes [[NOATTR_NO_TF]] = { nounwind } // BLFILE: attributes [[NOATTR]] = { nounwind{{.*}} } // BLFUNC: attributes [[WITH]] = { nounwind sanitize_address{{.*}} } -// BLFUNC: attributes [[WITH_NO_TF]] = { nounwind sanitize_address } // BLFUNC: attributes [[NOATTR]] = { nounwind{{.*}} } // ASAN: attributes [[WITH]] = { nounwind sanitize_address{{.*}} } -// ASAN: attributes [[WITH_NO_TF]] = { nounwind sanitize_address } // ASAN: attributes [[NOATTR]] = { nounwind{{.*}} } diff --git a/test/CodeGen/address-space-field1.c b/test/CodeGen/address-space-field1.c index c6b31812a1dd..109c69201cb2 100644 --- a/test/CodeGen/address-space-field1.c +++ b/test/CodeGen/address-space-field1.c @@ -5,17 +5,17 @@ // CHECK: [[p2addr:%.*]] = alloca %struct.S addrspace(2)* // CHECK: store %struct.S addrspace(1)* %p1, %struct.S addrspace(1)** [[p1addr]] // CHECK: store %struct.S addrspace(2)* %p2, %struct.S addrspace(2)** [[p2addr]] -// CHECK: [[t0:%.*]] = load %struct.S addrspace(2)** [[p2addr]], align 8 -// CHECK: [[t1:%.*]] = getelementptr inbounds %struct.S addrspace(2)* [[t0]], i32 0, i32 1 -// CHECK: [[t2:%.*]] = load i32 addrspace(2)* [[t1]], align 4 -// CHECK: [[t3:%.*]] = load %struct.S addrspace(1)** [[p1addr]], align 8 -// CHECK: [[t4:%.*]] = getelementptr inbounds %struct.S addrspace(1)* [[t3]], i32 0, i32 0 +// CHECK: [[t0:%.*]] = load %struct.S addrspace(2)*, %struct.S addrspace(2)** [[p2addr]], align 8 +// CHECK: [[t1:%.*]] = getelementptr inbounds %struct.S, %struct.S addrspace(2)* [[t0]], i32 0, i32 1 +// CHECK: [[t2:%.*]] = load i32, i32 addrspace(2)* [[t1]], align 4 +// CHECK: [[t3:%.*]] = load %struct.S addrspace(1)*, %struct.S addrspace(1)** [[p1addr]], align 8 +// CHECK: [[t4:%.*]] = getelementptr inbounds %struct.S, %struct.S addrspace(1)* [[t3]], i32 0, i32 0 // CHECK: store i32 [[t2]], i32 addrspace(1)* [[t4]], align 4 -// CHECK: [[t5:%.*]] = load %struct.S addrspace(2)** [[p2addr]], align 8 -// CHECK: [[t6:%.*]] = getelementptr inbounds %struct.S addrspace(2)* [[t5]], i32 0, i32 0 -// CHECK: [[t7:%.*]] = load i32 addrspace(2)* [[t6]], align 4 -// CHECK: [[t8:%.*]] = load %struct.S addrspace(1)** [[p1addr]], align 8 -// CHECK: [[t9:%.*]] = getelementptr inbounds %struct.S addrspace(1)* [[t8]], i32 0, i32 1 +// CHECK: [[t5:%.*]] = load %struct.S addrspace(2)*, %struct.S addrspace(2)** [[p2addr]], align 8 +// CHECK: [[t6:%.*]] = getelementptr inbounds %struct.S, %struct.S addrspace(2)* [[t5]], i32 0, i32 0 +// CHECK: [[t7:%.*]] = load i32, i32 addrspace(2)* [[t6]], align 4 +// CHECK: [[t8:%.*]] = load %struct.S addrspace(1)*, %struct.S addrspace(1)** [[p1addr]], align 8 +// CHECK: [[t9:%.*]] = getelementptr inbounds %struct.S, %struct.S addrspace(1)* [[t8]], i32 0, i32 1 // CHECK: store i32 [[t7]], i32 addrspace(1)* [[t9]], align 4 // CHECK: ret void // CHECK:} diff --git a/test/CodeGen/address-space.c b/test/CodeGen/address-space.c index 3e865fd3b775..61deb2625336 100644 --- a/test/CodeGen/address-space.c +++ b/test/CodeGen/address-space.c @@ -1,7 +1,4 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm < %s | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm < %s | grep 'load.*addrspace(2).. @A' -// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm < %s | grep 'load.*addrspace(2).. @B' - // CHECK: @foo = common addrspace(1) global int foo __attribute__((address_space(1))); @@ -10,11 +7,11 @@ int foo __attribute__((address_space(1))); int ban[10] __attribute__((address_space(1))); // CHECK-LABEL: define i32 @test1() -// CHECK: load i32 addrspace(1)* @foo +// CHECK: load i32, i32 addrspace(1)* @foo int test1() { return foo; } // CHECK-LABEL: define i32 @test2(i32 %i) -// CHECK: load i32 addrspace(1)* +// CHECK: load i32, i32 addrspace(1)* // CHECK-NEXT: ret i32 int test2(int i) { return ban[i]; } @@ -22,9 +19,9 @@ int test2(int i) { return ban[i]; } __attribute__((address_space(2))) int *A, *B; // CHECK-LABEL: define void @test3() -// CHECK: load i32 addrspace(2)** @B -// CHECK: load i32 addrspace(2)* -// CHECK: load i32 addrspace(2)** @A +// CHECK: load i32 addrspace(2)*, i32 addrspace(2)** @B +// CHECK: load i32, i32 addrspace(2)* +// CHECK: load i32 addrspace(2)*, i32 addrspace(2)** @A // CHECK: store i32 {{.*}}, i32 addrspace(2)* void test3() { *A = *B; diff --git a/test/CodeGen/align-local.c b/test/CodeGen/align-local.c index b839ee14a10b..c8b27a83c3ff 100644 --- a/test/CodeGen/align-local.c +++ b/test/CodeGen/align-local.c @@ -1,7 +1,9 @@ -// RUN: %clang_cc1 -emit-llvm < %s | grep "align 16" | count 2 +// RUN: %clang_cc1 -emit-llvm < %s | FileCheck %s typedef struct __attribute((aligned(16))) {int x[4];} ff; +// CHECK: alloca %struct.ff, align 16 +// CHECK: alloca %struct.anon, align 16 int a() { ff a; struct {int x[4];} b __attribute((aligned(16))); diff --git a/test/CodeGen/align-systemz.c b/test/CodeGen/align-systemz.c new file mode 100644 index 000000000000..68a21e39ab36 --- /dev/null +++ b/test/CodeGen/align-systemz.c @@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -triple s390x-linux-gnu -emit-llvm %s -o - | FileCheck %s + +// SystemZ prefers to align all global variables to two bytes. + +struct test { + signed char a; +}; + +char c; +// CHECK-DAG: @c = common global i8 0, align 2 + +struct test s; +// CHECK-DAG: @s = common global %struct.test zeroinitializer, align 2 + +extern char ec; +// CHECK-DAG: @ec = external global i8, align 2 + +extern struct test es; +// CHECK-DAG: @es = external global %struct.test, align 2 + +// Dummy function to make sure external symbols are used. +void func (void) +{ + c = ec; + s = es; +} + diff --git a/test/CodeGen/alignment.c b/test/CodeGen/alignment.c index 04d6aaccc219..0a598010c853 100644 --- a/test/CodeGen/alignment.c +++ b/test/CodeGen/alignment.c @@ -23,7 +23,7 @@ int test1a(myint *p) { return *p; } // CHECK: @test1a( -// CHECK: load i32* {{.*}}, align 1 +// CHECK: load i32, i32* {{.*}}, align 1 // CHECK: ret i32 diff --git a/test/CodeGen/annotations-builtin.c b/test/CodeGen/annotations-builtin.c index 7938e49aa646..8a3b3ffcec28 100644 --- a/test/CodeGen/annotations-builtin.c +++ b/test/CodeGen/annotations-builtin.c @@ -28,7 +28,7 @@ int main(int argc, char **argv) { // CHECK: call i64 @llvm.annotation.i64 int inta = __builtin_annotation(intfoo, "annotation_a"); -// CHECK: load i32* @intfoo +// CHECK: load i32, i32* @intfoo // CHECK-NEXT: call i32 @llvm.annotation.i32 // CHECK-NEXT: store diff --git a/test/CodeGen/annotations-field.c b/test/CodeGen/annotations-field.c index 6b443675850c..02bae15a2bc1 100644 --- a/test/CodeGen/annotations-field.c +++ b/test/CodeGen/annotations-field.c @@ -13,7 +13,7 @@ static struct foo gf; int main(int argc, char **argv) { struct foo f; f.v = argc; -// CHECK: getelementptr inbounds %struct.foo* %f, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.foo, %struct.foo* %f, i32 0, i32 0 // CHECK-NEXT: bitcast i32* {{.*}} to i8* // CHECK-NEXT: call i8* @llvm.ptr.annotation.p0i8({{.*}}str{{.*}}str{{.*}}i32 8) // CHECK-NEXT: bitcast i8* {{.*}} to i32* @@ -21,7 +21,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: call i8* @llvm.ptr.annotation.p0i8({{.*}}str{{.*}}str{{.*}}i32 8) // CHECK-NEXT: bitcast i8* {{.*}} to i32* gf.v = argc; -// CHECK: bitcast i32* getelementptr inbounds (%struct.foo* @gf, i32 0, i32 0) to i8* +// CHECK: bitcast i32* getelementptr inbounds (%struct.foo, %struct.foo* @gf, i32 0, i32 0) to i8* // CHECK-NEXT: call i8* @llvm.ptr.annotation.p0i8({{.*}}str{{.*}}str{{.*}}i32 8) return 0; } diff --git a/test/CodeGen/annotations-var.c b/test/CodeGen/annotations-var.c index da9e0b63eca3..6e8ad34c6515 100644 --- a/test/CodeGen/annotations-var.c +++ b/test/CodeGen/annotations-var.c @@ -34,9 +34,9 @@ void local(void) { // LOCAL-LABEL: define void @local() // LOCAL: [[LOCALVAR:%.*]] = alloca i32, // LOCAL-NEXT: [[T0:%.*]] = bitcast i32* [[LOCALVAR]] to i8* -// LOCAL-NEXT: call void @llvm.var.annotation(i8* [[T0]], i8* getelementptr inbounds ([15 x i8]* @{{.*}}), i8* getelementptr inbounds ({{.*}}), i32 33) +// LOCAL-NEXT: call void @llvm.var.annotation(i8* [[T0]], i8* getelementptr inbounds ([15 x i8], [15 x i8]* @{{.*}}), i8* getelementptr inbounds ({{.*}}), i32 33) // LOCAL-NEXT: [[T0:%.*]] = bitcast i32* [[LOCALVAR]] to i8* -// LOCAL-NEXT: call void @llvm.var.annotation(i8* [[T0]], i8* getelementptr inbounds ([15 x i8]* @{{.*}}), i8* getelementptr inbounds ({{.*}}), i32 33) +// LOCAL-NEXT: call void @llvm.var.annotation(i8* [[T0]], i8* getelementptr inbounds ([15 x i8], [15 x i8]* @{{.*}}), i8* getelementptr inbounds ({{.*}}), i32 33) } void undef(void) { @@ -44,5 +44,5 @@ void undef(void) { // UNDEF-LABEL: define void @undef() // UNDEF: [[UNDEFVAR:%.*]] = alloca i32, // UNDEF-NEXT: [[T0:%.*]] = bitcast i32* [[UNDEFVAR]] to i8* -// UNDEF-NEXT: call void @llvm.var.annotation(i8* [[T0]], i8* getelementptr inbounds ([15 x i8]* @{{.*}}), i8* getelementptr inbounds ({{.*}}), i32 43) +// UNDEF-NEXT: call void @llvm.var.annotation(i8* [[T0]], i8* getelementptr inbounds ([15 x i8], [15 x i8]* @{{.*}}), i8* getelementptr inbounds ({{.*}}), i32 43) } diff --git a/test/CodeGen/arm-aapcs-vfp.c b/test/CodeGen/arm-aapcs-vfp.c index 7ef7c4e52edb..38044cbb1e23 100644 --- a/test/CodeGen/arm-aapcs-vfp.c +++ b/test/CodeGen/arm-aapcs-vfp.c @@ -118,7 +118,7 @@ void test_neon(struct neon_struct arg) { neon_callee(arg); } -// CHECK-LABEL: define arm_aapcs_vfpcc void @f33(%struct.s33* byval align 1 %s) +// CHECK-LABEL: define arm_aapcs_vfpcc void @f33(%struct.s33* byval align 4 %s) struct s33 { char buf[32*32]; }; void f33(struct s33 s) { } @@ -126,19 +126,19 @@ typedef struct { long long x; int y; } struct_long_long_int; // CHECK: define arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_1(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, i64 %k, i32 %l) void test_vfp_stack_gpr_split_1(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, long long k, int l) {} -// CHECK: define arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_2(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [3 x i32], [2 x i64] %k.coerce) +// CHECK: define arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_2(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [2 x i64] %k.coerce) void test_vfp_stack_gpr_split_2(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_long_long_int k) {} -// CHECK: define arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(%struct.struct_long_long_int* noalias sret %agg.result, double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, [3 x i32], [2 x i64] %k.coerce) +// CHECK: define arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(%struct.struct_long_long_int* noalias sret %agg.result, double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, [2 x i64] %k.coerce) struct_long_long_int test_vfp_stack_gpr_split_3(double a, double b, double c, double d, double e, double f, double g, double h, double i, struct_long_long_int k) {} typedef struct { int a; int b:4; int c; } struct_int_bitfield_int; -// CHECK: define arm_aapcs_vfpcc void @test_test_vfp_stack_gpr_split_bitfield(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, i32 %k, [2 x i32], [3 x i32] %l.coerce) +// CHECK: define arm_aapcs_vfpcc void @test_test_vfp_stack_gpr_split_bitfield(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, i32 %k, [3 x i32] %l.coerce) void test_test_vfp_stack_gpr_split_bitfield(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, int k, struct_int_bitfield_int l) {} // Note: this struct requires internal padding typedef struct { int x; long long y; } struct_int_long_long; -// CHECK: define arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_4(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [3 x i32], [2 x i64] %k.coerce) +// CHECK: define arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_4(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [2 x i64] %k.coerce) void test_vfp_stack_gpr_split_4(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_int_long_long k) {} // This very large struct (passed byval) uses up the GPRs, so no padding is needed diff --git a/test/CodeGen/arm-abi-vector.c b/test/CodeGen/arm-abi-vector.c index 12e38ba43419..88bf593ed296 100644 --- a/test/CodeGen/arm-abi-vector.c +++ b/test/CodeGen/arm-abi-vector.c @@ -17,15 +17,15 @@ double varargs_vec_2i(int fixed, ...) { // CHECK: alloca <2 x i32>, align 8 // CHECK: [[ALIGN:%.*]] = and i32 [[VAR:%.*]], -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 8 // CHECK: bitcast i8* [[AP_ALIGN]] to <2 x i32>* // APCS-GNU: varargs_vec_2i // APCS-GNU: alloca <2 x i32>, align 8 // APCS-GNU: [[VAR_ALIGN:%.*]] = alloca <2 x i32> -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* {{%.*}}, i32 8 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* {{%.*}}, i32 8 // APCS-GNU: bitcast <2 x i32>* [[VAR_ALIGN]] to i8* // APCS-GNU: call void @llvm.memcpy -// APCS-GNU: load <2 x i32>* [[VAR_ALIGN]] +// APCS-GNU: load <2 x i32>, <2 x i32>* [[VAR_ALIGN]] va_list ap; double sum = fixed; va_start(ap, fixed); @@ -37,20 +37,20 @@ double varargs_vec_2i(int fixed, ...) { double test_2i(__int2 *in) { // CHECK: test_2i -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_vec_2i(i32 3, <2 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}}) // APCS-GNU: test_2i -// APCS-GNU: call double (i32, ...)* @varargs_vec_2i(i32 3, <2 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}}) return varargs_vec_2i(3, *in); } double varargs_vec_3c(int fixed, ...) { // CHECK: varargs_vec_3c // CHECK: alloca <3 x i8>, align 4 -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP:%.*]], i32 4 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP:%.*]], i32 4 // CHECK: bitcast i8* [[AP]] to <3 x i8>* // APCS-GNU: varargs_vec_3c // APCS-GNU: alloca <3 x i8>, align 4 -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* [[AP:%.*]], i32 4 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP:%.*]], i32 4 // APCS-GNU: bitcast i8* [[AP]] to <3 x i8>* va_list ap; double sum = fixed; @@ -63,9 +63,9 @@ double varargs_vec_3c(int fixed, ...) { double test_3c(__char3 *in) { // CHECK: test_3c -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_vec_3c(i32 3, i32 {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}}) // APCS-GNU: test_3c -// APCS-GNU: call double (i32, ...)* @varargs_vec_3c(i32 3, i32 {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}}) return varargs_vec_3c(3, *in); } @@ -74,15 +74,15 @@ double varargs_vec_5c(int fixed, ...) { // CHECK: alloca <5 x i8>, align 8 // CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 8 // CHECK: bitcast i8* [[AP_ALIGN]] to <5 x i8>* // APCS-GNU: varargs_vec_5c // APCS-GNU: alloca <5 x i8>, align 8 // APCS-GNU: [[VAR_ALIGN:%.*]] = alloca <5 x i8> -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* {{%.*}}, i32 8 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* {{%.*}}, i32 8 // APCS-GNU: bitcast <5 x i8>* [[VAR_ALIGN]] to i8* // APCS-GNU: call void @llvm.memcpy -// APCS-GNU: load <5 x i8>* [[VAR_ALIGN]] +// APCS-GNU: load <5 x i8>, <5 x i8>* [[VAR_ALIGN]] va_list ap; double sum = fixed; va_start(ap, fixed); @@ -94,9 +94,9 @@ double varargs_vec_5c(int fixed, ...) { double test_5c(__char5 *in) { // CHECK: test_5c -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) // APCS-GNU: test_5c -// APCS-GNU: call double (i32, ...)* @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) return varargs_vec_5c(5, *in); } @@ -106,17 +106,17 @@ double varargs_vec_9c(int fixed, ...) { // CHECK: [[VAR_ALIGN:%.*]] = alloca <9 x i8> // CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast <9 x i8>* [[VAR_ALIGN]] to i8* // CHECK: call void @llvm.memcpy -// CHECK: load <9 x i8>* [[VAR_ALIGN]] +// CHECK: load <9 x i8>, <9 x i8>* [[VAR_ALIGN]] // APCS-GNU: varargs_vec_9c // APCS-GNU: alloca <9 x i8>, align 16 // APCS-GNU: [[VAR_ALIGN:%.*]] = alloca <9 x i8> -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* {{%.*}}, i32 16 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* {{%.*}}, i32 16 // APCS-GNU: bitcast <9 x i8>* [[VAR_ALIGN]] to i8* // APCS-GNU: call void @llvm.memcpy -// APCS-GNU: load <9 x i8>* [[VAR_ALIGN]] +// APCS-GNU: load <9 x i8>, <9 x i8>* [[VAR_ALIGN]] va_list ap; double sum = fixed; va_start(ap, fixed); @@ -128,22 +128,22 @@ double varargs_vec_9c(int fixed, ...) { double test_9c(__char9 *in) { // CHECK: test_9c -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) // APCS-GNU: test_9c -// APCS-GNU: call double (i32, ...)* @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) return varargs_vec_9c(9, *in); } double varargs_vec_19c(int fixed, ...) { // CHECK: varargs_vec_19c -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP:%.*]], i32 4 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP:%.*]], i32 4 // CHECK: [[VAR:%.*]] = bitcast i8* [[AP]] to i8** -// CHECK: [[VAR2:%.*]] = load i8** [[VAR]] +// CHECK: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // CHECK: bitcast i8* [[VAR2]] to <19 x i8>* // APCS-GNU: varargs_vec_19c -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* [[AP:%.*]], i32 4 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP:%.*]], i32 4 // APCS-GNU: [[VAR:%.*]] = bitcast i8* [[AP]] to i8** -// APCS-GNU: [[VAR2:%.*]] = load i8** [[VAR]] +// APCS-GNU: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // APCS-GNU: bitcast i8* [[VAR2]] to <19 x i8>* va_list ap; double sum = fixed; @@ -156,9 +156,9 @@ double varargs_vec_19c(int fixed, ...) { double test_19c(__char19 *in) { // CHECK: test_19c -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) // APCS-GNU: test_19c -// APCS-GNU: call double (i32, ...)* @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) return varargs_vec_19c(19, *in); } @@ -167,15 +167,15 @@ double varargs_vec_3s(int fixed, ...) { // CHECK: alloca <3 x i16>, align 8 // CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 8 // CHECK: bitcast i8* [[AP_ALIGN]] to <3 x i16>* // APCS-GNU: varargs_vec_3s // APCS-GNU: alloca <3 x i16>, align 8 // APCS-GNU: [[VAR_ALIGN:%.*]] = alloca <3 x i16> -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* {{%.*}}, i32 8 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* {{%.*}}, i32 8 // APCS-GNU: bitcast <3 x i16>* [[VAR_ALIGN]] to i8* // APCS-GNU: call void @llvm.memcpy -// APCS-GNU: load <3 x i16>* [[VAR_ALIGN]] +// APCS-GNU: load <3 x i16>, <3 x i16>* [[VAR_ALIGN]] va_list ap; double sum = fixed; va_start(ap, fixed); @@ -187,9 +187,9 @@ double varargs_vec_3s(int fixed, ...) { double test_3s(__short3 *in) { // CHECK: test_3s -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) // APCS-GNU: test_3s -// APCS-GNU: call double (i32, ...)* @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) return varargs_vec_3s(3, *in); } @@ -199,17 +199,17 @@ double varargs_vec_5s(int fixed, ...) { // CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16> // CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast <5 x i16>* [[VAR_ALIGN]] to i8* // CHECK: call void @llvm.memcpy -// CHECK: load <5 x i16>* [[VAR_ALIGN]] +// CHECK: load <5 x i16>, <5 x i16>* [[VAR_ALIGN]] // APCS-GNU: varargs_vec_5s // APCS-GNU: alloca <5 x i16>, align 16 // APCS-GNU: [[VAR_ALIGN:%.*]] = alloca <5 x i16> -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* {{%.*}}, i32 16 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* {{%.*}}, i32 16 // APCS-GNU: bitcast <5 x i16>* [[VAR_ALIGN]] to i8* // APCS-GNU: call void @llvm.memcpy -// APCS-GNU: load <5 x i16>* [[VAR_ALIGN]] +// APCS-GNU: load <5 x i16>, <5 x i16>* [[VAR_ALIGN]] va_list ap; double sum = fixed; va_start(ap, fixed); @@ -221,9 +221,9 @@ double varargs_vec_5s(int fixed, ...) { double test_5s(__short5 *in) { // CHECK: test_5s -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) // APCS-GNU: test_5s -// APCS-GNU: call double (i32, ...)* @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) return varargs_vec_5s(5, *in); } @@ -238,11 +238,11 @@ double varargs_struct(int fixed, ...) { // CHECK: varargs_struct // CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast i8* [[AP_ALIGN]] to %struct.StructWithVec* // APCS-GNU: varargs_struct // APCS-GNU: [[VAR_ALIGN:%.*]] = alloca %struct.StructWithVec -// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8* {{%.*}}, i32 16 +// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr i8, i8* {{%.*}}, i32 16 // APCS-GNU: bitcast %struct.StructWithVec* [[VAR_ALIGN]] to i8* // APCS-GNU: call void @llvm.memcpy va_list ap; @@ -256,8 +256,8 @@ double varargs_struct(int fixed, ...) { double test_struct(StructWithVec* d) { // CHECK: test_struct -// CHECK: call arm_aapcscc double (i32, ...)* @varargs_struct(i32 3, [2 x i64] {{%.*}}) +// CHECK: call arm_aapcscc double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}}) // APCS-GNU: test_struct -// APCS-GNU: call double (i32, ...)* @varargs_struct(i32 3, [2 x i64] {{%.*}}) +// APCS-GNU: call double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}}) return varargs_struct(3, *d); } diff --git a/test/CodeGen/arm-arguments.c b/test/CodeGen/arm-arguments.c index e4a10fd9e27b..b671626939c9 100644 --- a/test/CodeGen/arm-arguments.c +++ b/test/CodeGen/arm-arguments.c @@ -176,8 +176,8 @@ void f32(struct s32 s) { } // PR13350 struct s33 { char buf[32*32]; }; void f33(struct s33 s) { } -// APCS-GNU-LABEL: define void @f33(%struct.s33* byval align 1 %s) -// AAPCS-LABEL: define arm_aapcscc void @f33(%struct.s33* byval align 1 %s) +// APCS-GNU-LABEL: define void @f33(%struct.s33* byval align 4 %s) +// AAPCS-LABEL: define arm_aapcscc void @f33(%struct.s33* byval align 4 %s) // PR14048 struct s34 { char c; }; @@ -185,7 +185,7 @@ void f34(struct s34 s); void g34(struct s34 *s) { f34(*s); } // AAPCS: @g34(%struct.s34* %s) // AAPCS: %[[a:.*]] = alloca [1 x i32] -// AAPCS: load [1 x i32]* %[[a]] +// AAPCS: load [1 x i32], [1 x i32]* %[[a]] // rdar://12596507 struct s35 @@ -204,17 +204,17 @@ float32x4_t f35(int i, s35_with_align s1, s35_with_align s2) { *(float32x4_t *)&s2); return v; } -// APCS-GNU-LABEL: define <4 x float> @f35(i32 %i, %struct.s35* byval align 16, %struct.s35* byval align 16) +// APCS-GNU-LABEL: define <4 x float> @f35(i32 %i, %struct.s35* byval align 4, %struct.s35* byval align 4) // APCS-GNU: %[[a:.*]] = alloca %struct.s35, align 16 // APCS-GNU: %[[b:.*]] = bitcast %struct.s35* %[[a]] to i8* // APCS-GNU: %[[c:.*]] = bitcast %struct.s35* %0 to i8* // APCS-GNU: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[b]], i8* %[[c]] // APCS-GNU: %[[d:.*]] = bitcast %struct.s35* %[[a]] to <4 x float>* -// APCS-GNU: load <4 x float>* %[[d]], align 16 -// AAPCS-LABEL: define arm_aapcscc <4 x float> @f35(i32 %i, %struct.s35* byval align 16, %struct.s35* byval align 16) +// APCS-GNU: load <4 x float>, <4 x float>* %[[d]], align 16 +// AAPCS-LABEL: define arm_aapcscc <4 x float> @f35(i32 %i, %struct.s35* byval align 8, %struct.s35* byval align 8) // AAPCS: %[[a:.*]] = alloca %struct.s35, align 16 // AAPCS: %[[b:.*]] = bitcast %struct.s35* %[[a]] to i8* // AAPCS: %[[c:.*]] = bitcast %struct.s35* %0 to i8* // AAPCS: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[b]], i8* %[[c]] // AAPCS: %[[d:.*]] = bitcast %struct.s35* %[[a]] to <4 x float>* -// AAPCS: load <4 x float>* %[[d]], align 16 +// AAPCS: load <4 x float>, <4 x float>* %[[d]], align 16 diff --git a/test/CodeGen/arm-asm-variable.c b/test/CodeGen/arm-asm-variable.c index f874269b0a01..6868cb7996ab 100644 --- a/test/CodeGen/arm-asm-variable.c +++ b/test/CodeGen/arm-asm-variable.c @@ -17,7 +17,7 @@ int64_t foo(int64_t v, volatile int64_t *p) : [_rl] "=&r" (rl), [_rh] "=&r" (rh) \ : [_p] "p" (p) : "memory"); - // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "={r1},={r2},r,~{memory}"(i64* + // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "=&{r1},=&{r2},r,~{memory}"(i64* return r; } diff --git a/test/CodeGen/arm-atomics-m.c b/test/CodeGen/arm-atomics-m.c index 51e2d1d9ebf2..cd9e71e5d944 100644 --- a/test/CodeGen/arm-atomics-m.c +++ b/test/CodeGen/arm-atomics-m.c @@ -15,7 +15,7 @@ void test_presence(void) __atomic_fetch_add(&i, 1, memory_order_seq_cst); // CHECK: atomicrmw sub i32* {{.*}} seq_cst __atomic_fetch_sub(&i, 1, memory_order_seq_cst); - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst int r; __atomic_load(&i, &r, memory_order_seq_cst); // CHECK: store atomic i32 {{.*}} seq_cst diff --git a/test/CodeGen/arm-atomics.c b/test/CodeGen/arm-atomics.c index b54e277120db..aa5a6ecd0caa 100644 --- a/test/CodeGen/arm-atomics.c +++ b/test/CodeGen/arm-atomics.c @@ -17,7 +17,7 @@ void test_presence(void) __atomic_fetch_add(&i, 1, memory_order_seq_cst); // CHECK: atomicrmw sub i32* {{.*}} seq_cst __atomic_fetch_sub(&i, 1, memory_order_seq_cst); - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst int r; __atomic_load(&i, &r, memory_order_seq_cst); // CHECK: store atomic i32 {{.*}} seq_cst @@ -28,7 +28,7 @@ void test_presence(void) __atomic_fetch_add(&l, 1, memory_order_seq_cst); // CHECK: atomicrmw sub i64* {{.*}} seq_cst __atomic_fetch_sub(&l, 1, memory_order_seq_cst); - // CHECK: load atomic i64* {{.*}} seq_cst + // CHECK: load atomic i64, i64* {{.*}} seq_cst long long rl; __atomic_load(&l, &rl, memory_order_seq_cst); // CHECK: store atomic i64 {{.*}} seq_cst diff --git a/test/CodeGen/arm-bitfield-alignment.c b/test/CodeGen/arm-bitfield-alignment.c new file mode 100644 index 000000000000..66bbdae57bbc --- /dev/null +++ b/test/CodeGen/arm-bitfield-alignment.c @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -triple arm-none-eabi -ffreestanding -emit-llvm -o - -O3 %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64 -ffreestanding -emit-llvm -o - -O3 %s | FileCheck %s + +extern struct T { + int b0 : 8; + int b1 : 24; + int b2 : 1; +} g; + +int func() { + return g.b1; +} + +// CHECK: @g = external global %struct.T, align 4 +// CHECK: %{{.*}} = load i64, i64* bitcast (%struct.T* @g to i64*), align 4 diff --git a/test/CodeGen/arm-clear.c b/test/CodeGen/arm-clear.c index 8ef3675641f8..566d5daf4d13 100644 --- a/test/CodeGen/arm-clear.c +++ b/test/CodeGen/arm-clear.c @@ -3,7 +3,7 @@ void clear(void *ptr, void *ptr2) { // CHECK: clear - // CHECK: load i8** - // CHECK: load i8** + // CHECK: load i8*, i8** + // CHECK: load i8*, i8** __clear_cache(ptr, ptr2); } diff --git a/test/CodeGen/arm-homogenous.c b/test/CodeGen/arm-homogenous.c index 3426d995caef..42a9bc1c1643 100644 --- a/test/CodeGen/arm-homogenous.c +++ b/test/CodeGen/arm-homogenous.c @@ -184,7 +184,7 @@ extern void takes_struct_of_four_doubles_variadic(double a, struct_of_four_doubl void test_struct_of_four_doubles_variadic(void) { // CHECK: test_struct_of_four_doubles_variadic -// CHECK: call arm_aapcs_vfpcc void (double, [4 x i64], [4 x i64], double, ...)* @takes_struct_of_four_doubles_variadic(double {{.*}}, [4 x i64] {{.*}}, [4 x i64] {{.*}}, double {{.*}}) +// CHECK: call arm_aapcs_vfpcc void (double, [4 x i64], [4 x i64], double, ...) @takes_struct_of_four_doubles_variadic(double {{.*}}, [4 x i64] {{.*}}, [4 x i64] {{.*}}, double {{.*}}) takes_struct_of_four_doubles_variadic(3.0, g_s4d, g_s4d, 4.0); } diff --git a/test/CodeGen/arm-pnaclcall.c b/test/CodeGen/arm-pnaclcall.c deleted file mode 100644 index 2faac1c676b9..000000000000 --- a/test/CodeGen/arm-pnaclcall.c +++ /dev/null @@ -1,33 +0,0 @@ -// RUN: %clang_cc1 -triple armv7-unknown-nacl-gnueabi \ -// RUN: -ffreestanding -mfloat-abi hard -target-cpu cortex-a8 \ -// RUN: -emit-llvm -w -o - %s | FileCheck %s - -// Test that functions with pnaclcall attribute generate portable bitcode -// like the le32 arch target - -typedef struct { - int a; - int b; -} s1; -// CHECK-LABEL: define i32 @f48(%struct.s1* byval %s) -int __attribute__((pnaclcall)) f48(s1 s) { return s.a; } - -// CHECK-LABEL: define void @f49(%struct.s1* noalias sret %agg.result) -s1 __attribute__((pnaclcall)) f49() { s1 s; s.a = s.b = 1; return s; } - -union simple_union { - int a; - char b; -}; -// Unions should be passed as byval structs -// CHECK-LABEL: define void @f50(%union.simple_union* byval %s) -void __attribute__((pnaclcall)) f50(union simple_union s) {} - -typedef struct { - int b4 : 4; - int b3 : 3; - int b8 : 8; -} bitfield1; -// Bitfields should be passed as byval structs -// CHECK-LABEL: define void @f51(%struct.bitfield1* byval %bf1) -void __attribute__((pnaclcall)) f51(bitfield1 bf1) {} diff --git a/test/CodeGen/arm-target-features.c b/test/CodeGen/arm-target-features.c new file mode 100644 index 000000000000..ece8bdfc5e2d --- /dev/null +++ b/test/CodeGen/arm-target-features.c @@ -0,0 +1,38 @@ +// REQUIRES: arm-registered-target + +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabihf -target-cpu cortex-a8 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP3 +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-a9 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP3 +// CHECK-VFP3: "target-features"="+neon,+vfp3" + + +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabihf -target-cpu cortex-a5 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4 +// CHECK-VFP4: "target-features"="+vfp4,+neon" + + +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabihf -target-cpu cortex-a7 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4-DIV +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-a12 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4-DIV +// RUN: %clang_cc1 -triple armv7-linux-gnueabihf -target-cpu cortex-a15 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4-DIV +// RUN: %clang_cc1 -triple armv7-linux-gnueabihf -target-cpu cortex-a17 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4-DIV +// RUN: %clang_cc1 -triple thumbv7s-linux-gnueabi -target-cpu swift -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4-DIV +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabihf -target-cpu krait -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-VFP4-DIV +// CHECK-VFP4-DIV: "target-features"="+vfp4,+neon,+hwdiv,+hwdiv-arm" + + +// RUN: %clang_cc1 -triple thumbv7s-apple-ios7.0 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8 +// RUN: %clang_cc1 -triple armv8-linux-gnueabi -target-cpu cortex-a53 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8 +// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8 +// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a72 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8 +// CHECK-BASIC-V8: "target-features"="+neon,+fp-armv8,+hwdiv,+crypto,+crc,+hwdiv-arm" + + +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-r5 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-DIV +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-r7 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-DIV +// CHECK-DIV: "target-features"="+hwdiv,+hwdiv-arm" + +// RUN: %clang_cc1 -triple armv7-linux-gnueabi -target-cpu cortex-r4 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-THUMB-DIV +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-m3 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-THUMB-DIV +// RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-m4 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-THUMB-DIV +// CHECK-THUMB-DIV: "target-features"="+hwdiv" + + +void foo() {} diff --git a/test/CodeGen/arm-vector-align.c b/test/CodeGen/arm-vector-align.c index 9e1ae5da11e2..15dd13e7c113 100644 --- a/test/CodeGen/arm-vector-align.c +++ b/test/CodeGen/arm-vector-align.c @@ -23,7 +23,7 @@ void t1(AlignedAddr *addr1, AlignedAddr *addr2) { // Radar 10538555: Make sure unaligned load/stores do not gain alignment. void t2(char *addr) { // CHECK: @t2 -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 int32x2_t vec = vld1_dup_s32(addr); // CHECK: store i32 %{{.*}}, i32* {{.*}}, align 1 vst1_lane_s32(addr, vec, 1); diff --git a/test/CodeGen/arm64-abi-vector.c b/test/CodeGen/arm64-abi-vector.c index 502fb080d701..4566c417909b 100644 --- a/test/CodeGen/arm64-abi-vector.c +++ b/test/CodeGen/arm64-abi-vector.c @@ -16,7 +16,7 @@ typedef __attribute__(( ext_vector_type(3) )) double __double3; double varargs_vec_3c(int fixed, ...) { // CHECK: varargs_vec_3c // CHECK: alloca <3 x i8>, align 4 -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: bitcast i8* [[AP_CUR]] to <3 x i8>* va_list ap; double sum = fixed; @@ -29,14 +29,14 @@ double varargs_vec_3c(int fixed, ...) { double test_3c(__char3 *in) { // CHECK: test_3c -// CHECK: call double (i32, ...)* @varargs_vec_3c(i32 3, i32 {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}}) return varargs_vec_3c(3, *in); } double varargs_vec_4c(int fixed, ...) { // CHECK: varargs_vec_4c // CHECK: alloca <4 x i8>, align 4 -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: bitcast i8* [[AP_CUR]] to <4 x i8>* va_list ap; double sum = fixed; @@ -49,14 +49,14 @@ double varargs_vec_4c(int fixed, ...) { double test_4c(__char4 *in) { // CHECK: test_4c -// CHECK: call double (i32, ...)* @varargs_vec_4c(i32 4, i32 {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_4c(i32 4, i32 {{%.*}}) return varargs_vec_4c(4, *in); } double varargs_vec_5c(int fixed, ...) { // CHECK: varargs_vec_5c // CHECK: alloca <5 x i8>, align 8 -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: bitcast i8* [[AP_CUR]] to <5 x i8>* va_list ap; double sum = fixed; @@ -69,7 +69,7 @@ double varargs_vec_5c(int fixed, ...) { double test_5c(__char5 *in) { // CHECK: test_5c -// CHECK: call double (i32, ...)* @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}}) return varargs_vec_5c(5, *in); } @@ -78,7 +78,7 @@ double varargs_vec_9c(int fixed, ...) { // CHECK: alloca <9 x i8>, align 16 // CHECK: [[ALIGN:%.*]] = and i64 {{%.*}}, -16 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i64 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast i8* [[AP_ALIGN]] to <9 x i8>* va_list ap; double sum = fixed; @@ -91,15 +91,15 @@ double varargs_vec_9c(int fixed, ...) { double test_9c(__char9 *in) { // CHECK: test_9c -// CHECK: call double (i32, ...)* @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}}) return varargs_vec_9c(9, *in); } double varargs_vec_19c(int fixed, ...) { // CHECK: varargs_vec_19c -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: [[VAR:%.*]] = bitcast i8* [[AP_CUR]] to i8** -// CHECK: [[VAR2:%.*]] = load i8** [[VAR]] +// CHECK: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // CHECK: bitcast i8* [[VAR2]] to <19 x i8>* va_list ap; double sum = fixed; @@ -112,14 +112,14 @@ double varargs_vec_19c(int fixed, ...) { double test_19c(__char19 *in) { // CHECK: test_19c -// CHECK: call double (i32, ...)* @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}}) return varargs_vec_19c(19, *in); } double varargs_vec_3s(int fixed, ...) { // CHECK: varargs_vec_3s // CHECK: alloca <3 x i16>, align 8 -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: bitcast i8* [[AP_CUR]] to <3 x i16>* va_list ap; double sum = fixed; @@ -132,7 +132,7 @@ double varargs_vec_3s(int fixed, ...) { double test_3s(__short3 *in) { // CHECK: test_3s -// CHECK: call double (i32, ...)* @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}}) return varargs_vec_3s(3, *in); } @@ -141,7 +141,7 @@ double varargs_vec_5s(int fixed, ...) { // CHECK: alloca <5 x i16>, align 16 // CHECK: [[ALIGN:%.*]] = and i64 {{%.*}}, -16 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i64 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast i8* [[AP_ALIGN]] to <5 x i16>* va_list ap; double sum = fixed; @@ -154,7 +154,7 @@ double varargs_vec_5s(int fixed, ...) { double test_5s(__short5 *in) { // CHECK: test_5s -// CHECK: call double (i32, ...)* @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}}) return varargs_vec_5s(5, *in); } @@ -163,7 +163,7 @@ double varargs_vec_3i(int fixed, ...) { // CHECK: alloca <3 x i32>, align 16 // CHECK: [[ALIGN:%.*]] = and i64 {{%.*}}, -16 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i64 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast i8* [[AP_ALIGN]] to <3 x i32>* va_list ap; double sum = fixed; @@ -176,16 +176,16 @@ double varargs_vec_3i(int fixed, ...) { double test_3i(__int3 *in) { // CHECK: test_3i -// CHECK: call double (i32, ...)* @varargs_vec_3i(i32 3, <4 x i32> {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3i(i32 3, <4 x i32> {{%.*}}) return varargs_vec_3i(3, *in); } double varargs_vec_5i(int fixed, ...) { // CHECK: varargs_vec_5i // CHECK: alloca <5 x i32>, align 16 -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: [[VAR:%.*]] = bitcast i8* [[AP_CUR]] to i8** -// CHECK: [[VAR2:%.*]] = load i8** [[VAR]] +// CHECK: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // CHECK: bitcast i8* [[VAR2]] to <5 x i32>* va_list ap; double sum = fixed; @@ -198,16 +198,16 @@ double varargs_vec_5i(int fixed, ...) { double test_5i(__int5 *in) { // CHECK: test_5i -// CHECK: call double (i32, ...)* @varargs_vec_5i(i32 5, <5 x i32>* {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_5i(i32 5, <5 x i32>* {{%.*}}) return varargs_vec_5i(5, *in); } double varargs_vec_3d(int fixed, ...) { // CHECK: varargs_vec_3d // CHECK: alloca <3 x double>, align 16 -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: [[VAR:%.*]] = bitcast i8* [[AP_CUR]] to i8** -// CHECK: [[VAR2:%.*]] = load i8** [[VAR]] +// CHECK: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // CHECK: bitcast i8* [[VAR2]] to <3 x double>* va_list ap; double sum = fixed; @@ -220,7 +220,7 @@ double varargs_vec_3d(int fixed, ...) { double test_3d(__double3 *in) { // CHECK: test_3d -// CHECK: call double (i32, ...)* @varargs_vec_3d(i32 3, <3 x double>* {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec_3d(i32 3, <3 x double>* {{%.*}}) return varargs_vec_3d(3, *in); } @@ -230,51 +230,51 @@ double varargs_vec(int fixed, ...) { double sum = fixed; va_start(ap, fixed); __char3 c3 = va_arg(ap, __char3); -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: bitcast i8* [[AP_CUR]] to <3 x i8>* sum = sum + c3.x + c3.y; __char5 c5 = va_arg(ap, __char5); -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: bitcast i8* [[AP_CUR]] to <5 x i8>* sum = sum + c5.x + c5.y; __char9 c9 = va_arg(ap, __char9); // CHECK: [[ALIGN:%.*]] = and i64 {{%.*}}, -16 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i64 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast i8* [[AP_ALIGN]] to <9 x i8>* sum = sum + c9.x + c9.y; __char19 c19 = va_arg(ap, __char19); -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: [[VAR:%.*]] = bitcast i8* [[AP_CUR]] to i8** -// CHECK: [[VAR2:%.*]] = load i8** [[VAR]] +// CHECK: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // CHECK: bitcast i8* [[VAR2]] to <19 x i8>* sum = sum + c19.x + c19.y; __short3 s3 = va_arg(ap, __short3); -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: bitcast i8* [[AP_CUR]] to <3 x i16>* sum = sum + s3.x + s3.y; __short5 s5 = va_arg(ap, __short5); // CHECK: [[ALIGN:%.*]] = and i64 {{%.*}}, -16 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i64 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast i8* [[AP_ALIGN]] to <5 x i16>* sum = sum + s5.x + s5.y; __int3 i3 = va_arg(ap, __int3); // CHECK: [[ALIGN:%.*]] = and i64 {{%.*}}, -16 // CHECK: [[AP_ALIGN:%.*]] = inttoptr i64 [[ALIGN]] to i8* -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_ALIGN]], i32 16 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_ALIGN]], i32 16 // CHECK: bitcast i8* [[AP_ALIGN]] to <3 x i32>* sum = sum + i3.x + i3.y; __int5 i5 = va_arg(ap, __int5); -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: [[VAR:%.*]] = bitcast i8* [[AP_CUR]] to i8** -// CHECK: [[VAR2:%.*]] = load i8** [[VAR]] +// CHECK: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // CHECK: bitcast i8* [[VAR2]] to <5 x i32>* sum = sum + i5.x + i5.y; __double3 d3 = va_arg(ap, __double3); -// CHECK: [[AP_NEXT:%.*]] = getelementptr i8* [[AP_CUR:%.*]], i32 8 +// CHECK: [[AP_NEXT:%.*]] = getelementptr i8, i8* [[AP_CUR:%.*]], i32 8 // CHECK: [[VAR:%.*]] = bitcast i8* [[AP_CUR]] to i8** -// CHECK: [[VAR2:%.*]] = load i8** [[VAR]] +// CHECK: [[VAR2:%.*]] = load i8*, i8** [[VAR]] // CHECK: bitcast i8* [[VAR2]] to <3 x double>* sum = sum + d3.x + d3.y; va_end(ap); @@ -285,7 +285,7 @@ double test(__char3 *c3, __char5 *c5, __char9 *c9, __char19 *c19, __short3 *s3, __short5 *s5, __int3 *i3, __int5 *i5, __double3 *d3) { double ret = varargs_vec(3, *c3, *c5, *c9, *c19, *s3, *s5, *i3, *i5, *d3); -// CHECK: call double (i32, ...)* @varargs_vec(i32 3, i32 {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <19 x i8>* {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <5 x i32>* {{%.*}}, <3 x double>* {{%.*}}) +// CHECK: call double (i32, ...) @varargs_vec(i32 3, i32 {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <19 x i8>* {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <5 x i32>* {{%.*}}, <3 x double>* {{%.*}}) return ret; } @@ -339,7 +339,7 @@ double fixed_9c(__char9 *in) { __attribute__((noinline)) double args_vec_19c(int fixed, __char19 c19) { // CHECK: args_vec_19c -// CHECK: [[C19:%.*]] = load <19 x i8>* {{.*}}, align 16 +// CHECK: [[C19:%.*]] = load <19 x i8>, <19 x i8>* {{.*}}, align 16 double sum = fixed; sum = sum + c19.x + c19.y; return sum; @@ -401,7 +401,7 @@ double fixed_3i(__int3 *in) { __attribute__((noinline)) double args_vec_5i(int fixed, __int5 c5) { // CHECK: args_vec_5i -// CHECK: [[C5:%.*]] = load <5 x i32>* {{%.*}}, align 16 +// CHECK: [[C5:%.*]] = load <5 x i32>, <5 x i32>* {{%.*}}, align 16 double sum = fixed; sum = sum + c5.x + c5.y; return sum; @@ -416,7 +416,7 @@ double fixed_5i(__int5 *in) { __attribute__((noinline)) double args_vec_3d(int fixed, __double3 c3) { // CHECK: args_vec_3d // CHECK: [[CAST:%.*]] = bitcast <3 x double>* {{%.*}} to <4 x double>* -// CHECK: [[LOAD:%.*]] = load <4 x double>* [[CAST]] +// CHECK: [[LOAD:%.*]] = load <4 x double>, <4 x double>* [[CAST]] // CHECK: shufflevector <4 x double> [[LOAD]], <4 x double> undef, <3 x i32> <i32 0, i32 1, i32 2> double sum = fixed; sum = sum + c3.x + c3.y; diff --git a/test/CodeGen/arm64-arguments.c b/test/CodeGen/arm64-arguments.c index ae1ff98800ac..4486bb4b18e2 100644 --- a/test/CodeGen/arm64-arguments.c +++ b/test/CodeGen/arm64-arguments.c @@ -92,7 +92,7 @@ struct s21 f21(void) {} // CHECK: define i64 @f22() // CHECK: define i64 @f23() // CHECK: define i64 @f24() -// CHECK: define i128 @f25() +// CHECK: define [2 x i64] @f25() // CHECK: define { float, float } @f26() // CHECK: define { double, double } @f27() _Complex char f22(void) {} @@ -134,7 +134,7 @@ struct s34 { char c; }; void f34(struct s34 s); void g34(struct s34 *s) { f34(*s); } // CHECK: @g34(%struct.s34* %s) -// CHECK: %[[a:.*]] = load i8* %{{.*}} +// CHECK: %[[a:.*]] = load i8, i8* %{{.*}} // CHECK: zext i8 %[[a]] to i64 // CHECK: call void @f34(i64 %{{.*}}) @@ -200,9 +200,9 @@ float32x4_t f35(int i, s35_with_align s1, s35_with_align s2) { // CHECK: %s1 = alloca %struct.s35, align 16 // CHECK: %s2 = alloca %struct.s35, align 16 // CHECK: %[[a:.*]] = bitcast %struct.s35* %s1 to <4 x float>* -// CHECK: load <4 x float>* %[[a]], align 16 +// CHECK: load <4 x float>, <4 x float>* %[[a]], align 16 // CHECK: %[[b:.*]] = bitcast %struct.s35* %s2 to <4 x float>* -// CHECK: load <4 x float>* %[[b]], align 16 +// CHECK: load <4 x float>, <4 x float>* %[[b]], align 16 float32x4_t v = vaddq_f32(*(float32x4_t *)&s1, *(float32x4_t *)&s2); return v; @@ -222,9 +222,9 @@ int32x4_t f36(int i, s36_with_align s1, s36_with_align s2) { // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 1 // CHECK: store i128 %s2.coerce, i128* %{{.*}}, align 1 // CHECK: %[[a:.*]] = bitcast %struct.s36* %s1 to <4 x i32>* -// CHECK: load <4 x i32>* %[[a]], align 16 +// CHECK: load <4 x i32>, <4 x i32>* %[[a]], align 16 // CHECK: %[[b:.*]] = bitcast %struct.s36* %s2 to <4 x i32>* -// CHECK: load <4 x i32>* %[[b]], align 16 +// CHECK: load <4 x i32>, <4 x i32>* %[[b]], align 16 int32x4_t v = vaddq_s32(*(int32x4_t *)&s1, *(int32x4_t *)&s2); return v; @@ -239,9 +239,9 @@ typedef struct s37 s37_with_align; int32x4_t f37(int i, s37_with_align s1, s37_with_align s2) { // CHECK: define <4 x i32> @f37(i32 %i, %struct.s37* %s1, %struct.s37* %s2) // CHECK: %[[a:.*]] = bitcast %struct.s37* %s1 to <4 x i32>* -// CHECK: load <4 x i32>* %[[a]], align 16 +// CHECK: load <4 x i32>, <4 x i32>* %[[a]], align 16 // CHECK: %[[b:.*]] = bitcast %struct.s37* %s2 to <4 x i32>* -// CHECK: load <4 x i32>* %[[b]], align 16 +// CHECK: load <4 x i32>, <4 x i32>* %[[b]], align 16 int32x4_t v = vaddq_s32(*(int32x4_t *)&s1, *(int32x4_t *)&s2); return v; @@ -277,18 +277,18 @@ int f38(int i, s38_no_align s1, s38_no_align s2) { // CHECK: %s2 = alloca %struct.s38, align 8 // CHECK: store i64 %s1.coerce, i64* %{{.*}}, align 1 // CHECK: store i64 %s2.coerce, i64* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s38* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s38* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s38* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s38* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s2, i32 0, i32 1 return s1.i + s2.i + i + s1.s + s2.s; } s38_no_align g38; s38_no_align g38_2; int caller38() { // CHECK: define i32 @caller38() -// CHECK: %[[a:.*]] = load i64* bitcast (%struct.s38* @g38 to i64*), align 1 -// CHECK: %[[b:.*]] = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 1 +// CHECK: %[[a:.*]] = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 1 +// CHECK: %[[b:.*]] = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 1 // CHECK: call i32 @f38(i32 3, i64 %[[a]], i64 %[[b]]) return f38(3, g38, g38_2); } @@ -301,16 +301,16 @@ int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, // CHECK: %s2 = alloca %struct.s38, align 8 // CHECK: store i64 %s1.coerce, i64* %{{.*}}, align 1 // CHECK: store i64 %s2.coerce, i64* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s38* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s38* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s38* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s38* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s38, %struct.s38* %s2, i32 0, i32 1 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; } int caller38_stack() { // CHECK: define i32 @caller38_stack() -// CHECK: %[[a:.*]] = load i64* bitcast (%struct.s38* @g38 to i64*), align 1 -// CHECK: %[[b:.*]] = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 1 +// CHECK: %[[a:.*]] = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 1 +// CHECK: %[[b:.*]] = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 1 // CHECK: call i32 @f38_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i64 %[[a]], i64 %[[b]]) return f38_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g38, g38_2); } @@ -330,18 +330,18 @@ int f39(int i, s39_with_align s1, s39_with_align s2) { // CHECK: %s2 = alloca %struct.s39, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 1 // CHECK: store i128 %s2.coerce, i128* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s39* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s39* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s39* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s39* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s2, i32 0, i32 1 return s1.i + s2.i + i + s1.s + s2.s; } s39_with_align g39; s39_with_align g39_2; int caller39() { // CHECK: define i32 @caller39() -// CHECK: %[[a:.*]] = load i128* bitcast (%struct.s39* @g39 to i128*), align 1 -// CHECK: %[[b:.*]] = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 1 +// CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 1 +// CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 1 // CHECK: call i32 @f39(i32 3, i128 %[[a]], i128 %[[b]]) return f39(3, g39, g39_2); } @@ -354,16 +354,16 @@ int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, // CHECK: %s2 = alloca %struct.s39, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 1 // CHECK: store i128 %s2.coerce, i128* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s39* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s39* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s39* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s39* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s39, %struct.s39* %s2, i32 0, i32 1 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; } int caller39_stack() { // CHECK: define i32 @caller39_stack() -// CHECK: %[[a:.*]] = load i128* bitcast (%struct.s39* @g39 to i128*), align 1 -// CHECK: %[[b:.*]] = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 1 +// CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 1 +// CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 1 // CHECK: call i32 @f39_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i128 %[[a]], i128 %[[b]]) return f39_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g39, g39_2); } @@ -385,18 +385,18 @@ int f40(int i, s40_no_align s1, s40_no_align s2) { // CHECK: %s2 = alloca %struct.s40, align 8 // CHECK: store [2 x i64] %s1.coerce, [2 x i64]* %{{.*}}, align 1 // CHECK: store [2 x i64] %s2.coerce, [2 x i64]* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s40* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s40* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s40* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s40* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s2, i32 0, i32 1 return s1.i + s2.i + i + s1.s + s2.s; } s40_no_align g40; s40_no_align g40_2; int caller40() { // CHECK: define i32 @caller40() -// CHECK: %[[a:.*]] = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 1 -// CHECK: %[[b:.*]] = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 1 +// CHECK: %[[a:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 1 +// CHECK: %[[b:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 1 // CHECK: call i32 @f40(i32 3, [2 x i64] %[[a]], [2 x i64] %[[b]]) return f40(3, g40, g40_2); } @@ -409,16 +409,16 @@ int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, // CHECK: %s2 = alloca %struct.s40, align 8 // CHECK: store [2 x i64] %s1.coerce, [2 x i64]* %{{.*}}, align 1 // CHECK: store [2 x i64] %s2.coerce, [2 x i64]* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s40* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s40* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s40* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s40* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s40, %struct.s40* %s2, i32 0, i32 1 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; } int caller40_stack() { // CHECK: define i32 @caller40_stack() -// CHECK: %[[a:.*]] = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 1 -// CHECK: %[[b:.*]] = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 1 +// CHECK: %[[a:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 1 +// CHECK: %[[b:.*]] = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 1 // CHECK: call i32 @f40_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, [2 x i64] %[[a]], [2 x i64] %[[b]]) return f40_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g40, g40_2); } @@ -440,18 +440,18 @@ int f41(int i, s41_with_align s1, s41_with_align s2) { // CHECK: %s2 = alloca %struct.s41, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 1 // CHECK: store i128 %s2.coerce, i128* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s41* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s41* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s41* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s41* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s2, i32 0, i32 1 return s1.i + s2.i + i + s1.s + s2.s; } s41_with_align g41; s41_with_align g41_2; int caller41() { // CHECK: define i32 @caller41() -// CHECK: %[[a:.*]] = load i128* bitcast (%struct.s41* @g41 to i128*), align 1 -// CHECK: %[[b:.*]] = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 1 +// CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 1 +// CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 1 // CHECK: call i32 @f41(i32 3, i128 %[[a]], i128 %[[b]]) return f41(3, g41, g41_2); } @@ -464,16 +464,16 @@ int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, // CHECK: %s2 = alloca %struct.s41, align 16 // CHECK: store i128 %s1.coerce, i128* %{{.*}}, align 1 // CHECK: store i128 %s2.coerce, i128* %{{.*}}, align 1 -// CHECK: getelementptr inbounds %struct.s41* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s41* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s41* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s41* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s41, %struct.s41* %s2, i32 0, i32 1 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; } int caller41_stack() { // CHECK: define i32 @caller41_stack() -// CHECK: %[[a:.*]] = load i128* bitcast (%struct.s41* @g41 to i128*), align 1 -// CHECK: %[[b:.*]] = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 1 +// CHECK: %[[a:.*]] = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 1 +// CHECK: %[[b:.*]] = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 1 // CHECK: call i32 @f41_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i128 %[[a]], i128 %[[b]]) return f41_stack(1, 2, 3, 4, 5, 6, 7, 8, 9, g41, g41_2); } @@ -493,10 +493,10 @@ typedef struct s42 s42_no_align; __attribute__ ((noinline)) int f42(int i, s42_no_align s1, s42_no_align s2) { // CHECK: define i32 @f42(i32 %i, %struct.s42* %s1, %struct.s42* %s2) -// CHECK: getelementptr inbounds %struct.s42* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s42* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s42* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s42* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s2, i32 0, i32 1 return s1.i + s2.i + i + s1.s + s2.s; } s42_no_align g42; @@ -517,10 +517,10 @@ __attribute__ ((noinline)) int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s42_no_align s1, s42_no_align s2) { // CHECK: define i32 @f42_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, %struct.s42* %s1, %struct.s42* %s2) -// CHECK: getelementptr inbounds %struct.s42* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s42* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s42* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s42* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s42, %struct.s42* %s2, i32 0, i32 1 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; } int caller42_stack() { @@ -550,10 +550,10 @@ typedef struct s43 s43_with_align; __attribute__ ((noinline)) int f43(int i, s43_with_align s1, s43_with_align s2) { // CHECK: define i32 @f43(i32 %i, %struct.s43* %s1, %struct.s43* %s2) -// CHECK: getelementptr inbounds %struct.s43* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s43* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s43* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s43* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s2, i32 0, i32 1 return s1.i + s2.i + i + s1.s + s2.s; } s43_with_align g43; @@ -574,10 +574,10 @@ __attribute__ ((noinline)) int f43_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, s43_with_align s1, s43_with_align s2) { // CHECK: define i32 @f43_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, %struct.s43* %s1, %struct.s43* %s2) -// CHECK: getelementptr inbounds %struct.s43* %s1, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s43* %s2, i32 0, i32 0 -// CHECK: getelementptr inbounds %struct.s43* %s1, i32 0, i32 1 -// CHECK: getelementptr inbounds %struct.s43* %s2, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s2, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s1, i32 0, i32 1 +// CHECK: getelementptr inbounds %struct.s43, %struct.s43* %s2, i32 0, i32 1 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; } int caller43_stack() { @@ -626,10 +626,10 @@ struct HFA { float test_hfa(int n, ...) { // CHECK-LABEL: define float @test_hfa(i32 %n, ...) // CHECK: [[THELIST:%.*]] = alloca i8* -// CHECK: [[CURLIST:%.*]] = load i8** [[THELIST]] +// CHECK: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] // HFA is not indirect, so occupies its full 16 bytes on the stack. -// CHECK: [[NEXTLIST:%.*]] = getelementptr i8* [[CURLIST]], i32 16 +// CHECK: [[NEXTLIST:%.*]] = getelementptr i8, i8* [[CURLIST]], i32 16 // CHECK: store i8* [[NEXTLIST]], i8** [[THELIST]] // CHECK: bitcast i8* [[CURLIST]] to %struct.HFA* @@ -641,7 +641,7 @@ float test_hfa(int n, ...) { float test_hfa_call(struct HFA *a) { // CHECK-LABEL: define float @test_hfa_call(%struct.HFA* %a) -// CHECK: call float (i32, ...)* @test_hfa(i32 1, [4 x float] {{.*}}) +// CHECK: call float (i32, ...) @test_hfa(i32 1, [4 x float] {{.*}}) test_hfa(1, *a); } @@ -652,15 +652,15 @@ struct TooBigHFA { float test_toobig_hfa(int n, ...) { // CHECK-LABEL: define float @test_toobig_hfa(i32 %n, ...) // CHECK: [[THELIST:%.*]] = alloca i8* -// CHECK: [[CURLIST:%.*]] = load i8** [[THELIST]] +// CHECK: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] // TooBigHFA is not actually an HFA, so gets passed indirectly. Only 8 bytes // of stack consumed. -// CHECK: [[NEXTLIST:%.*]] = getelementptr i8* [[CURLIST]], i32 8 +// CHECK: [[NEXTLIST:%.*]] = getelementptr i8, i8* [[CURLIST]], i32 8 // CHECK: store i8* [[NEXTLIST]], i8** [[THELIST]] // CHECK: [[HFAPTRPTR:%.*]] = bitcast i8* [[CURLIST]] to i8** -// CHECK: [[HFAPTR:%.*]] = load i8** [[HFAPTRPTR]] +// CHECK: [[HFAPTR:%.*]] = load i8*, i8** [[HFAPTRPTR]] // CHECK: bitcast i8* [[HFAPTR]] to %struct.TooBigHFA* __builtin_va_list thelist; __builtin_va_start(thelist, n); @@ -675,16 +675,16 @@ struct HVA { int32x4_t test_hva(int n, ...) { // CHECK-LABEL: define <4 x i32> @test_hva(i32 %n, ...) // CHECK: [[THELIST:%.*]] = alloca i8* -// CHECK: [[CURLIST:%.*]] = load i8** [[THELIST]] +// CHECK: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] // HVA is not indirect, so occupies its full 16 bytes on the stack. but it // must be properly aligned. -// CHECK: [[ALIGN0:%.*]] = getelementptr i8* [[CURLIST]], i32 15 +// CHECK: [[ALIGN0:%.*]] = getelementptr i8, i8* [[CURLIST]], i32 15 // CHECK: [[ALIGN1:%.*]] = ptrtoint i8* [[ALIGN0]] to i64 // CHECK: [[ALIGN2:%.*]] = and i64 [[ALIGN1]], -16 // CHECK: [[ALIGNED_LIST:%.*]] = inttoptr i64 [[ALIGN2]] to i8* -// CHECK: [[NEXTLIST:%.*]] = getelementptr i8* [[ALIGNED_LIST]], i32 32 +// CHECK: [[NEXTLIST:%.*]] = getelementptr i8, i8* [[ALIGNED_LIST]], i32 32 // CHECK: store i8* [[NEXTLIST]], i8** [[THELIST]] // CHECK: bitcast i8* [[ALIGNED_LIST]] to %struct.HVA* @@ -701,15 +701,15 @@ struct TooBigHVA { int32x4_t test_toobig_hva(int n, ...) { // CHECK-LABEL: define <4 x i32> @test_toobig_hva(i32 %n, ...) // CHECK: [[THELIST:%.*]] = alloca i8* -// CHECK: [[CURLIST:%.*]] = load i8** [[THELIST]] +// CHECK: [[CURLIST:%.*]] = load i8*, i8** [[THELIST]] // TooBigHVA is not actually an HVA, so gets passed indirectly. Only 8 bytes // of stack consumed. -// CHECK: [[NEXTLIST:%.*]] = getelementptr i8* [[CURLIST]], i32 8 +// CHECK: [[NEXTLIST:%.*]] = getelementptr i8, i8* [[CURLIST]], i32 8 // CHECK: store i8* [[NEXTLIST]], i8** [[THELIST]] // CHECK: [[HVAPTRPTR:%.*]] = bitcast i8* [[CURLIST]] to i8** -// CHECK: [[HVAPTR:%.*]] = load i8** [[HVAPTRPTR]] +// CHECK: [[HVAPTR:%.*]] = load i8*, i8** [[HVAPTRPTR]] // CHECK: bitcast i8* [[HVAPTR]] to %struct.TooBigHVA* __builtin_va_list thelist; __builtin_va_start(thelist, n); diff --git a/test/CodeGen/arm64_neon_high_half.c b/test/CodeGen/arm64_neon_high_half.c index 577a09e3a225..6008ba5e55c8 100644 --- a/test/CodeGen/arm64_neon_high_half.c +++ b/test/CodeGen/arm64_neon_high_half.c @@ -394,32 +394,32 @@ uint32x4_t test_vqrshrn_high_n_u64(uint32x2_t lowpart, uint64x2_t input) { } int8x16_t test_vaddhn_high_s16(int8x8_t lowpart, int16x8_t lhs, int16x8_t rhs) { - // CHECK: addhn2.16b v0, v1, v2 + // CHECK: addhn2.16b v0, {{v1, v2|v2, v1}} return vaddhn_high_s16(lowpart, lhs, rhs); } int16x8_t test_vaddhn_high_s32(int16x4_t lowpart, int32x4_t lhs, int32x4_t rhs) { - // CHECK: addhn2.8h v0, v1, v2 + // CHECK: addhn2.8h v0, {{v1, v2|v2, v1}} return vaddhn_high_s32(lowpart, lhs, rhs); } int32x4_t test_vaddhn_high_s64(int32x2_t lowpart, int64x2_t lhs, int64x2_t rhs) { - // CHECK: addhn2.4s v0, v1, v2 + // CHECK: addhn2.4s v0, {{v1, v2|v2, v1}} return vaddhn_high_s64(lowpart, lhs, rhs); } uint8x16_t test_vaddhn_high_u16(uint8x8_t lowpart, uint16x8_t lhs, uint16x8_t rhs) { - // CHECK: addhn2.16b v0, v1, v2 + // CHECK: addhn2.16b v0, {{v1, v2|v2, v1}} return vaddhn_high_s16(lowpart, lhs, rhs); } uint16x8_t test_vaddhn_high_u32(uint16x4_t lowpart, uint32x4_t lhs, uint32x4_t rhs) { - // CHECK: addhn2.8h v0, v1, v2 + // CHECK: addhn2.8h v0, {{v1, v2|v2, v1}} return vaddhn_high_s32(lowpart, lhs, rhs); } uint32x4_t test_vaddhn_high_u64(uint32x2_t lowpart, uint64x2_t lhs, uint64x2_t rhs) { - // CHECK: addhn2.4s v0, v1, v2 + // CHECK: addhn2.4s v0, {{v1, v2|v2, v1}} return vaddhn_high_s64(lowpart, lhs, rhs); } diff --git a/test/CodeGen/arm64_vMaxMin.c b/test/CodeGen/arm64_vMaxMin.c index 5f77b6c846a1..a1dd2adb255b 100644 --- a/test/CodeGen/arm64_vMaxMin.c +++ b/test/CodeGen/arm64_vMaxMin.c @@ -7,75 +7,75 @@ // Test a represntative sample of 8 and 16, signed and unsigned, 64 and 128 bit reduction int8_t test_vmaxv_s8(int8x8_t a1) { - // CHECK: test_vmaxv_s8 + // CHECK-LABEL: define i8 @test_vmaxv_s8( return vmaxv_s8(a1); - // CHECK @llvm.aarch64.neon.smaxv.i32.v8i8 + // CHECK: call i32 @llvm.aarch64.neon.smaxv.i32.v8i8( } uint16_t test_vminvq_u16(uint16x8_t a1) { - // CHECK: test_vminvq_u16 + // CHECK-LABEL: define i16 @test_vminvq_u16( return vminvq_u16(a1); - // CHECK llvm.aarch64.neon.uminv.i16.v8i16 + // CHECK: call i32 @llvm.aarch64.neon.uminv.i32.v8i16( } // Test a represntative sample of 8 and 16, signed and unsigned, 64 and 128 bit pairwise uint8x8_t test_vmin_u8(uint8x8_t a1, uint8x8_t a2) { - // CHECK: test_vmin_u8 + // CHECK-LABEL: define <8 x i8> @test_vmin_u8( return vmin_u8(a1, a2); - // CHECK llvm.aarch64.neon.umin.v8i8 + // CHECK: call <8 x i8> @llvm.aarch64.neon.umin.v8i8( } uint8x16_t test_vminq_u8(uint8x16_t a1, uint8x16_t a2) { - // CHECK: test_vminq_u8 + // CHECK-LABEL: define <16 x i8> @test_vminq_u8( return vminq_u8(a1, a2); - // CHECK llvm.aarch64.neon.umin.v16i8 + // CHECK: call <16 x i8> @llvm.aarch64.neon.umin.v16i8( } int16x8_t test_vmaxq_s16(int16x8_t a1, int16x8_t a2) { - // CHECK: test_vmaxq_s16 + // CHECK-LABEL: define <8 x i16> @test_vmaxq_s16( return vmaxq_s16(a1, a2); - // CHECK llvm.aarch64.neon.smax.v8i16 + // CHECK: call <8 x i16> @llvm.aarch64.neon.smax.v8i16( } // Test the more complicated cases of [suf]32 and f64 float64x2_t test_vmaxq_f64(float64x2_t a1, float64x2_t a2) { - // CHECK: test_vmaxq_f64 + // CHECK-LABEL: define <2 x double> @test_vmaxq_f64( return vmaxq_f64(a1, a2); - // CHECK llvm.aarch64.neon.fmax.v2f64 + // CHECK: call <2 x double> @llvm.aarch64.neon.fmax.v2f64( } float32x4_t test_vmaxq_f32(float32x4_t a1, float32x4_t a2) { - // CHECK: test_vmaxq_f32 + // CHECK-LABEL: define <4 x float> @test_vmaxq_f32( return vmaxq_f32(a1, a2); - // CHECK llvm.aarch64.neon.fmax.v4f32 + // CHECK: call <4 x float> @llvm.aarch64.neon.fmax.v4f32( } float64x2_t test_vminq_f64(float64x2_t a1, float64x2_t a2) { - // CHECK: test_vminq_f64 + // CHECK-LABEL: define <2 x double> @test_vminq_f64( return vminq_f64(a1, a2); - // CHECK llvm.aarch64.neon.fmin.v2f64 + // CHECK: call <2 x double> @llvm.aarch64.neon.fmin.v2f64( } float32x2_t test_vmax_f32(float32x2_t a1, float32x2_t a2) { - // CHECK: test_vmax_f32 + // CHECK-LABEL: define <2 x float> @test_vmax_f32( return vmax_f32(a1, a2); - // CHECK llvm.aarch64.neon.fmax.v2f32 + // CHECK: call <2 x float> @llvm.aarch64.neon.fmax.v2f32( } int32x2_t test_vmax_s32(int32x2_t a1, int32x2_t a2) { - // CHECK: test_vmax_s32 + // CHECK-LABEL: define <2 x i32> @test_vmax_s32( return vmax_s32(a1, a2); - // CHECK llvm.aarch64.neon.smax.v2i32 + // CHECK: call <2 x i32> @llvm.aarch64.neon.smax.v2i32( } uint32x2_t test_vmin_u32(uint32x2_t a1, uint32x2_t a2) { - // CHECK: test_vmin_u32 + // CHECK-LABEL: define <2 x i32> @test_vmin_u32( return vmin_u32(a1, a2); - // CHECK llvm.aarch64.neon.umin.v2i32 + // CHECK: call <2 x i32> @llvm.aarch64.neon.umin.v2i32( } float32_t test_vmaxnmv_f32(float32x2_t a1) { - // CHECK: test_vmaxnmv_f32 + // CHECK-LABEL: define float @test_vmaxnmv_f32( return vmaxnmv_f32(a1); // CHECK: llvm.aarch64.neon.fmaxnmv.f32.v2f32 // CHECK-NEXT: ret @@ -93,34 +93,34 @@ float64_t test_vmaxnmvq_f64(float64x2_t a1) { #endif float32_t test_vmaxnmvq_f32(float32x4_t a1) { - // CHECK: test_vmaxnmvq_f32 + // CHECK-LABEL: define float @test_vmaxnmvq_f32( return vmaxnmvq_f32(a1); - // CHECK: llvm.aarch64.neon.fmaxnmv.f32.v4f32 + // CHECK: call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32( // CHECK-NEXT: ret } float32_t test_vmaxv_f32(float32x2_t a1) { - // CHECK: test_vmaxv_f32 + // CHECK-LABEL: define float @test_vmaxv_f32( return vmaxv_f32(a1); - // CHECK: llvm.aarch64.neon.fmaxv.f32.v2f32 + // CHECK: call float @llvm.aarch64.neon.fmaxv.f32.v2f32( // FIXME check that the 2nd and 3rd arguments are the same V register below // CHECK-CODEGEN: fmaxp.2s // CHECK-NEXT: ret } int32_t test_vmaxv_s32(int32x2_t a1) { - // CHECK: test_vmaxv_s32 + // CHECK-LABEL: define i32 @test_vmaxv_s32( return vmaxv_s32(a1); - // CHECK: llvm.aarch64.neon.smaxv.i32.v2i32 + // CHECK: call i32 @llvm.aarch64.neon.smaxv.i32.v2i32( // FIXME check that the 2nd and 3rd arguments are the same V register below // CHECK-CODEGEN: smaxp.2s // CHECK-NEXT: ret } uint32_t test_vmaxv_u32(uint32x2_t a1) { - // CHECK: test_vmaxv_u32 + // CHECK-LABEL: define i32 @test_vmaxv_u32( return vmaxv_u32(a1); - // CHECK: llvm.aarch64.neon.umaxv.i32.v2i32 + // CHECK: call i32 @llvm.aarch64.neon.umaxv.i32.v2i32( // FIXME check that the 2nd and 3rd arguments are the same V register below // CHECK-CODEGEN: umaxp.2s // CHECK-NEXT: ret @@ -137,23 +137,23 @@ float64_t test_vmaxvq_f64(float64x2_t a1) { #endif float32_t test_vmaxvq_f32(float32x4_t a1) { - // CHECK: test_vmaxvq_f32 + // CHECK-LABEL: define float @test_vmaxvq_f32( return vmaxvq_f32(a1); - // CHECK: llvm.aarch64.neon.fmaxv.f32.v4f32 + // CHECK: call float @llvm.aarch64.neon.fmaxv.f32.v4f32( // CHECK-NEXT: ret } float32_t test_vminnmv_f32(float32x2_t a1) { - // CHECK: test_vminnmv_f32 + // CHECK-LABEL: define float @test_vminnmv_f32( return vminnmv_f32(a1); - // CHECK: llvm.aarch64.neon.fminnmv.f32.v2f32 + // CHECK: call float @llvm.aarch64.neon.fminnmv.f32.v2f32( // CHECK-NEXT: ret } float32_t test_vminvq_f32(float32x4_t a1) { - // CHECK: test_vminvq_f32 + // CHECK-LABEL: define float @test_vminvq_f32( return vminvq_f32(a1); - // CHECK: llvm.aarch64.neon.fminv.f32.v4f32 + // CHECK: call float @llvm.aarch64.neon.fminv.f32.v4f32( // CHECK-NEXT: ret } @@ -169,31 +169,31 @@ float64_t test_vminnmvq_f64(float64x2_t a1) { #endif float32_t test_vminnmvq_f32(float32x4_t a1) { - // CHECK: test_vminnmvq_f32 + // CHECK-LABEL: define float @test_vminnmvq_f32( return vminnmvq_f32(a1); - // CHECK: llvm.aarch64.neon.fminnmv.f32.v4f32 + // CHECK: call float @llvm.aarch64.neon.fminnmv.f32.v4f32( // CHECK-NEXT: ret } float32_t test_vminv_f32(float32x2_t a1) { - // CHECK: test_vminv_f32 + // CHECK-LABEL: define float @test_vminv_f32( return vminv_f32(a1); - // CHECK: llvm.aarch64.neon.fminv.f32.v2f32 + // CHECK: call float @llvm.aarch64.neon.fminv.f32.v2f32( // CHECK-NEXT: ret } int32_t test_vminv_s32(int32x2_t a1) { - // CHECK: test_vminv_s32 + // CHECK-LABEL: define i32 @test_vminv_s32( return vminv_s32(a1); - // CHECK: llvm.aarch64.neon.sminv.i32.v2i32 + // CHECK: call i32 @llvm.aarch64.neon.sminv.i32.v2i32( // CHECK-CODEGEN: sminp.2s // CHECK-NEXT: ret } uint32_t test_vminv_u32(uint32x2_t a1) { - // CHECK: test_vminv_u32 + // CHECK-LABEL: define i32 @test_vminv_u32( return vminv_u32(a1); - // CHECK: llvm.aarch64.neon.fminv.f32.v2f32 + // CHECK: call i32 @llvm.aarch64.neon.uminv.i32.v2i32( } // FIXME punt on this for now; don't forget to fix CHECKs diff --git a/test/CodeGen/arm64_vset_lane.c b/test/CodeGen/arm64_vset_lane.c index 6fbaaa7accbf..0508123b8473 100644 --- a/test/CodeGen/arm64_vset_lane.c +++ b/test/CodeGen/arm64_vset_lane.c @@ -6,13 +6,15 @@ float16x4_t test_vset_lane_f16(float16_t *a1, float16x4_t a2) { // CHECK-LABEL: test_vset_lane_f16 return vset_lane_f16(*a1, a2, 1); - // CHECK insertelement <4 x i16> %a2, i16 %a1, i32 1 + // CHECK: [[A1:%[0-9]+]] = load i16, i16* %a1 + // CHECK: insertelement <4 x i16> %a2, i16 [[A1]], i32 1 } float16x8_t test_vsetq_lane_f16(float16_t *a1, float16x8_t a2) { // CHECK-LABEL: test_vsetq_lane_f16 return vsetq_lane_f16(*a1, a2, 4); - // CHECK insertelement <8 x i16> %a2, i16 %a1, i32 4 + // CHECK: [[A1:%[0-9]+]] = load i16, i16* %a1 + // CHECK: insertelement <8 x i16> %a2, i16 [[A1]], i32 4 } // problem with scalar_to_vector in backend. Punt for now @@ -27,5 +29,5 @@ float64x1_t test_vset_lane_f64(float64_t a1, float64x1_t a2) { float64x2_t test_vsetq_lane_f64(float64_t a1, float64x2_t a2) { // CHECK-LABEL: test_vsetq_lane_f64 return vsetq_lane_f64(a1, a2, 0); - // CHECK insertelement <2 x double> %a2, double %a1, i32 0 + // CHECK: insertelement <2 x double> %a2, double %a1, i32 0 } diff --git a/test/CodeGen/arm64_vtst.c b/test/CodeGen/arm64_vtst.c index f40c62c4a303..9f3ed8423645 100644 --- a/test/CodeGen/arm64_vtst.c +++ b/test/CodeGen/arm64_vtst.c @@ -4,18 +4,18 @@ #include <arm_neon.h> uint64x2_t test_vtstq_s64(int64x2_t a1, int64x2_t a2) { - // CHECK: test_vtstq_s64 + // CHECK-LABEL: test_vtstq_s64 return vtstq_s64(a1, a2); - // CHECK: [[COMMONBITS:%[A-Za-z0-9.]+]] = and <2 x i64> %a1, %a2 + // CHECK: [[COMMONBITS:%[A-Za-z0-9.]+]] = and <2 x i64> {{%a1, %a2|%a2, %a1}} // CHECK: [[MASK:%[A-Za-z0-9.]+]] = icmp ne <2 x i64> [[COMMONBITS]], zeroinitializer // CHECK: [[RES:%[A-Za-z0-9.]+]] = sext <2 x i1> [[MASK]] to <2 x i64> // CHECK: ret <2 x i64> [[RES]] } uint64x2_t test_vtstq_u64(uint64x2_t a1, uint64x2_t a2) { - // CHECK: test_vtstq_u64 + // CHECK-LABEL: test_vtstq_u64 return vtstq_u64(a1, a2); - // CHECK: [[COMMONBITS:%[A-Za-z0-9.]+]] = and <2 x i64> %a1, %a2 + // CHECK: [[COMMONBITS:%[A-Za-z0-9.]+]] = and <2 x i64> {{%a1, %a2|%a2, %a1}} // CHECK: [[MASK:%[A-Za-z0-9.]+]] = icmp ne <2 x i64> [[COMMONBITS]], zeroinitializer // CHECK: [[RES:%[A-Za-z0-9.]+]] = sext <2 x i1> [[MASK]] to <2 x i64> // CHECK: ret <2 x i64> [[RES]] diff --git a/test/CodeGen/asm-errors.c b/test/CodeGen/asm-errors.c index 438c82ba74db..05751a8e690a 100644 --- a/test/CodeGen/asm-errors.c +++ b/test/CodeGen/asm-errors.c @@ -3,6 +3,12 @@ // RUN: true // UN: not %clang_cc1 -triple i386-apple-darwin10 -emit-obj %s -o /dev/null > %t 2>&1 // UN: FileCheck %s < %t +// RUN: %clang_cc1 -triple i386-apple-darwin10 -emit-llvm-bc %s -o %t.bc +// RUN: %clang_cc1 -triple i386-apple-darwin10 -emit-obj %t.bc -o /dev/null 2>&1 | \ +// RUN: FileCheck --check-prefix=CRASH-REPORT %s +// CRASH-REPORT: <inline asm>: +// CRASH-REPORT: error: invalid instruction mnemonic 'abc' +// CRASH-REPORT-NOT: note: diagnostic msg: int test1(int X) { // CHECK: error: invalid instruction mnemonic 'abc' diff --git a/test/CodeGen/asm-inout.c b/test/CodeGen/asm-inout.c index c7d1aeceb92f..e5da5c5e934a 100644 --- a/test/CodeGen/asm-inout.c +++ b/test/CodeGen/asm-inout.c @@ -12,7 +12,7 @@ void test1() { // CHECK: @test2 void test2() { // CHECK: [[REGCALLRESULT:%[a-zA-Z0-9\.]+]] = call i32* @foo() - // CHECK: load i32* [[REGCALLRESULT]] + // CHECK: load i32, i32* [[REGCALLRESULT]] // CHECK: call i32 asm // CHECK: store i32 {{%[a-zA-Z0-9\.]+}}, i32* [[REGCALLRESULT]] asm ("foobar" : "+r"(*foo())); diff --git a/test/CodeGen/asm-reg-var-local.c b/test/CodeGen/asm-reg-var-local.c index 9060e120ffc9..56dcab4cb906 100644 --- a/test/CodeGen/asm-reg-var-local.c +++ b/test/CodeGen/asm-reg-var-local.c @@ -2,6 +2,7 @@ // Exercise various use cases for local asm "register variables". int foo() { +// CHECK-LABEL: define i32 @foo() // CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32 register int a asm("rsi")=5; @@ -15,10 +16,33 @@ int foo() { // CHECK: store i32 42, i32* [[A]] asm volatile("; %0 This asm uses rsi" : : "r"(a)); -// CHECK: [[TMP:%[a-zA-Z0-9]+]] = load i32* [[A]] +// CHECK: [[TMP:%[a-zA-Z0-9]+]] = load i32, i32* [[A]] // CHECK: call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 [[TMP]]) return a; -// CHECK: [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]] +// CHECK: [[TMP1:%[a-zA-Z0-9]+]] = load i32, i32* [[A]] +// CHECK: ret i32 [[TMP1]] +} + +int earlyclobber() { +// CHECK-LABEL: define i32 @earlyclobber() +// CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32 + + register int a asm("rsi")=5; +// CHECK: store i32 5, i32* [[A]] + + asm volatile("; %0 This asm defines rsi" : "=&r"(a)); +// CHECK: [[Z:%[a-zA-Z0-9]+]] = call i32 asm sideeffect "; $0 This asm defines rsi", "=&{rsi},~{dirflag},~{fpsr},~{flags}"() +// CHECK: store i32 [[Z]], i32* [[A]] + + a = 42; +// CHECK: store i32 42, i32* [[A]] + + asm volatile("; %0 This asm uses rsi" : : "r"(a)); +// CHECK: [[TMP:%[a-zA-Z0-9]+]] = load i32, i32* [[A]] +// CHECK: call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 [[TMP]]) + + return a; +// CHECK: [[TMP1:%[a-zA-Z0-9]+]] = load i32, i32* [[A]] // CHECK: ret i32 [[TMP1]] } diff --git a/test/CodeGen/atomic-arm64.c b/test/CodeGen/atomic-arm64.c index 147b570e21c6..98f27aba4f7d 100644 --- a/test/CodeGen/atomic-arm64.c +++ b/test/CodeGen/atomic-arm64.c @@ -24,7 +24,7 @@ extern _Atomic(pointer_quad_t) a_pointer_quad; // CHECK: define void @test0() // CHECK: [[TEMP:%.*]] = alloca i8, align 1 // CHECK-NEXT: store i8 1, i8* [[TEMP]] -// CHECK-NEXT: [[T0:%.*]] = load i8* [[TEMP]], align 1 +// CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[TEMP]], align 1 // CHECK-NEXT: store atomic i8 [[T0]], i8* @a_bool seq_cst, align 1 void test0() { __c11_atomic_store(&a_bool, 1, memory_order_seq_cst); @@ -34,7 +34,7 @@ void test0() { // CHECK: [[TEMP:%.*]] = alloca float, align 4 // CHECK-NEXT: store float 3.000000e+00, float* [[TEMP]] // CHECK-NEXT: [[T0:%.*]] = bitcast float* [[TEMP]] to i32* -// CHECK-NEXT: [[T1:%.*]] = load i32* [[T0]], align 4 +// CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[T0]], align 4 // CHECK-NEXT: store atomic i32 [[T1]], i32* bitcast (float* @a_float to i32*) seq_cst, align 4 void test1() { __c11_atomic_store(&a_float, 3, memory_order_seq_cst); @@ -44,7 +44,7 @@ void test1() { // CHECK: [[TEMP:%.*]] = alloca i8*, align 8 // CHECK-NEXT: store i8* @a_bool, i8** [[TEMP]] // CHECK-NEXT: [[T0:%.*]] = bitcast i8** [[TEMP]] to i64* -// CHECK-NEXT: [[T1:%.*]] = load i64* [[T0]], align 8 +// CHECK-NEXT: [[T1:%.*]] = load i64, i64* [[T0]], align 8 // CHECK-NEXT: store atomic i64 [[T1]], i64* bitcast (i8** @a_pointer to i64*) seq_cst, align 8 void test2() { __c11_atomic_store(&a_pointer, &a_bool, memory_order_seq_cst); @@ -55,7 +55,7 @@ void test2() { // CHECK-NEXT: [[TEMP:%.*]] = alloca [[PAIR_T]], align 8 // CHECK: llvm.memcpy // CHECK-NEXT: [[T0:%.*]] = bitcast [[PAIR_T]]* [[TEMP]] to i128* -// CHECK-NEXT: [[T1:%.*]] = load i128* [[T0]], align 16 +// CHECK-NEXT: [[T1:%.*]] = load i128, i128* [[T0]], align 16 // CHECK-NEXT: store atomic i128 [[T1]], i128* bitcast ([[PAIR_T]]* @a_pointer_pair to i128*) seq_cst, align 16 void test3(pointer_pair_t pair) { __c11_atomic_store(&a_pointer_pair, pair, memory_order_seq_cst); diff --git a/test/CodeGen/atomic-ops.c b/test/CodeGen/atomic-ops.c index 559b13541323..733c60eb859c 100644 --- a/test/CodeGen/atomic-ops.c +++ b/test/CodeGen/atomic-ops.c @@ -13,13 +13,13 @@ int fi1(_Atomic(int) *i) { // CHECK-LABEL: @fi1 - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst return __c11_atomic_load(i, memory_order_seq_cst); } int fi1a(int *i) { // CHECK-LABEL: @fi1a - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst int v; __atomic_load(i, &v, memory_order_seq_cst); return v; @@ -27,13 +27,13 @@ int fi1a(int *i) { int fi1b(int *i) { // CHECK-LABEL: @fi1b - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst return __atomic_load_n(i, memory_order_seq_cst); } int fi1c(atomic_int *i) { // CHECK-LABEL: @fi1c - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst return atomic_load(i); } @@ -148,7 +148,7 @@ _Bool fi4c(atomic_int *i) { float ff1(_Atomic(float) *d) { // CHECK-LABEL: @ff1 - // CHECK: load atomic i32* {{.*}} monotonic + // CHECK: load atomic i32, i32* {{.*}} monotonic return __c11_atomic_load(d, memory_order_relaxed); } @@ -184,11 +184,11 @@ void fd2(struct S *a, struct S *b) { // CHECK-NEXT: [[B_ADDR:%.*]] = alloca %struct.S*, align 4 // CHECK-NEXT: store %struct.S* %a, %struct.S** [[A_ADDR]], align 4 // CHECK-NEXT: store %struct.S* %b, %struct.S** [[B_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_A_PTR:%.*]] = load %struct.S** [[A_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_B_PTR:%.*]] = load %struct.S** [[B_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_A_PTR:%.*]] = load %struct.S*, %struct.S** [[A_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_B_PTR:%.*]] = load %struct.S*, %struct.S** [[B_ADDR]], align 4 // CHECK-NEXT: [[COERCED_A:%.*]] = bitcast %struct.S* [[LOAD_A_PTR]] to i8* // CHECK-NEXT: [[COERCED_B:%.*]] = bitcast %struct.S* [[LOAD_B_PTR]] to i64* - // CHECK-NEXT: [[LOAD_B:%.*]] = load i64* [[COERCED_B]], align 4 + // CHECK-NEXT: [[LOAD_B:%.*]] = load i64, i64* [[COERCED_B]], align 4 // CHECK-NEXT: call void @__atomic_store_8(i8* [[COERCED_A]], i64 [[LOAD_B]], // CHECK-NEXT: ret void __atomic_store(a, b, memory_order_seq_cst); @@ -202,12 +202,12 @@ void fd3(struct S *a, struct S *b, struct S *c) { // CHECK-NEXT: store %struct.S* %a, %struct.S** [[A_ADDR]], align 4 // CHECK-NEXT: store %struct.S* %b, %struct.S** [[B_ADDR]], align 4 // CHECK-NEXT: store %struct.S* %c, %struct.S** [[C_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_A_PTR:%.*]] = load %struct.S** [[A_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_B_PTR:%.*]] = load %struct.S** [[B_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_C_PTR:%.*]] = load %struct.S** [[C_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_A_PTR:%.*]] = load %struct.S*, %struct.S** [[A_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_B_PTR:%.*]] = load %struct.S*, %struct.S** [[B_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_C_PTR:%.*]] = load %struct.S*, %struct.S** [[C_ADDR]], align 4 // CHECK-NEXT: [[COERCED_A:%.*]] = bitcast %struct.S* [[LOAD_A_PTR]] to i8* // CHECK-NEXT: [[COERCED_B:%.*]] = bitcast %struct.S* [[LOAD_B_PTR]] to i64* - // CHECK-NEXT: [[LOAD_B:%.*]] = load i64* [[COERCED_B]], align 4 + // CHECK-NEXT: [[LOAD_B:%.*]] = load i64, i64* [[COERCED_B]], align 4 // CHECK-NEXT: [[CALL:%.*]] = call i64 @__atomic_exchange_8(i8* [[COERCED_A]], i64 [[LOAD_B]], // CHECK-NEXT: [[COERCED_C:%.*]] = bitcast %struct.S* [[LOAD_C_PTR]] to i64* // CHECK-NEXT: store i64 [[CALL]], i64* [[COERCED_C]], align 4 @@ -223,13 +223,13 @@ _Bool fd4(struct S *a, struct S *b, struct S *c) { // CHECK: store %struct.S* %a, %struct.S** [[A_ADDR]], align 4 // CHECK-NEXT: store %struct.S* %b, %struct.S** [[B_ADDR]], align 4 // CHECK-NEXT: store %struct.S* %c, %struct.S** [[C_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_A_PTR:%.*]] = load %struct.S** [[A_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_B_PTR:%.*]] = load %struct.S** [[B_ADDR]], align 4 - // CHECK-NEXT: [[LOAD_C_PTR:%.*]] = load %struct.S** [[C_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_A_PTR:%.*]] = load %struct.S*, %struct.S** [[A_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_B_PTR:%.*]] = load %struct.S*, %struct.S** [[B_ADDR]], align 4 + // CHECK-NEXT: [[LOAD_C_PTR:%.*]] = load %struct.S*, %struct.S** [[C_ADDR]], align 4 // CHECK-NEXT: [[COERCED_A:%.*]] = bitcast %struct.S* [[LOAD_A_PTR]] to i8* // CHECK-NEXT: [[COERCED_B:%.*]] = bitcast %struct.S* [[LOAD_B_PTR]] to i8* // CHECK-NEXT: [[COERCED_C:%.*]] = bitcast %struct.S* [[LOAD_C_PTR]] to i64* - // CHECK-NEXT: [[LOAD_C:%.*]] = load i64* [[COERCED_C]], align 4 + // CHECK-NEXT: [[LOAD_C:%.*]] = load i64, i64* [[COERCED_C]], align 4 // CHECK-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange_8(i8* [[COERCED_A]], i8* [[COERCED_B]], i64 [[LOAD_C]] // CHECK-NEXT: ret i1 [[CALL]] return __atomic_compare_exchange(a, b, c, 1, 5, 5); @@ -237,7 +237,7 @@ _Bool fd4(struct S *a, struct S *b, struct S *c) { int* fp1(_Atomic(int*) *p) { // CHECK-LABEL: @fp1 - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst return __c11_atomic_load(p, memory_order_seq_cst); } @@ -388,7 +388,7 @@ int structAtomicCmpExchange() { // CHECK: %[[call1:.*]] = call zeroext i1 @__atomic_compare_exchange(i32 3, {{.*}} @smallThing{{.*}} @thing1{{.*}} @thing2 // CHECK: %[[zext1:.*]] = zext i1 %[[call1]] to i8 // CHECK: store i8 %[[zext1]], i8* %[[x_mem]], align 1 - // CHECK: %[[x:.*]] = load i8* %[[x_mem]] + // CHECK: %[[x:.*]] = load i8, i8* %[[x_mem]] // CHECK: %[[x_bool:.*]] = trunc i8 %[[x]] to i1 // CHECK: %[[conv1:.*]] = zext i1 %[[x_bool]] to i32 @@ -558,11 +558,11 @@ int PR21643() { // CHECK: %[[atomictmp:.*]] = alloca i32, align 4 // CHECK: %[[atomicdst:.*]] = alloca i32, align 4 // CHECK: store i32 1, i32* %[[atomictmp]] - // CHECK: %[[one:.*]] = load i32* %[[atomictmp]], align 4 + // CHECK: %[[one:.*]] = load i32, i32* %[[atomictmp]], align 4 // CHECK: %[[old:.*]] = atomicrmw or i32 addrspace(257)* inttoptr (i32 776 to i32 addrspace(257)*), i32 %[[one]] monotonic // CHECK: %[[new:.*]] = or i32 %[[old]], %[[one]] // CHECK: store i32 %[[new]], i32* %[[atomicdst]], align 4 - // CHECK: %[[ret:.*]] = load i32* %[[atomicdst]], align 4 + // CHECK: %[[ret:.*]] = load i32, i32* %[[atomicdst]], align 4 // CHECK: ret i32 %[[ret]] } @@ -571,10 +571,10 @@ int PR17306_1(volatile _Atomic(int) *i) { // CHECK: %[[i_addr:.*]] = alloca i32 // CHECK-NEXT: %[[atomicdst:.*]] = alloca i32 // CHECK-NEXT: store i32* %i, i32** %[[i_addr]] - // CHECK-NEXT: %[[addr:.*]] = load i32** %[[i_addr]] - // CHECK-NEXT: %[[res:.*]] = load atomic volatile i32* %[[addr]] seq_cst + // CHECK-NEXT: %[[addr:.*]] = load i32*, i32** %[[i_addr]] + // CHECK-NEXT: %[[res:.*]] = load atomic volatile i32, i32* %[[addr]] seq_cst // CHECK-NEXT: store i32 %[[res]], i32* %[[atomicdst]] - // CHECK-NEXT: %[[retval:.*]] = load i32* %[[atomicdst]] + // CHECK-NEXT: %[[retval:.*]] = load i32, i32* %[[atomicdst]] // CHECK-NEXT: ret i32 %[[retval]] return __c11_atomic_load(i, memory_order_seq_cst); } @@ -587,14 +587,14 @@ int PR17306_2(volatile int *i, int value) { // CHECK-NEXT: %[[atomicdst:.*]] = alloca i32 // CHECK-NEXT: store i32* %i, i32** %[[i_addr]] // CHECK-NEXT: store i32 %value, i32* %[[value_addr]] - // CHECK-NEXT: %[[i_lval:.*]] = load i32** %[[i_addr]] - // CHECK-NEXT: %[[value:.*]] = load i32* %[[value_addr]] + // CHECK-NEXT: %[[i_lval:.*]] = load i32*, i32** %[[i_addr]] + // CHECK-NEXT: %[[value:.*]] = load i32, i32* %[[value_addr]] // CHECK-NEXT: store i32 %[[value]], i32* %[[atomictmp]] - // CHECK-NEXT: %[[value_lval:.*]] = load i32* %[[atomictmp]] + // CHECK-NEXT: %[[value_lval:.*]] = load i32, i32* %[[atomictmp]] // CHECK-NEXT: %[[old_val:.*]] = atomicrmw volatile add i32* %[[i_lval]], i32 %[[value_lval]] seq_cst // CHECK-NEXT: %[[new_val:.*]] = add i32 %[[old_val]], %[[value_lval]] // CHECK-NEXT: store i32 %[[new_val]], i32* %[[atomicdst]] - // CHECK-NEXT: %[[retval:.*]] = load i32* %[[atomicdst]] + // CHECK-NEXT: %[[retval:.*]] = load i32, i32* %[[atomicdst]] // CHECK-NEXT: ret i32 %[[retval]] return __atomic_add_fetch(i, value, memory_order_seq_cst); } diff --git a/test/CodeGen/atomic_ops.c b/test/CodeGen/atomic_ops.c index 29009bef894c..980ecd20e660 100644 --- a/test/CodeGen/atomic_ops.c +++ b/test/CodeGen/atomic_ops.c @@ -1,4 +1,6 @@ +// XFAIL: hexagon // RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm %s -o - | FileCheck %s void foo(int x) { @@ -16,3 +18,21 @@ void foo(int x) // CHECK: {{(cmpxchg i16*|i1 @__atomic_compare_exchange\(i32 2, )}} } + +extern _Atomic _Bool b; + +_Bool bar() { +// CHECK-LABEL: @bar +// CHECK: %[[load:.*]] = load atomic i8, i8* @b seq_cst +// CHECK: %[[tobool:.*]] = trunc i8 %[[load]] to i1 +// CHECK: ret i1 %[[tobool]] + return b; +} + +extern _Atomic(_Complex int) x; + +void baz(int y) { +// CHECK-LABEL: @baz +// CHECK: {{store atomic|call void @__atomic_store}} + x += y; +} diff --git a/test/CodeGen/atomics-inlining.c b/test/CodeGen/atomics-inlining.c index 9cd280294f38..23a79a2d28f9 100644 --- a/test/CodeGen/atomics-inlining.c +++ b/test/CodeGen/atomics-inlining.c @@ -40,54 +40,54 @@ void test1(void) { // ARM: call{{.*}} void @__atomic_store_4(i8* bitcast (i32* @i1 to i8*), i32 // ARM: = call{{.*}} i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) // ARM: call{{.*}} void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 -// ARM: call{{.*}} void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) -// ARM: call{{.*}} void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) +// ARM: call{{.*}} void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// ARM: call{{.*}} void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // PPC32-LABEL: define void @test1 -// PPC32: = load atomic i8* @c1 seq_cst +// PPC32: = load atomic i8, i8* @c1 seq_cst // PPC32: store atomic i8 {{.*}}, i8* @c1 seq_cst -// PPC32: = load atomic i16* @s1 seq_cst +// PPC32: = load atomic i16, i16* @s1 seq_cst // PPC32: store atomic i16 {{.*}}, i16* @s1 seq_cst -// PPC32: = load atomic i32* @i1 seq_cst +// PPC32: = load atomic i32, i32* @i1 seq_cst // PPC32: store atomic i32 {{.*}}, i32* @i1 seq_cst // PPC32: = call i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) // PPC32: call void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 -// PPC32: call void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) -// PPC32: call void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) +// PPC32: call void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// PPC32: call void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // PPC64-LABEL: define void @test1 -// PPC64: = load atomic i8* @c1 seq_cst +// PPC64: = load atomic i8, i8* @c1 seq_cst // PPC64: store atomic i8 {{.*}}, i8* @c1 seq_cst -// PPC64: = load atomic i16* @s1 seq_cst +// PPC64: = load atomic i16, i16* @s1 seq_cst // PPC64: store atomic i16 {{.*}}, i16* @s1 seq_cst -// PPC64: = load atomic i32* @i1 seq_cst +// PPC64: = load atomic i32, i32* @i1 seq_cst // PPC64: store atomic i32 {{.*}}, i32* @i1 seq_cst -// PPC64: = load atomic i64* @ll1 seq_cst +// PPC64: = load atomic i64, i64* @ll1 seq_cst // PPC64: store atomic i64 {{.*}}, i64* @ll1 seq_cst -// PPC64: call void @__atomic_load(i64 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) -// PPC64: call void @__atomic_store(i64 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) +// PPC64: call void @__atomic_load(i64 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// PPC64: call void @__atomic_store(i64 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // MIPS32-LABEL: define void @test1 -// MIPS32: = load atomic i8* @c1 seq_cst +// MIPS32: = load atomic i8, i8* @c1 seq_cst // MIPS32: store atomic i8 {{.*}}, i8* @c1 seq_cst -// MIPS32: = load atomic i16* @s1 seq_cst +// MIPS32: = load atomic i16, i16* @s1 seq_cst // MIPS32: store atomic i16 {{.*}}, i16* @s1 seq_cst -// MIPS32: = load atomic i32* @i1 seq_cst +// MIPS32: = load atomic i32, i32* @i1 seq_cst // MIPS32: store atomic i32 {{.*}}, i32* @i1 seq_cst // MIPS32: call i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*) // MIPS32: call void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64 -// MIPS32: call void @__atomic_load(i32 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) -// MIPS32: call void @__atomic_store(i32 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) +// MIPS32: call void @__atomic_load(i32 signext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) +// MIPS32: call void @__atomic_store(i32 signext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) // MIPS64-LABEL: define void @test1 -// MIPS64: = load atomic i8* @c1 seq_cst +// MIPS64: = load atomic i8, i8* @c1 seq_cst // MIPS64: store atomic i8 {{.*}}, i8* @c1 seq_cst -// MIPS64: = load atomic i16* @s1 seq_cst +// MIPS64: = load atomic i16, i16* @s1 seq_cst // MIPS64: store atomic i16 {{.*}}, i16* @s1 seq_cst -// MIPS64: = load atomic i32* @i1 seq_cst +// MIPS64: = load atomic i32, i32* @i1 seq_cst // MIPS64: store atomic i32 {{.*}}, i32* @i1 seq_cst -// MIPS64: = load atomic i64* @ll1 seq_cst +// MIPS64: = load atomic i64, i64* @ll1 seq_cst // MIPS64: store atomic i64 {{.*}}, i64* @ll1 seq_cst -// MIPS64: call void @__atomic_load(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0) -// MIPS64: call void @__atomic_store(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8]* @a2, i32 0, i32 0) +// MIPS64: call void @__atomic_load(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0) +// MIPS64: call void @__atomic_store(i64 zeroext 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0) } diff --git a/test/CodeGen/attributes.c b/test/CodeGen/attributes.c index 5c9c90d7cee4..4da3eca9e49e 100644 --- a/test/CodeGen/attributes.c +++ b/test/CodeGen/attributes.c @@ -79,7 +79,7 @@ void (__attribute__((fastcall)) *fptr)(int); void t21(void) { fptr(10); } -// CHECK: [[FPTRVAR:%[a-z0-9]+]] = load void (i32)** @fptr +// CHECK: [[FPTRVAR:%[a-z0-9]+]] = load void (i32)*, void (i32)** @fptr // CHECK-NEXT: call x86_fastcallcc void [[FPTRVAR]](i32 inreg 10) diff --git a/test/CodeGen/avx-builtins.c b/test/CodeGen/avx-builtins.c index 5b5b6a56b4b6..99d063385c4f 100644 --- a/test/CodeGen/avx-builtins.c +++ b/test/CodeGen/avx-builtins.c @@ -10,17 +10,17 @@ // __m256 test__mm256_loadu_ps(void* p) { - // CHECK: load <8 x float>* %{{.*}}, align 1 + // CHECK: load <8 x float>, <8 x float>* %{{.*}}, align 1 return _mm256_loadu_ps(p); } __m256d test__mm256_loadu_pd(void* p) { - // CHECK: load <4 x double>* %{{.*}}, align 1 + // CHECK: load <4 x double>, <4 x double>* %{{.*}}, align 1 return _mm256_loadu_pd(p); } __m256i test__mm256_loadu_si256(void* p) { - // CHECK: load <4 x i64>* %{{.+}}, align 1 + // CHECK: load <4 x i64>, <4 x i64>* %{{.+}}, align 1 return _mm256_loadu_si256(p); } @@ -123,3 +123,27 @@ __m256 test_256_blend_ps(__m256 __a, __m256 __b) { // CHECK: shufflevector <8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x i32> <i32 8, i32 1, i32 10, i32 3, i32 12, i32 13, i32 6, i32 7> return _mm256_blend_ps(__a, __b, 0x35); } + +__m256i test_256_insert_epi8(__m256i __a) { + // CHECK-LABEL: @test_256_insert_epi8 + // CHECK: insertelement <32 x i8> {{.*}}, i8 {{.*}}, i32 {{.*}} + return _mm256_insert_epi8(__a, 42, 3); +} + +__m256i test_256_insert_epi16(__m256i __a) { + // CHECK-LABEL: @test_256_insert_epi16 + // CHECK: insertelement <16 x i16> {{.*}}, i16 {{.*}}, i32 {{.*}} + return _mm256_insert_epi16(__a, 42, 3); +} + +__m256i test_256_insert_epi32(__m256i __a) { + // CHECK-LABEL: @test_256_insert_epi32 + // CHECK: insertelement <8 x i32> {{.*}}, i32 {{.*}}, i32 {{.*}} + return _mm256_insert_epi32(__a, 42, 3); +} + +__m256i test_256_insert_epi64(__m256i __a) { + // CHECK-LABEL: @test_256_insert_epi64 + // CHECK: insertelement <4 x i64> {{.*}}, i64 {{.*}}, i32 {{.*}} + return _mm256_insert_epi64(__a, 42, 3); +} diff --git a/test/CodeGen/avx-shuffle-builtins.c b/test/CodeGen/avx-shuffle-builtins.c index 76e2395fe8e3..913f9d238130 100644 --- a/test/CodeGen/avx-shuffle-builtins.c +++ b/test/CodeGen/avx-shuffle-builtins.c @@ -48,19 +48,19 @@ __m256 test_mm256_permute_ps(__m256 a) { __m256d test_mm256_permute2f128_pd(__m256d a, __m256d b) { // Check if the mask is correct - // CHECK: @llvm.x86.avx.vperm2f128.pd.256 + // CHECK: shufflevector{{.*}}<i32 2, i32 3, i32 6, i32 7> return _mm256_permute2f128_pd(a, b, 0x31); } __m256 test_mm256_permute2f128_ps(__m256 a, __m256 b) { // Check if the mask is correct - // CHECK: @llvm.x86.avx.vperm2f128.ps.256 + // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15> return _mm256_permute2f128_ps(a, b, 0x13); } __m256i test_mm256_permute2f128_si256(__m256i a, __m256i b) { // Check if the mask is correct - // CHECK: @llvm.x86.avx.vperm2f128.si.256 + // CHECK: shufflevector{{.*}} <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> return _mm256_permute2f128_si256(a, b, 0x20); } @@ -97,3 +97,115 @@ test_mm256_broadcast_ss(float const *__a) { // CHECK: insertelement <8 x float> {{.*}}, i32 7 return _mm256_broadcast_ss(__a); } + +// Make sure we have the correct mask for each insertf128 case. + +__m256 test_mm256_insertf128_ps_0(__m256 a, __m128 b) { + // CHECK-LABEL: @test_mm256_insertf128_ps_0 + // CHECK: shufflevector{{.*}}<i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> + return _mm256_insertf128_ps(a, b, 0); +} + +__m256d test_mm256_insertf128_pd_0(__m256d a, __m128d b) { + // CHECK-LABEL: @test_mm256_insertf128_pd_0 + // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 2, i32 3> + return _mm256_insertf128_pd(a, b, 0); +} + +__m256i test_mm256_insertf128_si256_0(__m256i a, __m128i b) { + // CHECK-LABEL: @test_mm256_insertf128_si256_0 + // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 2, i32 3> + return _mm256_insertf128_si256(a, b, 0); +} + +__m256 test_mm256_insertf128_ps_1(__m256 a, __m128 b) { + // CHECK-LABEL: @test_mm256_insertf128_ps_1 + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> + return _mm256_insertf128_ps(a, b, 1); +} + +__m256d test_mm256_insertf128_pd_1(__m256d a, __m128d b) { + // CHECK-LABEL: @test_mm256_insertf128_pd_1 + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 4, i32 5> + return _mm256_insertf128_pd(a, b, 1); +} + +__m256i test_mm256_insertf128_si256_1(__m256i a, __m128i b) { + // CHECK-LABEL: @test_mm256_insertf128_si256_1 + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 4, i32 5> + return _mm256_insertf128_si256(a, b, 1); +} + +// Make sure we have the correct mask for each extractf128 case. + +__m128 test_mm256_extractf128_ps_0(__m256 a) { + // CHECK-LABEL: @test_mm256_extractf128_ps_0 + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3> + return _mm256_extractf128_ps(a, 0); +} + +__m128d test_mm256_extractf128_pd_0(__m256d a) { + // CHECK-LABEL: @test_mm256_extractf128_pd_0 + // CHECK: shufflevector{{.*}}<i32 0, i32 1> + return _mm256_extractf128_pd(a, 0); +} + +__m128i test_mm256_extractf128_si256_0(__m256i a) { + // CHECK-LABEL: @test_mm256_extractf128_si256_0 + // CHECK: shufflevector{{.*}}<i32 0, i32 1> + return _mm256_extractf128_si256(a, 0); +} + +__m128 test_mm256_extractf128_ps_1(__m256 a) { + // CHECK-LABEL: @test_mm256_extractf128_ps_1 + // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 6, i32 7> + return _mm256_extractf128_ps(a, 1); +} + +__m128d test_mm256_extractf128_pd_1(__m256d a) { + // CHECK-LABEL: @test_mm256_extractf128_pd_1 + // CHECK: shufflevector{{.*}}<i32 2, i32 3> + return _mm256_extractf128_pd(a, 1); +} + +__m128i test_mm256_extractf128_si256_1(__m256i a) { + // CHECK-LABEL: @test_mm256_extractf128_si256_1 + // CHECK: shufflevector{{.*}}<i32 2, i32 3> + return _mm256_extractf128_si256(a, 1); +} + +__m256 test_mm256_set_m128(__m128 hi, __m128 lo) { + // CHECK-LABEL: @test_mm256_set_m128 + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + return _mm256_set_m128(hi, lo); +} + +__m256d test_mm256_set_m128d(__m128d hi, __m128d lo) { + // CHECK-LABEL: @test_mm256_set_m128d + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + return _mm256_set_m128d(hi, lo); +} + +__m256i test_mm256_set_m128i(__m128i hi, __m128i lo) { + // CHECK-LABEL: @test_mm256_set_m128i + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + return _mm256_set_m128i(hi, lo); +} + +__m256 test_mm256_setr_m128(__m128 hi, __m128 lo) { + // CHECK-LABEL: @test_mm256_setr_m128 + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + return _mm256_setr_m128(lo, hi); +} + +__m256d test_mm256_setr_m128d(__m128d hi, __m128d lo) { + // CHECK-LABEL: @test_mm256_setr_m128d + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + return _mm256_setr_m128d(lo, hi); +} + +__m256i test_mm256_setr_m128i(__m128i hi, __m128i lo) { + // CHECK-LABEL: @test_mm256_setr_m128i + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + return _mm256_setr_m128i(lo, hi); +} diff --git a/test/CodeGen/avx2-builtins.c b/test/CodeGen/avx2-builtins.c index 04825ffa2f60..e3628717c5b0 100644 --- a/test/CodeGen/avx2-builtins.c +++ b/test/CodeGen/avx2-builtins.c @@ -96,7 +96,7 @@ __m256i test_mm256_alignr_epi8(__m256i a, __m256i b) { } __m256i test2_mm256_alignr_epi8(__m256i a, __m256i b) { - // CHECK: @llvm.x86.avx2.psrl.dq({{.*}}, i32 8) + // CHECK: shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48> return _mm256_alignr_epi8(a, b, 17); } @@ -462,10 +462,15 @@ __m256i test_mm256_sign_epi32(__m256i a, __m256i b) { } __m256i test_mm256_slli_si256(__m256i a) { - // CHECK: @llvm.x86.avx2.psll.dq + // CHECK: shufflevector <32 x i8> zeroinitializer, <32 x i8> %{{.*}}, <32 x i32> <i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60> return _mm256_slli_si256(a, 3); } +__m256i test_mm256_bslli_epi128(__m256i a) { + // CHECK: shufflevector <32 x i8> zeroinitializer, <32 x i8> %{{.*}}, <32 x i32> <i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60> + return _mm256_bslli_epi128(a, 3); +} + __m256i test_mm256_slli_epi16(__m256i a) { // CHECK: @llvm.x86.avx2.pslli.w return _mm256_slli_epi16(a, 3); @@ -517,10 +522,15 @@ __m256i test_mm256_sra_epi32(__m256i a, __m128i b) { } __m256i test_mm256_srli_si256(__m256i a) { - // CHECK: @llvm.x86.avx2.psrl.dq + // CHECK: shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50> return _mm256_srli_si256(a, 3); } +__m256i test_mm256_bsrli_epi128(__m256i a) { + // CHECK: shufflevector <32 x i8> %{{.*}}, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50> + return _mm256_bsrli_epi128(a, 3); +} + __m256i test_mm256_srli_epi16(__m256i a) { // CHECK: @llvm.x86.avx2.psrli.w return _mm256_srli_epi16(a, 3); @@ -601,6 +611,11 @@ __m128 test_mm_broadcastss_ps(__m128 a) { return _mm_broadcastss_ps(a); } +__m128d test_mm_broadcastsd_pd(__m128d a) { + // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x i32> zeroinitializer + return _mm_broadcastsd_pd(a); +} + __m256 test_mm256_broadcastss_ps(__m128 a) { // CHECK: @llvm.x86.avx2.vbroadcast.ss.ps.256 return _mm256_broadcastss_ps(a); @@ -612,7 +627,7 @@ __m256d test_mm256_broadcastsd_pd(__m128d a) { } __m256i test_mm256_broadcastsi128_si256(__m128i a) { - // CHECK: @llvm.x86.avx2.vbroadcasti128 + // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 0, i32 1> return _mm256_broadcastsi128_si256(a); } @@ -695,16 +710,44 @@ __m256i test_mm256_permute2x128_si256(__m256i a, __m256i b) { return _mm256_permute2x128_si256(a, b, 0x31); } -__m128i test_mm256_extracti128_si256(__m256i a) { - // CHECK: @llvm.x86.avx2.vextracti128 +__m128i test_mm256_extracti128_si256_0(__m256i a) { + // CHECK-LABEL: @test_mm256_extracti128_si256_0 + // CHECK: shufflevector{{.*}}<i32 0, i32 1> + return _mm256_extracti128_si256(a, 0); +} + +__m128i test_mm256_extracti128_si256_1(__m256i a) { + // CHECK-LABEL: @test_mm256_extracti128_si256_1 + // CHECK: shufflevector{{.*}}<i32 2, i32 3> return _mm256_extracti128_si256(a, 1); } -__m256i test_mm256_inserti128_si256(__m256i a, __m128i b) { - // CHECK: @llvm.x86.avx2.vinserti128 +// Immediate should be truncated to one bit. +__m128i test_mm256_extracti128_si256_2(__m256i a) { + // CHECK-LABEL: @test_mm256_extracti128_si256_2 + // CHECK: shufflevector{{.*}}<i32 0, i32 1> + return _mm256_extracti128_si256(a, 2); +} + +__m256i test_mm256_inserti128_si256_0(__m256i a, __m128i b) { + // CHECK-LABEL: @test_mm256_inserti128_si256_0 + // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 2, i32 3> + return _mm256_inserti128_si256(a, b, 0); +} + +__m256i test_mm256_inserti128_si256_1(__m256i a, __m128i b) { + // CHECK-LABEL: @test_mm256_inserti128_si256_1 + // CHECK: shufflevector{{.*}}<i32 0, i32 1, i32 4, i32 5> return _mm256_inserti128_si256(a, b, 1); } +// Immediate should be truncated to one bit. +__m256i test_mm256_inserti128_si256_2(__m256i a, __m128i b) { + // CHECK-LABEL: @test_mm256_inserti128_si256_2 + // CHECK: shufflevector{{.*}}<i32 4, i32 5, i32 2, i32 3> + return _mm256_inserti128_si256(a, b, 2); +} + __m256i test_mm256_maskload_epi32(int const *a, __m256i m) { // CHECK: @llvm.x86.avx2.maskload.d.256 return _mm256_maskload_epi32(a, m); diff --git a/test/CodeGen/avx512bw-builtins.c b/test/CodeGen/avx512bw-builtins.c index ada84657a607..452d737beaa2 100644 --- a/test/CodeGen/avx512bw-builtins.c +++ b/test/CodeGen/avx512bw-builtins.c @@ -25,3 +25,405 @@ __mmask32 test_mm512_mask_cmpeq_epi16_mask(__mmask32 __u, __m512i __a, __m512i _ // CHECK: @llvm.x86.avx512.mask.pcmpeq.w.512 return (__mmask32)_mm512_mask_cmpeq_epi16_mask(__u, __a, __b); } + +__mmask64 test_mm512_cmpgt_epi8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.b.512 + return (__mmask64)_mm512_cmpgt_epi8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmpgt_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.b.512 + return (__mmask64)_mm512_mask_cmpgt_epi8_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmpgt_epi16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.w.512 + return (__mmask32)_mm512_cmpgt_epi16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmpgt_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.w.512 + return (__mmask32)_mm512_mask_cmpgt_epi16_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmpeq_epu8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpeq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 0, i64 -1) + return (__mmask64)_mm512_cmpeq_epu8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmpeq_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpeq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 0, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmpeq_epu8_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmpeq_epu16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpeq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 0, i32 -1) + return (__mmask32)_mm512_cmpeq_epu16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmpeq_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpeq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 0, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmpeq_epu16_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmpgt_epu8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 6, i64 -1) + return (__mmask64)_mm512_cmpgt_epu8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmpgt_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 6, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmpgt_epu8_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmpgt_epu16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 6, i32 -1) + return (__mmask32)_mm512_cmpgt_epu16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmpgt_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 6, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmpgt_epu16_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmpge_epi8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 5, i64 -1) + return (__mmask64)_mm512_cmpge_epi8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmpge_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 5, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmpge_epi8_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmpge_epu8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 5, i64 -1) + return (__mmask64)_mm512_cmpge_epu8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmpge_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 5, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmpge_epu8_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmpge_epi16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 5, i32 -1) + return (__mmask32)_mm512_cmpge_epi16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmpge_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 5, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmpge_epi16_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmpge_epu16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 5, i32 -1) + return (__mmask32)_mm512_cmpge_epu16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmpge_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 5, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmpge_epu16_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmple_epi8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 2, i64 -1) + return (__mmask64)_mm512_cmple_epi8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmple_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 2, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmple_epi8_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmple_epu8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 2, i64 -1) + return (__mmask64)_mm512_cmple_epu8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmple_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 2, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmple_epu8_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmple_epi16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 2, i32 -1) + return (__mmask32)_mm512_cmple_epi16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmple_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 2, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmple_epi16_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmple_epu16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 2, i32 -1) + return (__mmask32)_mm512_cmple_epu16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmple_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 2, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmple_epu16_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmplt_epi8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 1, i64 -1) + return (__mmask64)_mm512_cmplt_epi8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmplt_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 1, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmplt_epi8_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmplt_epu8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 1, i64 -1) + return (__mmask64)_mm512_cmplt_epu8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmplt_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 1, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmplt_epu8_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmplt_epi16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 1, i32 -1) + return (__mmask32)_mm512_cmplt_epi16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmplt_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 1, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmplt_epi16_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmplt_epu16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 1, i32 -1) + return (__mmask32)_mm512_cmplt_epu16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmplt_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 1, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmplt_epu16_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmpneq_epi8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 4, i64 -1) + return (__mmask64)_mm512_cmpneq_epi8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmpneq_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 4, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmpneq_epi8_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmpneq_epu8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 4, i64 -1) + return (__mmask64)_mm512_cmpneq_epu8_mask(__a, __b); +} + +__mmask64 test_mm512_mask_cmpneq_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 4, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmpneq_epu8_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmpneq_epi16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 4, i32 -1) + return (__mmask32)_mm512_cmpneq_epi16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmpneq_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 4, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmpneq_epi16_mask(__u, __a, __b); +} + +__mmask32 test_mm512_cmpneq_epu16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 4, i32 -1) + return (__mmask32)_mm512_cmpneq_epu16_mask(__a, __b); +} + +__mmask32 test_mm512_mask_cmpneq_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 4, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmpneq_epu16_mask(__u, __a, __b); +} + +__mmask64 test_mm512_cmp_epi8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 7, i64 -1) + return (__mmask64)_mm512_cmp_epi8_mask(__a, __b, 7); +} + +__mmask64 test_mm512_mask_cmp_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 7, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmp_epi8_mask(__u, __a, __b, 7); +} + +__mmask64 test_mm512_cmp_epu8_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 7, i64 -1) + return (__mmask64)_mm512_cmp_epu8_mask(__a, __b, 7); +} + +__mmask64 test_mm512_mask_cmp_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> {{.*}}, <64 x i8> {{.*}}, i32 7, i64 {{.*}}) + return (__mmask64)_mm512_mask_cmp_epu8_mask(__u, __a, __b, 7); +} + +__mmask32 test_mm512_cmp_epi16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 7, i32 -1) + return (__mmask32)_mm512_cmp_epi16_mask(__a, __b, 7); +} + +__mmask32 test_mm512_mask_cmp_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 7, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmp_epi16_mask(__u, __a, __b, 7); +} + +__mmask32 test_mm512_cmp_epu16_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 7, i32 -1) + return (__mmask32)_mm512_cmp_epu16_mask(__a, __b, 7); +} + +__mmask32 test_mm512_mask_cmp_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16> {{.*}}, <32 x i16> {{.*}}, i32 7, i32 {{.*}}) + return (__mmask32)_mm512_mask_cmp_epu16_mask(__u, __a, __b, 7); +} + +__m512i test_mm512_add_epi8 (__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_add_epi8 + //CHECK: add <64 x i8> + return _mm512_add_epi8(__A,__B); +} + +__m512i test_mm512_mask_add_epi8 (__m512i __W, __mmask64 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_mask_add_epi8 + //CHECK: @llvm.x86.avx512.mask.padd.b.512 + return _mm512_mask_add_epi8(__W, __U, __A, __B); +} + +__m512i test_mm512_maskz_add_epi8 (__mmask64 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_add_epi8 + //CHECK: @llvm.x86.avx512.mask.padd.b.512 + return _mm512_maskz_add_epi8(__U, __A, __B); +} + +__m512i test_mm512_sub_epi8 (__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_sub_epi8 + //CHECK: sub <64 x i8> + return _mm512_sub_epi8(__A, __B); +} + +__m512i test_mm512_mask_sub_epi8 (__m512i __W, __mmask64 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_mask_sub_epi8 + //CHECK: @llvm.x86.avx512.mask.psub.b.512 + return _mm512_mask_sub_epi8(__W, __U, __A, __B); +} + +__m512i test_mm512_maskz_sub_epi8 (__mmask64 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_sub_epi8 + //CHECK: @llvm.x86.avx512.mask.psub.b.512 + return _mm512_maskz_sub_epi8(__U, __A, __B); +} + +__m512i test_mm512_add_epi16 (__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_add_epi16 + //CHECK: add <32 x i16> + return _mm512_add_epi16(__A, __B); +} + +__m512i test_mm512_mask_add_epi16 (__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_mask_add_epi16 + //CHECK: @llvm.x86.avx512.mask.padd.w.512 + return _mm512_mask_add_epi16(__W, __U, __A, __B); +} + +__m512i test_mm512_maskz_add_epi16 (__mmask32 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_add_epi16 + //CHECK: @llvm.x86.avx512.mask.padd.w.512 + return _mm512_maskz_add_epi16(__U, __A, __B); +} + +__m512i test_mm512_sub_epi16 (__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_sub_epi16 + //CHECK: sub <32 x i16> + return _mm512_sub_epi16(__A, __B); +} + +__m512i test_mm512_mask_sub_epi16 (__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_mask_sub_epi16 + //CHECK: @llvm.x86.avx512.mask.psub.w.512 + return _mm512_mask_sub_epi16(__W, __U, __A, __B); +} + +__m512i test_mm512_maskz_sub_epi16 (__mmask32 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_sub_epi16 + //CHECK: @llvm.x86.avx512.mask.psub.w.512 + return _mm512_maskz_sub_epi16(__U, __A, __B); +} + +__m512i test_mm512_mullo_epi16 (__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_mullo_epi16 + //CHECK: mul <32 x i16> + return _mm512_mullo_epi16(__A, __B); +} + +__m512i test_mm512_mask_mullo_epi16 (__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_mask_mullo_epi16 + //CHECK: @llvm.x86.avx512.mask.pmull.w.512 + return _mm512_mask_mullo_epi16(__W, __U, __A, __B); +} + +__m512i test_mm512_maskz_mullo_epi16 (__mmask32 __U, __m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_mullo_epi16 + //CHECK: @llvm.x86.avx512.mask.pmull.w.512 + return _mm512_maskz_mullo_epi16(__U, __A, __B); +} diff --git a/test/CodeGen/avx512dq-builtins.c b/test/CodeGen/avx512dq-builtins.c new file mode 100644 index 000000000000..e35b243534a4 --- /dev/null +++ b/test/CodeGen/avx512dq-builtins.c @@ -0,0 +1,164 @@ +// RUN: %clang_cc1 %s -O0 -triple=x86_64-apple-darwin -ffreestanding -target-feature +avx512dq -emit-llvm -o - -Werror | FileCheck %s + +#include <immintrin.h> +__m512i test_mm512_mullo_epi64 (__m512i __A, __m512i __B) { + // CHECK-LABEL: @test_mm512_mullo_epi64 + // CHECK: mul <8 x i64> + return (__m512i) ((__v8di) __A * (__v8di) __B); +} + +__m512i test_mm512_mask_mullo_epi64 (__m512i __W, __mmask8 __U, __m512i __A, __m512i __B) { + // CHECK-LABEL: @test_mm512_mask_mullo_epi64 + // CHECK: @llvm.x86.avx512.mask.pmull.q.512 + return (__m512i) _mm512_mask_mullo_epi64(__W, __U, __A, __B); +} + +__m512i test_mm512_maskz_mullo_epi64 (__mmask8 __U, __m512i __A, __m512i __B) { + // CHECK-LABEL: @test_mm512_maskz_mullo_epi64 + // CHECK: @llvm.x86.avx512.mask.pmull.q.512 + return (__m512i) _mm512_maskz_mullo_epi64(__U, __A, __B); +} + +__m512d test_mm512_xor_pd (__m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_xor_pd + // CHECK: xor <8 x i64> + return (__m512d) _mm512_xor_pd(__A, __B); +} + +__m512d test_mm512_mask_xor_pd (__m512d __W, __mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_mask_xor_pd + // CHECK: @llvm.x86.avx512.mask.xor.pd.512 + return (__m512d) _mm512_mask_xor_pd(__W, __U, __A, __B); +} + +__m512d test_mm512_maskz_xor_pd (__mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_maskz_xor_pd + // CHECK: @llvm.x86.avx512.mask.xor.pd.512 + return (__m512d) _mm512_maskz_xor_pd(__U, __A, __B); +} + +__m512 test_mm512_xor_ps (__m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_xor_ps + // CHECK: xor <16 x i32> + return (__m512) _mm512_xor_ps(__A, __B); +} + +__m512 test_mm512_mask_xor_ps (__m512 __W, __mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_mask_xor_ps + // CHECK: @llvm.x86.avx512.mask.xor.ps.512 + return (__m512) _mm512_mask_xor_ps(__W, __U, __A, __B); +} + +__m512 test_mm512_maskz_xor_ps (__mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_maskz_xor_ps + // CHECK: @llvm.x86.avx512.mask.xor.ps.512 + return (__m512) _mm512_maskz_xor_ps(__U, __A, __B); +} + +__m512d test_mm512_or_pd (__m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_or_pd + // CHECK: or <8 x i64> + return (__m512d) _mm512_or_pd(__A, __B); +} + +__m512d test_mm512_mask_or_pd (__m512d __W, __mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_mask_or_pd + // CHECK: @llvm.x86.avx512.mask.or.pd.512 + return (__m512d) _mm512_mask_or_pd(__W, __U, __A, __B); +} + +__m512d test_mm512_maskz_or_pd (__mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_maskz_or_pd + // CHECK: @llvm.x86.avx512.mask.or.pd.512 + return (__m512d) _mm512_maskz_or_pd(__U, __A, __B); +} + +__m512 test_mm512_or_ps (__m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_or_ps + // CHECK: or <16 x i32> + return (__m512) _mm512_or_ps(__A, __B); +} + +__m512 test_mm512_mask_or_ps (__m512 __W, __mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_mask_or_ps + // CHECK: @llvm.x86.avx512.mask.or.ps.512 + return (__m512) _mm512_mask_or_ps(__W, __U, __A, __B); +} + +__m512 test_mm512_maskz_or_ps (__mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_maskz_or_ps + // CHECK: @llvm.x86.avx512.mask.or.ps.512 + return (__m512) _mm512_maskz_or_ps(__U, __A, __B); +} + +__m512d test_mm512_and_pd (__m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_and_pd + // CHECK: and <8 x i64> + return (__m512d) _mm512_and_pd(__A, __B); +} + +__m512d test_mm512_mask_and_pd (__m512d __W, __mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_mask_and_pd + // CHECK: @llvm.x86.avx512.mask.and.pd.512 + return (__m512d) _mm512_mask_and_pd(__W, __U, __A, __B); +} + +__m512d test_mm512_maskz_and_pd (__mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_maskz_and_pd + // CHECK: @llvm.x86.avx512.mask.and.pd.512 + return (__m512d) _mm512_maskz_and_pd(__U, __A, __B); +} + +__m512 test_mm512_and_ps (__m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_and_ps + // CHECK: and <16 x i32> + return (__m512) _mm512_and_ps(__A, __B); +} + +__m512 test_mm512_mask_and_ps (__m512 __W, __mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_mask_and_ps + // CHECK: @llvm.x86.avx512.mask.and.ps.512 + return (__m512) _mm512_mask_and_ps(__W, __U, __A, __B); +} + +__m512 test_mm512_maskz_and_ps (__mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_maskz_and_ps + // CHECK: @llvm.x86.avx512.mask.and.ps.512 + return (__m512) _mm512_maskz_and_ps(__U, __A, __B); +} + +__m512d test_mm512_andnot_pd (__m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_andnot_pd + // CHECK: @llvm.x86.avx512.mask.andn.pd.512 + return (__m512d) _mm512_andnot_pd(__A, __B); +} + +__m512d test_mm512_mask_andnot_pd (__m512d __W, __mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_mask_andnot_pd + // CHECK: @llvm.x86.avx512.mask.andn.pd.512 + return (__m512d) _mm512_mask_andnot_pd(__W, __U, __A, __B); +} + +__m512d test_mm512_maskz_andnot_pd (__mmask8 __U, __m512d __A, __m512d __B) { + // CHECK-LABEL: @test_mm512_maskz_andnot_pd + // CHECK: @llvm.x86.avx512.mask.andn.pd.512 + return (__m512d) _mm512_maskz_andnot_pd(__U, __A, __B); +} + +__m512 test_mm512_andnot_ps (__m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_andnot_ps + // CHECK: @llvm.x86.avx512.mask.andn.ps.512 + return (__m512) _mm512_andnot_ps(__A, __B); +} + +__m512 test_mm512_mask_andnot_ps (__m512 __W, __mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_mask_andnot_ps + // CHECK: @llvm.x86.avx512.mask.andn.ps.512 + return (__m512) _mm512_mask_andnot_ps(__W, __U, __A, __B); +} + +__m512 test_mm512_maskz_andnot_ps (__mmask16 __U, __m512 __A, __m512 __B) { + // CHECK-LABEL: @test_mm512_maskz_andnot_ps + // CHECK: @llvm.x86.avx512.mask.andn.ps.512 + return (__m512) _mm512_maskz_andnot_ps(__U, __A, __B); +} diff --git a/test/CodeGen/avx512er-builtins.c b/test/CodeGen/avx512er-builtins.c new file mode 100644 index 000000000000..993f177a1168 --- /dev/null +++ b/test/CodeGen/avx512er-builtins.c @@ -0,0 +1,346 @@ +// RUN: %clang_cc1 %s -O0 -triple=x86_64-apple-darwin -ffreestanding -target-feature +avx512f -target-feature +avx512er -emit-llvm -o - -Werror | FileCheck %s + +#include <immintrin.h> + +__m512d test_mm512_rsqrt28_round_pd(__m512d a) { + // CHECK-LABEL: @test_mm512_rsqrt28_round_pd + // CHECK: @llvm.x86.avx512.rsqrt28.pd + return _mm512_rsqrt28_round_pd(a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m, __m512d a) { + // check-label: @test_mm512_mask_rsqrt28_round_pd + // check: @llvm.x86.avx512.rsqrt28.pd + return _mm512_mask_rsqrt28_round_pd(s, m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_maskz_rsqrt28_round_pd(__mmask8 m, __m512d a) { + // check-label: @test_mm512_maskz_rsqrt28_round_pd + // check: @llvm.x86.avx512.rsqrt28.pd + return _mm512_maskz_rsqrt28_round_pd(m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_rsqrt28_pd(__m512d a) { + // CHECK-LABEL: @test_mm512_rsqrt28_pd + // CHECK: @llvm.x86.avx512.rsqrt28.pd + return _mm512_rsqrt28_pd(a); +} + +__m512d test_mm512_mask_rsqrt28_pd(__m512d s, __mmask8 m, __m512d a) { + // check-label: @test_mm512_mask_rsqrt28_pd + // check: @llvm.x86.avx512.rsqrt28.pd + return _mm512_mask_rsqrt28_pd(s, m, a); +} + +__m512d test_mm512_maskz_rsqrt28_pd(__mmask8 m, __m512d a) { + // check-label: @test_mm512_maskz_rsqrt28_pd + // check: @llvm.x86.avx512.rsqrt28.pd + return _mm512_maskz_rsqrt28_pd(m, a); +} + +__m512 test_mm512_rsqrt28_round_ps(__m512 a) { + // CHECK-LABEL: @test_mm512_rsqrt28_round_ps + // CHECK: @llvm.x86.avx512.rsqrt28.ps + return _mm512_rsqrt28_round_ps(a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_mask_rsqrt28_round_ps(__m512 s, __mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_mask_rsqrt28_round_ps + // CHECK: @llvm.x86.avx512.rsqrt28.ps + return _mm512_mask_rsqrt28_round_ps(s, m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_maskz_rsqrt28_round_ps(__mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_maskz_rsqrt28_round_ps + // CHECK: @llvm.x86.avx512.rsqrt28.ps + return _mm512_maskz_rsqrt28_round_ps(m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_rsqrt28_ps(__m512 a) { + // CHECK-LABEL: @test_mm512_rsqrt28_ps + // CHECK: @llvm.x86.avx512.rsqrt28.ps + return _mm512_rsqrt28_ps(a); +} + +__m512 test_mm512_mask_rsqrt28_ps(__m512 s, __mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_mask_rsqrt28_ps + // CHECK: @llvm.x86.avx512.rsqrt28.ps + return _mm512_mask_rsqrt28_ps(s, m, a); +} + +__m512 test_mm512_maskz_rsqrt28_ps(__mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_maskz_rsqrt28_ps + // CHECK: @llvm.x86.avx512.rsqrt28.ps + return _mm512_maskz_rsqrt28_ps(m, a); +} + +__m128 test_mm_rsqrt28_round_ss(__m128 a, __m128 b) { + // check-label: @test_mm_rsqrt28_round_ss + // check: @llvm.x86.avx512.rsqrt28.ss + return _mm_rsqrt28_round_ss(a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128 test_mm_mask_rsqrt28_round_ss(__m128 s, __mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_mask_rsqrt28_round_ss + // check: @llvm.x86.avx512.rsqrt28.ss + return _mm_mask_rsqrt28_round_ss(s, m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128 test_mm_maskz_rsqrt28_round_ss(__mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_maskz_rsqrt28_round_ss + // check: @llvm.x86.avx512.rsqrt28.ss + return _mm_maskz_rsqrt28_round_ss(m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128 test_mm_rsqrt28_ss(__m128 a, __m128 b) { + // check-label: @test_mm_rsqrt28_ss + // check: @llvm.x86.avx512.rsqrt28.ss + return _mm_rsqrt28_ss(a, b); +} + +__m128 test_mm_mask_rsqrt28_ss(__m128 s, __mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_mask_rsqrt28_ss + // check: @llvm.x86.avx512.rsqrt28.ss + return _mm_mask_rsqrt28_ss(s, m, a, b); +} + +__m128 test_mm_maskz_rsqrt28_ss(__mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_maskz_rsqrt28_ss + // check: @llvm.x86.avx512.rsqrt28.ss + return _mm_maskz_rsqrt28_ss(m, a, b); +} + +__m128d test_mm_rsqrt28_round_sd(__m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_rsqrt28_round_sd + // CHECK: @llvm.x86.avx512.rsqrt28.sd + return _mm_rsqrt28_round_sd(a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128d test_mm_mask_rsqrt28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_mask_rsqrt28_round_sd + // CHECK: @llvm.x86.avx512.rsqrt28.sd + return _mm_mask_rsqrt28_round_sd(s, m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128d test_mm_maskz_rsqrt28_round_sd(__mmask8 m, __m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_maskz_rsqrt28_round_sd + // CHECK: @llvm.x86.avx512.rsqrt28.sd + return _mm_maskz_rsqrt28_round_sd(m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_rcp28_round_pd(__m512d a) { + // CHECK-LABEL: @test_mm512_rcp28_round_pd + // CHECK: @llvm.x86.avx512.rcp28.pd + return _mm512_rcp28_round_pd(a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_mask_rcp28_round_pd(__m512d s, __mmask8 m, __m512d a) { + // check-label: @test_mm512_mask_rcp28_round_pd + // check: @llvm.x86.avx512.rcp28.pd + return _mm512_mask_rcp28_round_pd(s, m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_maskz_rcp28_round_pd(__mmask8 m, __m512d a) { + // check-label: @test_mm512_maskz_rcp28_round_pd + // check: @llvm.x86.avx512.rcp28.pd + return _mm512_maskz_rcp28_round_pd(m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_rcp28_pd(__m512d a) { + // CHECK-LABEL: @test_mm512_rcp28_pd + // CHECK: @llvm.x86.avx512.rcp28.pd + return _mm512_rcp28_pd(a); +} + +__m512d test_mm512_mask_rcp28_pd(__m512d s, __mmask8 m, __m512d a) { + // check-label: @test_mm512_mask_rcp28_pd + // check: @llvm.x86.avx512.rcp28.pd + return _mm512_mask_rcp28_pd(s, m, a); +} + +__m512d test_mm512_maskz_rcp28_pd(__mmask8 m, __m512d a) { + // check-label: @test_mm512_maskz_rcp28_pd + // check: @llvm.x86.avx512.rcp28.pd + return _mm512_maskz_rcp28_pd(m, a); +} + +__m512 test_mm512_rcp28_round_ps(__m512 a) { + // CHECK-LABEL: @test_mm512_rcp28_round_ps + // CHECK: @llvm.x86.avx512.rcp28.ps + return _mm512_rcp28_round_ps(a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_mask_rcp28_round_ps + // CHECK: @llvm.x86.avx512.rcp28.ps + return _mm512_mask_rcp28_round_ps(s, m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_maskz_rcp28_round_ps(__mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_maskz_rcp28_round_ps + // CHECK: @llvm.x86.avx512.rcp28.ps + return _mm512_maskz_rcp28_round_ps(m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_rcp28_ps(__m512 a) { + // CHECK-LABEL: @test_mm512_rcp28_ps + // CHECK: @llvm.x86.avx512.rcp28.ps + return _mm512_rcp28_ps(a); +} + +__m512 test_mm512_mask_rcp28_ps(__m512 s, __mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_mask_rcp28_ps + // CHECK: @llvm.x86.avx512.rcp28.ps + return _mm512_mask_rcp28_ps(s, m, a); +} + +__m512 test_mm512_maskz_rcp28_ps(__mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_maskz_rcp28_ps + // CHECK: @llvm.x86.avx512.rcp28.ps + return _mm512_maskz_rcp28_ps(m, a); +} + +__m128 test_mm_rcp28_round_ss(__m128 a, __m128 b) { + // check-label: @test_mm_rcp28_round_ss + // check: @llvm.x86.avx512.rcp28.ss + return _mm_rcp28_round_ss(a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128 test_mm_mask_rcp28_round_ss(__m128 s, __mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_mask_rcp28_round_ss + // check: @llvm.x86.avx512.rcp28.ss + return _mm_mask_rcp28_round_ss(s, m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128 test_mm_maskz_rcp28_round_ss(__mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_maskz_rcp28_round_ss + // check: @llvm.x86.avx512.rcp28.ss + return _mm_maskz_rcp28_round_ss(m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128 test_mm_rcp28_ss(__m128 a, __m128 b) { + // check-label: @test_mm_rcp28_ss + // check: @llvm.x86.avx512.rcp28.ss + return _mm_rcp28_ss(a, b); +} + +__m128 test_mm_mask_rcp28_ss(__m128 s, __mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_mask_rcp28_ss + // check: @llvm.x86.avx512.rcp28.ss + return _mm_mask_rcp28_ss(s, m, a, b); +} + +__m128 test_mm_maskz_rcp28_ss(__mmask16 m, __m128 a, __m128 b) { + // check-label: @test_mm_maskz_rcp28_ss + // check: @llvm.x86.avx512.rcp28.ss + return _mm_maskz_rcp28_ss(m, a, b); +} + +__m128d test_mm_rcp28_round_sd(__m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_rcp28_round_sd + // CHECK: @llvm.x86.avx512.rcp28.sd + return _mm_rcp28_round_sd(a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128d test_mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_mask_rcp28_round_sd + // CHECK: @llvm.x86.avx512.rcp28.sd + return _mm_mask_rcp28_round_sd(s, m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128d test_mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_maskz_rcp28_round_sd + // CHECK: @llvm.x86.avx512.rcp28.sd + return _mm_maskz_rcp28_round_sd(m, a, b, _MM_FROUND_TO_NEAREST_INT); +} + +__m128d test_mm_rcp28_sd(__m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_rcp28_sd + // CHECK: @llvm.x86.avx512.rcp28.sd + return _mm_rcp28_sd(a, b); +} + +__m128d test_mm_mask_rcp28_sd(__m128d s, __mmask8 m, __m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_mask_rcp28_sd + // CHECK: @llvm.x86.avx512.rcp28.sd + return _mm_mask_rcp28_sd(s, m, a, b); +} + +__m128d test_mm_maskz_rcp28_sd(__mmask8 m, __m128d a, __m128d b) { + // CHECK-LABEL: @test_mm_maskz_rcp28_sd + // CHECK: @llvm.x86.avx512.rcp28.sd + return _mm_maskz_rcp28_sd(m, a, b); +} + +__m512d test_mm512_exp2a23_round_pd(__m512d a) { + // CHECK-LABEL: @test_mm512_exp2a23_round_pd + // CHECK: @llvm.x86.avx512.exp2.pd + return _mm512_exp2a23_round_pd(a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_mask_exp2a23_round_pd(__m512d s, __mmask8 m, __m512d a) { + // check-label: @test_mm512_mask_exp2a23_round_pd + // check: @llvm.x86.avx512.exp2.pd + return _mm512_mask_exp2a23_round_pd(s, m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_maskz_exp2a23_round_pd(__mmask8 m, __m512d a) { + // check-label: @test_mm512_maskz_exp2a23_round_pd + // check: @llvm.x86.avx512.exp2.pd + return _mm512_maskz_exp2a23_round_pd(m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512d test_mm512_exp2a23_pd(__m512d a) { + // CHECK-LABEL: @test_mm512_exp2a23_pd + // CHECK: @llvm.x86.avx512.exp2.pd + return _mm512_exp2a23_pd(a); +} + +__m512d test_mm512_mask_exp2a23_pd(__m512d s, __mmask8 m, __m512d a) { + // check-label: @test_mm512_mask_exp2a23_pd + // check: @llvm.x86.avx512.exp2.pd + return _mm512_mask_exp2a23_pd(s, m, a); +} + +__m512d test_mm512_maskz_exp2a23_pd(__mmask8 m, __m512d a) { + // check-label: @test_mm512_maskz_exp2a23_pd + // check: @llvm.x86.avx512.exp2.pd + return _mm512_maskz_exp2a23_pd(m, a); +} + +__m512 test_mm512_exp2a23_round_ps(__m512 a) { + // CHECK-LABEL: @test_mm512_exp2a23_round_ps + // CHECK: @llvm.x86.avx512.exp2.ps + return _mm512_exp2a23_round_ps(a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_mask_exp2a23_round_ps(__m512 s, __mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_mask_exp2a23_round_ps + // CHECK: @llvm.x86.avx512.exp2.ps + return _mm512_mask_exp2a23_round_ps(s, m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_maskz_exp2a23_round_ps(__mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_maskz_exp2a23_round_ps + // CHECK: @llvm.x86.avx512.exp2.ps + return _mm512_maskz_exp2a23_round_ps(m, a, _MM_FROUND_TO_NEAREST_INT); +} + +__m512 test_mm512_exp2a23_ps(__m512 a) { + // CHECK-LABEL: @test_mm512_exp2a23_ps + // CHECK: @llvm.x86.avx512.exp2.ps + return _mm512_exp2a23_ps(a); +} + +__m512 test_mm512_mask_exp2a23_ps(__m512 s, __mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_mask_exp2a23_ps + // CHECK: @llvm.x86.avx512.exp2.ps + return _mm512_mask_exp2a23_ps(s, m, a); +} + +__m512 test_mm512_maskz_exp2a23_ps(__mmask16 m, __m512 a) { + // CHECK-LABEL: @test_mm512_maskz_exp2a23_ps + // CHECK: @llvm.x86.avx512.exp2.ps + return _mm512_maskz_exp2a23_ps(m, a); +} + diff --git a/test/CodeGen/avx512f-builtins.c b/test/CodeGen/avx512f-builtins.c index 8bb013fef731..2f19f99e4f25 100644 --- a/test/CodeGen/avx512f-builtins.c +++ b/test/CodeGen/avx512f-builtins.c @@ -75,6 +75,13 @@ void test_mm512_storeu_pd(void *p, __m512d a) _mm512_storeu_pd(p, a); } +void test_mm512_mask_store_ps(void *p, __m512 a, __mmask16 m) +{ + // CHECK-LABEL: @test_mm512_mask_store_ps + // CHECK: @llvm.x86.avx512.mask.store.ps.512 + _mm512_mask_store_ps(p, m, a); +} + void test_mm512_store_ps(void *p, __m512 a) { // CHECK-LABEL: @test_mm512_store_ps @@ -82,6 +89,13 @@ void test_mm512_store_ps(void *p, __m512 a) _mm512_store_ps(p, a); } +void test_mm512_mask_store_pd(void *p, __m512d a, __mmask8 m) +{ + // CHECK-LABEL: @test_mm512_mask_store_pd + // CHECK: @llvm.x86.avx512.mask.store.pd.512 + _mm512_mask_store_pd(p, m, a); +} + void test_mm512_store_pd(void *p, __m512d a) { // CHECK-LABEL: @test_mm512_store_pd @@ -92,17 +106,45 @@ void test_mm512_store_pd(void *p, __m512d a) __m512 test_mm512_loadu_ps(void *p) { // CHECK-LABEL: @test_mm512_loadu_ps - // CHECK: load <16 x float>* {{.*}}, align 1{{$}} + // CHECK: load <16 x float>, <16 x float>* {{.*}}, align 1{{$}} return _mm512_loadu_ps(p); } __m512d test_mm512_loadu_pd(void *p) { // CHECK-LABEL: @test_mm512_loadu_pd - // CHECK: load <8 x double>* {{.*}}, align 1{{$}} + // CHECK: load <8 x double>, <8 x double>* {{.*}}, align 1{{$}} return _mm512_loadu_pd(p); } +__m512 test_mm512_maskz_load_ps(void *p, __mmask16 m) +{ + // CHECK-LABEL: @test_mm512_maskz_load_ps + // CHECK: @llvm.x86.avx512.mask.load.ps.512 + return _mm512_maskz_load_ps(m, p); +} + +__m512 test_mm512_load_ps(void *p) +{ + // CHECK-LABEL: @test_mm512_load_ps + // CHECK: @llvm.x86.avx512.mask.load.ps.512 + return _mm512_load_ps(p); +} + +__m512d test_mm512_maskz_load_pd(void *p, __mmask8 m) +{ + // CHECK-LABEL: @test_mm512_maskz_load_pd + // CHECK: @llvm.x86.avx512.mask.load.pd.512 + return _mm512_maskz_load_pd(m, p); +} + +__m512d test_mm512_load_pd(void *p) +{ + // CHECK-LABEL: @test_mm512_load_pd + // CHECK: @llvm.x86.avx512.mask.load.pd.512 + return _mm512_load_pd(p); +} + __m512d test_mm512_set1_pd(double d) { // CHECK-LABEL: @test_mm512_set1_pd @@ -131,11 +173,18 @@ __mmask16 test_mm512_knot(__mmask16 a) return _mm512_knot(a); } -__m512i test_mm512_valign_epi64(__m512i a, __m512i b) +__m512i test_mm512_alignr_epi32(__m512i a, __m512i b) { - // CHECK-LABEL: @test_mm512_valign_epi64 + // CHECK-LABEL: @test_mm512_alignr_epi32 + // CHECK: @llvm.x86.avx512.mask.valign.d.512 + return _mm512_alignr_epi32(a, b, 2); +} + +__m512i test_mm512_alignr_epi64(__m512i a, __m512i b) +{ + // CHECK-LABEL: @test_mm512_alignr_epi64 // CHECK: @llvm.x86.avx512.mask.valign.q.512 - return _mm512_valign_epi64(a, b, 2); + return _mm512_alignr_epi64(a, b, 2); } __m512d test_mm512_broadcastsd_pd(__m128d a) @@ -183,6 +232,30 @@ __mmask8 test_mm512_cmpeq_epi64_mask(__m512i __a, __m512i __b) { return (__mmask8)_mm512_cmpeq_epi64_mask(__a, __b); } +__mmask16 test_mm512_cmpgt_epi32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.d.512 + return (__mmask16)_mm512_cmpgt_epi32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmpgt_epi32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.d.512 + return (__mmask16)_mm512_mask_cmpgt_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_mask_cmpgt_epi64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.q.512 + return (__mmask8)_mm512_mask_cmpgt_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmpgt_epi64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.q.512 + return (__mmask8)_mm512_cmpgt_epi64_mask(__a, __b); +} + __m512d test_mm512_unpackhi_pd(__m512d a, __m512d b) { // CHECK-LABEL: @test_mm512_unpackhi_pd @@ -197,16 +270,632 @@ __m512d test_mm512_unpacklo_pd(__m512d a, __m512d b) return _mm512_unpacklo_pd(a, b); } -__m512d test_mm512_unpackhi_ps(__m512d a, __m512d b) +__m512 test_mm512_unpackhi_ps(__m512 a, __m512 b) { // CHECK-LABEL: @test_mm512_unpackhi_ps // CHECK: shufflevector <16 x float> {{.*}} <i32 2, i32 18, i32 3, i32 19, i32 6, i32 22, i32 7, i32 23, i32 10, i32 26, i32 11, i32 27, i32 14, i32 30, i32 15, i32 31> return _mm512_unpackhi_ps(a, b); } -__m512d test_mm512_unpacklo_ps(__m512d a, __m512d b) +__m512 test_mm512_unpacklo_ps(__m512 a, __m512 b) { // CHECK-LABEL: @test_mm512_unpacklo_ps // CHECK: shufflevector <16 x float> {{.*}} <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29> return _mm512_unpacklo_ps(a, b); } + +__mmask16 test_mm512_cmp_round_ps_mask(__m512 a, __m512 b) { + // CHECK-LABEL: @test_mm512_cmp_round_ps_mask + // CHECK: @llvm.x86.avx512.mask.cmp.ps.512 + return _mm512_cmp_round_ps_mask(a, b, 0, _MM_FROUND_TO_NEAREST_INT); +} + +__mmask16 test_mm512_mask_cmp_round_ps_mask(__mmask16 m, __m512 a, __m512 b) { + // CHECK-LABEL: @test_mm512_mask_cmp_round_ps_mask + // CHECK: @llvm.x86.avx512.mask.cmp.ps.512 + return _mm512_mask_cmp_round_ps_mask(m, a, b, 0, _MM_FROUND_TO_NEAREST_INT); +} + +__mmask16 test_mm512_cmp_ps_mask(__m512 a, __m512 b) { + // check-label: @test_mm512_cmp_ps_mask + // check: @llvm.x86.avx512.mask.cmp.ps.512 + return _mm512_cmp_ps_mask(a, b, 0); +} + +__mmask16 test_mm512_mask_cmp_ps_mask(__mmask16 m, __m512 a, __m512 b) { + // CHECK-LABEL: @test_mm512_mask_cmp_ps_mask + // CHECK: @llvm.x86.avx512.mask.cmp.ps.512 + return _mm512_mask_cmp_ps_mask(m, a, b, 0); +} + +__mmask8 test_mm512_cmp_round_pd_mask(__m512d a, __m512d b) { + // CHECK-LABEL: @test_mm512_cmp_round_pd_mask + // CHECK: @llvm.x86.avx512.mask.cmp.pd.512 + return _mm512_cmp_round_pd_mask(a, b, 0, _MM_FROUND_TO_NEAREST_INT); +} + +__mmask8 test_mm512_mask_cmp_round_pd_mask(__mmask8 m, __m512d a, __m512d b) { + // CHECK-LABEL: @test_mm512_mask_cmp_round_pd_mask + // CHECK: @llvm.x86.avx512.mask.cmp.pd.512 + return _mm512_mask_cmp_round_pd_mask(m, a, b, 0, _MM_FROUND_TO_NEAREST_INT); +} + +__mmask8 test_mm512_cmp_pd_mask(__m512d a, __m512d b) { + // check-label: @test_mm512_cmp_pd_mask + // check: @llvm.x86.avx512.mask.cmp.pd.512 + return _mm512_cmp_pd_mask(a, b, 0); +} + +__mmask8 test_mm512_mask_cmp_pd_mask(__mmask8 m, __m512d a, __m512d b) { + // CHECK-LABEL: @test_mm512_mask_cmp_pd_mask + // CHECK: @llvm.x86.avx512.mask.cmp.pd.512 + return _mm512_mask_cmp_pd_mask(m, a, b, 0); +} + +__m256d test_mm512_extractf64x4_pd(__m512d a) +{ + // CHECK-LABEL: @test_mm512_extractf64x4_pd + // CHECK: @llvm.x86.avx512.mask.vextractf64x4.512 + return _mm512_extractf64x4_pd(a, 1); +} + +__m128 test_mm512_extractf32x4_ps(__m512 a) +{ + // CHECK-LABEL: @test_mm512_extractf32x4_ps + // CHECK: @llvm.x86.avx512.mask.vextractf32x4.512 + return _mm512_extractf32x4_ps(a, 1); +} + +__mmask16 test_mm512_cmpeq_epu32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpeq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 0, i16 -1) + return (__mmask16)_mm512_cmpeq_epu32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmpeq_epu32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpeq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 0, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmpeq_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmpeq_epu64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpeq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 0, i8 -1) + return (__mmask8)_mm512_cmpeq_epu64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmpeq_epu64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpeq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 0, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmpeq_epu64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmpge_epi32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 5, i16 -1) + return (__mmask16)_mm512_cmpge_epi32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmpge_epi32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 5, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmpge_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmpge_epi64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm512_cmpge_epi64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmpge_epi64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmpge_epi64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmpge_epu32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 5, i16 -1) + return (__mmask16)_mm512_cmpge_epu32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmpge_epu32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 5, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmpge_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmpge_epu64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpge_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm512_cmpge_epu64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmpge_epu64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpge_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmpge_epu64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmpgt_epu32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 6, i16 -1) + return (__mmask16)_mm512_cmpgt_epu32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmpgt_epu32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 6, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmpgt_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmpgt_epu64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpgt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 6, i8 -1) + return (__mmask8)_mm512_cmpgt_epu64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmpgt_epu64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpgt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 6, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmpgt_epu64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmple_epi32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 2, i16 -1) + return (__mmask16)_mm512_cmple_epi32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmple_epi32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 2, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmple_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmple_epi64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm512_cmple_epi64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmple_epi64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmple_epi64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmple_epu32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 2, i16 -1) + return (__mmask16)_mm512_cmple_epu32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmple_epu32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 2, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmple_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmple_epu64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmple_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm512_cmple_epu64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmple_epu64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmple_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmple_epu64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmplt_epi32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 1, i16 -1) + return (__mmask16)_mm512_cmplt_epi32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmplt_epi32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 1, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmplt_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmplt_epi64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm512_cmplt_epi64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmplt_epi64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmplt_epi64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmplt_epu32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 1, i16 -1) + return (__mmask16)_mm512_cmplt_epu32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmplt_epu32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 1, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmplt_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmplt_epu64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmplt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm512_cmplt_epu64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmplt_epu64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmplt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmplt_epu64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmpneq_epi32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 4, i16 -1) + return (__mmask16)_mm512_cmpneq_epi32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmpneq_epi32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 4, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmpneq_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmpneq_epi64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm512_cmpneq_epi64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmpneq_epi64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmpneq_epi64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmpneq_epu32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 4, i16 -1) + return (__mmask16)_mm512_cmpneq_epu32_mask(__a, __b); +} + +__mmask16 test_mm512_mask_cmpneq_epu32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 4, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmpneq_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm512_cmpneq_epu64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmpneq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm512_cmpneq_epu64_mask(__a, __b); +} + +__mmask8 test_mm512_mask_cmpneq_epu64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmpneq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmpneq_epu64_mask(__u, __a, __b); +} + +__mmask16 test_mm512_cmp_epi32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 3, i16 -1) + return (__mmask16)_mm512_cmp_epi32_mask(__a, __b, 3); +} + +__mmask16 test_mm512_mask_cmp_epi32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 3, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmp_epi32_mask(__u, __a, __b, 3); +} + +__mmask8 test_mm512_cmp_epi64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 3, i8 -1) + return (__mmask8)_mm512_cmp_epi64_mask(__a, __b, 3); +} + +__mmask8 test_mm512_mask_cmp_epi64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 3, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmp_epi64_mask(__u, __a, __b, 3); +} + +__mmask16 test_mm512_cmp_epu32_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 3, i16 -1) + return (__mmask16)_mm512_cmp_epu32_mask(__a, __b, 3); +} + +__mmask16 test_mm512_mask_cmp_epu32_mask(__mmask16 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.512(<16 x i32> {{.*}}, <16 x i32> {{.*}}, i32 3, i16 {{.*}}) + return (__mmask16)_mm512_mask_cmp_epu32_mask(__u, __a, __b, 3); +} + +__mmask8 test_mm512_cmp_epu64_mask(__m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_cmp_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 3, i8 -1) + return (__mmask8)_mm512_cmp_epu64_mask(__a, __b, 3); +} + +__mmask8 test_mm512_mask_cmp_epu64_mask(__mmask8 __u, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_cmp_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.512(<8 x i64> {{.*}}, <8 x i64> {{.*}}, i32 3, i8 {{.*}}) + return (__mmask8)_mm512_mask_cmp_epu64_mask(__u, __a, __b, 3); +} + +__m512i test_mm512_mask_and_epi32(__m512i __src,__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_and_epi32 + // CHECK: @llvm.x86.avx512.mask.pand.d.512 + return _mm512_mask_and_epi32(__src, __k,__a, __b); +} + +__m512i test_mm512_maskz_and_epi32(__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_maskz_and_epi32 + // CHECK: @llvm.x86.avx512.mask.pand.d.512 + return _mm512_maskz_and_epi32(__k,__a, __b); +} + +__m512i test_mm512_mask_and_epi64(__m512i __src,__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_and_epi64 + // CHECK: @llvm.x86.avx512.mask.pand.q.512 + return _mm512_mask_and_epi64(__src, __k,__a, __b); +} + +__m512i test_mm512_maskz_and_epi64(__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_maskz_and_epi64 + // CHECK: @llvm.x86.avx512.mask.pand.q.512 + return _mm512_maskz_and_epi64(__k,__a, __b); +} + +__m512i test_mm512_mask_or_epi32(__m512i __src,__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_or_epi32 + // CHECK: @llvm.x86.avx512.mask.por.d.512 + return _mm512_mask_or_epi32(__src, __k,__a, __b); +} + +__m512i test_mm512_maskz_or_epi32(__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_maskz_or_epi32 + // CHECK: @llvm.x86.avx512.mask.por.d.512 + return _mm512_maskz_or_epi32(__k,__a, __b); +} + +__m512i test_mm512_mask_or_epi64(__m512i __src,__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_or_epi64 + // CHECK: @llvm.x86.avx512.mask.por.q.512 + return _mm512_mask_or_epi64(__src, __k,__a, __b); +} + +__m512i test_mm512_maskz_or_epi64(__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_maskz_or_epi64 + // CHECK: @llvm.x86.avx512.mask.por.q.512 + return _mm512_maskz_or_epi64(__k,__a, __b); +} + +__m512i test_mm512_mask_xor_epi32(__m512i __src,__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_xor_epi32 + // CHECK: @llvm.x86.avx512.mask.pxor.d.512 + return _mm512_mask_xor_epi32(__src, __k,__a, __b); +} + +__m512i test_mm512_maskz_xor_epi32(__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_maskz_xor_epi32 + // CHECK: @llvm.x86.avx512.mask.pxor.d.512 + return _mm512_maskz_xor_epi32(__k,__a, __b); +} + +__m512i test_mm512_mask_xor_epi64(__m512i __src,__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_mask_xor_epi64 + // CHECK: @llvm.x86.avx512.mask.pxor.q.512 + return _mm512_mask_xor_epi64(__src, __k,__a, __b); +} + +__m512i test_mm512_maskz_xor_epi64(__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_maskz_xor_epi64 + // CHECK: @llvm.x86.avx512.mask.pxor.q.512 + return _mm512_maskz_xor_epi64(__k,__a, __b); +} + +__m512i test_mm512_and_epi32(__m512i __src,__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_and_epi32 + // CHECK: and <8 x i64> + return _mm512_and_epi32(__a, __b); +} + +__m512i test_mm512_and_epi64(__m512i __src,__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_and_epi64 + // CHECK: and <8 x i64> + return _mm512_and_epi64(__a, __b); +} + +__m512i test_mm512_or_epi32(__m512i __src,__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_or_epi32 + // CHECK: or <8 x i64> + return _mm512_or_epi32(__a, __b); +} + +__m512i test_mm512_or_epi64(__m512i __src,__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_or_epi64 + // CHECK: or <8 x i64> + return _mm512_or_epi64(__a, __b); +} + +__m512i test_mm512_xor_epi32(__m512i __src,__mmask16 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_xor_epi32 + // CHECK: xor <8 x i64> + return _mm512_xor_epi32(__a, __b); +} + +__m512i test_mm512_xor_epi64(__m512i __src,__mmask8 __k, __m512i __a, __m512i __b) { + // CHECK-LABEL: @test_mm512_xor_epi64 + // CHECK: xor <8 x i64> + return _mm512_xor_epi64(__a, __b); +} + +__m512i test_mm512_maskz_andnot_epi32 (__mmask16 __k,__m512i __A, __m512i __B){ + //CHECK-LABEL: @test_mm512_maskz_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.512 + return _mm512_maskz_andnot_epi32(__k,__A,__B); +} + +__m512i test_mm512_mask_andnot_epi32 (__mmask16 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.512 + return _mm512_mask_andnot_epi32(__src,__k,__A,__B); +} + +__m512i test_mm512_andnot_epi32(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.512 + return _mm512_andnot_epi32(__A,__B); +} + +__m512i test_mm512_maskz_andnot_epi64 (__mmask8 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.512 + return _mm512_maskz_andnot_epi64(__k,__A,__B); +} + +__m512i test_mm512_mask_andnot_epi64 (__mmask8 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.512 + return _mm512_mask_andnot_epi64(__src,__k,__A,__B); +} + +__m512i test_mm512_andnot_epi64(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.512 + return _mm512_andnot_epi64(__A,__B); +} + +__m512i test_mm512_maskz_sub_epi32 (__mmask16 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_sub_epi32 + //CHECK: @llvm.x86.avx512.mask.psub.d.512 + return _mm512_maskz_sub_epi32(__k,__A,__B); +} + +__m512i test_mm512_mask_sub_epi32 (__mmask16 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_sub_epi32 + //CHECK: @llvm.x86.avx512.mask.psub.d.512 + return _mm512_mask_sub_epi32(__src,__k,__A,__B); +} + +__m512i test_mm512_sub_epi32(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_sub_epi32 + //CHECK: sub <16 x i32> + return _mm512_sub_epi32(__A,__B); +} + +__m512i test_mm512_maskz_sub_epi64 (__mmask8 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_sub_epi64 + //CHECK: @llvm.x86.avx512.mask.psub.q.512 + return _mm512_maskz_sub_epi64(__k,__A,__B); +} + +__m512i test_mm512_mask_sub_epi64 (__mmask8 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_sub_epi64 + //CHECK: @llvm.x86.avx512.mask.psub.q.512 + return _mm512_mask_sub_epi64(__src,__k,__A,__B); +} + +__m512i test_mm512_sub_epi64(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_sub_epi64 + //CHECK: sub <8 x i64> + return _mm512_sub_epi64(__A,__B); +} + +__m512i test_mm512_maskz_add_epi32 (__mmask16 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_add_epi32 + //CHECK: @llvm.x86.avx512.mask.padd.d.512 + return _mm512_maskz_add_epi32(__k,__A,__B); +} + +__m512i test_mm512_mask_add_epi32 (__mmask16 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_add_epi32 + //CHECK: @llvm.x86.avx512.mask.padd.d.512 + return _mm512_mask_add_epi32(__src,__k,__A,__B); +} + +__m512i test_mm512_add_epi32(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_add_epi32 + //CHECK: add <16 x i32> + return _mm512_add_epi32(__A,__B); +} + +__m512i test_mm512_maskz_add_epi64 (__mmask8 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_add_epi64 + //CHECK: @llvm.x86.avx512.mask.padd.q.512 + return _mm512_maskz_add_epi64(__k,__A,__B); +} + +__m512i test_mm512_mask_add_epi64 (__mmask8 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_add_epi64 + //CHECK: @llvm.x86.avx512.mask.padd.q.512 + return _mm512_mask_add_epi64(__src,__k,__A,__B); +} + +__m512i test_mm512_add_epi64(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_add_epi64 + //CHECK: add <8 x i64> + return _mm512_add_epi64(__A,__B); +} + +__m512i test_mm512_maskz_mul_epi32 (__mmask16 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_mul_epi32 + //CHECK: @llvm.x86.avx512.mask.pmul.dq.512 + return _mm512_maskz_mul_epi32(__k,__A,__B); +} + +__m512i test_mm512_mask_mul_epi32 (__mmask16 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_mul_epi32 + //CHECK: @llvm.x86.avx512.mask.pmul.dq.512 + return _mm512_mask_mul_epi32(__src,__k,__A,__B); +} + +__m512i test_mm512_maskz_mul_epu32 (__mmask16 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_mul_epu32 + //CHECK: @llvm.x86.avx512.mask.pmulu.dq.512 + return _mm512_maskz_mul_epu32(__k,__A,__B); +} + +__m512i test_mm512_mask_mul_epu32 (__mmask16 __k,__m512i __A, __m512i __B, + __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_mul_epu32 + //CHECK: @llvm.x86.avx512.mask.pmulu.dq.512 + return _mm512_mask_mul_epu32(__src,__k,__A,__B); +} + +__m512i test_mm512_maskz_mullo_epi32 (__mmask16 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_mullo_epi32 + //CHECK: @llvm.x86.avx512.mask.pmull.d.512 + return _mm512_maskz_mullo_epi32(__k,__A,__B); +} + +__m512i test_mm512_mask_mullo_epi32 (__mmask16 __k,__m512i __A, __m512i __B, __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_mullo_epi32 + //CHECK: @llvm.x86.avx512.mask.pmull.d.512 + return _mm512_mask_mullo_epi32(__src,__k,__A,__B); +} + +__m512i test_mm512_mullo_epi32(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_mullo_epi32 + //CHECK: mul <16 x i32> + return _mm512_mullo_epi32(__A,__B); +}
\ No newline at end of file diff --git a/test/CodeGen/avx512vl-builtins.c b/test/CodeGen/avx512vl-builtins.c index e4b45173bb13..9446d467f78e 100644 --- a/test/CodeGen/avx512vl-builtins.c +++ b/test/CodeGen/avx512vl-builtins.c @@ -49,3 +49,1075 @@ __mmask8 test_mm_mask_cmpeq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) { // CHECK: @llvm.x86.avx512.mask.pcmpeq.q.128 return (__mmask8)_mm_mask_cmpeq_epi64_mask(__u, __a, __b); } + +__mmask8 test_mm256_cmpgt_epi32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.d.256 + return (__mmask8)_mm256_cmpgt_epi32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpgt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.d.256 + return (__mmask8)_mm256_mask_cmpgt_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpgt_epi32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.d.128 + return (__mmask8)_mm_cmpgt_epi32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpgt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.d.128 + return (__mmask8)_mm_mask_cmpgt_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpgt_epi64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.q.256 + return (__mmask8)_mm256_cmpgt_epi64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpgt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.q.256 + return (__mmask8)_mm256_mask_cmpgt_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpgt_epi64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.q.128 + return (__mmask8)_mm_cmpgt_epi64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpgt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.q.128 + return (__mmask8)_mm_mask_cmpgt_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpeq_epu32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpeq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 0, i8 -1) + return (__mmask8)_mm_cmpeq_epu32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpeq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpeq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 0, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpeq_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpeq_epu64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpeq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 0, i8 -1) + return (__mmask8)_mm_cmpeq_epu64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpeq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpeq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 0, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpeq_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpge_epi32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm_cmpge_epi32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpge_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpge_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpge_epi64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm_cmpge_epi64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpge_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpge_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpge_epi32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm256_cmpge_epi32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpge_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpge_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpge_epi64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm256_cmpge_epi64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpge_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpge_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpge_epu32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm_cmpge_epu32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpge_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpge_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpge_epu64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm_cmpge_epu64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpge_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpge_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpge_epu32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm256_cmpge_epu32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpge_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpge_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpge_epu64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 5, i8 -1) + return (__mmask8)_mm256_cmpge_epu64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpge_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpge_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpgt_epu32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 6, i8 -1) + return (__mmask8)_mm_cmpgt_epu32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpgt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 6, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpgt_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpgt_epu64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 6, i8 -1) + return (__mmask8)_mm_cmpgt_epu64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpgt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 6, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpgt_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpgt_epu32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 6, i8 -1) + return (__mmask8)_mm256_cmpgt_epu32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpgt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 6, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpgt_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpgt_epu64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 6, i8 -1) + return (__mmask8)_mm256_cmpgt_epu64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpgt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 6, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpgt_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmple_epi32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm_cmple_epi32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmple_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm_mask_cmple_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmple_epi64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm_cmple_epi64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmple_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm_mask_cmple_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmple_epi32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm256_cmple_epi32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmple_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmple_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmple_epi64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm256_cmple_epi64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmple_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmple_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmple_epu32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm_cmple_epu32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmple_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm_mask_cmple_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmple_epu64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm_cmple_epu64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmple_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm_mask_cmple_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmple_epu32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm256_cmple_epu32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmple_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmple_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmple_epu64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 2, i8 -1) + return (__mmask8)_mm256_cmple_epu64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmple_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmple_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmplt_epi32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm_cmplt_epi32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmplt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm_mask_cmplt_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmplt_epi64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm_cmplt_epi64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmplt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm_mask_cmplt_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmplt_epi32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm256_cmplt_epi32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmplt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmplt_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmplt_epi64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm256_cmplt_epi64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmplt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmplt_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmplt_epu32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm_cmplt_epu32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmplt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm_mask_cmplt_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmplt_epu64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm_cmplt_epu64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmplt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm_mask_cmplt_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmplt_epu32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm256_cmplt_epu32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmplt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmplt_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmplt_epu64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 1, i8 -1) + return (__mmask8)_mm256_cmplt_epu64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmplt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmplt_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpneq_epi32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm_cmpneq_epi32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpneq_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpneq_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpneq_epi64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm_cmpneq_epi64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpneq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpneq_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpneq_epi32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm256_cmpneq_epi32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpneq_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpneq_epi32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpneq_epi64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm256_cmpneq_epi64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpneq_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpneq_epi64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpneq_epu32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm_cmpneq_epu32_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpneq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpneq_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpneq_epu64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm_cmpneq_epu64_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpneq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm_mask_cmpneq_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpneq_epu32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm256_cmpneq_epu32_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpneq_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpneq_epu32_mask(__u, __a, __b); +} + +__mmask8 test_mm256_cmpneq_epu64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 4, i8 -1) + return (__mmask8)_mm256_cmpneq_epu64_mask(__a, __b); +} + +__mmask8 test_mm256_mask_cmpneq_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmpneq_epu64_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmp_epi32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm_cmp_epi32_mask(__a, __b, 7); +} + +__mmask8 test_mm_mask_cmp_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm_mask_cmp_epi32_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm_cmp_epi64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm_cmp_epi64_mask(__a, __b, 7); +} + +__mmask8 test_mm_mask_cmp_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm_mask_cmp_epi64_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm256_cmp_epi32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm256_cmp_epi32_mask(__a, __b, 7); +} + +__mmask8 test_mm256_mask_cmp_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epi32_mask + // CHECK: @llvm.x86.avx512.mask.cmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmp_epi32_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm256_cmp_epi64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm256_cmp_epi64_mask(__a, __b, 7); +} + +__mmask8 test_mm256_mask_cmp_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epi64_mask + // CHECK: @llvm.x86.avx512.mask.cmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmp_epi64_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm_cmp_epu32_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm_cmp_epu32_mask(__a, __b, 7); +} + +__mmask8 test_mm_mask_cmp_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.128(<4 x i32> {{.*}}, <4 x i32> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm_mask_cmp_epu32_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm_cmp_epu64_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm_cmp_epu64_mask(__a, __b, 7); +} + +__mmask8 test_mm_mask_cmp_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.128(<2 x i64> {{.*}}, <2 x i64> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm_mask_cmp_epu64_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm256_cmp_epu32_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm256_cmp_epu32_mask(__a, __b, 7); +} + +__mmask8 test_mm256_mask_cmp_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epu32_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.d.256(<8 x i32> {{.*}}, <8 x i32> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmp_epu32_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm256_cmp_epu64_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 7, i8 -1) + return (__mmask8)_mm256_cmp_epu64_mask(__a, __b, 7); +} + +__mmask8 test_mm256_mask_cmp_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epu64_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.q.256(<4 x i64> {{.*}}, <4 x i64> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask8)_mm256_mask_cmp_epu64_mask(__u, __a, __b, 7); +} + +__m512i test_mm512_maskz_andnot_epi32 (__mmask16 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.512 + return _mm512_maskz_andnot_epi32(__k,__A,__B); +} + +__m512i test_mm512_mask_andnot_epi32 (__mmask16 __k,__m512i __A, __m512i __B, __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.512 + return _mm512_mask_andnot_epi32(__src,__k,__A,__B); +} + +__m512i test_mm512_andnot_epi32(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.512 + return _mm512_andnot_epi32(__A,__B); +} + +__m512i test_mm512_maskz_andnot_epi64 (__mmask8 __k,__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_maskz_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.512 + return _mm512_maskz_andnot_epi64(__k,__A,__B); +} + +__m512i test_mm512_mask_andnot_epi64 (__mmask8 __k,__m512i __A, __m512i __B, __m512i __src) { + //CHECK-LABEL: @test_mm512_mask_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.512 + return _mm512_mask_andnot_epi64(__src,__k,__A,__B); +} + +__m512i test_mm512_andnot_epi64(__m512i __A, __m512i __B) { + //CHECK-LABEL: @test_mm512_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.512 + return _mm512_andnot_epi64(__A,__B); +} + +__m256i test_mm256_mask_add_epi32 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_add_epi32 + //CHECK: @llvm.x86.avx512.mask.padd.d.256 + return _mm256_mask_add_epi32(__W, __U, __A, __B); +} + +__m256i test_mm256_maskz_add_epi32 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_add_epi32 + //CHECK: @llvm.x86.avx512.mask.padd.d.256 + return _mm256_maskz_add_epi32(__U, __A, __B); +} + +__m256i test_mm256_mask_add_epi64 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_add_epi64 + //CHECK: @llvm.x86.avx512.mask.padd.q.256 + return _mm256_mask_add_epi64(__W,__U,__A,__B); +} + +__m256i test_mm256_maskz_add_epi64 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_add_epi64 + //CHECK: @llvm.x86.avx512.mask.padd.q.256 + return _mm256_maskz_add_epi64 (__U,__A,__B); +} + +__m256i test_mm256_mask_sub_epi32 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_sub_epi32 + //CHECK: @llvm.x86.avx512.mask.psub.d.256 + return _mm256_mask_sub_epi32 (__W,__U,__A,__B); +} + +__m256i test_mm256_maskz_sub_epi32 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_sub_epi32 + //CHECK: @llvm.x86.avx512.mask.psub.d.256 + return _mm256_maskz_sub_epi32 (__U,__A,__B); +} + +__m256i test_mm256_mask_sub_epi64 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_sub_epi64 + //CHECK: @llvm.x86.avx512.mask.psub.q.256 + return _mm256_mask_sub_epi64 (__W,__U,__A,__B); +} + +__m256i test_mm256_maskz_sub_epi64 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_sub_epi64 + //CHECK: @llvm.x86.avx512.mask.psub.q.256 + return _mm256_maskz_sub_epi64 (__U,__A,__B); +} + +__m128i test_mm_mask_add_epi32 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_add_epi32 + //CHECK: @llvm.x86.avx512.mask.padd.d.128 + return _mm_mask_add_epi32(__W,__U,__A,__B); +} + + +__m128i test_mm_maskz_add_epi32 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_add_epi32 + //CHECK: @llvm.x86.avx512.mask.padd.d.128 + return _mm_maskz_add_epi32 (__U,__A,__B); +} + +__m128i test_mm_mask_add_epi64 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { +//CHECK-LABEL: @test_mm_mask_add_epi64 + //CHECK: @llvm.x86.avx512.mask.padd.q.128 + return _mm_mask_add_epi64 (__W,__U,__A,__B); +} + +__m128i test_mm_maskz_add_epi64 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_add_epi64 + //CHECK: @llvm.x86.avx512.mask.padd.q.128 + return _mm_maskz_add_epi64 (__U,__A,__B); +} + +__m128i test_mm_mask_sub_epi32 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_sub_epi32 + //CHECK: @llvm.x86.avx512.mask.psub.d.128 + return _mm_mask_sub_epi32(__W, __U, __A, __B); +} + +__m128i test_mm_maskz_sub_epi32 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_sub_epi32 + //CHECK: @llvm.x86.avx512.mask.psub.d.128 + return _mm_maskz_sub_epi32(__U, __A, __B); +} + +__m128i test_mm_mask_sub_epi64 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_sub_epi64 + //CHECK: @llvm.x86.avx512.mask.psub.q.128 + return _mm_mask_sub_epi64 (__W, __U, __A, __B); +} + +__m128i test_mm_maskz_sub_epi64 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_sub_epi64 + //CHECK: @llvm.x86.avx512.mask.psub.q.128 + return _mm_maskz_sub_epi64 (__U, __A, __B); +} + +__m256i test_mm256_mask_mul_epi32 (__m256i __W, __mmask8 __M, __m256i __X, + __m256i __Y) { + //CHECK-LABEL: @test_mm256_mask_mul_epi32 + //CHECK: @llvm.x86.avx512.mask.pmul.dq.256 + return _mm256_mask_mul_epi32(__W, __M, __X, __Y); +} + +__m256i test_mm256_maskz_mul_epi32 (__mmask8 __M, __m256i __X, __m256i __Y) { + //CHECK-LABEL: @test_mm256_maskz_mul_epi32 + //CHECK: @llvm.x86.avx512.mask.pmul.dq.256 + return _mm256_maskz_mul_epi32(__M, __X, __Y); +} + + +__m128i test_mm_mask_mul_epi32 (__m128i __W, __mmask8 __M, __m128i __X, + __m128i __Y) { + //CHECK-LABEL: @test_mm_mask_mul_epi32 + //CHECK: @llvm.x86.avx512.mask.pmul.dq.128 + return _mm_mask_mul_epi32(__W, __M, __X, __Y); +} + +__m128i test_mm_maskz_mul_epi32 (__mmask8 __M, __m128i __X, __m128i __Y) { + //CHECK-LABEL: @test_mm_maskz_mul_epi32 + //CHECK: @llvm.x86.avx512.mask.pmul.dq.128 + return _mm_maskz_mul_epi32(__M, __X, __Y); +} + +__m256i test_mm256_mask_mul_epu32 (__m256i __W, __mmask8 __M, __m256i __X, + __m256i __Y) { + //CHECK-LABEL: @test_mm256_mask_mul_epu32 + //CHECK: @llvm.x86.avx512.mask.pmulu.dq.256 + return _mm256_mask_mul_epu32(__W, __M, __X, __Y); +} + +__m256i test_mm256_maskz_mul_epu32 (__mmask8 __M, __m256i __X, __m256i __Y) { + //CHECK-LABEL: @test_mm256_maskz_mul_epu32 + //CHECK: @llvm.x86.avx512.mask.pmulu.dq.256 + return _mm256_maskz_mul_epu32(__M, __X, __Y); +} + +__m128i test_mm_mask_mul_epu32 (__m128i __W, __mmask8 __M, __m128i __X, + __m128i __Y) { + //CHECK-LABEL: @test_mm_mask_mul_epu32 + //CHECK: @llvm.x86.avx512.mask.pmulu.dq.128 + return _mm_mask_mul_epu32(__W, __M, __X, __Y); +} + +__m128i test_mm_maskz_mul_epu32 (__mmask8 __M, __m128i __X, __m128i __Y) { + //CHECK-LABEL: @test_mm_maskz_mul_epu32 + //CHECK: @llvm.x86.avx512.mask.pmulu.dq.128 + return _mm_maskz_mul_epu32(__M, __X, __Y); +} + +__m128i test_mm_maskz_mullo_epi32 (__mmask8 __M, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_mullo_epi32 + //CHECK: @llvm.x86.avx512.mask.pmull.d.128 + return _mm_maskz_mullo_epi32(__M, __A, __B); +} + +__m128i test_mm_mask_mullo_epi32 (__m128i __W, __mmask8 __M, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_mullo_epi32 + //CHECK: @llvm.x86.avx512.mask.pmull.d.128 + return _mm_mask_mullo_epi32(__W, __M, __A, __B); +} + +__m256i test_mm256_maskz_mullo_epi32 (__mmask8 __M, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_mullo_epi32 + //CHECK: @llvm.x86.avx512.mask.pmull.d.256 + return _mm256_maskz_mullo_epi32(__M, __A, __B); +} + +__m256i test_mm256_mask_mullo_epi32 (__m256i __W, __mmask8 __M, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_mullo_epi32 + //CHECK: @llvm.x86.avx512.mask.pmull.d.256 + return _mm256_mask_mullo_epi32(__W, __M, __A, __B); +} + +__m256i test_mm256_mask_and_epi32 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_and_epi32 + //CHECK: @llvm.x86.avx512.mask.pand.d.256 + return _mm256_mask_and_epi32(__W, __U, __A, __B); +} + +__m256i test_mm256_maskz_and_epi32 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_and_epi32 + //CHECK: @llvm.x86.avx512.mask.pand.d.256 + return _mm256_maskz_and_epi32(__U, __A, __B); +} + +__m128i test_mm_mask_and_epi32 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_and_epi32 + //CHECK: @llvm.x86.avx512.mask.pand.d.128 + return _mm_mask_and_epi32(__W, __U, __A, __B); +} + +__m128i test_mm_maskz_and_epi32 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_and_epi32 + //CHECK: @llvm.x86.avx512.mask.pand.d.128 + return _mm_maskz_and_epi32(__U, __A, __B); +} + +__m256i test_mm256_mask_andnot_epi32 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.256 + return _mm256_mask_andnot_epi32(__W, __U, __A, __B); +} + +__m256i test_mm256_maskz_andnot_epi32 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.256 + return _mm256_maskz_andnot_epi32(__U, __A, __B); +} + +__m128i test_mm_mask_andnot_epi32 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.128 + return _mm_mask_andnot_epi32(__W, __U, __A, __B); +} + +__m128i test_mm_maskz_andnot_epi32 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_andnot_epi32 + //CHECK: @llvm.x86.avx512.mask.pandn.d.128 + return _mm_maskz_andnot_epi32(__U, __A, __B); +} + +__m256i test_mm256_mask_or_epi32 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_or_epi32 + //CHECK: @llvm.x86.avx512.mask.por.d.256 + return _mm256_mask_or_epi32(__W, __U, __A, __B); +} + + __m256i test_mm256_maskz_or_epi32 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_or_epi32 + //CHECK: @llvm.x86.avx512.mask.por.d.256 + return _mm256_maskz_or_epi32(__U, __A, __B); +} + + __m128i test_mm_mask_or_epi32 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_or_epi32 + //CHECK: @llvm.x86.avx512.mask.por.d.128 + return _mm_mask_or_epi32(__W, __U, __A, __B); +} + +__m128i test_mm_maskz_or_epi32 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_or_epi32 + //CHECK: @llvm.x86.avx512.mask.por.d.128 + return _mm_maskz_or_epi32(__U, __A, __B); +} + +__m256i test_mm256_mask_xor_epi32 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_xor_epi32 + //CHECK: @llvm.x86.avx512.mask.pxor.d.256 + return _mm256_mask_xor_epi32(__W, __U, __A, __B); +} + +__m256i test_mm256_maskz_xor_epi32 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_xor_epi32 + //CHECK: @llvm.x86.avx512.mask.pxor.d.256 + return _mm256_maskz_xor_epi32(__U, __A, __B); +} + +__m128i test_mm_mask_xor_epi32 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_xor_epi32 + //CHECK: @llvm.x86.avx512.mask.pxor.d.128 + return _mm_mask_xor_epi32(__W, __U, __A, __B); +} + +__m128i test_mm_maskz_xor_epi32 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_xor_epi32 + //CHECK: @llvm.x86.avx512.mask.pxor.d.128 + return _mm_maskz_xor_epi32(__U, __A, __B); +} + +__m256i test_mm256_mask_and_epi64 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_and_epi64 + //CHECK: @llvm.x86.avx512.mask.pand.q.256 + return _mm256_mask_and_epi64(__W, __U, __A, __B); +} + +__m256i test_mm256_maskz_and_epi64 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_and_epi64 + //CHECK: @llvm.x86.avx512.mask.pand.q.256 + return _mm256_maskz_and_epi64(__U, __A, __B); +} + +__m128i test_mm_mask_and_epi64 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_and_epi64 + //CHECK: @llvm.x86.avx512.mask.pand.q.128 + return _mm_mask_and_epi64(__W,__U, __A, __B); +} + +__m128i test_mm_maskz_and_epi64 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_and_epi64 + //CHECK: @llvm.x86.avx512.mask.pand.q.128 + return _mm_maskz_and_epi64(__U, __A, __B); +} + +__m256i test_mm256_mask_andnot_epi64 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.256 + return _mm256_mask_andnot_epi64(__W, __U, __A, __B); +} + +__m256i test_mm256_maskz_andnot_epi64 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.256 + return _mm256_maskz_andnot_epi64(__U, __A, __B); +} + +__m128i test_mm_mask_andnot_epi64 (__m128i __W, __mmask8 __U, __m128i __A, + __m128i __B) { + //CHECK-LABEL: @test_mm_mask_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.128 + return _mm_mask_andnot_epi64(__W,__U, __A, __B); +} + +__m128i test_mm_maskz_andnot_epi64 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_andnot_epi64 + //CHECK: @llvm.x86.avx512.mask.pandn.q.128 + return _mm_maskz_andnot_epi64(__U, __A, __B); +} + +__m256i test_mm256_mask_or_epi64 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_or_epi64 + //CHECK: @llvm.x86.avx512.mask.por.q.256 + return _mm256_mask_or_epi64(__W,__U, __A, __B); +} + +__m256i test_mm256_maskz_or_epi64 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_or_epi64 + //CHECK: @llvm.x86.avx512.mask.por.q.256 + return _mm256_maskz_or_epi64(__U, __A, __B); +} + +__m128i test_mm_mask_or_epi64 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_or_epi64 + //CHECK: @llvm.x86.avx512.mask.por.q.128 + return _mm_mask_or_epi64(__W, __U, __A, __B); +} + +__m128i test_mm_maskz_or_epi64 (__mmask8 __U, __m128i __A, __m128i __B) { +//CHECK-LABEL: @test_mm_maskz_or_epi64 + //CHECK: @llvm.x86.avx512.mask.por.q.128 + return _mm_maskz_or_epi64( __U, __A, __B); +} + +__m256i test_mm256_mask_xor_epi64 (__m256i __W, __mmask8 __U, __m256i __A, + __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_xor_epi64 + //CHECK: @llvm.x86.avx512.mask.pxor.q.256 + return _mm256_mask_xor_epi64(__W,__U, __A, __B); +} + +__m256i test_mm256_maskz_xor_epi64 (__mmask8 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_xor_epi64 + //CHECK: @llvm.x86.avx512.mask.pxor.q.256 + return _mm256_maskz_xor_epi64(__U, __A, __B); +} + +__m128i test_mm_mask_xor_epi64 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_xor_epi64 + //CHECK: @llvm.x86.avx512.mask.pxor.q.128 + return _mm_mask_xor_epi64(__W, __U, __A, __B); +} + +__m128i test_mm_maskz_xor_epi64 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_xor_epi64 + //CHECK: @llvm.x86.avx512.mask.pxor.q.128 + return _mm_maskz_xor_epi64( __U, __A, __B); +} + +__mmask8 test_mm256_cmp_ps_mask(__m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_cmp_ps_mask + // CHECK: @llvm.x86.avx512.mask.cmp.ps.256 + return (__mmask8)_mm256_cmp_ps_mask(__A, __B, 0); +} + +__mmask8 test_mm256_mask_cmp_ps_mask(__mmask8 m, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_mask_cmp_ps_mask + // CHECK: @llvm.x86.avx512.mask.cmp.ps.256 + return _mm256_mask_cmp_ps_mask(m, __A, __B, 0); +} + +__mmask8 test_mm128_cmp_ps_mask(__m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm128_cmp_ps_mask + // CHECK: @llvm.x86.avx512.mask.cmp.ps.128 + return (__mmask8)_mm128_cmp_ps_mask(__A, __B, 0); +} + +__mmask8 test_mm128_mask_cmp_ps_mask(__mmask8 m, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm128_mask_cmp_ps_mask + // CHECK: @llvm.x86.avx512.mask.cmp.ps.128 + return _mm128_mask_cmp_ps_mask(m, __A, __B, 0); +} + +__mmask8 test_mm256_cmp_pd_mask(__m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_cmp_pd_mask + // CHECK: @llvm.x86.avx512.mask.cmp.pd.256 + return (__mmask8)_mm256_cmp_pd_mask(__A, __B, 0); +} + +__mmask8 test_mm256_mask_cmp_pd_mask(__mmask8 m, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_mask_cmp_pd_mask + // CHECK: @llvm.x86.avx512.mask.cmp.pd.256 + return _mm256_mask_cmp_pd_mask(m, __A, __B, 0); +} + +__mmask8 test_mm128_cmp_pd_mask(__m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm128_cmp_pd_mask + // CHECK: @llvm.x86.avx512.mask.cmp.pd.128 + return (__mmask8)_mm128_cmp_pd_mask(__A, __B, 0); +} + +__mmask8 test_mm128_mask_cmp_pd_mask(__mmask8 m, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm128_mask_cmp_pd_mask + // CHECK: @llvm.x86.avx512.mask.cmp.pd.128 + return _mm128_mask_cmp_pd_mask(m, __A, __B, 0); +} diff --git a/test/CodeGen/avx512vlbw-builtins.c b/test/CodeGen/avx512vlbw-builtins.c index a304f7b3d361..a4a12440dc11 100644 --- a/test/CodeGen/avx512vlbw-builtins.c +++ b/test/CodeGen/avx512vlbw-builtins.c @@ -49,3 +49,746 @@ __mmask8 test_mm_mask_cmpeq_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) { // CHECK: @llvm.x86.avx512.mask.pcmpeq.w.128 return (__mmask8)_mm_mask_cmpeq_epi16_mask(__u, __a, __b); } + +__mmask32 test_mm256_cmpgt_epi8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.b.256 + return (__mmask32)_mm256_cmpgt_epi8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmpgt_epi8_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.b.256 + return (__mmask32)_mm256_mask_cmpgt_epi8_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmpgt_epi8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.b.128 + return (__mmask16)_mm_cmpgt_epi8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmpgt_epi8_mask(__mmask16 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.b.128 + return (__mmask16)_mm_mask_cmpgt_epi8_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmpgt_epi16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.w.256 + return (__mmask16)_mm256_cmpgt_epi16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmpgt_epi16_mask(__mmask16 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.w.256 + return (__mmask16)_mm256_mask_cmpgt_epi16_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpgt_epi16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.w.128 + return (__mmask8)_mm_cmpgt_epi16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpgt_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.pcmpgt.w.128 + return (__mmask8)_mm_mask_cmpgt_epi16_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmpeq_epu8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpeq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 0, i16 -1) + return (__mmask64)_mm_cmpeq_epu8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmpeq_epu8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpeq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 0, i16 {{.*}}) + return (__mmask64)_mm_mask_cmpeq_epu8_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpeq_epu16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpeq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 0, i8 -1) + return (__mmask32)_mm_cmpeq_epu16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpeq_epu16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpeq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 0, i8 {{.*}}) + return (__mmask32)_mm_mask_cmpeq_epu16_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmpeq_epu8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpeq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 0, i32 -1) + return (__mmask64)_mm256_cmpeq_epu8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmpeq_epu8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpeq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 0, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmpeq_epu8_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmpeq_epu16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpeq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 0, i16 -1) + return (__mmask32)_mm256_cmpeq_epu16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmpeq_epu16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpeq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 0, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmpeq_epu16_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmpgt_epu8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 6, i16 -1) + return (__mmask64)_mm_cmpgt_epu8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmpgt_epu8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 6, i16 {{.*}}) + return (__mmask64)_mm_mask_cmpgt_epu8_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpgt_epu16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpgt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 6, i8 -1) + return (__mmask32)_mm_cmpgt_epu16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpgt_epu16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpgt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 6, i8 {{.*}}) + return (__mmask32)_mm_mask_cmpgt_epu16_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmpgt_epu8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 6, i32 -1) + return (__mmask64)_mm256_cmpgt_epu8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmpgt_epu8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 6, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmpgt_epu8_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmpgt_epu16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpgt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 6, i16 -1) + return (__mmask32)_mm256_cmpgt_epu16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmpgt_epu16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpgt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 6, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmpgt_epu16_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmpge_epi8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 5, i16 -1) + return (__mmask64)_mm_cmpge_epi8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmpge_epi8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 5, i16 {{.*}}) + return (__mmask64)_mm_mask_cmpge_epi8_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmpge_epu8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 5, i16 -1) + return (__mmask64)_mm_cmpge_epu8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmpge_epu8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 5, i16 {{.*}}) + return (__mmask64)_mm_mask_cmpge_epu8_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpge_epi16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 5, i8 -1) + return (__mmask32)_mm_cmpge_epi16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpge_epi16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask32)_mm_mask_cmpge_epi16_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpge_epu16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpge_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 5, i8 -1) + return (__mmask32)_mm_cmpge_epu16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpge_epu16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpge_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 5, i8 {{.*}}) + return (__mmask32)_mm_mask_cmpge_epu16_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmpge_epi8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 5, i32 -1) + return (__mmask64)_mm256_cmpge_epi8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmpge_epi8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 5, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmpge_epi8_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmpge_epu8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 5, i32 -1) + return (__mmask64)_mm256_cmpge_epu8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmpge_epu8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 5, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmpge_epu8_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmpge_epi16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 5, i16 -1) + return (__mmask32)_mm256_cmpge_epi16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmpge_epi16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 5, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmpge_epi16_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmpge_epu16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpge_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 5, i16 -1) + return (__mmask32)_mm256_cmpge_epu16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmpge_epu16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpge_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 5, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmpge_epu16_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmple_epi8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 2, i16 -1) + return (__mmask64)_mm_cmple_epi8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmple_epi8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 2, i16 {{.*}}) + return (__mmask64)_mm_mask_cmple_epi8_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmple_epu8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 2, i16 -1) + return (__mmask64)_mm_cmple_epu8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmple_epu8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 2, i16 {{.*}}) + return (__mmask64)_mm_mask_cmple_epu8_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmple_epi16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 2, i8 -1) + return (__mmask32)_mm_cmple_epi16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmple_epi16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask32)_mm_mask_cmple_epi16_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmple_epu16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmple_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 2, i8 -1) + return (__mmask32)_mm_cmple_epu16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmple_epu16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmple_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 2, i8 {{.*}}) + return (__mmask32)_mm_mask_cmple_epu16_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmple_epi8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 2, i32 -1) + return (__mmask64)_mm256_cmple_epi8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmple_epi8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 2, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmple_epi8_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmple_epu8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 2, i32 -1) + return (__mmask64)_mm256_cmple_epu8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmple_epu8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 2, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmple_epu8_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmple_epi16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 2, i16 -1) + return (__mmask32)_mm256_cmple_epi16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmple_epi16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 2, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmple_epi16_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmple_epu16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmple_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 2, i16 -1) + return (__mmask32)_mm256_cmple_epu16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmple_epu16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmple_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 2, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmple_epu16_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmplt_epi8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 1, i16 -1) + return (__mmask64)_mm_cmplt_epi8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmplt_epi8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 1, i16 {{.*}}) + return (__mmask64)_mm_mask_cmplt_epi8_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmplt_epu8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 1, i16 -1) + return (__mmask64)_mm_cmplt_epu8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmplt_epu8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 1, i16 {{.*}}) + return (__mmask64)_mm_mask_cmplt_epu8_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmplt_epi16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 1, i8 -1) + return (__mmask32)_mm_cmplt_epi16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmplt_epi16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask32)_mm_mask_cmplt_epi16_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmplt_epu16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmplt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 1, i8 -1) + return (__mmask32)_mm_cmplt_epu16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmplt_epu16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmplt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 1, i8 {{.*}}) + return (__mmask32)_mm_mask_cmplt_epu16_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmplt_epi8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 1, i32 -1) + return (__mmask64)_mm256_cmplt_epi8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmplt_epi8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 1, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmplt_epi8_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmplt_epu8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 1, i32 -1) + return (__mmask64)_mm256_cmplt_epu8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmplt_epu8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 1, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmplt_epu8_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmplt_epi16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 1, i16 -1) + return (__mmask32)_mm256_cmplt_epi16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmplt_epi16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 1, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmplt_epi16_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmplt_epu16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmplt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 1, i16 -1) + return (__mmask32)_mm256_cmplt_epu16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmplt_epu16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmplt_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 1, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmplt_epu16_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmpneq_epi8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 4, i16 -1) + return (__mmask64)_mm_cmpneq_epi8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmpneq_epi8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 4, i16 {{.*}}) + return (__mmask64)_mm_mask_cmpneq_epi8_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmpneq_epu8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 4, i16 -1) + return (__mmask64)_mm_cmpneq_epu8_mask(__a, __b); +} + +__mmask16 test_mm_mask_cmpneq_epu8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 4, i16 {{.*}}) + return (__mmask64)_mm_mask_cmpneq_epu8_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpneq_epi16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 4, i8 -1) + return (__mmask32)_mm_cmpneq_epi16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpneq_epi16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask32)_mm_mask_cmpneq_epi16_mask(__u, __a, __b); +} + +__mmask8 test_mm_cmpneq_epu16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmpneq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 4, i8 -1) + return (__mmask32)_mm_cmpneq_epu16_mask(__a, __b); +} + +__mmask8 test_mm_mask_cmpneq_epu16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmpneq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 4, i8 {{.*}}) + return (__mmask32)_mm_mask_cmpneq_epu16_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmpneq_epi8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 4, i32 -1) + return (__mmask64)_mm256_cmpneq_epi8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmpneq_epi8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 4, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmpneq_epi8_mask(__u, __a, __b); +} + +__mmask32 test_mm256_cmpneq_epu8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 4, i32 -1) + return (__mmask64)_mm256_cmpneq_epu8_mask(__a, __b); +} + +__mmask32 test_mm256_mask_cmpneq_epu8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 4, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmpneq_epu8_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmpneq_epi16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 4, i16 -1) + return (__mmask32)_mm256_cmpneq_epi16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmpneq_epi16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 4, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmpneq_epi16_mask(__u, __a, __b); +} + +__mmask16 test_mm256_cmpneq_epu16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmpneq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 4, i16 -1) + return (__mmask32)_mm256_cmpneq_epu16_mask(__a, __b); +} + +__mmask16 test_mm256_mask_cmpneq_epu16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmpneq_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 4, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmpneq_epu16_mask(__u, __a, __b); +} + +__mmask16 test_mm_cmp_epi8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 7, i16 -1) + return (__mmask64)_mm_cmp_epi8_mask(__a, __b, 7); +} + +__mmask16 test_mm_mask_cmp_epi8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 7, i16 {{.*}}) + return (__mmask64)_mm_mask_cmp_epi8_mask(__u, __a, __b, 7); +} + +__mmask16 test_mm_cmp_epu8_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 7, i16 -1) + return (__mmask64)_mm_cmp_epu8_mask(__a, __b, 7); +} + +__mmask16 test_mm_mask_cmp_epu8_mask(__mmask64 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.128(<16 x i8> {{.*}}, <16 x i8> {{.*}}, i32 7, i16 {{.*}}) + return (__mmask64)_mm_mask_cmp_epu8_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm_cmp_epi16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 7, i8 -1) + return (__mmask32)_mm_cmp_epi16_mask(__a, __b, 7); +} + +__mmask8 test_mm_mask_cmp_epi16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask32)_mm_mask_cmp_epi16_mask(__u, __a, __b, 7); +} + +__mmask8 test_mm_cmp_epu16_mask(__m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_cmp_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 7, i8 -1) + return (__mmask32)_mm_cmp_epu16_mask(__a, __b, 7); +} + +__mmask8 test_mm_mask_cmp_epu16_mask(__mmask32 __u, __m128i __a, __m128i __b) { + // CHECK-LABEL: @test_mm_mask_cmp_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.128(<8 x i16> {{.*}}, <8 x i16> {{.*}}, i32 7, i8 {{.*}}) + return (__mmask32)_mm_mask_cmp_epu16_mask(__u, __a, __b, 7); +} + +__mmask32 test_mm256_cmp_epi8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 7, i32 -1) + return (__mmask64)_mm256_cmp_epi8_mask(__a, __b, 7); +} + +__mmask32 test_mm256_mask_cmp_epi8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epi8_mask + // CHECK: @llvm.x86.avx512.mask.cmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 7, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmp_epi8_mask(__u, __a, __b, 7); +} + +__mmask32 test_mm256_cmp_epu8_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 7, i32 -1) + return (__mmask64)_mm256_cmp_epu8_mask(__a, __b, 7); +} + +__mmask32 test_mm256_mask_cmp_epu8_mask(__mmask64 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epu8_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.b.256(<32 x i8> {{.*}}, <32 x i8> {{.*}}, i32 7, i32 {{.*}}) + return (__mmask64)_mm256_mask_cmp_epu8_mask(__u, __a, __b, 7); +} + +__mmask16 test_mm256_cmp_epi16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 7, i16 -1) + return (__mmask32)_mm256_cmp_epi16_mask(__a, __b, 7); +} + +__mmask16 test_mm256_mask_cmp_epi16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epi16_mask + // CHECK: @llvm.x86.avx512.mask.cmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 7, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmp_epi16_mask(__u, __a, __b, 7); +} + +__mmask16 test_mm256_cmp_epu16_mask(__m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_cmp_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 7, i16 -1) + return (__mmask32)_mm256_cmp_epu16_mask(__a, __b, 7); +} + +__mmask16 test_mm256_mask_cmp_epu16_mask(__mmask32 __u, __m256i __a, __m256i __b) { + // CHECK-LABEL: @test_mm256_mask_cmp_epu16_mask + // CHECK: @llvm.x86.avx512.mask.ucmp.w.256(<16 x i16> {{.*}}, <16 x i16> {{.*}}, i32 7, i16 {{.*}}) + return (__mmask32)_mm256_mask_cmp_epu16_mask(__u, __a, __b, 7); +} + + +__m256i test_mm256_mask_add_epi8 (__m256i __W, __mmask32 __U, __m256i __A, __m256i __B){ + //CHECK-LABEL: @test_mm256_mask_add_epi8 + //CHECK: @llvm.x86.avx512.mask.padd.b.256 + return _mm256_mask_add_epi8(__W, __U , __A, __B); +} + +__m256i test_mm256_maskz_add_epi8 (__mmask32 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_add_epi8 + //CHECK: @llvm.x86.avx512.mask.padd.b.256 + return _mm256_maskz_add_epi8(__U , __A, __B); +} +__m256i test_mm256_mask_add_epi16 (__m256i __W, __mmask16 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_add_epi16 + //CHECK: @llvm.x86.avx512.mask.padd.w.256 + return _mm256_mask_add_epi16(__W, __U , __A, __B); +} + +__m256i test_mm256_maskz_add_epi16 (__mmask16 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_add_epi16 + //CHECK: @llvm.x86.avx512.mask.padd.w.256 + return _mm256_maskz_add_epi16(__U , __A, __B); +} + +__m256i test_mm256_mask_sub_epi8 (__m256i __W, __mmask32 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_sub_epi8 + //CHECK: @llvm.x86.avx512.mask.psub.b.256 + return _mm256_mask_sub_epi8(__W, __U , __A, __B); +} + +__m256i test_mm256_maskz_sub_epi8 (__mmask32 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_sub_epi8 + //CHECK: @llvm.x86.avx512.mask.psub.b.256 + return _mm256_maskz_sub_epi8(__U , __A, __B); +} + +__m256i test_mm256_mask_sub_epi16 (__m256i __W, __mmask16 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_sub_epi16 + //CHECK: @llvm.x86.avx512.mask.psub.w.256 + return _mm256_mask_sub_epi16(__W, __U , __A, __B); +} + +__m256i test_mm256_maskz_sub_epi16 (__mmask16 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_sub_epi16 + //CHECK: @llvm.x86.avx512.mask.psub.w.256 + return _mm256_maskz_sub_epi16(__U , __A, __B); +} +__m128i test_mm_mask_add_epi8 (__m128i __W, __mmask16 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_add_epi8 + //CHECK: @llvm.x86.avx512.mask.padd.b.128 + return _mm_mask_add_epi8(__W, __U , __A, __B); +} + +__m128i test_mm_maskz_add_epi8 (__mmask16 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_add_epi8 + //CHECK: @llvm.x86.avx512.mask.padd.b.128 + return _mm_maskz_add_epi8(__U , __A, __B); +} + +__m128i test_mm_mask_add_epi16 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_add_epi16 + //CHECK: @llvm.x86.avx512.mask.padd.w.128 + return _mm_mask_add_epi16(__W, __U , __A, __B); +} + +__m128i test_mm_maskz_add_epi16 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_add_epi16 + //CHECK: @llvm.x86.avx512.mask.padd.w.128 + return _mm_maskz_add_epi16(__U , __A, __B); +} + +__m128i test_mm_mask_sub_epi8 (__m128i __W, __mmask16 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_sub_epi8 + //CHECK: @llvm.x86.avx512.mask.psub.b.128 + return _mm_mask_sub_epi8(__W, __U , __A, __B); +} + +__m128i test_mm_maskz_sub_epi8 (__mmask16 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_sub_epi8 + //CHECK: @llvm.x86.avx512.mask.psub.b.128 + return _mm_maskz_sub_epi8(__U , __A, __B); +} + +__m128i test_mm_mask_sub_epi16 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_sub_epi16 + //CHECK: @llvm.x86.avx512.mask.psub.w.128 + return _mm_mask_sub_epi16(__W, __U , __A, __B); +} + +__m128i test_mm_maskz_sub_epi16 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_sub_epi16 + //CHECK: @llvm.x86.avx512.mask.psub.w.128 + return _mm_maskz_sub_epi16(__U , __A, __B); +} + +__m256i test_mm256_mask_mullo_epi16 (__m256i __W, __mmask16 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_mask_mullo_epi16 + //CHECK: @llvm.x86.avx512.mask.pmull.w.256 + return _mm256_mask_mullo_epi16(__W, __U , __A, __B); +} + +__m256i test_mm256_maskz_mullo_epi16 (__mmask16 __U, __m256i __A, __m256i __B) { + //CHECK-LABEL: @test_mm256_maskz_mullo_epi16 + //CHECK: @llvm.x86.avx512.mask.pmull.w.256 + return _mm256_maskz_mullo_epi16(__U , __A, __B); +} + +__m128i test_mm_mask_mullo_epi16 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_mask_mullo_epi16 + //CHECK: @llvm.x86.avx512.mask.pmull.w.128 + return _mm_mask_mullo_epi16(__W, __U , __A, __B); +} + +__m128i test_mm_maskz_mullo_epi16 (__mmask8 __U, __m128i __A, __m128i __B) { + //CHECK-LABEL: @test_mm_maskz_mullo_epi16 + //CHECK: @llvm.x86.avx512.mask.pmull.w.128 + return _mm_maskz_mullo_epi16(__U , __A, __B); +} diff --git a/test/CodeGen/avx512vldq-builtins.c b/test/CodeGen/avx512vldq-builtins.c new file mode 100644 index 000000000000..a9b6dbfa6fc9 --- /dev/null +++ b/test/CodeGen/avx512vldq-builtins.c @@ -0,0 +1,231 @@ +// RUN: %clang_cc1 %s -O0 -triple=x86_64-apple-darwin -ffreestanding -target-feature +avx512dq -target-feature +avx512vl -emit-llvm -o - -Werror | FileCheck %s + +#include <immintrin.h> + +__m256i test_mm256_mullo_epi64 (__m256i __A, __m256i __B) { + // CHECK-LABEL: @test_mm256_mullo_epi64 + // CHECK: mul <4 x i64> + return _mm256_mullo_epi64(__A, __B); +} + +__m256i test_mm256_mask_mullo_epi64 (__m256i __W, __mmask8 __U, __m256i __A, __m256i __B) { + // CHECK-LABEL: @test_mm256_mask_mullo_epi64 + // CHECK: @llvm.x86.avx512.mask.pmull.q.256 + return (__m256i) _mm256_mask_mullo_epi64 ( __W, __U, __A, __B); +} + +__m256i test_mm256_maskz_mullo_epi64 (__mmask8 __U, __m256i __A, __m256i __B) { + // CHECK-LABEL: @test_mm256_maskz_mullo_epi64 + // CHECK: @llvm.x86.avx512.mask.pmull.q.256 + return (__m256i) _mm256_maskz_mullo_epi64 (__U, __A, __B); +} + +__m128i test_mm_mullo_epi64 (__m128i __A, __m128i __B) { + // CHECK-LABEL: @test_mm_mullo_epi64 + // CHECK: mul <2 x i64> + return (__m128i) _mm_mullo_epi64(__A, __B); +} + +__m128i test_mm_mask_mullo_epi64 (__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) { + // CHECK-LABEL: @test_mm_mask_mullo_epi64 + // CHECK: @llvm.x86.avx512.mask.pmull.q.128 + return (__m128i) _mm_mask_mullo_epi64 ( __W, __U, __A, __B); +} + +__m128i test_mm_maskz_mullo_epi64 (__mmask8 __U, __m128i __A, __m128i __B) { + // CHECK-LABEL: @test_mm_maskz_mullo_epi64 + // CHECK: @llvm.x86.avx512.mask.pmull.q.128 + return (__m128i) _mm_maskz_mullo_epi64 (__U, __A, __B); +} + +__m256d test_mm256_mask_andnot_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_mask_andnot_pd + // CHECK: @llvm.x86.avx512.mask.andn.pd.256 + return (__m256d) _mm256_mask_andnot_pd ( __W, __U, __A, __B); +} + +__m256d test_mm256_maskz_andnot_pd (__mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_maskz_andnot_pd + // CHECK: @llvm.x86.avx512.mask.andn.pd.256 + return (__m256d) _mm256_maskz_andnot_pd (__U, __A, __B); +} + +__m128d test_mm_mask_andnot_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_mask_andnot_pd + // CHECK: @llvm.x86.avx512.mask.andn.pd.128 + return (__m128d) _mm_mask_andnot_pd ( __W, __U, __A, __B); +} + +__m128d test_mm_maskz_andnot_pd (__mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_maskz_andnot_pd + // CHECK: @llvm.x86.avx512.mask.andn.pd.128 + return (__m128d) _mm_maskz_andnot_pd (__U, __A, __B); +} + +__m256 test_mm256_mask_andnot_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_mask_andnot_ps + // CHECK: @llvm.x86.avx512.mask.andn.ps.256 + return (__m256) _mm256_mask_andnot_ps ( __W, __U, __A, __B); +} + +__m256 test_mm256_maskz_andnot_ps (__mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_maskz_andnot_ps + // CHECK: @llvm.x86.avx512.mask.andn.ps.256 + return (__m256) _mm256_maskz_andnot_ps (__U, __A, __B); +} + +__m128 test_mm_mask_andnot_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_mask_andnot_ps + // CHECK: @llvm.x86.avx512.mask.andn.ps.128 + return (__m128) _mm_mask_andnot_ps ( __W, __U, __A, __B); +} + +__m128 test_mm_maskz_andnot_ps (__mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_maskz_andnot_ps + // CHECK: @llvm.x86.avx512.mask.andn.ps.128 + return (__m128) _mm_maskz_andnot_ps (__U, __A, __B); +} + +__m256d test_mm256_mask_and_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_mask_and_pd + // CHECK: @llvm.x86.avx512.mask.and.pd.256 + return (__m256d) _mm256_mask_and_pd ( __W, __U, __A, __B); +} + +__m256d test_mm256_maskz_and_pd (__mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_maskz_and_pd + // CHECK: @llvm.x86.avx512.mask.and.pd.256 + return (__m256d) _mm256_maskz_and_pd (__U, __A, __B); +} + +__m128d test_mm_mask_and_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_mask_and_pd + // CHECK: @llvm.x86.avx512.mask.and.pd.128 + return (__m128d) _mm_mask_and_pd ( __W, __U, __A, __B); +} + +__m128d test_mm_maskz_and_pd (__mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_maskz_and_pd + // CHECK: @llvm.x86.avx512.mask.and.pd.128 + return (__m128d) _mm_maskz_and_pd (__U, __A, __B); +} + +__m256 test_mm256_mask_and_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_mask_and_ps + // CHECK: @llvm.x86.avx512.mask.and.ps.256 + return (__m256) _mm256_mask_and_ps ( __W, __U, __A, __B); +} + +__m256 test_mm256_maskz_and_ps (__mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_maskz_and_ps + // CHECK: @llvm.x86.avx512.mask.and.ps.256 + return (__m256) _mm256_maskz_and_ps (__U, __A, __B); +} + +__m128 test_mm_mask_and_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_mask_and_ps + // CHECK: @llvm.x86.avx512.mask.and.ps.128 + return (__m128) _mm_mask_and_ps ( __W, __U, __A, __B); +} + +__m128 test_mm_maskz_and_ps (__mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_maskz_and_ps + // CHECK: @llvm.x86.avx512.mask.and.ps.128 + return (__m128) _mm_maskz_and_ps (__U, __A, __B); +} + +__m256d test_mm256_mask_xor_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_mask_xor_pd + // CHECK: @llvm.x86.avx512.mask.xor.pd.256 + return (__m256d) _mm256_mask_xor_pd ( __W, __U, __A, __B); +} + +__m256d test_mm256_maskz_xor_pd (__mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_maskz_xor_pd + // CHECK: @llvm.x86.avx512.mask.xor.pd.256 + return (__m256d) _mm256_maskz_xor_pd (__U, __A, __B); +} + +__m128d test_mm_mask_xor_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_mask_xor_pd + // CHECK: @llvm.x86.avx512.mask.xor.pd.128 + return (__m128d) _mm_mask_xor_pd ( __W, __U, __A, __B); +} + +__m128d test_mm_maskz_xor_pd (__mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_maskz_xor_pd + // CHECK: @llvm.x86.avx512.mask.xor.pd.128 + return (__m128d) _mm_maskz_xor_pd (__U, __A, __B); +} + +__m256 test_mm256_mask_xor_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_mask_xor_ps + // CHECK: @llvm.x86.avx512.mask.xor.ps.256 + return (__m256) _mm256_mask_xor_ps ( __W, __U, __A, __B); +} + +__m256 test_mm256_maskz_xor_ps (__mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_maskz_xor_ps + // CHECK: @llvm.x86.avx512.mask.xor.ps.256 + return (__m256) _mm256_maskz_xor_ps (__U, __A, __B); +} + +__m128 test_mm_mask_xor_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_mask_xor_ps + // CHECK: @llvm.x86.avx512.mask.xor.ps.128 + return (__m128) _mm_mask_xor_ps ( __W, __U, __A, __B); +} + +__m128 test_mm_maskz_xor_ps (__mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_maskz_xor_ps + // CHECK: @llvm.x86.avx512.mask.xor.ps.128 + return (__m128) _mm_maskz_xor_ps (__U, __A, __B); +} + +__m256d test_mm256_mask_or_pd (__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_mask_or_pd + // CHECK: @llvm.x86.avx512.mask.or.pd.256 + return (__m256d) _mm256_mask_or_pd ( __W, __U, __A, __B); +} + +__m256d test_mm256_maskz_or_pd (__mmask8 __U, __m256d __A, __m256d __B) { + // CHECK-LABEL: @test_mm256_maskz_or_pd + // CHECK: @llvm.x86.avx512.mask.or.pd.256 + return (__m256d) _mm256_maskz_or_pd (__U, __A, __B); +} + +__m128d test_mm_mask_or_pd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_mask_or_pd + // CHECK: @llvm.x86.avx512.mask.or.pd.128 + return (__m128d) _mm_mask_or_pd ( __W, __U, __A, __B); +} + +__m128d test_mm_maskz_or_pd (__mmask8 __U, __m128d __A, __m128d __B) { + // CHECK-LABEL: @test_mm_maskz_or_pd + // CHECK: @llvm.x86.avx512.mask.or.pd.128 + return (__m128d) _mm_maskz_or_pd (__U, __A, __B); +} + +__m256 test_mm256_mask_or_ps (__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_mask_or_ps + // CHECK: @llvm.x86.avx512.mask.or.ps.256 + return (__m256) _mm256_mask_or_ps ( __W, __U, __A, __B); +} + +__m256 test_mm256_maskz_or_ps (__mmask8 __U, __m256 __A, __m256 __B) { + // CHECK-LABEL: @test_mm256_maskz_or_ps + // CHECK: @llvm.x86.avx512.mask.or.ps.256 + return (__m256) _mm256_maskz_or_ps (__U, __A, __B); +} + +__m128 test_mm_mask_or_ps (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_mask_or_ps + // CHECK: @llvm.x86.avx512.mask.or.ps.128 + return (__m128) _mm_mask_or_ps ( __W, __U, __A, __B); +} + +__m128 test_mm_maskz_or_ps (__mmask8 __U, __m128 __A, __m128 __B) { + // CHECK-LABEL: @test_mm_maskz_or_ps + // CHECK: @llvm.x86.avx512.mask.or.ps.128 + return (__m128) _mm_maskz_or_ps(__U, __A, __B); +} diff --git a/test/CodeGen/big-atomic-ops.c b/test/CodeGen/big-atomic-ops.c index 74096616ace6..28b7b5d70822 100644 --- a/test/CodeGen/big-atomic-ops.c +++ b/test/CodeGen/big-atomic-ops.c @@ -16,13 +16,13 @@ typedef enum memory_order { int fi1(_Atomic(int) *i) { // CHECK: @fi1 - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst return __c11_atomic_load(i, memory_order_seq_cst); } int fi1a(int *i) { // CHECK: @fi1a - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst int v; __atomic_load(i, &v, memory_order_seq_cst); return v; @@ -30,7 +30,7 @@ int fi1a(int *i) { int fi1b(int *i) { // CHECK: @fi1b - // CHECK: load atomic i32* {{.*}} seq_cst + // CHECK: load atomic i32, i32* {{.*}} seq_cst return __atomic_load_n(i, memory_order_seq_cst); } @@ -113,7 +113,7 @@ _Bool fi4b(int *i) { float ff1(_Atomic(float) *d) { // CHECK: @ff1 - // CHECK: load atomic i32* {{.*}} monotonic + // CHECK: load atomic i32, i32* {{.*}} monotonic return __c11_atomic_load(d, memory_order_relaxed); } @@ -129,7 +129,7 @@ float ff3(_Atomic(float) *d) { int* fp1(_Atomic(int*) *p) { // CHECK: @fp1 - // CHECK: load atomic i64* {{.*}} seq_cst + // CHECK: load atomic i64, i64* {{.*}} seq_cst return __c11_atomic_load(p, memory_order_seq_cst); } diff --git a/test/CodeGen/block-byref-aggr.c b/test/CodeGen/block-byref-aggr.c index eed023956cd3..910f6da3cccd 100644 --- a/test/CodeGen/block-byref-aggr.c +++ b/test/CodeGen/block-byref-aggr.c @@ -16,12 +16,12 @@ void test0() { // CHECK: [[A:%.*]] = alloca [[BYREF:%.*]], align 8 // CHECK-NEXT: [[TEMP:%.*]] = alloca [[AGG]], align 4 // CHECK: [[RESULT:%.*]] = call i32 @makeAgg() -// CHECK-NEXT: [[T0:%.*]] = getelementptr [[AGG]]* [[TEMP]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr [[AGG]], [[AGG]]* [[TEMP]], i32 0, i32 0 // CHECK-NEXT: store i32 [[RESULT]], i32* [[T0]] // Check that we properly assign into the forwarding pointer. -// CHECK-NEXT: [[A_FORWARDING:%.*]] = getelementptr inbounds [[BYREF]]* [[A]], i32 0, i32 1 -// CHECK-NEXT: [[T0:%.*]] = load [[BYREF]]** [[A_FORWARDING]] -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[BYREF]]* [[T0]], i32 0, i32 4 +// CHECK-NEXT: [[A_FORWARDING:%.*]] = getelementptr inbounds [[BYREF]], [[BYREF]]* [[A]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = load [[BYREF]]*, [[BYREF]]** [[A_FORWARDING]] +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[BYREF]], [[BYREF]]* [[T0]], i32 0, i32 4 // CHECK-NEXT: [[T2:%.*]] = bitcast [[AGG]]* [[T1]] to i8* // CHECK-NEXT: [[T3:%.*]] = bitcast [[AGG]]* [[TEMP]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[T2]], i8* [[T3]], i64 4, i32 4, i1 false) @@ -42,19 +42,19 @@ void test1() { // CHECK-NEXT: [[B:%.*]] = alloca [[B_BYREF:%.*]], align 8 // CHECK-NEXT: [[TEMP:%.*]] = alloca [[AGG]], align 4 // CHECK: [[RESULT:%.*]] = call i32 @makeAgg() -// CHECK-NEXT: [[T0:%.*]] = getelementptr [[AGG]]* [[TEMP]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr [[AGG]], [[AGG]]* [[TEMP]], i32 0, i32 0 // CHECK-NEXT: store i32 [[RESULT]], i32* [[T0]] // Check that we properly assign into the forwarding pointer, first for b: -// CHECK-NEXT: [[B_FORWARDING:%.*]] = getelementptr inbounds [[B_BYREF]]* [[B]], i32 0, i32 1 -// CHECK-NEXT: [[T0:%.*]] = load [[B_BYREF]]** [[B_FORWARDING]] -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[B_BYREF]]* [[T0]], i32 0, i32 4 +// CHECK-NEXT: [[B_FORWARDING:%.*]] = getelementptr inbounds [[B_BYREF]], [[B_BYREF]]* [[B]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = load [[B_BYREF]]*, [[B_BYREF]]** [[B_FORWARDING]] +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[B_BYREF]], [[B_BYREF]]* [[T0]], i32 0, i32 4 // CHECK-NEXT: [[T2:%.*]] = bitcast [[AGG]]* [[T1]] to i8* // CHECK-NEXT: [[T3:%.*]] = bitcast [[AGG]]* [[TEMP]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[T2]], i8* [[T3]], i64 4, i32 4, i1 false) // Then for 'a': -// CHECK-NEXT: [[A_FORWARDING:%.*]] = getelementptr inbounds [[A_BYREF]]* [[A]], i32 0, i32 1 -// CHECK-NEXT: [[T0:%.*]] = load [[A_BYREF]]** [[A_FORWARDING]] -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[A_BYREF]]* [[T0]], i32 0, i32 4 +// CHECK-NEXT: [[A_FORWARDING:%.*]] = getelementptr inbounds [[A_BYREF]], [[A_BYREF]]* [[A]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = load [[A_BYREF]]*, [[A_BYREF]]** [[A_FORWARDING]] +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[A_BYREF]], [[A_BYREF]]* [[T0]], i32 0, i32 4 // CHECK-NEXT: [[T2:%.*]] = bitcast [[AGG]]* [[T1]] to i8* // CHECK-NEXT: [[T3:%.*]] = bitcast [[AGG]]* [[TEMP]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[T2]], i8* [[T3]], i64 4, i32 4, i1 false) diff --git a/test/CodeGen/blocks-opencl.cl b/test/CodeGen/blocks-opencl.cl index ab80f5eb7a2c..d3562988b738 100644 --- a/test/CodeGen/blocks-opencl.cl +++ b/test/CodeGen/blocks-opencl.cl @@ -6,7 +6,7 @@ void dummy(float (^op)(float)) { } -// CHECK: i8 addrspace(3)* getelementptr inbounds ([9 x i8] addrspace(3)* @.str, i32 0, i32 0) +// CHECK: i8 addrspace(3)* getelementptr inbounds ([9 x i8], [9 x i8] addrspace(3)* @.str, i32 0, i32 0) kernel void test_block() { diff --git a/test/CodeGen/blocks-seq.c b/test/CodeGen/blocks-seq.c index 8db9e606b1a0..b3e672976cab 100644 --- a/test/CodeGen/blocks-seq.c +++ b/test/CodeGen/blocks-seq.c @@ -1,11 +1,11 @@ // RUN: %clang_cc1 -fblocks -triple x86_64-apple-darwin10 -emit-llvm -o - %s | FileCheck %s // CHECK: [[Vi:%.+]] = alloca %struct.__block_byref_i, align 8 -// CHECK: call i32 (...)* @rhs() -// CHECK: [[V7:%.+]] = getelementptr inbounds %struct.__block_byref_i* [[Vi]], i32 0, i32 1 -// CHECK: load %struct.__block_byref_i** [[V7]] -// CHECK: call i32 (...)* @rhs() -// CHECK: [[V11:%.+]] = getelementptr inbounds %struct.__block_byref_i* [[Vi]], i32 0, i32 1 -// CHECK: load %struct.__block_byref_i** [[V11]] +// CHECK: call i32 (...) @rhs() +// CHECK: [[V7:%.+]] = getelementptr inbounds %struct.__block_byref_i, %struct.__block_byref_i* [[Vi]], i32 0, i32 1 +// CHECK: load %struct.__block_byref_i*, %struct.__block_byref_i** [[V7]] +// CHECK: call i32 (...) @rhs() +// CHECK: [[V11:%.+]] = getelementptr inbounds %struct.__block_byref_i, %struct.__block_byref_i* [[Vi]], i32 0, i32 1 +// CHECK: load %struct.__block_byref_i*, %struct.__block_byref_i** [[V11]] int rhs(); diff --git a/test/CodeGen/blocks.c b/test/CodeGen/blocks.c index 5871e8c2429c..2a8182691156 100644 --- a/test/CodeGen/blocks.c +++ b/test/CodeGen/blocks.c @@ -72,7 +72,7 @@ void (^b)() = ^{}; int main() { (b?: ^{})(); } -// CHECK: [[ZERO:%.*]] = load void (...)** @b +// CHECK: [[ZERO:%.*]] = load void (...)*, void (...)** @b // CHECK-NEXT: [[TB:%.*]] = icmp ne void (...)* [[ZERO]], null // CHECK-NEXT: br i1 [[TB]], label [[CT:%.*]], label [[CF:%.*]] // CHECK: [[ONE:%.*]] = bitcast void (...)* [[ZERO]] to void ()* diff --git a/test/CodeGen/blocksignature.c b/test/CodeGen/blocksignature.c index fd586eb1e139..a383960e560d 100644 --- a/test/CodeGen/blocksignature.c +++ b/test/CodeGen/blocksignature.c @@ -3,14 +3,14 @@ // X64: @.str = private unnamed_addr constant [6 x i8] c"v8@?0\00" // X64: @__block_literal_global = internal constant {{.*}} { i8** @_NSConcreteGlobalBlock, i32 1342177280, -// X64: @.str1 = private unnamed_addr constant [12 x i8] c"i16@?0c8f12\00" +// X64: @.str.1 = private unnamed_addr constant [12 x i8] c"i16@?0c8f12\00" // X64: store i32 1073741824, i32* // X32: [[STR1:@.*]] = private unnamed_addr constant [6 x i8] c"v4@?0\00" -// X32: @__block_descriptor_tmp = internal constant [[FULL_DESCRIPTOR_T:.*]] { i32 0, i32 20, i8* getelementptr inbounds ([6 x i8]* [[STR1]], i32 0, i32 0), i8* null } +// X32: @__block_descriptor_tmp = internal constant [[FULL_DESCRIPTOR_T:.*]] { i32 0, i32 20, i8* getelementptr inbounds ([6 x i8], [6 x i8]* [[STR1]], i32 0, i32 0), i8* null } // X32: @__block_literal_global = internal constant [[GLOBAL_LITERAL_T:.*]] { i8** @_NSConcreteGlobalBlock, i32 1342177280, i32 0, i8* bitcast (void (i8*)* @global_block_invoke{{.*}} to i8*), [[DESCRIPTOR_T:%.*]]* bitcast ([[FULL_DESCRIPTOR_T]]* @__block_descriptor_tmp to {{%.*}}*) } // X32: [[STR2:@.*]] = private unnamed_addr constant [11 x i8] c"i12@?0c4f8\00" -// X32: @__block_descriptor_tmp{{.*}} = internal constant [[FULL_DESCRIPTOR_T]] { i32 0, i32 24, i8* getelementptr inbounds ([11 x i8]* [[STR2]], i32 0, i32 0), i8* null } +// X32: @__block_descriptor_tmp{{.*}} = internal constant [[FULL_DESCRIPTOR_T]] { i32 0, i32 24, i8* getelementptr inbounds ([11 x i8], [11 x i8]* [[STR2]], i32 0, i32 0), i8* null } // X32: store i32 1073741824, i32* // rdar://7635294 diff --git a/test/CodeGen/bool_test.c b/test/CodeGen/bool_test.c index cf62dba1df21..b48da3748e60 100644 --- a/test/CodeGen/bool_test.c +++ b/test/CodeGen/bool_test.c @@ -9,7 +9,7 @@ void f(_Bool *x, _Bool *y) { } // CHECK-LABEL: define void @f( -// CHECK: [[FROMMEM:%.*]] = load i32* % +// CHECK: [[FROMMEM:%.*]] = load i32, i32* % // CHECK: [[BOOLVAL:%.*]] = trunc i32 [[FROMMEM]] to i1 // CHECK: [[TOMEM:%.*]] = zext i1 [[BOOLVAL]] to i32 // CHECK: store i32 [[TOMEM]] diff --git a/test/CodeGen/builtin-assume.c b/test/CodeGen/builtin-assume.c index 8411b729abf5..19afec69e787 100644 --- a/test/CodeGen/builtin-assume.c +++ b/test/CodeGen/builtin-assume.c @@ -1,25 +1,44 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple i386-mingw32 -fms-extensions -emit-llvm -o - %s | FileCheck %s +int nonconst(void); +int isconst(void) __attribute__((const)); +int ispure(void) __attribute__((pure)); + // CHECK-LABEL: @test1 int test1(int *a, int i) { // CHECK: store i32* %a, i32** [[A_ADDR:%.+]], align -// CHECK: [[A:%.+]] = load i32** [[A_ADDR]] +// CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]] // CHECK: [[CMP:%.+]] = icmp ne i32* [[A]], null // CHECK: call void @llvm.assume(i1 [[CMP]]) + +// CHECK: [[CALL:%.+]] = call i32 @isconst() +// CHECK: [[BOOL:%.+]] = icmp ne i32 [[CALL]], 0 +// CHECK: call void @llvm.assume(i1 [[BOOL]]) + +// CHECK: [[CALLPURE:%.+]] = call i32 @ispure() +// CHECK: [[BOOLPURE:%.+]] = icmp ne i32 [[CALLPURE]], 0 +// CHECK: call void @llvm.assume(i1 [[BOOLPURE]]) #ifdef _MSC_VER __assume(a != 0) + __assume(isconst()); + __assume(ispure()); #else __builtin_assume(a != 0); + __builtin_assume(isconst()); + __builtin_assume(ispure()); #endif // Nothing is generated for an assume with side effects... -// CHECK-NOT: load i32** %i.addr +// CHECK-NOT: load i32*, i32** %i.addr // CHECK-NOT: call void @llvm.assume +// CHECK-NOT: call i32 @nonconst() #ifdef _MSC_VER __assume(++i != 0) + __assume(nonconst()); #else __builtin_assume(++i != 0); + __builtin_assume(nonconst()); #endif return a[0]; diff --git a/test/CodeGen/builtin-expect.c b/test/CodeGen/builtin-expect.c index 664c6b6a470e..884110cbe905 100644 --- a/test/CodeGen/builtin-expect.c +++ b/test/CodeGen/builtin-expect.c @@ -1,10 +1,14 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -O0 | FileCheck %s --check-prefix=CHECK_O0 int x; int y(void); void foo(); void FUNC() { +// CHECK-LABEL: define void @FUNC() // CHECK: [[call:%.*]] = call i32 @y +// CHECK_O0: [[call:%.*]] = call i32 @y +// CHECK_O0-NOT: call i64 @llvm.expect if (__builtin_expect (x, y())) foo (); } @@ -17,21 +21,25 @@ int main() { (void) __builtin_expect((isigprocmask(), 0), bar()); } +// CHECK-LABEL: define i32 @main() // CHECK: call void @isigprocmask() -// CHECK: [[C:%.*]] = call i64 (...)* @bar() +// CHECK: [[C:%.*]] = call i64 (...) @bar() +// CHECK_O0: call void @isigprocmask() +// CHECK_O0: [[C:%.*]] = call i64 (...) @bar() +// CHECK_O0-NOT: call i64 @llvm.expect -// CHECK: @test1 +// CHECK-LABEL: define i32 @test1 int test1(int x) { -// CHECK: @llvm.expect +// CHECK_O0-NOT: call i64 @llvm.expect if (__builtin_expect (x, 1)) return 0; return x; } -// CHECK: @test2 +// CHECK: define i32 @test2 int test2(int x) { -// CHECK: @llvm.expect +// CHECK_O0-NOT: call i64 @llvm.expect switch(__builtin_expect(x, 5)) { default: return 0; diff --git a/test/CodeGen/builtin-nan-legacy.c b/test/CodeGen/builtin-nan-legacy.c new file mode 100644 index 000000000000..cd0f0fd14f14 --- /dev/null +++ b/test/CodeGen/builtin-nan-legacy.c @@ -0,0 +1,13 @@ +// RUN: %clang -target mipsel-unknown-linux -mnan=legacy -emit-llvm -S %s -o - | FileCheck %s +// CHECK: float 0x7FF4000000000000, float 0x7FF8000000000000 +// CHECK: double 0x7FF4000000000000, double 0x7FF8000000000000 + +float f[] = { + __builtin_nan(""), + __builtin_nans(""), +}; + +double d[] = { + __builtin_nan(""), + __builtin_nans(""), +}; diff --git a/test/CodeGen/builtins-ppc-crypto-disabled.c b/test/CodeGen/builtins-ppc-crypto-disabled.c new file mode 100644 index 000000000000..e6a8a9337aaf --- /dev/null +++ b/test/CodeGen/builtins-ppc-crypto-disabled.c @@ -0,0 +1,53 @@ +// REQUIRES: powerpc-registered-target +// RUN: not %clang_cc1 -faltivec -triple powerpc64le-unknown-unknown \ +// RUN: -target-cpu pwr8 -target-feature -crypto -emit-llvm %s -o - 2>&1 \ +// RUN: | FileCheck %s + +// RUN: not %clang_cc1 -faltivec -triple powerpc64-unknown-unknown \ +// RUN: -target-cpu pwr8 -target-feature -crypto -emit-llvm %s -o - 2>&1 \ +// RUN: | FileCheck %s + +// RUN: not %clang_cc1 -faltivec -triple powerpc64-unknown-unknown \ +// RUN: -target-cpu pwr8 -target-feature -power8-vector \ +// RUN: -target-feature -crypto -emit-llvm %s -o - 2>&1 \ +// RUN: | FileCheck %s -check-prefix=CHECK-P8V +#include <altivec.h> + +#define W_INIT1 { 0x01020304, 0x05060708, \ + 0x090A0B0C, 0x0D0E0F10 }; +#define D_INIT1 { 0x0102030405060708, \ + 0x090A0B0C0D0E0F10 }; +#define D_INIT2 { 0x7172737475767778, \ + 0x797A7B7C7D7E7F70 }; + +// Test cases for the builtins the way they are exposed to +// users through altivec.h +void call_crypto_intrinsics(void) +{ + vector unsigned int aw = W_INIT1 + vector unsigned long long ad = D_INIT1 + vector unsigned long long bd = D_INIT2 + vector unsigned long long cd = D_INIT2 + + vector unsigned long long r1 = __builtin_crypto_vsbox(ad); + vector unsigned long long r2 = __builtin_crypto_vcipher(ad, bd); + vector unsigned long long r3 = __builtin_crypto_vcipherlast(ad, bd); + vector unsigned long long r4 = __builtin_crypto_vncipher(ad, bd); + vector unsigned long long r5 = __builtin_crypto_vncipherlast(ad, bd); + vector unsigned int r6 = __builtin_crypto_vshasigmaw(aw, 1, 15); + vector unsigned long long r7 = __builtin_crypto_vshasigmad(ad, 0, 15); + + // The ones that do not require -mcrypto, but require -mpower8-vector + vector unsigned long long r8 = __builtin_crypto_vpmsumb(ad, bd); + vector unsigned long long r9 = __builtin_crypto_vpermxor(ad, bd, cd); +} + +// CHECK: use of unknown builtin '__builtin_crypto_vsbox' +// CHECK: use of unknown builtin '__builtin_crypto_vcipher' +// CHECK: use of unknown builtin '__builtin_crypto_vcipherlast' +// CHECK: use of unknown builtin '__builtin_crypto_vncipher' +// CHECK: use of unknown builtin '__builtin_crypto_vncipherlast' +// CHECK: use of unknown builtin '__builtin_crypto_vshasigmaw' +// CHECK: use of unknown builtin '__builtin_crypto_vshasigmad' +// CHECK-P8V: use of unknown builtin '__builtin_crypto_vpmsumb' +// CHECK-P8V: use of unknown builtin '__builtin_crypto_vpermxor' diff --git a/test/CodeGen/builtins-ppc-crypto.c b/test/CodeGen/builtins-ppc-crypto.c new file mode 100644 index 000000000000..0ade413cb6ae --- /dev/null +++ b/test/CodeGen/builtins-ppc-crypto.c @@ -0,0 +1,303 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -faltivec -triple powerpc64le-unknown-unknown \ +// RUN: -target-feature +crypto -target-feature +power8-vector \ +// RUN: -emit-llvm %s -o - | FileCheck %s + +// RUN: %clang_cc1 -faltivec -triple powerpc64-unknown-unknown \ +// RUN: -target-feature +crypto -target-feature +power8-vector \ +// RUN: -emit-llvm %s -o - | FileCheck %s + +// RUN: %clang_cc1 -faltivec -triple powerpc-unknown-unknown \ +// RUN: -target-feature +crypto -target-feature +power8-vector \ +// RUN: -emit-llvm %s -o - | FileCheck %s +#include <altivec.h> +#define B_INIT1 { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, \ + 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10 }; +#define B_INIT2 { 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, \ + 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x70 }; +#define H_INIT1 { 0x0102, 0x0304, 0x0506, 0x0708, \ + 0x090A, 0x0B0C, 0x0D0E, 0x0F10 }; +#define H_INIT2 { 0x7172, 0x7374, 0x7576, 0x7778, \ + 0x797A, 0x7B7C, 0x7D7E, 0x7F70 }; +#define W_INIT1 { 0x01020304, 0x05060708, \ + 0x090A0B0C, 0x0D0E0F10 }; +#define W_INIT2 { 0x71727374, 0x75767778, \ + 0x797A7B7C, 0x7D7E7F70 }; +#define D_INIT1 { 0x0102030405060708, \ + 0x090A0B0C0D0E0F10 }; +#define D_INIT2 { 0x7172737475767778, \ + 0x797A7B7C7D7E7F70 }; + +// CHECK-LABEL: define <16 x i8> @test_vpmsumb +vector unsigned char test_vpmsumb(void) +{ + vector unsigned char a = B_INIT1 + vector unsigned char b = B_INIT2 + return __builtin_altivec_crypto_vpmsumb(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumb +} + +// CHECK-LABEL: define <8 x i16> @test_vpmsumh +vector unsigned short test_vpmsumh(void) +{ + vector unsigned short a = H_INIT1 + vector unsigned short b = H_INIT2 + return __builtin_altivec_crypto_vpmsumh(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumh +} + +// CHECK-LABEL: define <4 x i32> @test_vpmsumw +vector unsigned int test_vpmsumw(void) +{ + vector unsigned int a = W_INIT1 + vector unsigned int b = W_INIT2 + return __builtin_altivec_crypto_vpmsumw(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumw +} + +// CHECK-LABEL: define <2 x i64> @test_vpmsumd +vector unsigned long long test_vpmsumd(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_altivec_crypto_vpmsumd(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumd +} + +// CHECK-LABEL: define <2 x i64> @test_vsbox +vector unsigned long long test_vsbox(void) +{ + vector unsigned long long a = D_INIT1 + return __builtin_altivec_crypto_vsbox(a); +// CHECK: @llvm.ppc.altivec.crypto.vsbox +} + +// CHECK-LABEL: define <16 x i8> @test_vpermxorb +vector unsigned char test_vpermxorb(void) +{ + vector unsigned char a = B_INIT1 + vector unsigned char b = B_INIT2 + vector unsigned char c = B_INIT2 + return __builtin_altivec_crypto_vpermxor(a, b, c); +// CHECK: @llvm.ppc.altivec.crypto.vpermxor +} + +// CHECK-LABEL: define <8 x i16> @test_vpermxorh +vector unsigned short test_vpermxorh(void) +{ + vector unsigned short a = H_INIT1 + vector unsigned short b = H_INIT2 + vector unsigned short c = H_INIT2 + return __builtin_altivec_crypto_vpermxor(a, b, c); +// CHECK: @llvm.ppc.altivec.crypto.vpermxor +} + +// CHECK-LABEL: define <4 x i32> @test_vpermxorw +vector unsigned int test_vpermxorw(void) +{ + vector unsigned int a = W_INIT1 + vector unsigned int b = W_INIT2 + vector unsigned int c = W_INIT2 + return __builtin_altivec_crypto_vpermxor(a, b, c); +// CHECK: @llvm.ppc.altivec.crypto.vpermxor +} + +// CHECK-LABEL: define <2 x i64> @test_vpermxord +vector unsigned long long test_vpermxord(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + vector unsigned long long c = D_INIT2 + return __builtin_altivec_crypto_vpermxor(a, b, c); +// CHECK: @llvm.ppc.altivec.crypto.vpermxor +} + +// CHECK-LABEL: define <2 x i64> @test_vcipher +vector unsigned long long test_vcipher(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_altivec_crypto_vcipher(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vcipher +} + +// CHECK-LABEL: define <2 x i64> @test_vcipherlast +vector unsigned long long test_vcipherlast(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_altivec_crypto_vcipherlast(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vcipherlast +} + +// CHECK: @llvm.ppc.altivec.crypto.vncipher +vector unsigned long long test_vncipher(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_altivec_crypto_vncipher(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vncipher +} + +// CHECK-LABEL: define <2 x i64> @test_vncipherlast +vector unsigned long long test_vncipherlast(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_altivec_crypto_vncipherlast(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vncipherlast +} + +// CHECK-LABEL: define <4 x i32> @test_vshasigmaw +vector unsigned int test_vshasigmaw(void) +{ + vector unsigned int a = W_INIT1 + return __builtin_altivec_crypto_vshasigmaw(a, 1, 15); +// CHECK: @llvm.ppc.altivec.crypto.vshasigmaw +} + +// CHECK-LABEL: define <2 x i64> @test_vshasigmad +vector unsigned long long test_vshasigmad(void) +{ + vector unsigned long long a = D_INIT2 + return __builtin_altivec_crypto_vshasigmad(a, 1, 15); +// CHECK: @llvm.ppc.altivec.crypto.vshasigmad +} + +// Test cases for the builtins the way they are exposed to +// users through altivec.h +// CHECK-LABEL: define <16 x i8> @test_vpmsumb_e +vector unsigned char test_vpmsumb_e(void) +{ + vector unsigned char a = B_INIT1 + vector unsigned char b = B_INIT2 + return __builtin_crypto_vpmsumb(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumb +} + +// CHECK-LABEL: define <8 x i16> @test_vpmsumh_e +vector unsigned short test_vpmsumh_e(void) +{ + vector unsigned short a = H_INIT1 + vector unsigned short b = H_INIT2 + return __builtin_crypto_vpmsumb(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumh +} + +// CHECK-LABEL: define <4 x i32> @test_vpmsumw_e +vector unsigned int test_vpmsumw_e(void) +{ + vector unsigned int a = W_INIT1 + vector unsigned int b = W_INIT2 + return __builtin_crypto_vpmsumb(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumw +} + +// CHECK-LABEL: define <2 x i64> @test_vpmsumd_e +vector unsigned long long test_vpmsumd_e(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_crypto_vpmsumb(a, b); +// CHECK @llvm.ppc.altivec.crypto.vpmsumd +} + +// CHECK-LABEL: define <2 x i64> @test_vsbox_e +vector unsigned long long test_vsbox_e(void) +{ + vector unsigned long long a = D_INIT1 + return __builtin_crypto_vsbox(a); +// CHECK: @llvm.ppc.altivec.crypto.vsbox +} + +// CHECK-LABEL: define <16 x i8> @test_vpermxorb_e +vector unsigned char test_vpermxorb_e(void) +{ + vector unsigned char a = B_INIT1 + vector unsigned char b = B_INIT2 + vector unsigned char c = B_INIT2 + return __builtin_crypto_vpermxor(a, b, c); +// CHECK: @llvm.ppc.altivec.crypto.vpermxor +} + +// CHECK-LABEL: define <8 x i16> @test_vpermxorh_e +vector unsigned short test_vpermxorh_e(void) +{ + vector unsigned short a = H_INIT1 + vector unsigned short b = H_INIT2 + vector unsigned short c = H_INIT2 + return __builtin_crypto_vpermxor(a, b, c); +} + +// CHECK-LABEL: define <4 x i32> @test_vpermxorw_e +vector unsigned int test_vpermxorw_e(void) +{ + vector unsigned int a = W_INIT1 + vector unsigned int b = W_INIT2 + vector unsigned int c = W_INIT2 + return __builtin_crypto_vpermxor(a, b, c); +// CHECK: @llvm.ppc.altivec.crypto.vpermxor +} + +// CHECK-LABEL: define <2 x i64> @test_vpermxord_e +vector unsigned long long test_vpermxord_e(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + vector unsigned long long c = D_INIT2 + return __builtin_crypto_vpermxor(a, b, c); +// CHECK: @llvm.ppc.altivec.crypto.vpermxor +} + +// CHECK-LABEL: define <2 x i64> @test_vcipher_e +vector unsigned long long test_vcipher_e(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_crypto_vcipher(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vcipher +} + +// CHECK-LABEL: define <2 x i64> @test_vcipherlast_e +vector unsigned long long test_vcipherlast_e(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_crypto_vcipherlast(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vcipherlast +} + +// CHECK-LABEL: define <2 x i64> @test_vncipher_e +vector unsigned long long test_vncipher_e(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_crypto_vncipher(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vncipher +} + +// CHECK-LABEL: define <2 x i64> @test_vncipherlast_e +vector unsigned long long test_vncipherlast_e(void) +{ + vector unsigned long long a = D_INIT1 + vector unsigned long long b = D_INIT2 + return __builtin_crypto_vncipherlast(a, b); +// CHECK: @llvm.ppc.altivec.crypto.vncipherlast +} + +// CHECK-LABEL: define <4 x i32> @test_vshasigmaw_e +vector unsigned int test_vshasigmaw_e(void) +{ + vector unsigned int a = W_INIT1 + return __builtin_crypto_vshasigmaw(a, 1, 15); +// CHECK: @llvm.ppc.altivec.crypto.vshasigmaw +} + +// CHECK-LABEL: define <2 x i64> @test_vshasigmad_e +vector unsigned long long test_vshasigmad_e(void) +{ + vector unsigned long long a = D_INIT2 + return __builtin_crypto_vshasigmad(a, 0, 15); +// CHECK: @llvm.ppc.altivec.crypto.vshasigmad +} + diff --git a/test/CodeGen/builtins-ppc-htm.c b/test/CodeGen/builtins-ppc-htm.c new file mode 100644 index 000000000000..87baa77af81f --- /dev/null +++ b/test/CodeGen/builtins-ppc-htm.c @@ -0,0 +1,62 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -faltivec -target-feature +htm -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s + +void test1(long int *r, int code, long int *a, long int *b) { +// CHECK-LABEL: define void @test1 + + r[0] = __builtin_tbegin (0); +// CHECK: @llvm.ppc.tbegin + r[1] = __builtin_tbegin (1); +// CHECK: @llvm.ppc.tbegin + r[2] = __builtin_tend (0); +// CHECK: @llvm.ppc.tend + r[3] = __builtin_tendall (); +// CHECK: @llvm.ppc.tendall + + r[4] = __builtin_tabort (code); +// CHECK: @llvm.ppc.tabort + r[5] = __builtin_tabort (0x1); +// CHECK: @llvm.ppc.tabort + r[6] = __builtin_tabortdc (0xf, a[0], b[0]); +// CHECK: @llvm.ppc.tabortdc + r[7] = __builtin_tabortdci (0xf, a[1], 0x1); +// CHECK: @llvm.ppc.tabortdc + r[8] = __builtin_tabortwc (0xf, a[2], b[2]); +// CHECK: @llvm.ppc.tabortwc + r[9] = __builtin_tabortwci (0xf, a[3], 0x1); +// CHECK: @llvm.ppc.tabortwc + + r[10] = __builtin_tcheck (); +// CHECK: @llvm.ppc.tcheck + r[11] = __builtin_trechkpt (); +// CHECK: @llvm.ppc.trechkpt + r[12] = __builtin_treclaim (0); +// CHECK: @llvm.ppc.treclaim + r[13] = __builtin_tresume (); +// CHECK: @llvm.ppc.tresume + r[14] = __builtin_tsuspend (); +// CHECK: @llvm.ppc.tsuspend + r[15] = __builtin_tsr (0); +// CHECK: @llvm.ppc.tsr + + r[16] = __builtin_ttest (); +// CHECK: @llvm.ppc.ttest + + r[17] = __builtin_get_texasr (); +// CHECK: @llvm.ppc.get.texasr + r[18] = __builtin_get_texasru (); +// CHECK: @llvm.ppc.get.texasru + r[19] = __builtin_get_tfhar (); +// CHECK: @llvm.ppc.get.tfhar + r[20] = __builtin_get_tfiar (); +// CHECK: @llvm.ppc.get.tfiar + + __builtin_set_texasr (a[21]); +// CHECK: @llvm.ppc.set.texasr + __builtin_set_texasru (a[22]); +// CHECK: @llvm.ppc.set.texasru + __builtin_set_tfhar (a[23]); +// CHECK: @llvm.ppc.set.tfhar + __builtin_set_tfiar (a[24]); +// CHECK: @llvm.ppc.set.tfiar +} diff --git a/test/CodeGen/builtins-ppc-p7-disabled.c b/test/CodeGen/builtins-ppc-p7-disabled.c new file mode 100644 index 000000000000..9ccedd2ce894 --- /dev/null +++ b/test/CodeGen/builtins-ppc-p7-disabled.c @@ -0,0 +1,33 @@ +// REQUIRES: powerpc-registered-target +// RUN: not %clang_cc1 -triple powerpc64-unknown-unknown \ +// RUN: -target-cpu pwr6 -emit-llvm %s -o - 2>&1 \ +// RUN: | FileCheck %s + +// RUN: not %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - 2>&1 \ +// RUN: -target-cpu pwr7 | FileCheck %s -check-prefix=CHECK-32 + +void call_p7_builtins(void) +{ + int a = __builtin_divwe(33, 11); + unsigned int b = __builtin_divweu(33U, 11U); + unsigned long long d = __builtin_divde(33ULL, 11ULL); + unsigned long long e = __builtin_divdeu(33ULL, 11ULL); + unsigned long long f = __builtin_bpermd(33ULL, 11ULL); +} + +// CHECK: error: this builtin is only valid on POWER7 or later CPUs +// CHECK: __builtin_divwe +// CHECK: error: this builtin is only valid on POWER7 or later CPUs +// CHECK: __builtin_divweu +// CHECK: error: this builtin is only valid on POWER7 or later CPUs +// CHECK: __builtin_divde +// CHECK: error: this builtin is only valid on POWER7 or later CPUs +// CHECK: __builtin_divdeu +// CHECK: error: this builtin is only valid on POWER7 or later CPUs +// CHECK: __builtin_bpermd +// CHECK-32: error: this builtin is only available on 64-bit targets +// CHECK-32: __builtin_divde +// CHECK-32: error: this builtin is only available on 64-bit targets +// CHECK-32: __builtin_divdeu +// CHECK-32: error: this builtin is only available on 64-bit targets +// CHECK-32: __builtin_bpermd diff --git a/test/CodeGen/builtins-ppc-p7.c b/test/CodeGen/builtins-ppc-p7.c new file mode 100644 index 000000000000..f58441030808 --- /dev/null +++ b/test/CodeGen/builtins-ppc-p7.c @@ -0,0 +1,52 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr7 \ +// RUN: -emit-llvm %s -o - | FileCheck %s + +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr8 \ +// RUN: -emit-llvm %s -o - | FileCheck %s + +// CHECK-LABEL: define signext i32 @test_divwe +int test_divwe(void) +{ + int a = 74; + int b = 32; + return __builtin_divwe(a, b); +// CHECK @llvm.ppc.divwe +} + +// CHECK-LABEL: define zeroext i32 @test_divweu +unsigned int test_divweu(void) +{ + unsigned int a = 74; + unsigned int b = 32; + return __builtin_divweu(a, b); +// CHECK @llvm.ppc.divweu +} + +// CHECK-LABEL: define i64 @test_divde +long long test_divde(void) +{ + long long a = 74LL; + long long b = 32LL; + return __builtin_divde(a, b); +// CHECK @llvm.ppc.divde +} + +// CHECK-LABEL: define i64 @test_divdeu +unsigned long long test_divdeu(void) +{ + unsigned long long a = 74ULL; + unsigned long long b = 32ULL; + return __builtin_divdeu(a, b); +// CHECK @llvm.ppc.divdeu +} + +// CHECK-LABEL: define i64 @test_bpermd +long long test_bpermd(void) +{ + long long a = 74LL; + long long b = 32LL; + return __builtin_bpermd(a, b); +// CHECK @llvm.ppc.bpermd +} + diff --git a/test/CodeGen/builtins-ppc-p8vector.c b/test/CodeGen/builtins-ppc-p8vector.c new file mode 100644 index 000000000000..c91686c0ea7c --- /dev/null +++ b/test/CodeGen/builtins-ppc-p8vector.c @@ -0,0 +1,698 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -faltivec -target-feature +power8-vector -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -faltivec -target-feature +power8-vector -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE +// RUN: not %clang_cc1 -faltivec -triple powerpc64-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC + +vector int vi = { -1, 2, -3, 4 }; +vector unsigned int vui = { 1, 2, 3, 4 }; +vector bool int vbi = {0, -1, -1, 0}; +vector bool long long vbll = { 1, 0 }; +vector long long vll = { 1, 2 }; +vector unsigned long long vull = { 1, 2 }; + +int res_i; +vector int res_vi; +vector unsigned int res_vui; +vector bool int res_vbi; +vector long long res_vll; +vector unsigned long long res_vull; +vector bool long long res_vbll; + +// CHECK-LABEL: define void @test1 +void test1() { + + /* vec_cmpeq */ + res_vbll = vec_cmpeq(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd +// CHECK-LE: @llvm.ppc.altivec.vcmpequd +// CHECK-PPC: error: call to 'vec_cmpeq' is ambiguous + + res_vbll = vec_cmpeq(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd +// CHECK-LE: @llvm.ppc.altivec.vcmpequd +// CHECK-PPC: error: call to 'vec_cmpeq' is ambiguous + + /* vec_cmpgt */ + res_vbll = vec_cmpgt(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd +// CHECK-PPC: error: call to 'vec_cmpgt' is ambiguous + + res_vbll = vec_cmpgt(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud +// CHECK-PPC: error: call to 'vec_cmpgt' is ambiguous + + /* ----------------------- predicates --------------------------- */ + /* vec_all_eq */ + res_i = vec_all_eq(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_eq' is ambiguous + + res_i = vec_all_eq(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_eq' is ambiguous + + res_i = vec_all_eq(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_eq' is ambiguous + + res_i = vec_all_eq(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_eq' is ambiguous + + res_i = vec_all_eq(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_eq' is ambiguous + + res_i = vec_all_eq(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_eq' is ambiguous + + res_i = vec_all_eq(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_eq' is ambiguous + + /* vec_all_ne */ + res_i = vec_all_ne(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_ne' is ambiguous + + res_i = vec_all_ne(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_ne' is ambiguous + + res_i = vec_all_ne(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_ne' is ambiguous + + res_i = vec_all_ne(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_ne' is ambiguous + + res_i = vec_all_ne(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_ne' is ambiguous + + res_i = vec_all_ne(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_ne' is ambiguous + + res_i = vec_all_ne(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_all_ne' is ambiguous + + /* vec_any_eq */ + res_i = vec_any_eq(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_eq' is ambiguous + + res_i = vec_any_eq(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_eq' is ambiguous + + res_i = vec_any_eq(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_eq' is ambiguous + + res_i = vec_any_eq(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_eq' is ambiguous + + res_i = vec_any_eq(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_eq' is ambiguous + + res_i = vec_any_eq(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_eq' is ambiguous + + res_i = vec_any_eq(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_eq' is ambiguous + + /* vec_any_ne */ + res_i = vec_any_ne(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_ne' is ambiguous + + res_i = vec_any_ne(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_ne' is ambiguous + + res_i = vec_any_ne(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_ne' is ambiguous + + res_i = vec_any_ne(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_ne' is ambiguous + + res_i = vec_any_ne(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_ne' is ambiguous + + res_i = vec_any_ne(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_ne' is ambiguous + + res_i = vec_any_ne(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpequd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpequd.p +// CHECK-PPC: error: call to 'vec_any_ne' is ambiguous + + /* vec_all_ge */ + res_i = vec_all_ge(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_ge' is ambiguous + + res_i = vec_all_ge(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_ge' is ambiguous + + res_i = vec_all_ge(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_ge' is ambiguous + + res_i = vec_all_ge(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_ge' is ambiguous + + res_i = vec_all_ge(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_ge' is ambiguous + + res_i = vec_all_ge(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_ge' is ambiguous + + res_i = vec_all_ge(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_ge' is ambiguous + + /* vec_all_gt */ + res_i = vec_all_gt(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_gt' is ambiguous + + res_i = vec_all_gt(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_gt' is ambiguous + + res_i = vec_all_gt(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_gt' is ambiguous + + res_i = vec_all_gt(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_gt' is ambiguous + + res_i = vec_all_gt(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_gt' is ambiguous + + res_i = vec_all_gt(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_gt' is ambiguous + + res_i = vec_all_gt(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_gt' is ambiguous + + /* vec_all_le */ + res_i = vec_all_le(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_le' is ambiguous + + res_i = vec_all_le(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_le' is ambiguous + + res_i = vec_all_le(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_le' is ambiguous + + res_i = vec_all_le(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_le' is ambiguous + + res_i = vec_all_le(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_le' is ambiguous + + res_i = vec_all_le(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_le' is ambiguous + + res_i = vec_all_le(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_le' is ambiguous + + /* vec_all_lt */ + res_i = vec_all_lt(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_lt' is ambiguous + + res_i = vec_all_lt(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_all_lt' is ambiguous + + res_i = vec_all_lt(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_lt' is ambiguous + + res_i = vec_all_lt(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_lt' is ambiguous + + res_i = vec_all_lt(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_lt' is ambiguous + + res_i = vec_all_lt(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_lt' is ambiguous + + res_i = vec_all_lt(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_all_lt' is ambiguous + + /* vec_any_ge */ + res_i = vec_any_ge(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_ge' is ambiguous + + res_i = vec_any_ge(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_ge' is ambiguous + + res_i = vec_any_ge(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_ge' is ambiguous + + res_i = vec_any_ge(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_ge' is ambiguous + + res_i = vec_any_ge(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_ge' is ambiguous + + res_i = vec_any_ge(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_ge' is ambiguous + + res_i = vec_any_ge(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_ge' is ambiguous + + /* vec_any_gt */ + res_i = vec_any_gt(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_gt' is ambiguous + + res_i = vec_any_gt(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_gt' is ambiguous + + res_i = vec_any_gt(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_gt' is ambiguous + + res_i = vec_any_gt(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_gt' is ambiguous + + res_i = vec_any_gt(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_gt' is ambiguous + + res_i = vec_any_gt(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_gt' is ambiguous + + res_i = vec_any_gt(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_gt' is ambiguous + + /* vec_any_le */ + res_i = vec_any_le(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_le' is ambiguous + + res_i = vec_any_le(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_le' is ambiguous + + res_i = vec_any_le(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_le' is ambiguous + + res_i = vec_any_le(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_le' is ambiguous + + res_i = vec_any_le(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_le' is ambiguous + + res_i = vec_any_le(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_le' is ambiguous + + res_i = vec_any_le(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_le' is ambiguous + + /* vec_any_lt */ + res_i = vec_any_lt(vll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_lt' is ambiguous + + res_i = vec_any_lt(vll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtsd.p +// CHECK-PPC: error: call to 'vec_any_lt' is ambiguous + + res_i = vec_any_lt(vull, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_lt' is ambiguous + + res_i = vec_any_lt(vull, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_lt' is ambiguous + + res_i = vec_any_lt(vbll, vll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_lt' is ambiguous + + res_i = vec_any_lt(vbll, vull); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_lt' is ambiguous + + res_i = vec_any_lt(vbll, vbll); +// CHECK: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-LE: @llvm.ppc.altivec.vcmpgtud.p +// CHECK-PPC: error: call to 'vec_any_lt' is ambiguous + + /* vec_max */ + res_vll = vec_max(vll, vll); +// CHECK: @llvm.ppc.altivec.vmaxsd +// CHECK-LE: @llvm.ppc.altivec.vmaxsd +// CHECK-PPC: error: call to 'vec_max' is ambiguous + + res_vll = vec_max(vbll, vll); +// CHECK: @llvm.ppc.altivec.vmaxsd +// CHECK-LE: @llvm.ppc.altivec.vmaxsd +// CHECK-PPC: error: call to 'vec_max' is ambiguous + + res_vll = vec_max(vll, vbll); +// CHECK: @llvm.ppc.altivec.vmaxsd +// CHECK-LE: @llvm.ppc.altivec.vmaxsd +// CHECK-PPC: error: call to 'vec_max' is ambiguous + + res_vull = vec_max(vull, vull); +// CHECK: @llvm.ppc.altivec.vmaxud +// CHECK-LE: @llvm.ppc.altivec.vmaxud +// CHECK-PPC: error: call to 'vec_max' is ambiguous + + res_vull = vec_max(vbll, vull); +// CHECK: @llvm.ppc.altivec.vmaxud +// CHECK-LE: @llvm.ppc.altivec.vmaxud +// CHECK-PPC: error: call to 'vec_max' is ambiguous + + res_vull = vec_max(vull, vbll); +// CHECK: @llvm.ppc.altivec.vmaxud +// CHECK-LE: @llvm.ppc.altivec.vmaxud +// CHECK-PPC: error: call to 'vec_max' is ambiguous + + /* vec_min */ + res_vll = vec_min(vll, vll); +// CHECK: @llvm.ppc.altivec.vminsd +// CHECK-LE: @llvm.ppc.altivec.vminsd +// CHECK-PPC: error: call to 'vec_min' is ambiguous + + res_vll = vec_min(vbll, vll); +// CHECK: @llvm.ppc.altivec.vminsd +// CHECK-LE: @llvm.ppc.altivec.vminsd +// CHECK-PPC: error: call to 'vec_min' is ambiguous + + res_vll = vec_min(vll, vbll); +// CHECK: @llvm.ppc.altivec.vminsd +// CHECK-LE: @llvm.ppc.altivec.vminsd +// CHECK-PPC: error: call to 'vec_min' is ambiguous + + res_vull = vec_min(vull, vull); +// CHECK: @llvm.ppc.altivec.vminud +// CHECK-LE: @llvm.ppc.altivec.vminud +// CHECK-PPC: error: call to 'vec_min' is ambiguous + + res_vull = vec_min(vbll, vull); +// CHECK: @llvm.ppc.altivec.vminud +// CHECK-LE: @llvm.ppc.altivec.vminud +// CHECK-PPC: error: call to 'vec_min' is ambiguous + + res_vull = vec_min(vull, vbll); +// CHECK: @llvm.ppc.altivec.vminud +// CHECK-LE: @llvm.ppc.altivec.vminud +// CHECK-PPC: error: call to 'vec_min' is ambiguous + + /* vec_mule */ + res_vll = vec_mule(vi, vi); +// CHECK: @llvm.ppc.altivec.vmulesw +// CHECK-LE: @llvm.ppc.altivec.vmulosw +// CHECK-PPC: error: call to 'vec_mule' is ambiguous + + res_vull = vec_mule(vui , vui); +// CHECK: @llvm.ppc.altivec.vmuleuw +// CHECK-LE: @llvm.ppc.altivec.vmulouw +// CHECK-PPC: error: call to 'vec_mule' is ambiguous + + /* vec_mulo */ + res_vll = vec_mulo(vi, vi); +// CHECK: @llvm.ppc.altivec.vmulosw +// CHECK-LE: @llvm.ppc.altivec.vmulesw +// CHECK-PPC: error: call to 'vec_mulo' is ambiguous + + res_vull = vec_mulo(vui, vui); +// CHECK: @llvm.ppc.altivec.vmulouw +// CHECK-LE: @llvm.ppc.altivec.vmuleuw +// CHECK-PPC: error: call to 'vec_mulo' is ambiguous + + /* vec_packs */ + res_vi = vec_packs(vll, vll); +// CHECK: @llvm.ppc.altivec.vpksdss +// CHECK-LE: @llvm.ppc.altivec.vpksdss +// CHECK-PPC: error: call to 'vec_packs' is ambiguous + + res_vui = vec_packs(vull, vull); +// CHECK: @llvm.ppc.altivec.vpkudus +// CHECK-LE: @llvm.ppc.altivec.vpkudus +// CHECK-PPC: error: call to 'vec_packs' is ambiguous + + /* vec_packsu */ + res_vui = vec_packsu(vll, vll); +// CHECK: @llvm.ppc.altivec.vpksdus +// CHECK-LE: @llvm.ppc.altivec.vpksdus +// CHECK-PPC: error: call to 'vec_packsu' is ambiguous + + res_vui = vec_packsu(vull, vull); +// CHECK: @llvm.ppc.altivec.vpkudus +// CHECK-LE: @llvm.ppc.altivec.vpkudus +// CHECK-PPC: error: call to 'vec_packsu' is ambiguous + + /* vec_rl */ + res_vll = vec_rl(vll, vull); +// CHECK: @llvm.ppc.altivec.vrld +// CHECK-LE: @llvm.ppc.altivec.vrld +// CHECK-PPC: error: call to 'vec_rl' is ambiguous + + res_vull = vec_rl(vull, vull); +// CHECK: @llvm.ppc.altivec.vrld +// CHECK-LE: @llvm.ppc.altivec.vrld +// CHECK-PPC: error: call to 'vec_rl' is ambiguous + + /* vec_sl */ + res_vll = vec_sl(vll, vull); +// CHECK: shl <2 x i64> +// CHECK-LE: shl <2 x i64> +// CHECK-PPC: error: call to 'vec_sl' is ambiguous + + res_vull = vec_sl(vull, vull); +// CHECK: shl <2 x i64> +// CHECK-LE: shl <2 x i64> +// CHECK-PPC: error: call to 'vec_sl' is ambiguous + + /* vec_sr */ + res_vll = vec_sr(vll, vull); +// CHECK: ashr <2 x i64> +// CHECK-LE: ashr <2 x i64> +// CHECK-PPC: error: call to 'vec_sr' is ambiguous + + res_vull = vec_sr(vull, vull); +// CHECK: lshr <2 x i64> +// CHECK-LE: lshr <2 x i64> +// CHECK-PPC: error: call to 'vec_sr' is ambiguous + + /* vec_sra */ + res_vll = vec_sra(vll, vull); +// CHECK: ashr <2 x i64> +// CHECK-LE: ashr <2 x i64> +// CHECK-PPC: error: call to 'vec_sra' is ambiguous + + res_vull = vec_sra(vull, vull); +// CHECK: ashr <2 x i64> +// CHECK-LE: ashr <2 x i64> +// CHECK-PPC: error: call to 'vec_sra' is ambiguous + + /* vec_unpackh */ + res_vll = vec_unpackh(vi); +// CHECK: llvm.ppc.altivec.vupkhsw +// CHECK-LE: llvm.ppc.altivec.vupklsw +// CHECK-PPC: error: call to 'vec_unpackh' is ambiguous + + res_vbll = vec_unpackh(vbi); +// CHECK: llvm.ppc.altivec.vupkhsw +// CHECK-LE: llvm.ppc.altivec.vupklsw +// CHECK-PPC: error: call to 'vec_unpackh' is ambiguous + + /* vec_unpackl */ + res_vll = vec_unpackl(vi); +// CHECK: llvm.ppc.altivec.vupklsw +// CHECK-LE: llvm.ppc.altivec.vupkhsw +// CHECK-PPC: error: call to 'vec_unpackl' is ambiguous + + res_vbll = vec_unpackl(vbi); +// CHECK: llvm.ppc.altivec.vupklsw +// CHECK-LE: llvm.ppc.altivec.vupkhsw +// CHECK-PPC: error: call to 'vec_unpackl' is ambiguous + + /* vec_vpksdss */ + res_vi = vec_vpksdss(vll, vll); +// CHECK: llvm.ppc.altivec.vpksdss +// CHECK-LE: llvm.ppc.altivec.vpksdss +// CHECK-PPC: warning: implicit declaration of function 'vec_vpksdss' + + /* vec_vpksdus */ + res_vui = vec_vpksdus(vll, vll); +// CHECK: llvm.ppc.altivec.vpksdus +// CHECK-LE: llvm.ppc.altivec.vpksdus +// CHECK-PPC: warning: implicit declaration of function 'vec_vpksdus' + + /* vec_vpkudum */ + res_vi = vec_vpkudum(vll, vll); +// CHECK: vperm +// CHECK-LE: vperm +// CHECK-PPC: warning: implicit declaration of function 'vec_vpkudum' + + res_vui = vec_vpkudum(vull, vull); +// CHECK: vperm +// CHECK-LE: vperm + + res_vui = vec_vpkudus(vull, vull); +// CHECK: llvm.ppc.altivec.vpkudus +// CHECK-LE: llvm.ppc.altivec.vpkudus +// CHECK-PPC: warning: implicit declaration of function 'vec_vpkudus' + + /* vec_vupkhsw */ + res_vll = vec_vupkhsw(vi); +// CHECK: llvm.ppc.altivec.vupkhsw +// CHECK-LE: llvm.ppc.altivec.vupklsw +// CHECK-PPC: warning: implicit declaration of function 'vec_vupkhsw' + + res_vbll = vec_vupkhsw(vbi); +// CHECK: llvm.ppc.altivec.vupkhsw +// CHECK-LE: llvm.ppc.altivec.vupklsw + + /* vec_vupklsw */ + res_vll = vec_vupklsw(vi); +// CHECK: llvm.ppc.altivec.vupklsw +// CHECK-LE: llvm.ppc.altivec.vupkhsw +// CHECK-PPC: warning: implicit declaration of function 'vec_vupklsw' + + res_vbll = vec_vupklsw(vbi); +// CHECK: llvm.ppc.altivec.vupklsw +// CHECK-LE: llvm.ppc.altivec.vupkhsw + +} diff --git a/test/CodeGen/builtins-ppc-quadword.c b/test/CodeGen/builtins-ppc-quadword.c new file mode 100644 index 000000000000..e17b6791d5f6 --- /dev/null +++ b/test/CodeGen/builtins-ppc-quadword.c @@ -0,0 +1,159 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -faltivec -target-feature +power8-vector \ +// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s + +// RUN: %clang_cc1 -faltivec -target-feature +power8-vector \ +// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix=CHECK-LE + +// RUN: not %clang_cc1 -faltivec -triple powerpc-unknown-unknown \ +// RUN: -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC + +// CHECK-PPC: error: __int128 is not supported on this target +vector signed __int128 vlll = { -1 }; +// CHECK-PPC: error: __int128 is not supported on this target +vector unsigned __int128 vulll = { 1 }; + +// CHECK-PPC: error: __int128 is not supported on this target +vector signed __int128 res_vlll; +// CHECK-PPC: error: __int128 is not supported on this target +vector unsigned __int128 res_vulll; + + +// CHECK-LABEL: define void @test1 +void test1() { + + /* vec_add */ + res_vlll = vec_add(vlll, vlll); +// CHECK: add <1 x i128> +// CHECK-LE: add <1 x i128> +// CHECK-PPC: error: call to 'vec_add' is ambiguous + + res_vulll = vec_add(vulll, vulll); +// CHECK: add <1 x i128> +// CHECK-LE: add <1 x i128> +// CHECK-PPC: error: call to 'vec_add' is ambiguous + + /* vec_vadduqm */ + res_vlll = vec_vadduqm(vlll, vlll); +// CHECK: add <1 x i128> +// CHECK-LE: add <1 x i128> +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vadduqm(vulll, vulll); +// CHECK: add <1 x i128> +// CHECK-LE: add <1 x i128> +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + + /* vec_vaddeuqm */ + res_vlll = vec_vaddeuqm(vlll, vlll, vlll); +// CHECK: @llvm.ppc.altivec.vaddeuqm +// CHECK-LE: @llvm.ppc.altivec.vaddeuqm +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vaddeuqm(vulll, vulll, vulll); +// CHECK: @llvm.ppc.altivec.vaddeuqm +// CHECK-LE: @llvm.ppc.altivec.vaddeuqm +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + + /* vec_addc */ + res_vlll = vec_addc(vlll, vlll); +// CHECK: @llvm.ppc.altivec.vaddcuq +// CHECK-LE: @llvm.ppc.altivec.vaddcuq +// KCHECK-PPC: error: call to 'vec_addc' is ambiguous + + res_vulll = vec_addc(vulll, vulll); +// CHECK: @llvm.ppc.altivec.vaddcuq +// CHECK-LE: @llvm.ppc.altivec.vaddcuq +// KCHECK-PPC: error: call to 'vec_addc' is ambiguous + + + /* vec_vaddcuq */ + res_vlll = vec_vaddcuq(vlll, vlll); +// CHECK: @llvm.ppc.altivec.vaddcuq +// CHECK-LE: @llvm.ppc.altivec.vaddcuq +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vaddcuq(vulll, vulll); +// CHECK: @llvm.ppc.altivec.vaddcuq +// CHECK-LE: @llvm.ppc.altivec.vaddcuq +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + + /* vec_vaddecuq */ + res_vlll = vec_vaddecuq(vlll, vlll, vlll); +// CHECK: @llvm.ppc.altivec.vaddecuq +// CHECK-LE: @llvm.ppc.altivec.vaddecuq +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vaddecuq(vulll, vulll, vulll); +// CHECK: @llvm.ppc.altivec.vaddecuq +// CHECK-LE: @llvm.ppc.altivec.vaddecuq +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + + /* vec_sub */ + res_vlll = vec_sub(vlll, vlll); +// CHECK: sub <1 x i128> +// CHECK-LE: sub <1 x i128> +// CHECK-PPC: error: call to 'vec_sub' is ambiguous + + res_vulll = vec_sub(vulll, vulll); +// CHECK: sub <1 x i128> +// CHECK-LE: sub <1 x i128> +// CHECK-PPC: error: call to 'vec_sub' is ambiguous + + /* vec_vsubuqm */ + res_vlll = vec_vsubuqm(vlll, vlll); +// CHECK: sub <1 x i128> +// CHECK-LE: sub <1 x i128> +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vsubuqm(vulll, vulll); +// CHECK: sub <1 x i128> +// CHECK-LE: sub <1 x i128> +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + + /* vec_vsubeuqm */ + res_vlll = vec_vsubeuqm(vlll, vlll, vlll); +// CHECK: @llvm.ppc.altivec.vsubeuqm +// CHECK-LE: @llvm.ppc.altivec.vsubeuqm +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vsubeuqm(vulll, vulll, vulll); +// CHECK: @llvm.ppc.altivec.vsubeuqm +// CHECK-LE: @llvm.ppc.altivec.vsubeuqm +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + + /* vec_subc */ + res_vlll = vec_subc(vlll, vlll); +// CHECK: @llvm.ppc.altivec.vsubcuq +// CHECK-LE: @llvm.ppc.altivec.vsubcuq +// KCHECK-PPC: error: call to 'vec_subc' is ambiguous + + res_vulll = vec_subc(vulll, vulll); +// CHECK: @llvm.ppc.altivec.vsubcuq +// CHECK-LE: @llvm.ppc.altivec.vsubcuq +// KCHECK-PPC: error: call to 'vec_subc' is ambiguous + + /* vec_vsubcuq */ + res_vlll = vec_vsubcuq(vlll, vlll); +// CHECK: @llvm.ppc.altivec.vsubcuq +// CHECK-LE: @llvm.ppc.altivec.vsubcuq +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vsubcuq(vulll, vulll); +// CHECK: @llvm.ppc.altivec.vsubcuq +// CHECK-LE: @llvm.ppc.altivec.vsubcuq +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + + /* vec_vsubecuq */ + res_vlll = vec_vsubecuq(vlll, vlll, vlll); +// CHECK: @llvm.ppc.altivec.vsubecuq +// CHECK-LE: @llvm.ppc.altivec.vsubecuq +// CHECK-PPC: error: assigning to '__vector __int128' (vector of 1 '__int128' value) from incompatible type 'int' + + res_vulll = vec_vsubecuq(vulll, vulll, vulll); +// CHECK: @llvm.ppc.altivec.vsubecuq +// CHECK-LE: @llvm.ppc.altivec.vsubecuq +// CHECK-PPC: error: assigning to '__vector unsigned __int128' (vector of 1 'unsigned __int128' value) from incompatible type 'int' + +} diff --git a/test/CodeGen/builtins-systemz-error.c b/test/CodeGen/builtins-systemz-error.c new file mode 100644 index 000000000000..73431b0a320e --- /dev/null +++ b/test/CodeGen/builtins-systemz-error.c @@ -0,0 +1,9 @@ +// REQUIRES: systemz-registered-target +// RUN: %clang_cc1 -target-cpu zEC12 -triple s390x-unknown-unknown \ +// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s + +void test1(void) { + __builtin_tabort (0); // expected-error {{invalid transaction abort code}} + __builtin_tabort (255); // expected-error {{invalid transaction abort code}} +} + diff --git a/test/CodeGen/builtins-systemz-vector-error.c b/test/CodeGen/builtins-systemz-vector-error.c new file mode 100644 index 000000000000..6f4ecc2acad3 --- /dev/null +++ b/test/CodeGen/builtins-systemz-vector-error.c @@ -0,0 +1,174 @@ +// REQUIRES: systemz-registered-target +// RUN: %clang_cc1 -target-cpu z13 -triple s390x-unknown-unknown \ +// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s + +typedef __attribute__((vector_size(16))) signed char vec_schar; +typedef __attribute__((vector_size(16))) signed short vec_sshort; +typedef __attribute__((vector_size(16))) signed int vec_sint; +typedef __attribute__((vector_size(16))) signed long long vec_slong; +typedef __attribute__((vector_size(16))) unsigned char vec_uchar; +typedef __attribute__((vector_size(16))) unsigned short vec_ushort; +typedef __attribute__((vector_size(16))) unsigned int vec_uint; +typedef __attribute__((vector_size(16))) unsigned long long vec_ulong; +typedef __attribute__((vector_size(16))) double vec_double; + +volatile vec_schar vsc; +volatile vec_sshort vss; +volatile vec_sint vsi; +volatile vec_slong vsl; +volatile vec_uchar vuc; +volatile vec_ushort vus; +volatile vec_uint vui; +volatile vec_ulong vul; +volatile vec_double vd; + +volatile unsigned int len; +const void * volatile cptr; +int cc; + +void test_core(void) { + __builtin_s390_lcbb(cptr, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_lcbb(cptr, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_lcbb(cptr, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vlbb(cptr, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vlbb(cptr, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vlbb(cptr, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vpdi(vul, vul, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vpdi(vul, vul, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vpdi(vul, vul, len); // expected-error {{must be a constant integer}} +} + +void test_integer(void) { + __builtin_s390_verimb(vuc, vuc, vuc, -1); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimb(vuc, vuc, vuc, 256); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimb(vuc, vuc, vuc, len); // expected-error {{must be a constant integer}} + + __builtin_s390_verimh(vus, vus, vus, -1); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimh(vus, vus, vus, 256); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimh(vus, vus, vus, len); // expected-error {{must be a constant integer}} + + __builtin_s390_verimf(vui, vui, vui, -1); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimf(vui, vui, vui, 256); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimf(vui, vui, vui, len); // expected-error {{must be a constant integer}} + + __builtin_s390_verimg(vul, vul, vul, -1); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimg(vul, vul, vul, 256); // expected-error {{argument should be a value from 0 to 255}} + __builtin_s390_verimg(vul, vul, vul, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vsldb(vuc, vuc, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vsldb(vuc, vuc, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vsldb(vuc, vuc, len); // expected-error {{must be a constant integer}} +} + +void test_string(void) { + __builtin_s390_vfaeb(vuc, vuc, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaeb(vuc, vuc, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaeb(vuc, vuc, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaeh(vus, vus, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaeh(vus, vus, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaeh(vus, vus, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaef(vui, vui, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaef(vui, vui, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaef(vui, vui, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaezb(vuc, vuc, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezb(vuc, vuc, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezb(vuc, vuc, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaezh(vus, vus, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezh(vus, vus, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezh(vus, vus, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaezf(vui, vui, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezf(vui, vui, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezf(vui, vui, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrcb(vuc, vuc, vuc, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcb(vuc, vuc, vuc, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcb(vuc, vuc, vuc, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrch(vus, vus, vus, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrch(vus, vus, vus, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrch(vus, vus, vus, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrcf(vui, vui, vui, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcf(vui, vui, vui, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcf(vui, vui, vui, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrczb(vuc, vuc, vuc, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczb(vuc, vuc, vuc, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczb(vuc, vuc, vuc, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrczh(vus, vus, vus, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczh(vus, vus, vus, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczh(vus, vus, vus, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrczf(vui, vui, vui, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczf(vui, vui, vui, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczf(vui, vui, vui, len); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaebs(vuc, vuc, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaebs(vuc, vuc, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaebs(vuc, vuc, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaehs(vus, vus, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaehs(vus, vus, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaehs(vus, vus, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaefs(vui, vui, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaefs(vui, vui, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaefs(vui, vui, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaezbs(vuc, vuc, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezbs(vuc, vuc, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezbs(vuc, vuc, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaezhs(vus, vus, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezhs(vus, vus, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezhs(vus, vus, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vfaezfs(vui, vui, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezfs(vui, vui, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfaezfs(vui, vui, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrcbs(vuc, vuc, vuc, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcbs(vuc, vuc, vuc, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcbs(vuc, vuc, vuc, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrchs(vus, vus, vus, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrchs(vus, vus, vus, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrchs(vus, vus, vus, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrcfs(vui, vui, vui, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcfs(vui, vui, vui, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrcfs(vui, vui, vui, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrczbs(vuc, vuc, vuc, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczbs(vuc, vuc, vuc, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczbs(vuc, vuc, vuc, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrczhs(vus, vus, vus, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczhs(vus, vus, vus, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczhs(vus, vus, vus, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vstrczfs(vui, vui, vui, -1, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczfs(vui, vui, vui, 16, &cc); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vstrczfs(vui, vui, vui, len, &cc); // expected-error {{must be a constant integer}} +} + +void test_float(void) { + __builtin_s390_vftcidb(vd, -1, &cc); // expected-error {{argument should be a value from 0 to 4095}} + __builtin_s390_vftcidb(vd, 4096, &cc); // expected-error {{argument should be a value from 0 to 4095}} + __builtin_s390_vftcidb(vd, len, &cc); // expected-error {{must be a constant integer}} + + __builtin_s390_vfidb(vd, -1, 0); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfidb(vd, 16, 0); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfidb(vd, len, 0); // expected-error {{must be a constant integer}} + __builtin_s390_vfidb(vd, 0, -1); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfidb(vd, 0, 16); // expected-error {{argument should be a value from 0 to 15}} + __builtin_s390_vfidb(vd, 0, len); // expected-error {{must be a constant integer}} +} diff --git a/test/CodeGen/builtins-systemz-vector.c b/test/CodeGen/builtins-systemz-vector.c new file mode 100644 index 000000000000..6d94cfae9a74 --- /dev/null +++ b/test/CodeGen/builtins-systemz-vector.c @@ -0,0 +1,610 @@ +// REQUIRES: systemz-registered-target +// RUN: %clang_cc1 -target-cpu z13 -triple s390x-ibm-linux -fno-lax-vector-conversions \ +// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s + +typedef __attribute__((vector_size(16))) signed char vec_schar; +typedef __attribute__((vector_size(16))) signed short vec_sshort; +typedef __attribute__((vector_size(16))) signed int vec_sint; +typedef __attribute__((vector_size(16))) signed long long vec_slong; +typedef __attribute__((vector_size(16))) unsigned char vec_uchar; +typedef __attribute__((vector_size(16))) unsigned short vec_ushort; +typedef __attribute__((vector_size(16))) unsigned int vec_uint; +typedef __attribute__((vector_size(16))) unsigned long long vec_ulong; +typedef __attribute__((vector_size(16))) double vec_double; + +volatile vec_schar vsc; +volatile vec_sshort vss; +volatile vec_sint vsi; +volatile vec_slong vsl; +volatile vec_uchar vuc; +volatile vec_ushort vus; +volatile vec_uint vui; +volatile vec_ulong vul; +volatile vec_double vd; + +volatile unsigned int len; +const void * volatile cptr; +void * volatile ptr; +int cc; + +void test_core(void) { + len = __builtin_s390_lcbb(cptr, 0); + // CHECK: call i32 @llvm.s390.lcbb(i8* %{{.*}}, i32 0) + len = __builtin_s390_lcbb(cptr, 15); + // CHECK: call i32 @llvm.s390.lcbb(i8* %{{.*}}, i32 15) + + vsc = __builtin_s390_vlbb(cptr, 0); + // CHECK: call <16 x i8> @llvm.s390.vlbb(i8* %{{.*}}, i32 0) + vsc = __builtin_s390_vlbb(cptr, 15); + // CHECK: call <16 x i8> @llvm.s390.vlbb(i8* %{{.*}}, i32 15) + + vsc = __builtin_s390_vll(len, cptr); + // CHECK: call <16 x i8> @llvm.s390.vll(i32 %{{.*}}, i8* %{{.*}}) + + vul = __builtin_s390_vpdi(vul, vul, 0); + // CHECK: call <2 x i64> @llvm.s390.vpdi(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, i32 0) + vul = __builtin_s390_vpdi(vul, vul, 15); + // CHECK: call <2 x i64> @llvm.s390.vpdi(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, i32 15) + + vuc = __builtin_s390_vperm(vuc, vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vperm(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + + vuc = __builtin_s390_vpklsh(vus, vus); + // CHECK: call <16 x i8> @llvm.s390.vpklsh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vus = __builtin_s390_vpklsf(vui, vui); + // CHECK: call <8 x i16> @llvm.s390.vpklsf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vui = __builtin_s390_vpklsg(vul, vul); + // CHECK: call <4 x i32> @llvm.s390.vpklsg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vuc = __builtin_s390_vpklshs(vus, vus, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vpklshs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vus = __builtin_s390_vpklsfs(vui, vui, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vpklsfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vui = __builtin_s390_vpklsgs(vul, vul, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vpklsgs(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vsc = __builtin_s390_vpksh(vss, vss); + // CHECK: call <16 x i8> @llvm.s390.vpksh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vss = __builtin_s390_vpksf(vsi, vsi); + // CHECK: call <8 x i16> @llvm.s390.vpksf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vsi = __builtin_s390_vpksg(vsl, vsl); + // CHECK: call <4 x i32> @llvm.s390.vpksg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vsc = __builtin_s390_vpkshs(vss, vss, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vpkshs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vss = __builtin_s390_vpksfs(vsi, vsi, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vpksfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vsi = __builtin_s390_vpksgs(vsl, vsl, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vpksgs(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + __builtin_s390_vstl(vsc, len, ptr); + // CHECK: call void @llvm.s390.vstl(<16 x i8> %{{.*}}, i32 %{{.*}}, i8* %{{.*}}) + + vss = __builtin_s390_vuphb(vsc); + // CHECK: call <8 x i16> @llvm.s390.vuphb(<16 x i8> %{{.*}}) + vsi = __builtin_s390_vuphh(vss); + // CHECK: call <4 x i32> @llvm.s390.vuphh(<8 x i16> %{{.*}}) + vsl = __builtin_s390_vuphf(vsi); + // CHECK: call <2 x i64> @llvm.s390.vuphf(<4 x i32> %{{.*}}) + + vss = __builtin_s390_vuplb(vsc); + // CHECK: call <8 x i16> @llvm.s390.vuplb(<16 x i8> %{{.*}}) + vsi = __builtin_s390_vuplhw(vss); + // CHECK: call <4 x i32> @llvm.s390.vuplhw(<8 x i16> %{{.*}}) + vsl = __builtin_s390_vuplf(vsi); + // CHECK: call <2 x i64> @llvm.s390.vuplf(<4 x i32> %{{.*}}) + + vus = __builtin_s390_vuplhb(vuc); + // CHECK: call <8 x i16> @llvm.s390.vuplhb(<16 x i8> %{{.*}}) + vui = __builtin_s390_vuplhh(vus); + // CHECK: call <4 x i32> @llvm.s390.vuplhh(<8 x i16> %{{.*}}) + vul = __builtin_s390_vuplhf(vui); + // CHECK: call <2 x i64> @llvm.s390.vuplhf(<4 x i32> %{{.*}}) + + vus = __builtin_s390_vupllb(vuc); + // CHECK: call <8 x i16> @llvm.s390.vupllb(<16 x i8> %{{.*}}) + vui = __builtin_s390_vupllh(vus); + // CHECK: call <4 x i32> @llvm.s390.vupllh(<8 x i16> %{{.*}}) + vul = __builtin_s390_vupllf(vui); + // CHECK: call <2 x i64> @llvm.s390.vupllf(<4 x i32> %{{.*}}) +} + +void test_integer(void) { + vuc = __builtin_s390_vaq(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vaq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vacq(vuc, vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vacq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vaccq(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vaccq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vacccq(vuc, vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vacccq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + + vuc = __builtin_s390_vaccb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vaccb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vacch(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vacch(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vaccf(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vaccf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vul = __builtin_s390_vaccg(vul, vul); + // CHECK: call <2 x i64> @llvm.s390.vaccg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vsc = __builtin_s390_vavgb(vsc, vsc); + // CHECK: call <16 x i8> @llvm.s390.vavgb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vss = __builtin_s390_vavgh(vss, vss); + // CHECK: call <8 x i16> @llvm.s390.vavgh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vavgf(vsi, vsi); + // CHECK: call <4 x i32> @llvm.s390.vavgf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vsl = __builtin_s390_vavgg(vsl, vsl); + // CHECK: call <2 x i64> @llvm.s390.vavgg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vuc = __builtin_s390_vavglb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vavglb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vavglh(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vavglh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vavglf(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vavglf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vul = __builtin_s390_vavglg(vul, vul); + // CHECK: call <2 x i64> @llvm.s390.vavglg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vui = __builtin_s390_vcksm(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vcksm(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vclzb(vuc); + // CHECK: call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %{{.*}}, i1 false) + vus = __builtin_s390_vclzh(vus); + // CHECK: call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %{{.*}}, i1 false) + vui = __builtin_s390_vclzf(vui); + // CHECK: call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %{{.*}}, i1 false) + vul = __builtin_s390_vclzg(vul); + // CHECK: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.*}}, i1 false) + + vuc = __builtin_s390_vctzb(vuc); + // CHECK: call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %{{.*}}, i1 false) + vus = __builtin_s390_vctzh(vus); + // CHECK: call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %{{.*}}, i1 false) + vui = __builtin_s390_vctzf(vui); + // CHECK: call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %{{.*}}, i1 false) + vul = __builtin_s390_vctzg(vul); + // CHECK: call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %{{.*}}, i1 false) + + vuc = __builtin_s390_verimb(vuc, vuc, vuc, 0); + // CHECK: call <16 x i8> @llvm.s390.verimb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_verimb(vuc, vuc, vuc, 255); + // CHECK: call <16 x i8> @llvm.s390.verimb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 255) + vus = __builtin_s390_verimh(vus, vus, vus, 0); + // CHECK: call <8 x i16> @llvm.s390.verimh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_verimh(vus, vus, vus, 255); + // CHECK: call <8 x i16> @llvm.s390.verimh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 255) + vui = __builtin_s390_verimf(vui, vui, vui, 0); + // CHECK: call <4 x i32> @llvm.s390.verimf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_verimf(vui, vui, vui, 255); + // CHECK: call <4 x i32> @llvm.s390.verimf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 255) + vul = __builtin_s390_verimg(vul, vul, vul, 0); + // CHECK: call <2 x i64> @llvm.s390.verimg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, i32 0) + vul = __builtin_s390_verimg(vul, vul, vul, 255); + // CHECK: call <2 x i64> @llvm.s390.verimg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, i32 255) + + vuc = __builtin_s390_verllb(vuc, len); + // CHECK: call <16 x i8> @llvm.s390.verllb(<16 x i8> %{{.*}}, i32 %{{.*}}) + vus = __builtin_s390_verllh(vus, len); + // CHECK: call <8 x i16> @llvm.s390.verllh(<8 x i16> %{{.*}}, i32 %{{.*}}) + vui = __builtin_s390_verllf(vui, len); + // CHECK: call <4 x i32> @llvm.s390.verllf(<4 x i32> %{{.*}}, i32 %{{.*}}) + vul = __builtin_s390_verllg(vul, len); + // CHECK: call <2 x i64> @llvm.s390.verllg(<2 x i64> %{{.*}}, i32 %{{.*}}) + + vuc = __builtin_s390_verllvb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.verllvb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_verllvh(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.verllvh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_verllvf(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.verllvf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vul = __builtin_s390_verllvg(vul, vul); + // CHECK: call <2 x i64> @llvm.s390.verllvg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vus = __builtin_s390_vgfmb(vuc, vuc); + // CHECK: call <8 x i16> @llvm.s390.vgfmb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vui = __builtin_s390_vgfmh(vus, vus); + // CHECK: call <4 x i32> @llvm.s390.vgfmh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vul = __builtin_s390_vgfmf(vui, vui); + // CHECK: call <2 x i64> @llvm.s390.vgfmf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vuc = __builtin_s390_vgfmg(vul, vul); + // CHECK: call <16 x i8> @llvm.s390.vgfmg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vus = __builtin_s390_vgfmab(vuc, vuc, vus); + // CHECK: call <8 x i16> @llvm.s390.vgfmab(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vgfmah(vus, vus, vui); + // CHECK: call <4 x i32> @llvm.s390.vgfmah(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <4 x i32> %{{.*}}) + vul = __builtin_s390_vgfmaf(vui, vui, vul); + // CHECK: call <2 x i64> @llvm.s390.vgfmaf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <2 x i64> %{{.*}}) + vuc = __builtin_s390_vgfmag(vul, vul, vuc); + // CHECK: call <16 x i8> @llvm.s390.vgfmag(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <16 x i8> %{{.*}}) + + vsc = __builtin_s390_vmahb(vsc, vsc, vsc); + // CHECK: call <16 x i8> @llvm.s390.vmahb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vss = __builtin_s390_vmahh(vss, vss, vss); + // CHECK: call <8 x i16> @llvm.s390.vmahh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vmahf(vsi, vsi, vsi); + // CHECK: call <4 x i32> @llvm.s390.vmahf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vuc = __builtin_s390_vmalhb(vuc, vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vmalhb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vmalhh(vus, vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vmalhh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vmalhf(vui, vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vmalhf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vss = __builtin_s390_vmaeb(vsc, vsc, vss); + // CHECK: call <8 x i16> @llvm.s390.vmaeb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vmaeh(vss, vss, vsi); + // CHECK: call <4 x i32> @llvm.s390.vmaeh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <4 x i32> %{{.*}}) + vsl = __builtin_s390_vmaef(vsi, vsi, vsl); + // CHECK: call <2 x i64> @llvm.s390.vmaef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <2 x i64> %{{.*}}) + vus = __builtin_s390_vmaleb(vuc, vuc, vus); + // CHECK: call <8 x i16> @llvm.s390.vmaleb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vmaleh(vus, vus, vui); + // CHECK: call <4 x i32> @llvm.s390.vmaleh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <4 x i32> %{{.*}}) + vul = __builtin_s390_vmalef(vui, vui, vul); + // CHECK: call <2 x i64> @llvm.s390.vmalef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <2 x i64> %{{.*}}) + + vss = __builtin_s390_vmaob(vsc, vsc, vss); + // CHECK: call <8 x i16> @llvm.s390.vmaob(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vmaoh(vss, vss, vsi); + // CHECK: call <4 x i32> @llvm.s390.vmaoh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <4 x i32> %{{.*}}) + vsl = __builtin_s390_vmaof(vsi, vsi, vsl); + // CHECK: call <2 x i64> @llvm.s390.vmaof(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <2 x i64> %{{.*}}) + vus = __builtin_s390_vmalob(vuc, vuc, vus); + // CHECK: call <8 x i16> @llvm.s390.vmalob(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vmaloh(vus, vus, vui); + // CHECK: call <4 x i32> @llvm.s390.vmaloh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <4 x i32> %{{.*}}) + vul = __builtin_s390_vmalof(vui, vui, vul); + // CHECK: call <2 x i64> @llvm.s390.vmalof(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <2 x i64> %{{.*}}) + + vsc = __builtin_s390_vmhb(vsc, vsc); + // CHECK: call <16 x i8> @llvm.s390.vmhb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vss = __builtin_s390_vmhh(vss, vss); + // CHECK: call <8 x i16> @llvm.s390.vmhh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vmhf(vsi, vsi); + // CHECK: call <4 x i32> @llvm.s390.vmhf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vuc = __builtin_s390_vmlhb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vmlhb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vmlhh(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vmlhh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vmlhf(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vmlhf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vss = __builtin_s390_vmeb(vsc, vsc); + // CHECK: call <8 x i16> @llvm.s390.vmeb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vsi = __builtin_s390_vmeh(vss, vss); + // CHECK: call <4 x i32> @llvm.s390.vmeh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsl = __builtin_s390_vmef(vsi, vsi); + // CHECK: call <2 x i64> @llvm.s390.vmef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vus = __builtin_s390_vmleb(vuc, vuc); + // CHECK: call <8 x i16> @llvm.s390.vmleb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vui = __builtin_s390_vmleh(vus, vus); + // CHECK: call <4 x i32> @llvm.s390.vmleh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vul = __builtin_s390_vmlef(vui, vui); + // CHECK: call <2 x i64> @llvm.s390.vmlef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vss = __builtin_s390_vmob(vsc, vsc); + // CHECK: call <8 x i16> @llvm.s390.vmob(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vsi = __builtin_s390_vmoh(vss, vss); + // CHECK: call <4 x i32> @llvm.s390.vmoh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsl = __builtin_s390_vmof(vsi, vsi); + // CHECK: call <2 x i64> @llvm.s390.vmof(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vus = __builtin_s390_vmlob(vuc, vuc); + // CHECK: call <8 x i16> @llvm.s390.vmlob(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vui = __builtin_s390_vmloh(vus, vus); + // CHECK: call <4 x i32> @llvm.s390.vmloh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vul = __builtin_s390_vmlof(vui, vui); + // CHECK: call <2 x i64> @llvm.s390.vmlof(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vpopctb(vuc); + // CHECK: call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) + vus = __builtin_s390_vpopcth(vus); + // CHECK: call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) + vui = __builtin_s390_vpopctf(vui); + // CHECK: call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) + vul = __builtin_s390_vpopctg(vul); + // CHECK: call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) + + vuc = __builtin_s390_vsq(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vsbiq(vuc, vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsbiq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vscbiq(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vscbiq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vsbcbiq(vuc, vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsbcbiq(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + + vuc = __builtin_s390_vscbib(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vscbib(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vscbih(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vscbih(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vscbif(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vscbif(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vul = __builtin_s390_vscbig(vul, vul); + // CHECK: call <2 x i64> @llvm.s390.vscbig(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vuc = __builtin_s390_vsldb(vuc, vuc, 0); + // CHECK: call <16 x i8> @llvm.s390.vsldb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vsldb(vuc, vuc, 15); + // CHECK: call <16 x i8> @llvm.s390.vsldb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + + vuc = __builtin_s390_vsl(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsl(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vslb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vslb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + + vuc = __builtin_s390_vsra(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsra(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vsrab(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsrab(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + + vuc = __builtin_s390_vsrl(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsrl(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vuc = __builtin_s390_vsrlb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vsrlb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + + vui = __builtin_s390_vsumb(vuc, vuc); + // CHECK: call <4 x i32> @llvm.s390.vsumb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vui = __builtin_s390_vsumh(vus, vus); + // CHECK: call <4 x i32> @llvm.s390.vsumh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vul = __builtin_s390_vsumgh(vus, vus); + // CHECK: call <2 x i64> @llvm.s390.vsumgh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vul = __builtin_s390_vsumgf(vui, vui); + // CHECK: call <2 x i64> @llvm.s390.vsumgf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vuc = __builtin_s390_vsumqf(vui, vui); + // CHECK: call <16 x i8> @llvm.s390.vsumqf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vuc = __builtin_s390_vsumqg(vul, vul); + // CHECK: call <16 x i8> @llvm.s390.vsumqg(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + len = __builtin_s390_vtm(vuc, vuc); + // CHECK: call i32 @llvm.s390.vtm(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + + vsc = __builtin_s390_vceqbs(vsc, vsc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vceqbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vss = __builtin_s390_vceqhs(vss, vss, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vceqhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vceqfs(vsi, vsi, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vceqfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vsl = __builtin_s390_vceqgs(vsl, vsl, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vceqgs(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vsc = __builtin_s390_vchbs(vsc, vsc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vchbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vss = __builtin_s390_vchhs(vss, vss, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vchhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vchfs(vsi, vsi, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vchfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vsl = __builtin_s390_vchgs(vsl, vsl, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vchgs(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + vsc = __builtin_s390_vchlbs(vuc, vuc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vchlbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vss = __builtin_s390_vchlhs(vus, vus, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vchlhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vsi = __builtin_s390_vchlfs(vui, vui, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vchlfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + vsl = __builtin_s390_vchlgs(vul, vul, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vchlgs(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}) +} + +void test_string(void) { + vuc = __builtin_s390_vfaeb(vuc, vuc, 0); + // CHECK: call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vfaeb(vuc, vuc, 15); + // CHECK: call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vfaeh(vus, vus, 0); + // CHECK: call <8 x i16> @llvm.s390.vfaeh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vfaeh(vus, vus, 15); + // CHECK: call <8 x i16> @llvm.s390.vfaeh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vfaef(vui, vui, 0); + // CHECK: call <4 x i32> @llvm.s390.vfaef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vfaef(vui, vui, 15); + // CHECK: call <4 x i32> @llvm.s390.vfaef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) + + vuc = __builtin_s390_vfaezb(vuc, vuc, 0); + // CHECK: call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vfaezb(vuc, vuc, 15); + // CHECK: call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vfaezh(vus, vus, 0); + // CHECK: call <8 x i16> @llvm.s390.vfaezh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vfaezh(vus, vus, 15); + // CHECK: call <8 x i16> @llvm.s390.vfaezh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vfaezf(vui, vui, 0); + // CHECK: call <4 x i32> @llvm.s390.vfaezf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vfaezf(vui, vui, 15); + // CHECK: call <4 x i32> @llvm.s390.vfaezf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) + + vuc = __builtin_s390_vfeeb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vfeeb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfeeh(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vfeeh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfeef(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vfeef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vfeezb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vfeezb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfeezh(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vfeezh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfeezf(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vfeezf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vfeneb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vfeneb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfeneh(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vfeneh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfenef(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vfenef(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vfenezb(vuc, vuc); + // CHECK: call <16 x i8> @llvm.s390.vfenezb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfenezh(vus, vus); + // CHECK: call <8 x i16> @llvm.s390.vfenezh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfenezf(vui, vui); + // CHECK: call <4 x i32> @llvm.s390.vfenezf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vistrb(vuc); + // CHECK: call <16 x i8> @llvm.s390.vistrb(<16 x i8> %{{.*}}) + vus = __builtin_s390_vistrh(vus); + // CHECK: call <8 x i16> @llvm.s390.vistrh(<8 x i16> %{{.*}}) + vui = __builtin_s390_vistrf(vui); + // CHECK: call <4 x i32> @llvm.s390.vistrf(<4 x i32> %{{.*}}) + + vuc = __builtin_s390_vstrcb(vuc, vuc, vuc, 0); + // CHECK: call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vstrcb(vuc, vuc, vuc, 15); + // CHECK: call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vstrch(vus, vus, vus, 0); + // CHECK: call <8 x i16> @llvm.s390.vstrch(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vstrch(vus, vus, vus, 15); + // CHECK: call <8 x i16> @llvm.s390.vstrch(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vstrcf(vui, vui, vui, 0); + // CHECK: call <4 x i32> @llvm.s390.vstrcf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vstrcf(vui, vui, vui, 15); + // CHECK: call <4 x i32> @llvm.s390.vstrcf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) + + vuc = __builtin_s390_vstrczb(vuc, vuc, vuc, 0); + // CHECK: call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vstrczb(vuc, vuc, vuc, 15); + // CHECK: call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vstrczh(vus, vus, vus, 0); + // CHECK: call <8 x i16> @llvm.s390.vstrczh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vstrczh(vus, vus, vus, 15); + // CHECK: call <8 x i16> @llvm.s390.vstrczh(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vstrczf(vui, vui, vui, 0); + // CHECK: call <4 x i32> @llvm.s390.vstrczf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vstrczf(vui, vui, vui, 15); + // CHECK: call <4 x i32> @llvm.s390.vstrczf(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) + + vuc = __builtin_s390_vfaebs(vuc, vuc, 0, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfaebs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vfaebs(vuc, vuc, 15, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfaebs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vfaehs(vus, vus, 0, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfaehs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vfaehs(vus, vus, 15, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfaehs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vfaefs(vui, vui, 0, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfaefs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vfaefs(vui, vui, 15, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfaefs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) + + vuc = __builtin_s390_vfaezbs(vuc, vuc, 0, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfaezbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vfaezbs(vuc, vuc, 15, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfaezbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vfaezhs(vus, vus, 0, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfaezhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vfaezhs(vus, vus, 15, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfaezhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vfaezfs(vui, vui, 0, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfaezfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vfaezfs(vui, vui, 15, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfaezfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) + + vuc = __builtin_s390_vfeebs(vuc, vuc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfeebs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfeehs(vus, vus, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfeehs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfeefs(vui, vui, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfeefs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vfeezbs(vuc, vuc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfeezbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfeezhs(vus, vus, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfeezhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfeezfs(vui, vui, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfeezfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vfenebs(vuc, vuc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfenebs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfenehs(vus, vus, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfenehs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfenefs(vui, vui, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfenefs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vfenezbs(vuc, vuc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vfenezbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) + vus = __builtin_s390_vfenezhs(vus, vus, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vfenezhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) + vui = __builtin_s390_vfenezfs(vui, vui, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vfenezfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) + + vuc = __builtin_s390_vistrbs(vuc, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vistrbs(<16 x i8> %{{.*}}) + vus = __builtin_s390_vistrhs(vus, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vistrhs(<8 x i16> %{{.*}}) + vui = __builtin_s390_vistrfs(vui, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vistrfs(<4 x i32> %{{.*}}) + + vuc = __builtin_s390_vstrcbs(vuc, vuc, vuc, 0, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vstrcbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vstrcbs(vuc, vuc, vuc, 15, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vstrcbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vstrchs(vus, vus, vus, 0, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vstrchs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vstrchs(vus, vus, vus, 15, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vstrchs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vstrcfs(vui, vui, vui, 0, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vstrcfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vstrcfs(vui, vui, vui, 15, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vstrcfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) + + vuc = __builtin_s390_vstrczbs(vuc, vuc, vuc, 0, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vstrczbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 0) + vuc = __builtin_s390_vstrczbs(vuc, vuc, vuc, 15, &cc); + // CHECK: call { <16 x i8>, i32 } @llvm.s390.vstrczbs(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, i32 15) + vus = __builtin_s390_vstrczhs(vus, vus, vus, 0, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vstrczhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 0) + vus = __builtin_s390_vstrczhs(vus, vus, vus, 15, &cc); + // CHECK: call { <8 x i16>, i32 } @llvm.s390.vstrczhs(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, i32 15) + vui = __builtin_s390_vstrczfs(vui, vui, vui, 0, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vstrczfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 0) + vui = __builtin_s390_vstrczfs(vui, vui, vui, 15, &cc); + // CHECK: call { <4 x i32>, i32 } @llvm.s390.vstrczfs(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, i32 15) +} + +void test_float(void) { + vsl = __builtin_s390_vfcedbs(vd, vd, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vfcedbs(<2 x double> %{{.*}}, <2 x double> %{{.*}}) + vsl = __builtin_s390_vfchdbs(vd, vd, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vfchdbs(<2 x double> %{{.*}}, <2 x double> %{{.*}}) + vsl = __builtin_s390_vfchedbs(vd, vd, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vfchedbs(<2 x double> %{{.*}}, <2 x double> %{{.*}}) + + vsl = __builtin_s390_vftcidb(vd, 0, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vftcidb(<2 x double> %{{.*}}, i32 0) + vsl = __builtin_s390_vftcidb(vd, 4095, &cc); + // CHECK: call { <2 x i64>, i32 } @llvm.s390.vftcidb(<2 x double> %{{.*}}, i32 4095) + + vd = __builtin_s390_vfsqdb(vd); + // CHECK: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{.*}}) + + vd = __builtin_s390_vfmadb(vd, vd, vd); + // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) + vd = __builtin_s390_vfmsdb(vd, vd, vd); + // CHECK: [[NEG:%[^ ]+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}} + // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]]) + + vd = __builtin_s390_vflpdb(vd); + // CHECK: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{.*}}) + vd = __builtin_s390_vflndb(vd); + // CHECK: [[ABS:%[^ ]+]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{.*}}) + // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, [[ABS]] + + vd = __builtin_s390_vfidb(vd, 0, 0); + // CHECK: call <2 x double> @llvm.rint.v2f64(<2 x double> %{{.*}}) + vd = __builtin_s390_vfidb(vd, 4, 0); + // CHECK: call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %{{.*}}) + vd = __builtin_s390_vfidb(vd, 4, 1); + // CHECK: call <2 x double> @llvm.round.v2f64(<2 x double> %{{.*}}) + vd = __builtin_s390_vfidb(vd, 4, 5); + // CHECK: call <2 x double> @llvm.trunc.v2f64(<2 x double> %{{.*}}) + vd = __builtin_s390_vfidb(vd, 4, 6); + // CHECK: call <2 x double> @llvm.ceil.v2f64(<2 x double> %{{.*}}) + vd = __builtin_s390_vfidb(vd, 4, 7); + // CHECK: call <2 x double> @llvm.floor.v2f64(<2 x double> %{{.*}}) + vd = __builtin_s390_vfidb(vd, 4, 4); + // CHECK: call <2 x double> @llvm.s390.vfidb(<2 x double> %{{.*}}, i32 4, i32 4) +} diff --git a/test/CodeGen/builtins-systemz.c b/test/CodeGen/builtins-systemz.c new file mode 100644 index 000000000000..f5de7009acba --- /dev/null +++ b/test/CodeGen/builtins-systemz.c @@ -0,0 +1,144 @@ +// REQUIRES: systemz-registered-target +// RUN: %clang_cc1 -target-cpu zEC12 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -target-cpu zEC12 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s + +#include <stdint.h> +#include <htmintrin.h> + +int global = 0; +uint64_t g; +struct __htm_tdb global_tdb; + +void test_htm1(struct __htm_tdb *tdb, int reg, int *mem, uint64_t *mem64) { +// CHECK-LABEL: test_htm1 + + __builtin_tbegin ((void *)0); +// CHECK: call i32 @llvm.s390.tbegin(i8* null, i32 65292) + __builtin_tbegin ((void *)0x12345678); +// CHECK: call i32 @llvm.s390.tbegin(i8* inttoptr (i64 305419896 to i8*), i32 65292) + __builtin_tbegin (tdb); +// CHECK: call i32 @llvm.s390.tbegin(i8* %{{.*}}, i32 65292) + __builtin_tbegin (&global_tdb); +// CHECK: call i32 @llvm.s390.tbegin(i8* getelementptr inbounds (%struct.__htm_tdb, %struct.__htm_tdb* @global_tdb, i32 0, i32 0), i32 65292) + + __builtin_tbegin_nofloat ((void *)0); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* null, i32 65292) + __builtin_tbegin_nofloat ((void *)0x12345678); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* inttoptr (i64 305419896 to i8*), i32 65292) + __builtin_tbegin_nofloat (tdb); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* %{{.*}}, i32 65292) + __builtin_tbegin_nofloat (&global_tdb); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* getelementptr inbounds (%struct.__htm_tdb, %struct.__htm_tdb* @global_tdb, i32 0, i32 0), i32 65292) + + __builtin_tbegin_retry ((void *)0, 6); +// CHECK: call i32 @llvm.s390.tbegin(i8* null, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tbegin_retry ((void *)0x12345678, 6); +// CHECK: call i32 @llvm.s390.tbegin(i8* %{{.*}}, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tbegin_retry (tdb, 6); +// CHECK: call i32 @llvm.s390.tbegin(i8* %{{.*}}, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tbegin_retry (&global_tdb, 6); +// CHECK: call i32 @llvm.s390.tbegin(i8* %{{.*}}, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + + __builtin_tbegin_retry_nofloat ((void *)0, 6); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* null, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tbegin_retry_nofloat ((void *)0x12345678, 6); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* %{{.*}}, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tbegin_retry_nofloat (tdb, 6); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* %{{.*}}, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tbegin_retry_nofloat (&global_tdb, 6); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* %{{.*}}, i32 65292) +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + + __builtin_tbeginc (); +// CHECK: call void @llvm.s390.tbeginc(i8* null, i32 65288) + + __builtin_tabort (256); +// CHECK: call void @llvm.s390.tabort(i64 256) + __builtin_tabort (-1); +// CHECK: call void @llvm.s390.tabort(i64 -1) + __builtin_tabort (reg); +// CHECK: call void @llvm.s390.tabort(i64 %{{.*}}) + + __builtin_tend(); +// CHECK: call i32 @llvm.s390.tend() + + int n = __builtin_tx_nesting_depth(); +// CHECK: call i32 @llvm.s390.etnd() + + __builtin_non_tx_store (mem64, 0); +// CHECK: call void @llvm.s390.ntstg(i64 0, i64* %{{.*}}) + const uint64_t val_var = 0x1122334455667788; + __builtin_non_tx_store (mem64, val_var); +// CHECK: call void @llvm.s390.ntstg(i64 1234605616436508552, i64* %{{.*}}) + __builtin_non_tx_store (mem64, (uint64_t)reg); +// CHECK: call void @llvm.s390.ntstg(i64 %{{.*}}, i64* %{{.*}}) + __builtin_non_tx_store (mem64, g); +// CHECK: call void @llvm.s390.ntstg(i64 %{{.*}}, i64* %{{.*}}) + __builtin_non_tx_store ((uint64_t *)0, 0); +// CHECK: call void @llvm.s390.ntstg(i64 0, i64* null) + __builtin_non_tx_store ((uint64_t *)0x12345678, 0); +// CHECK: call void @llvm.s390.ntstg(i64 0, i64* inttoptr (i64 305419896 to i64*)) + __builtin_non_tx_store (&g, 23); +// CHECK: call void @llvm.s390.ntstg(i64 23, i64* @g) + __builtin_non_tx_store (&g, reg); +// CHECK: call void @llvm.s390.ntstg(i64 %{{.*}}, i64* @g) + __builtin_non_tx_store (&g, *mem); +// CHECK: call void @llvm.s390.ntstg(i64 %{{.*}}, i64* @g) + __builtin_non_tx_store (&g, global); +// CHECK: call void @llvm.s390.ntstg(i64 %{{.*}}, i64* @g) + + __builtin_tx_assist (0); +// CHECK: call void @llvm.s390.ppa.txassist(i32 0) + __builtin_tx_assist (1); +// CHECK: call void @llvm.s390.ppa.txassist(i32 1) + __builtin_tx_assist (reg); +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tx_assist (*mem); +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) + __builtin_tx_assist (global); +// CHECK: call void @llvm.s390.ppa.txassist(i32 %{{.*}}) +} + +#include <htmxlintrin.h> + +void test_htmxl1(void) { +// CHECK-LABEL: test_htmxl1 + + struct __htm_tdb tdb_struct; + void * const tdb = &tdb_struct; + long result; + unsigned char code; + + result = __TM_simple_begin (); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* null, i32 65292) + result = __TM_begin (tdb); +// CHECK: call i32 @llvm.s390.tbegin.nofloat(i8* %{{.*}}, i32 65292) + result = __TM_end (); +// CHECK: call i32 @llvm.s390.tend() + __TM_abort (); +// CHECK: call void @llvm.s390.tabort(i64 256) + __TM_named_abort (42); +// CHECK: call void @llvm.s390.tabort(i64 %{{.*}}) + __TM_non_transactional_store (&g, 42); +// CHECK: call void @llvm.s390.ntstg(i64 %{{.*}}, i64* %{{.*}}) + result = __TM_nesting_depth (tdb); +// CHECK: call i32 @llvm.s390.etnd() + + result = __TM_is_user_abort (tdb); + result = __TM_is_named_user_abort (tdb, &code); + result = __TM_is_illegal (tdb); + result = __TM_is_footprint_exceeded (tdb); + result = __TM_is_nested_too_deep (tdb); + result = __TM_is_conflict (tdb); + result = __TM_is_failure_persistent (result); + result = __TM_failure_address (tdb); + result = __TM_failure_code (tdb); +} + diff --git a/test/CodeGen/builtins-x86.c b/test/CodeGen/builtins-x86.c index e9ae834b3cfa..8a5b5a272d4c 100644 --- a/test/CodeGen/builtins-x86.c +++ b/test/CodeGen/builtins-x86.c @@ -354,9 +354,6 @@ void f0() { tmp_V1LLi = __builtin_ia32_palignr(tmp_V1LLi, tmp_V1LLi, imm_i); #ifdef USE_SSE4 tmp_V16c = __builtin_ia32_pblendvb128(tmp_V16c, tmp_V16c, tmp_V16c); - tmp_V8s = __builtin_ia32_pblendw128(tmp_V8s, tmp_V8s, imm_i_0_256); - tmp_V2d = __builtin_ia32_blendpd(tmp_V2d, tmp_V2d, imm_i_0_256); - tmp_V4f = __builtin_ia32_blendps(tmp_V4f, tmp_V4f, imm_i_0_256); tmp_V2d = __builtin_ia32_blendvpd(tmp_V2d, tmp_V2d, tmp_V2d); tmp_V4f = __builtin_ia32_blendvps(tmp_V4f, tmp_V4f, tmp_V4f); tmp_V8s = __builtin_ia32_packusdw128(tmp_V4i, tmp_V4i); @@ -403,16 +400,11 @@ void f0() { tmp_V4f = __builtin_ia32_vpermilvarps(tmp_V4f, tmp_V4i); tmp_V4d = __builtin_ia32_vpermilvarpd256(tmp_V4d, tmp_V4LLi); tmp_V8f = __builtin_ia32_vpermilvarps256(tmp_V8f, tmp_V8i); - tmp_V4d = __builtin_ia32_blendpd256(tmp_V4d, tmp_V4d, 0x7); - tmp_V8f = __builtin_ia32_blendps256(tmp_V8f, tmp_V8f, 0x7); tmp_V4d = __builtin_ia32_blendvpd256(tmp_V4d, tmp_V4d, tmp_V4d); tmp_V8f = __builtin_ia32_blendvps256(tmp_V8f, tmp_V8f, tmp_V8f); tmp_V8f = __builtin_ia32_dpps256(tmp_V8f, tmp_V8f, 0x7); tmp_V4d = __builtin_ia32_cmppd256(tmp_V4d, tmp_V4d, 0); tmp_V8f = __builtin_ia32_cmpps256(tmp_V8f, tmp_V8f, 0); - tmp_V2d = __builtin_ia32_vextractf128_pd256(tmp_V4d, 0x7); - tmp_V4f = __builtin_ia32_vextractf128_ps256(tmp_V8f, 0x7); - tmp_V4i = __builtin_ia32_vextractf128_si256(tmp_V8i, 0x7); tmp_V4d = __builtin_ia32_cvtdq2pd256(tmp_V4i); tmp_V8f = __builtin_ia32_cvtdq2ps256(tmp_V8i); tmp_V4f = __builtin_ia32_cvtpd2ps256(tmp_V4d); @@ -424,9 +416,6 @@ void f0() { tmp_V4d = __builtin_ia32_vperm2f128_pd256(tmp_V4d, tmp_V4d, 0x7); tmp_V8f = __builtin_ia32_vperm2f128_ps256(tmp_V8f, tmp_V8f, 0x7); tmp_V8i = __builtin_ia32_vperm2f128_si256(tmp_V8i, tmp_V8i, 0x7); - tmp_V4d = __builtin_ia32_vinsertf128_pd256(tmp_V4d, tmp_V2d, 0x7); - tmp_V8f = __builtin_ia32_vinsertf128_ps256(tmp_V8f, tmp_V4f, 0x7); - tmp_V8i = __builtin_ia32_vinsertf128_si256(tmp_V8i, tmp_V4i, 0x7); tmp_V4d = __builtin_ia32_sqrtpd256(tmp_V4d); tmp_V8f = __builtin_ia32_sqrtps256(tmp_V8f); tmp_V8f = __builtin_ia32_rsqrtps256(tmp_V8f); @@ -497,7 +486,7 @@ void f0() { tmp_V2f = __builtin_ia32_pswapdsf(tmp_V2f); tmp_V2i = __builtin_ia32_pswapdsi(tmp_V2i); - tmp_V4i = __builtin_ia32_sha1rnds4(tmp_V4i, tmp_V4i, imm_i); + tmp_V4i = __builtin_ia32_sha1rnds4(tmp_V4i, tmp_V4i, imm_i_0_4); tmp_V4i = __builtin_ia32_sha1nexte(tmp_V4i, tmp_V4i); tmp_V4i = __builtin_ia32_sha1msg1(tmp_V4i, tmp_V4i); tmp_V4i = __builtin_ia32_sha1msg2(tmp_V4i, tmp_V4i); diff --git a/test/CodeGen/builtins.c b/test/CodeGen/builtins.c index bf7874b08862..39b2c1209f12 100644 --- a/test/CodeGen/builtins.c +++ b/test/CodeGen/builtins.c @@ -42,8 +42,6 @@ int main() { P(fpclassify, (0, 1, 2, 3, 4, 1.0)); P(fpclassify, (0, 1, 2, 3, 4, 1.0f)); P(fpclassify, (0, 1, 2, 3, 4, 1.0l)); - // FIXME: - // P(isinf_sign, (1.0)); Q(nan, ("")); Q(nanf, ("")); @@ -61,6 +59,8 @@ int main() { P(islessgreater, (1., 2.)); P(isunordered, (1., 2.)); + P(isinf, (1.)); + P(isinf_sign, (1.)); P(isnan, (1.)); // Bitwise & Numeric Functions @@ -177,11 +177,35 @@ void test_float_builtins(float F, double D, long double LD) { res = __builtin_isinf(D); // CHECK: call double @llvm.fabs.f64(double // CHECK: fcmp oeq double {{.*}}, 0x7FF0000000000000 - + res = __builtin_isinf(LD); // CHECK: call x86_fp80 @llvm.fabs.f80(x86_fp80 // CHECK: fcmp oeq x86_fp80 {{.*}}, 0xK7FFF8000000000000000 - + + res = __builtin_isinf_sign(F); + // CHECK: %[[ABS:.*]] = call float @llvm.fabs.f32(float %[[ARG:.*]]) + // CHECK: %[[ISINF:.*]] = fcmp oeq float %[[ABS]], 0x7FF0000000000000 + // CHECK: %[[BITCAST:.*]] = bitcast float %[[ARG]] to i32 + // CHECK: %[[ISNEG:.*]] = icmp slt i32 %[[BITCAST]], 0 + // CHECK: %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1 + // CHECK: select i1 %[[ISINF]], i32 %[[SIGN]], i32 0 + + res = __builtin_isinf_sign(D); + // CHECK: %[[ABS:.*]] = call double @llvm.fabs.f64(double %[[ARG:.*]]) + // CHECK: %[[ISINF:.*]] = fcmp oeq double %[[ABS]], 0x7FF0000000000000 + // CHECK: %[[BITCAST:.*]] = bitcast double %[[ARG]] to i64 + // CHECK: %[[ISNEG:.*]] = icmp slt i64 %[[BITCAST]], 0 + // CHECK: %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1 + // CHECK: select i1 %[[ISINF]], i32 %[[SIGN]], i32 0 + + res = __builtin_isinf_sign(LD); + // CHECK: %[[ABS:.*]] = call x86_fp80 @llvm.fabs.f80(x86_fp80 %[[ARG:.*]]) + // CHECK: %[[ISINF:.*]] = fcmp oeq x86_fp80 %[[ABS]], 0xK7FFF8000000000000000 + // CHECK: %[[BITCAST:.*]] = bitcast x86_fp80 %[[ARG]] to i80 + // CHECK: %[[ISNEG:.*]] = icmp slt i80 %[[BITCAST]], 0 + // CHECK: %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1 + // CHECK: select i1 %[[ISINF]], i32 %[[SIGN]], i32 0 + res = __builtin_isfinite(F); // CHECK: fcmp oeq float // CHECK: call float @llvm.fabs.f32(float diff --git a/test/CodeGen/c-strings.c b/test/CodeGen/c-strings.c index d82bc2572e44..588a716a16a4 100644 --- a/test/CodeGen/c-strings.c +++ b/test/CodeGen/c-strings.c @@ -6,13 +6,13 @@ // CHECK: @align = global i8 [[ALIGN:[0-9]+]] // ITANIUM: @.str = private unnamed_addr constant [6 x i8] c"hello\00" -// MSABI: @"\01??_C@_05CJBACGMB@hello?$AA@" = linkonce_odr unnamed_addr constant [6 x i8] c"hello\00", align 1 -// ITANIUM: @f1.x = internal global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0) -// MSABI: @f1.x = internal global i8* getelementptr inbounds ([6 x i8]* @"\01??_C@_05CJBACGMB@hello?$AA@", i32 0, i32 0) +// MSABI: @"\01??_C@_05CJBACGMB@hello?$AA@" = linkonce_odr unnamed_addr constant [6 x i8] c"hello\00", comdat, align 1 +// ITANIUM: @f1.x = internal global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0) +// MSABI: @f1.x = internal global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @"\01??_C@_05CJBACGMB@hello?$AA@", i32 0, i32 0) // CHECK: @f2.x = internal global [6 x i8] c"hello\00", align [[ALIGN]] // CHECK: @f3.x = internal global [8 x i8] c"hello\00\00\00", align [[ALIGN]] -// ITANIUM: @f4.x = internal global %struct.s { i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0) } -// MSABI: @f4.x = internal global %struct.s { i8* getelementptr inbounds ([6 x i8]* @"\01??_C@_05CJBACGMB@hello?$AA@", i32 0, i32 0) } +// ITANIUM: @f4.x = internal global %struct.s { i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0) } +// MSABI: @f4.x = internal global %struct.s { i8* getelementptr inbounds ([6 x i8], [6 x i8]* @"\01??_C@_05CJBACGMB@hello?$AA@", i32 0, i32 0) } // CHECK: @x = global [3 x i8] c"ola", align [[ALIGN]] #if defined(__s390x__) @@ -34,7 +34,7 @@ void f0() { void f1() { static char *x = "hello"; bar(x); - // CHECK: [[T1:%.*]] = load i8** @f1.x + // CHECK: [[T1:%.*]] = load i8*, i8** @f1.x // CHECK: call void @bar(i8* [[T1:%.*]]) } diff --git a/test/CodeGen/c11atomics-ios.c b/test/CodeGen/c11atomics-ios.c index ad57550441b0..a869982b17b0 100644 --- a/test/CodeGen/c11atomics-ios.c +++ b/test/CodeGen/c11atomics-ios.c @@ -13,22 +13,22 @@ void testFloat(_Atomic(float) *fp) { // CHECK-NEXT: [[F:%.*]] = alloca float // CHECK-NEXT: store float* {{%.*}}, float** [[FP]] -// CHECK-NEXT: [[T0:%.*]] = load float** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]] // CHECK-NEXT: store float 1.000000e+00, float* [[T0]], align 4 __c11_atomic_init(fp, 1.0f); // CHECK-NEXT: store float 2.000000e+00, float* [[X]], align 4 _Atomic(float) x = 2.0f; -// CHECK-NEXT: [[T0:%.*]] = load float** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast float* [[T0]] to i32* -// CHECK-NEXT: [[T2:%.*]] = load atomic i32* [[T1]] seq_cst, align 4 +// CHECK-NEXT: [[T2:%.*]] = load atomic i32, i32* [[T1]] seq_cst, align 4 // CHECK-NEXT: [[T3:%.*]] = bitcast i32 [[T2]] to float // CHECK-NEXT: store float [[T3]], float* [[F]] float f = *fp; -// CHECK-NEXT: [[T0:%.*]] = load float* [[F]], align 4 -// CHECK-NEXT: [[T1:%.*]] = load float** [[FP]], align 4 +// CHECK-NEXT: [[T0:%.*]] = load float, float* [[F]], align 4 +// CHECK-NEXT: [[T1:%.*]] = load float*, float** [[FP]], align 4 // CHECK-NEXT: [[T2:%.*]] = bitcast float [[T0]] to i32 // CHECK-NEXT: [[T3:%.*]] = bitcast float* [[T1]] to i32* // CHECK-NEXT: store atomic i32 [[T2]], i32* [[T3]] seq_cst, align 4 @@ -46,45 +46,45 @@ void testComplexFloat(_Atomic(_Complex float) *fp) { // CHECK-NEXT: [[TMP1:%.*]] = alloca [[CF]], align 8 // CHECK-NEXT: store [[CF]]* -// CHECK-NEXT: [[P:%.*]] = load [[CF]]** [[FP]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[P]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[P]], i32 0, i32 1 +// CHECK-NEXT: [[P:%.*]] = load [[CF]]*, [[CF]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[P]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[P]], i32 0, i32 1 // CHECK-NEXT: store float 1.000000e+00, float* [[T0]] // CHECK-NEXT: store float 0.000000e+00, float* [[T1]] __c11_atomic_init(fp, 1.0f); -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[X]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[X]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[X]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[X]], i32 0, i32 1 // CHECK-NEXT: store float 2.000000e+00, float* [[T0]] // CHECK-NEXT: store float 0.000000e+00, float* [[T1]] _Atomic(_Complex float) x = 2.0f; -// CHECK-NEXT: [[T0:%.*]] = load [[CF]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[CF]]*, [[CF]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[CF]]* [[T0]] to i64* -// CHECK-NEXT: [[T2:%.*]] = load atomic i64* [[T1]] seq_cst, align 8 +// CHECK-NEXT: [[T2:%.*]] = load atomic i64, i64* [[T1]] seq_cst, align 8 // CHECK-NEXT: [[T3:%.*]] = bitcast [[CF]]* [[TMP0]] to i64* // CHECK-NEXT: store i64 [[T2]], i64* [[T3]], align 8 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: [[R:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[TMP0]], i32 0, i32 1 -// CHECK-NEXT: [[I:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[R:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 1 +// CHECK-NEXT: [[I:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 1 // CHECK-NEXT: store float [[R]], float* [[T0]] // CHECK-NEXT: store float [[I]], float* [[T1]] _Complex float f = *fp; -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 0 -// CHECK-NEXT: [[R:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 1 -// CHECK-NEXT: [[I:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[DEST:%.*]] = load [[CF]]** [[FP]], align 4 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[TMP1]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 0 +// CHECK-NEXT: [[R:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 1 +// CHECK-NEXT: [[I:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[DEST:%.*]] = load [[CF]]*, [[CF]]** [[FP]], align 4 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP1]], i32 0, i32 1 // CHECK-NEXT: store float [[R]], float* [[T0]] // CHECK-NEXT: store float [[I]], float* [[T1]] // CHECK-NEXT: [[T0:%.*]] = bitcast [[CF]]* [[TMP1]] to i64* -// CHECK-NEXT: [[T1:%.*]] = load i64* [[T0]], align 8 +// CHECK-NEXT: [[T1:%.*]] = load i64, i64* [[T0]], align 8 // CHECK-NEXT: [[T2:%.*]] = bitcast [[CF]]* [[DEST]] to i64* // CHECK-NEXT: store atomic i64 [[T1]], i64* [[T2]] seq_cst, align 8 *fp = f; @@ -101,40 +101,40 @@ void testStruct(_Atomic(S) *fp) { // CHECK-NEXT: [[TMP0:%.*]] = alloca [[S]], align 8 // CHECK-NEXT: store [[S]]* -// CHECK-NEXT: [[P:%.*]] = load [[S]]** [[FP]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 0 +// CHECK-NEXT: [[P:%.*]] = load [[S]]*, [[S]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 2 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 3 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 3 // CHECK-NEXT: store i16 4, i16* [[T0]], align 2 __c11_atomic_init(fp, (S){1,2,3,4}); -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 2 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 3 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 3 // CHECK-NEXT: store i16 4, i16* [[T0]], align 2 _Atomic(S) x = (S){1,2,3,4}; -// CHECK-NEXT: [[T0:%.*]] = load [[S]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[S]]* [[T0]] to i64* -// CHECK-NEXT: [[T2:%.*]] = load atomic i64* [[T1]] seq_cst, align 8 +// CHECK-NEXT: [[T2:%.*]] = load atomic i64, i64* [[T1]] seq_cst, align 8 // CHECK-NEXT: [[T3:%.*]] = bitcast [[S]]* [[F]] to i64* // CHECK-NEXT: store i64 [[T2]], i64* [[T3]], align 2 S f = *fp; -// CHECK-NEXT: [[T0:%.*]] = load [[S]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[S]]* [[TMP0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[S]]* [[F]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T1]], i8* [[T2]], i32 8, i32 2, i1 false) // CHECK-NEXT: [[T3:%.*]] = bitcast [[S]]* [[TMP0]] to i64* -// CHECK-NEXT: [[T4:%.*]] = load i64* [[T3]], align 8 +// CHECK-NEXT: [[T4:%.*]] = load i64, i64* [[T3]], align 8 // CHECK-NEXT: [[T5:%.*]] = bitcast [[S]]* [[T0]] to i64* // CHECK-NEXT: store atomic i64 [[T4]], i64* [[T5]] seq_cst, align 8 *fp = f; @@ -152,49 +152,49 @@ void testPromotedStruct(_Atomic(PS) *fp) { // CHECK-NEXT: [[TMP1:%.*]] = alloca [[APS]], align 8 // CHECK-NEXT: store [[APS]]* -// CHECK-NEXT: [[P:%.*]] = load [[APS]]** [[FP]] +// CHECK-NEXT: [[P:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[P]] to i8* // CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[T0]], i8 0, i64 8, i32 8, i1 false) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]]* [[P]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[P]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 1 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 2 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T1]], align 2 __c11_atomic_init(fp, (PS){1,2,3}); // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[X]] to i8* // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* [[T0]], i8 0, i32 8, i32 8, i1 false) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]]* [[X]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[X]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 1 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 2 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T1]], align 2 _Atomic(PS) x = (PS){1,2,3}; -// CHECK-NEXT: [[T0:%.*]] = load [[APS]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[APS]]* [[T0]] to i64* -// CHECK-NEXT: [[T2:%.*]] = load atomic i64* [[T1]] seq_cst, align 8 +// CHECK-NEXT: [[T2:%.*]] = load atomic i64, i64* [[T1]] seq_cst, align 8 // CHECK-NEXT: [[T3:%.*]] = bitcast [[APS]]* [[TMP0]] to i64* // CHECK-NEXT: store i64 [[T2]], i64* [[T3]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]]* [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = bitcast [[PS]]* [[F]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[PS]]* [[T0]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T1]], i8* [[T2]], i32 6, i32 2, i1 false) PS f = *fp; -// CHECK-NEXT: [[T0:%.*]] = load [[APS]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[TMP1]] to i8* // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* [[T1]], i8 0, i32 8, i32 8, i1 false) -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[APS]]* [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP1]], i32 0, i32 0 // CHECK-NEXT: [[T2:%.*]] = bitcast [[PS]]* [[T1]] to i8* // CHECK-NEXT: [[T3:%.*]] = bitcast [[PS]]* [[F]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T2]], i8* [[T3]], i32 6, i32 2, i1 false) // CHECK-NEXT: [[T4:%.*]] = bitcast [[APS]]* [[TMP1]] to i64* -// CHECK-NEXT: [[T5:%.*]] = load i64* [[T4]], align 8 +// CHECK-NEXT: [[T5:%.*]] = load i64, i64* [[T4]], align 8 // CHECK-NEXT: [[T6:%.*]] = bitcast [[APS]]* [[T0]] to i64* // CHECK-NEXT: store atomic i64 [[T5]], i64* [[T6]] seq_cst, align 8 *fp = f; diff --git a/test/CodeGen/c11atomics.c b/test/CodeGen/c11atomics.c index 376c58267410..a35eef942648 100644 --- a/test/CodeGen/c11atomics.c +++ b/test/CodeGen/c11atomics.c @@ -147,23 +147,23 @@ void testFloat(_Atomic(float) *fp) { // CHECK-NEXT: [[TMP1:%.*]] = alloca float // CHECK-NEXT: store float* {{%.*}}, float** [[FP]] -// CHECK-NEXT: [[T0:%.*]] = load float** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]] // CHECK-NEXT: store float 1.000000e+00, float* [[T0]], align 4 __c11_atomic_init(fp, 1.0f); // CHECK-NEXT: store float 2.000000e+00, float* [[X]], align 4 _Atomic(float) x = 2.0f; -// CHECK-NEXT: [[T0:%.*]] = load float** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast float* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast float* [[TMP0]] to i8* // CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 4, i8* [[T1]], i8* [[T2]], i32 5) -// CHECK-NEXT: [[T3:%.*]] = load float* [[TMP0]], align 4 +// CHECK-NEXT: [[T3:%.*]] = load float, float* [[TMP0]], align 4 // CHECK-NEXT: store float [[T3]], float* [[F]] float f = *fp; -// CHECK-NEXT: [[T0:%.*]] = load float* [[F]], align 4 -// CHECK-NEXT: [[T1:%.*]] = load float** [[FP]], align 4 +// CHECK-NEXT: [[T0:%.*]] = load float, float* [[F]], align 4 +// CHECK-NEXT: [[T1:%.*]] = load float*, float** [[FP]], align 4 // CHECK-NEXT: store float [[T0]], float* [[TMP1]], align 4 // CHECK-NEXT: [[T2:%.*]] = bitcast float* [[T1]] to i8* // CHECK-NEXT: [[T3:%.*]] = bitcast float* [[TMP1]] to i8* @@ -182,40 +182,40 @@ void testComplexFloat(_Atomic(_Complex float) *fp) { // CHECK-NEXT: [[TMP1:%.*]] = alloca [[CF]], align 8 // CHECK-NEXT: store [[CF]]* -// CHECK-NEXT: [[P:%.*]] = load [[CF]]** [[FP]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[P]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[P]], i32 0, i32 1 +// CHECK-NEXT: [[P:%.*]] = load [[CF]]*, [[CF]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[P]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[P]], i32 0, i32 1 // CHECK-NEXT: store float 1.000000e+00, float* [[T0]] // CHECK-NEXT: store float 0.000000e+00, float* [[T1]] __c11_atomic_init(fp, 1.0f); -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[X]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[X]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[X]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[X]], i32 0, i32 1 // CHECK-NEXT: store float 2.000000e+00, float* [[T0]] // CHECK-NEXT: store float 0.000000e+00, float* [[T1]] _Atomic(_Complex float) x = 2.0f; -// CHECK-NEXT: [[T0:%.*]] = load [[CF]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[CF]]*, [[CF]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[CF]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[CF]]* [[TMP0]] to i8* // CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: [[R:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[TMP0]], i32 0, i32 1 -// CHECK-NEXT: [[I:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[R:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 1 +// CHECK-NEXT: [[I:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 1 // CHECK-NEXT: store float [[R]], float* [[T0]] // CHECK-NEXT: store float [[I]], float* [[T1]] _Complex float f = *fp; -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 0 -// CHECK-NEXT: [[R:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[F]], i32 0, i32 1 -// CHECK-NEXT: [[I:%.*]] = load float* [[T0]] -// CHECK-NEXT: [[DEST:%.*]] = load [[CF]]** [[FP]], align 4 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]]* [[TMP1]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]]* [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 0 +// CHECK-NEXT: [[R:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 1 +// CHECK-NEXT: [[I:%.*]] = load float, float* [[T0]] +// CHECK-NEXT: [[DEST:%.*]] = load [[CF]]*, [[CF]]** [[FP]], align 4 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP1]], i32 0, i32 1 // CHECK-NEXT: store float [[R]], float* [[T0]] // CHECK-NEXT: store float [[I]], float* [[T1]] // CHECK-NEXT: [[T0:%.*]] = bitcast [[CF]]* [[DEST]] to i8* @@ -236,34 +236,34 @@ void testStruct(_Atomic(S) *fp) { // CHECK-NEXT: [[TMP0:%.*]] = alloca [[S]], align 8 // CHECK-NEXT: store [[S]]* -// CHECK-NEXT: [[P:%.*]] = load [[S]]** [[FP]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 0 +// CHECK-NEXT: [[P:%.*]] = load [[S]]*, [[S]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 2 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[P]], i32 0, i32 3 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 3 // CHECK-NEXT: store i16 4, i16* [[T0]], align 2 __c11_atomic_init(fp, (S){1,2,3,4}); -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 1 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 2 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T0]], align 2 -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]]* [[X]], i32 0, i32 3 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 3 // CHECK-NEXT: store i16 4, i16* [[T0]], align 2 _Atomic(S) x = (S){1,2,3,4}; -// CHECK-NEXT: [[T0:%.*]] = load [[S]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[S]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[S]]* [[F]] to i8* // CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) S f = *fp; -// CHECK-NEXT: [[T0:%.*]] = load [[S]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[S]]* [[TMP0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[S]]* [[F]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T1]], i8* [[T2]], i32 8, i32 2, i1 false) @@ -289,43 +289,43 @@ void testPromotedStruct(_Atomic(PS) *fp) { // CHECK-NEXT: [[TMP3:%.*]] = alloca [[APS]], align 8 // CHECK-NEXT: store [[APS]]* -// CHECK-NEXT: [[P:%.*]] = load [[APS]]** [[FP]] +// CHECK-NEXT: [[P:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[P]] to i8* // CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[T0]], i8 0, i64 8, i32 8, i1 false) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]]* [[P]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[P]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 1 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 2 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T1]], align 2 __c11_atomic_init(fp, (PS){1,2,3}); // CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[X]] to i8* // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* [[T0]], i8 0, i32 8, i32 8, i1 false) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]]* [[X]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[X]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0 // CHECK-NEXT: store i16 1, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 1 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1 // CHECK-NEXT: store i16 2, i16* [[T1]], align 2 -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]]* [[T0]], i32 0, i32 2 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2 // CHECK-NEXT: store i16 3, i16* [[T1]], align 2 _Atomic(PS) x = (PS){1,2,3}; -// CHECK-NEXT: [[T0:%.*]] = load [[APS]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast [[APS]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[APS]]* [[TMP0]] to i8* // CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]]* [[TMP0]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = bitcast [[PS]]* [[F]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[PS]]* [[T0]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T1]], i8* [[T2]], i32 6, i32 2, i1 false) PS f = *fp; -// CHECK-NEXT: [[T0:%.*]] = load [[APS]]** [[FP]] +// CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]] // CHECK-NEXT: [[T1:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[TMP1]] to i8* // CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* [[T1]], i8 0, i32 8, i32 8, i1 false) -// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[APS]]* [[TMP1]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP1]], i32 0, i32 0 // CHECK-NEXT: [[T2:%.*]] = bitcast [[PS]]* [[T1]] to i8* // CHECK-NEXT: [[T3:%.*]] = bitcast [[PS]]* [[F]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T2]], i8* [[T3]], i32 6, i32 2, i1 false) @@ -334,16 +334,16 @@ void testPromotedStruct(_Atomic(PS) *fp) { // CHECK-NEXT: call arm_aapcscc void @__atomic_store(i32 8, i8* [[T4]], i8* [[T5]], i32 5) *fp = f; -// CHECK-NEXT: [[T0:%.*]] = load [[APS]]** [[FP]], align 4 +// CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]], align 4 // CHECK-NEXT: [[T1:%.*]] = bitcast [[APS]]* [[T0]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast [[APS]]* [[TMP3]] to i8* // CHECK-NEXT: call arm_aapcscc void @__atomic_load(i32 8, i8* [[T1]], i8* [[T2]], i32 5) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]]* [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP3]], i32 0, i32 0 // CHECK-NEXT: [[T1:%.*]] = bitcast %struct.PS* [[TMP2]] to i8* // CHECK-NEXT: [[T2:%.*]] = bitcast %struct.PS* [[T0]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T1]], i8* [[T2]], i32 6, i32 2, i1 false) -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds %struct.PS* [[TMP2]], i32 0, i32 0 -// CHECK-NEXT: [[T1:%.*]] = load i16* [[T0]], align 2 +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds %struct.PS, %struct.PS* [[TMP2]], i32 0, i32 0 +// CHECK-NEXT: [[T1:%.*]] = load i16, i16* [[T0]], align 2 // CHECK-NEXT: [[T2:%.*]] = sext i16 [[T1]] to i32 // CHECK-NEXT: store i32 [[T2]], i32* [[A]], align 4 int a = ((PS)*fp).x; diff --git a/test/CodeGen/call.c b/test/CodeGen/call.c index ef327751b3ad..723911158c05 100644 --- a/test/CodeGen/call.c +++ b/test/CodeGen/call.c @@ -18,7 +18,7 @@ void JS_ReportErrorNumber(JSErrorCallback errorCallback, ...); void Interpret() { JS_ReportErrorNumber(js_GetErrorMessage, 0); - // CHECK: call void ({{.*}}, ...)* @JS_ReportErrorNumber({{.*}}@js_GetErrorMessage + // CHECK: call void ({{.*}}, ...) @JS_ReportErrorNumber({{.*}}@js_GetErrorMessage } diff --git a/test/CodeGen/capture-complex-expr-in-block.c b/test/CodeGen/capture-complex-expr-in-block.c index 83695a8b734d..20e078e66150 100644 --- a/test/CodeGen/capture-complex-expr-in-block.c +++ b/test/CodeGen/capture-complex-expr-in-block.c @@ -14,7 +14,7 @@ int main () // CHECK-LABEL: define internal void @__main_block_invoke // CHECK: [[C1:%.*]] = alloca { double, double }, align 8 -// CHECK: [[RP:%.*]] = getelementptr inbounds { double, double }* [[C1]], i32 0, i32 0 -// CHECK-NEXT: [[R:%.*]] = load double* [[RP]] -// CHECK-NEXT: [[IP:%.*]] = getelementptr inbounds { double, double }* [[C1]], i32 0, i32 1 -// CHECK-NEXT: [[I:%.*]] = load double* [[IP]] +// CHECK: [[RP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[C1]], i32 0, i32 0 +// CHECK-NEXT: [[R:%.*]] = load double, double* [[RP]] +// CHECK-NEXT: [[IP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[C1]], i32 0, i32 1 +// CHECK-NEXT: [[I:%.*]] = load double, double* [[IP]] diff --git a/test/CodeGen/captured-statements-nested.c b/test/CodeGen/captured-statements-nested.c index cd20b5a66462..646424339b7f 100644 --- a/test/CodeGen/captured-statements-nested.c +++ b/test/CodeGen/captured-statements-nested.c @@ -31,63 +31,63 @@ void test_nest_captured_stmt(int param, int size, int param_arr[size]) { arr[10][z.a] = 12; // CHECK1: define internal void @__captured_stmt{{.*}}([[T]] - // CHECK1: [[PARAM_ARR_SIZE_REF:%.+]] = getelementptr inbounds [[T]]* {{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 5 - // CHECK1: [[PARAM_ARR_SIZE:%.+]] = load [[SIZE_TYPE]]* [[PARAM_ARR_SIZE_REF]] - // CHECK1: [[ARR_SIZE1_REF:%.+]] = getelementptr inbounds [[T]]* {{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 8 - // CHECK1: [[ARR_SIZE1:%.+]] = load [[SIZE_TYPE]]* [[ARR_SIZE1_REF]] - // CHECK1: [[ARR_SIZE2_REF:%.+]] = getelementptr inbounds [[T]]* {{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 9 - // CHECK1: [[ARR_SIZE2:%.+]] = load [[SIZE_TYPE]]* [[ARR_SIZE2_REF]] + // CHECK1: [[PARAM_ARR_SIZE_REF:%.+]] = getelementptr inbounds [[T]], [[T]]* {{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 5 + // CHECK1: [[PARAM_ARR_SIZE:%.+]] = load [[SIZE_TYPE]], [[SIZE_TYPE]]* [[PARAM_ARR_SIZE_REF]] + // CHECK1: [[ARR_SIZE1_REF:%.+]] = getelementptr inbounds [[T]], [[T]]* {{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 8 + // CHECK1: [[ARR_SIZE1:%.+]] = load [[SIZE_TYPE]], [[SIZE_TYPE]]* [[ARR_SIZE1_REF]] + // CHECK1: [[ARR_SIZE2_REF:%.+]] = getelementptr inbounds [[T]], [[T]]* {{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 9 + // CHECK1: [[ARR_SIZE2:%.+]] = load [[SIZE_TYPE]], [[SIZE_TYPE]]* [[ARR_SIZE2_REF]] // - // CHECK1: getelementptr inbounds [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 2 - // CHECK1-NEXT: load %struct.A** - // CHECK1-NEXT: getelementptr inbounds %struct.A* + // CHECK1: getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 2 + // CHECK1-NEXT: load %struct.A*, %struct.A** + // CHECK1-NEXT: getelementptr inbounds %struct.A, %struct.A* // CHECK1-NEXT: store i{{.+}} 1 // - // CHECK1: getelementptr inbounds [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK1-NEXT: load i{{[0-9]+}}** + // CHECK1: getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK1-NEXT: load i{{[0-9]+}}*, i{{[0-9]+}}** // CHECK1-NEXT: store i{{[0-9]+}} 1 // - // CHECK1: getelementptr inbounds [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK1-NEXT: load i{{[0-9]+}}** + // CHECK1: getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK1-NEXT: load i{{[0-9]+}}*, i{{[0-9]+}}** // CHECK1-NEXT: store i{{[0-9]+}} 1 // - // CHECK1: getelementptr inbounds [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 4 - // CHECK1-NEXT: load i{{[0-9]+}}** - // CHECK1-NEXT: load i{{[0-9]+}}* - // CHECK1-NEXT: getelementptr inbounds [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 3 - // CHECK1-NEXT: load i{{[0-9]+}}*** - // CHECK1-NEXT: load i{{[0-9]+}}** + // CHECK1: getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 4 + // CHECK1-NEXT: load i{{[0-9]+}}*, i{{[0-9]+}}** + // CHECK1-NEXT: load i{{[0-9]+}}, i{{[0-9]+}}* + // CHECK1-NEXT: getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 3 + // CHECK1-NEXT: load i{{[0-9]+}}**, i{{[0-9]+}}*** + // CHECK1-NEXT: load i{{[0-9]+}}*, i{{[0-9]+}}** // CHECK1-NEXT: store i{{[0-9]+}} // - // CHECK1: getelementptr inbounds [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 2 - // CHECK1-NEXT: load %struct.A** - // CHECK1-NEXT: getelementptr inbounds %struct.A* + // CHECK1: getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 2 + // CHECK1-NEXT: load %struct.A*, %struct.A** + // CHECK1-NEXT: getelementptr inbounds %struct.A, %struct.A* // CHECK1-NEXT: store float // - // CHECK1: getelementptr inbounds [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 2 - // CHECK1-NEXT: load %struct.A** - // CHECK1-NEXT: getelementptr inbounds %struct.A* + // CHECK1: getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 2 + // CHECK1-NEXT: load %struct.A*, %struct.A** + // CHECK1-NEXT: getelementptr inbounds %struct.A, %struct.A* // CHECK1-NEXT: store i8 99 // - // CHECK1: [[SIZE_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 7 - // CHECK1-DAG: [[SIZE_ADDR:%.*]] = load i{{.+}}** [[SIZE_ADDR_REF]] - // CHECK1-DAG: [[SIZE:%.*]] = load i{{.+}}* [[SIZE_ADDR]] + // CHECK1: [[SIZE_ADDR_REF:%.*]] = getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 7 + // CHECK1-DAG: [[SIZE_ADDR:%.*]] = load i{{.+}}*, i{{.+}}** [[SIZE_ADDR_REF]] + // CHECK1-DAG: [[SIZE:%.*]] = load i{{.+}}, i{{.+}}* [[SIZE_ADDR]] // CHECK1-DAG: [[PARAM_ARR_IDX:%.*]] = sub nsw i{{.+}} [[SIZE]], 1 - // CHECK1-DAG: [[PARAM_ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 6 - // CHECK1-DAG: [[PARAM_ARR_ADDR:%.*]] = load i{{.+}}*** [[PARAM_ARR_ADDR_REF]] - // CHECK1-DAG: [[PARAM_ARR:%.*]] = load i{{.+}}** [[PARAM_ARR_ADDR]] - // CHECK1-DAG: [[PARAM_ARR_SIZE_MINUS_1_ADDR:%.*]] = getelementptr inbounds i{{.+}}* [[PARAM_ARR]], i{{.*}} + // CHECK1-DAG: [[PARAM_ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 6 + // CHECK1-DAG: [[PARAM_ARR_ADDR:%.*]] = load i{{.+}}**, i{{.+}}*** [[PARAM_ARR_ADDR_REF]] + // CHECK1-DAG: [[PARAM_ARR:%.*]] = load i{{.+}}*, i{{.+}}** [[PARAM_ARR_ADDR]] + // CHECK1-DAG: [[PARAM_ARR_SIZE_MINUS_1_ADDR:%.*]] = getelementptr inbounds i{{.+}}, i{{.+}}* [[PARAM_ARR]], i{{.*}} // CHECK1: store i{{.+}} 2, i{{.+}}* [[PARAM_ARR_SIZE_MINUS_1_ADDR]] // - // CHECK1: [[Z_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 2 - // CHECK1-DAG: [[Z_ADDR:%.*]] = load %struct.A** [[Z_ADDR_REF]] - // CHECK1-DAG: [[Z_A_ADDR:%.*]] = getelementptr inbounds %struct.A* [[Z_ADDR]], i{{.+}} 0, i{{.+}} 0 - // CHECK1-DAG: [[ARR_IDX_2:%.*]] = load i{{.+}}* [[Z_A_ADDR]] - // CHECK1-DAG: [[ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 10 - // CHECK1-DAG: [[ARR_ADDR:%.*]] = load i{{.+}}** [[ARR_ADDR_REF]] + // CHECK1: [[Z_ADDR_REF:%.*]] = getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 2 + // CHECK1-DAG: [[Z_ADDR:%.*]] = load %struct.A*, %struct.A** [[Z_ADDR_REF]] + // CHECK1-DAG: [[Z_A_ADDR:%.*]] = getelementptr inbounds %struct.A, %struct.A* [[Z_ADDR]], i{{.+}} 0, i{{.+}} 0 + // CHECK1-DAG: [[ARR_IDX_2:%.*]] = load i{{.+}}, i{{.+}}* [[Z_A_ADDR]] + // CHECK1-DAG: [[ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]], [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 10 + // CHECK1-DAG: [[ARR_ADDR:%.*]] = load i{{.+}}*, i{{.+}}** [[ARR_ADDR_REF]] // CHECK1-DAG: [[ARR_IDX_1:%.*]] = mul {{.*}} 10 - // CHECK1-DAG: [[ARR_10_ADDR:%.*]] = getelementptr inbounds i{{.+}}* [[ARR_ADDR]], i{{.*}} [[ARR_IDX_1]] - // CHECK1-DAG: [[ARR_10_Z_A_ADDR:%.*]] = getelementptr inbounds i{{.+}}* [[ARR_10_ADDR]], i{{.*}} + // CHECK1-DAG: [[ARR_10_ADDR:%.*]] = getelementptr inbounds i{{.+}}, i{{.+}}* [[ARR_ADDR]], i{{.*}} [[ARR_IDX_1]] + // CHECK1-DAG: [[ARR_10_Z_A_ADDR:%.*]] = getelementptr inbounds i{{.+}}, i{{.+}}* [[ARR_10_ADDR]], i{{.*}} // CHECK1: store i{{.+}} 12, i{{.+}}* [[ARR_10_Z_A_ADDR]] } } @@ -143,12 +143,12 @@ void test_nest_block() { // CHECK2: [[CapA:%[0-9a-z_.]*]] = getelementptr inbounds {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 7 // // CHECK2: getelementptr inbounds %struct.anon{{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK2: load i{{[0-9]+}}** - // CHECK2: load i{{[0-9]+}}* + // CHECK2: load i{{[0-9]+}}*, i{{[0-9]+}}** + // CHECK2: load i{{[0-9]+}}, i{{[0-9]+}}* // CHECK2: store i{{[0-9]+}} {{.*}}, i{{[0-9]+}}* [[CapA]] // // CHECK2: [[CapC:%[0-9a-z_.]*]] = getelementptr inbounds {{.*}}, i{{[0-9]+}} 0, i{{[0-9]+}} 8 - // CHECK2-NEXT: [[Val:%[0-9a-z_]*]] = load i{{[0-9]+}}* [[C]] + // CHECK2-NEXT: [[Val:%[0-9a-z_]*]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[C]] // CHECK2-NEXT: store i{{[0-9]+}} [[Val]], i{{[0-9]+}}* [[CapC]] // // CHECK2: bitcast %struct.__block_byref_d* diff --git a/test/CodeGen/captured-statements.c b/test/CodeGen/captured-statements.c index 52747fba1e90..b4fbfd43d5ca 100644 --- a/test/CodeGen/captured-statements.c +++ b/test/CodeGen/captured-statements.c @@ -14,21 +14,24 @@ void test1() { int i = 0; #pragma clang __debug captured { + static float inner = 3.0; + (void)inner; i++; } // CHECK-1: %struct.anon = type { i32* } + // CHECK-1: {{.+}} global float 3.0 // // CHECK-1: test1 // CHECK-1: alloca %struct.anon - // CHECK-1: getelementptr inbounds %struct.anon* + // CHECK-1: getelementptr inbounds %struct.anon, %struct.anon* // CHECK-1: store i32* %i - // CHECK-1: call void @[[HelperName:__captured_stmt[0-9]+]] + // CHECK-1: call void @[[HelperName:__captured_stmt[\.0-9]+]] } // CHECK-1: define internal void @[[HelperName]](%struct.anon // CHECK-1: getelementptr inbounds %struct.anon{{.*}}, i32 0, i32 0 -// CHECK-1: load i32** -// CHECK-1: load i32* +// CHECK-1: load i32*, i32** +// CHECK-1: load i32, i32* // CHECK-1: add nsw i32 // CHECK-1: store i32 @@ -42,7 +45,7 @@ void test2(int x) { } // CHECK-2: test2 // CHECK-2-NOT: %i - // CHECK-2: call void @[[HelperName:__captured_stmt[0-9]+]] + // CHECK-2: call void @[[HelperName:__captured_stmt[\.0-9]+]] } // CHECK-2: define internal void @[[HelperName]] @@ -70,7 +73,7 @@ void test4(intptr_t size, intptr_t vla_arr[size]) { } // CHECK-3: test4([[INTPTR_T:i.+]] {{.*}}[[SIZE_ARG:%.+]], [[INTPTR_T]]* // CHECK-3: store [[INTPTR_T]] {{.*}}[[SIZE_ARG]], [[INTPTR_T]]* [[SIZE_ADDR:%.+]], - // CHECK-3: [[SIZE:%.+]] = load [[INTPTR_T]]* [[SIZE_ADDR]], + // CHECK-3: [[SIZE:%.+]] = load [[INTPTR_T]], [[INTPTR_T]]* [[SIZE_ADDR]], // CHECK-3: [[REF:%.+]] = getelementptr inbounds // CHECK-3: store [[INTPTR_T]] [[SIZE]], [[INTPTR_T]]* [[REF]] // CHECK-3: call void @__captured_stmt @@ -87,11 +90,11 @@ void dont_capture_global() { } // CHECK-GLOBALS: %[[Capture:struct\.anon[\.0-9]*]] = type {} - // CHECK-GLOBALS: call void @__captured_stmt[[HelperName:[0-9]+]](%[[Capture]] + // CHECK-GLOBALS: call void @__captured_stmt[[HelperName:[\.0-9]+]](%[[Capture]] } // CHECK-GLOBALS: define internal void @__captured_stmt[[HelperName]] // CHECK-GLOBALS-NOT: ret -// CHECK-GLOBALS: load i32* @global -// CHECK-GLOBALS: load i32* @ -// CHECK-GLOBALS: load i32* @e +// CHECK-GLOBALS: load i32, i32* @global +// CHECK-GLOBALS: load i32, i32* @ +// CHECK-GLOBALS: load i32, i32* @e diff --git a/test/CodeGen/catch-undef-behavior.c b/test/CodeGen/catch-undef-behavior.c index c41b37c39bc8..a4386588757d 100644 --- a/test/CodeGen/catch-undef-behavior.c +++ b/test/CodeGen/catch-undef-behavior.c @@ -1,7 +1,8 @@ -// RUN: %clang_cc1 -fsanitize=alignment,null,object-size,shift,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-UBSAN -// RUN: %clang_cc1 -fsanitize-undefined-trap-on-error -fsanitize=alignment,null,object-size,shift,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-TRAP +// RUN: %clang_cc1 -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-UBSAN +// RUN: %clang_cc1 -fsanitize-undefined-trap-on-error -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-TRAP // RUN: %clang_cc1 -fsanitize=null -fsanitize-recover=null -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-NULL // RUN: %clang_cc1 -fsanitize=signed-integer-overflow -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-OVERFLOW +// REQUIRES: asserts // CHECK-UBSAN: @[[INT:.*]] = private unnamed_addr constant { i16, i16, [6 x i8] } { i16 0, i16 11, [6 x i8] c"'int'\00" } @@ -83,15 +84,19 @@ int addr_space(int __attribute__((address_space(256))) *a) { // CHECK-COMMON-LABEL: @lsh_overflow int lsh_overflow(int a, int b) { - // CHECK-COMMON: %[[INBOUNDS:.*]] = icmp ule i32 %[[RHS:.*]], 31 - // CHECK-COMMON-NEXT: br i1 %[[INBOUNDS]], label %[[CHECKBB:.*]], label %[[CONTBB:.*]] + // CHECK-COMMON: %[[RHS_INBOUNDS:.*]] = icmp ule i32 %[[RHS:.*]], 31 + // CHECK-COMMON-NEXT: br i1 %[[RHS_INBOUNDS]], label %[[CHECK_BB:.*]], label %[[CONT_BB:.*]], - // CHECK-COMMON: %[[SHIFTED_OUT_WIDTH:.*]] = sub nuw nsw i32 31, %[[RHS]] + // CHECK-COMMON: [[CHECK_BB]]: + // CHECK-COMMON-NEXT: %[[SHIFTED_OUT_WIDTH:.*]] = sub nuw nsw i32 31, %[[RHS]] // CHECK-COMMON-NEXT: %[[SHIFTED_OUT:.*]] = lshr i32 %[[LHS:.*]], %[[SHIFTED_OUT_WIDTH]] // CHECK-COMMON-NEXT: %[[NO_OVERFLOW:.*]] = icmp eq i32 %[[SHIFTED_OUT]], 0 - // CHECK-COMMON-NEXT: br label %[[CONTBB]] + // CHECK-COMMON-NEXT: br label %[[CONT_BB]] + + // CHECK-COMMON: [[CONT_BB]]: + // CHECK-COMMON-NEXT: %[[VALID_BASE:.*]] = phi i1 [ true, {{.*}} ], [ %[[NO_OVERFLOW]], %[[CHECK_BB]] ] + // CHECK-COMMON-NEXT: %[[VALID:.*]] = and i1 %[[RHS_INBOUNDS]], %[[VALID_BASE]] - // CHECK-COMMON: %[[VALID:.*]] = phi i1 [ %[[INBOUNDS]], {{.*}} ], [ %[[NO_OVERFLOW]], %[[CHECKBB]] ] // CHECK-UBSAN: br i1 %[[VALID]], {{.*}} !prof ![[WEIGHT_MD]] // CHECK-TRAP: br i1 %[[VALID]] @@ -122,7 +127,7 @@ int rsh_inbounds(int a, int b) { // CHECK-TRAP: call void @llvm.trap() [[NR_NUW]] // CHECK-TRAP-NEXT: unreachable - // CHECK-COMMON: %[[RET:.*]] = ashr i32 %[[LHS]], %[[RHS]] + // CHECK-COMMON: %[[RET:.*]] = ashr i32 {{.*}}, %[[RHS]] // CHECK-COMMON-NEXT: ret i32 %[[RET]] #line 400 return a >> b; @@ -375,7 +380,7 @@ void call_nonnull_variadic(int a, int *b) { // CHECK-UBSAN: call void @__ubsan_handle_nonnull_arg // CHECK-UBSAN-NOT: __ubsan_handle_nonnull_arg - // CHECK-COMMON: call void (i32, ...)* @nonnull_variadic + // CHECK-COMMON: call void (i32, ...) @nonnull_variadic nonnull_variadic(a, b); } diff --git a/test/CodeGen/cfstring.c b/test/CodeGen/cfstring.c index fc86e42a6fca..97d39b6a6595 100644 --- a/test/CodeGen/cfstring.c +++ b/test/CodeGen/cfstring.c @@ -6,8 +6,8 @@ // RUN: %clang_cc1 -fwritable-strings -emit-llvm %s -o - | FileCheck %s // // CHECK: @.str = private unnamed_addr constant [14 x i8] c"Hello, World!\00", section "__TEXT,__cstring,cstring_literals", align 1 -// CHECK: @.str1 = private unnamed_addr constant [7 x i8] c"yo joe\00", section "__TEXT,__cstring,cstring_literals", align 1 -// CHECK: @.str3 = private unnamed_addr constant [16 x i8] c"Goodbye, World!\00", section "__TEXT,__cstring,cstring_literals", align 1 +// CHECK: @.str.1 = private unnamed_addr constant [7 x i8] c"yo joe\00", section "__TEXT,__cstring,cstring_literals", align 1 +// CHECK: @.str.3 = private unnamed_addr constant [16 x i8] c"Goodbye, World!\00", section "__TEXT,__cstring,cstring_literals", align 1 #define CFSTR __builtin___CFStringMakeConstantString diff --git a/test/CodeGen/cleanup-destslot-simple.c b/test/CodeGen/cleanup-destslot-simple.c new file mode 100644 index 000000000000..bae97c81cbba --- /dev/null +++ b/test/CodeGen/cleanup-destslot-simple.c @@ -0,0 +1,19 @@ +// RUN: %clang_cc1 -O1 -triple x86_64-none-linux-gnu -emit-llvm -gline-tables-only %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=LIFETIME + +// We shouldn't have markers at -O0 or with msan. +// RUN: %clang_cc1 -O0 -triple x86_64-none-linux-gnu -emit-llvm -gline-tables-only %s -o - | FileCheck %s --check-prefix=CHECK +// RUN: %clang_cc1 -O1 -triple x86_64-none-linux-gnu -emit-llvm -gline-tables-only %s -o - -fsanitize=memory | FileCheck %s --check-prefix=CHECK + +// There is no exception to handle here, lifetime.end is not a destructor, +// so there is no need have cleanup dest slot related code +// CHECK-LABEL: define i32 @test +int test() { + int x = 3; + int *volatile p = &x; + return *p; +// CHECK: [[X:%.*]] = alloca i32 +// CHECK: [[P:%.*]] = alloca i32* +// LIFETIME: call void @llvm.lifetime.start(i64 4, i8* %{{.*}}) +// LIFETIME: call void @llvm.lifetime.start(i64 8, i8* %{{.*}}) +// CHECK-NOT: store i32 %{{.*}}, i32* %cleanup.dest.slot +} diff --git a/test/CodeGen/cleanup-stack.c b/test/CodeGen/cleanup-stack.c index 72a1a6c751a9..6448aac2384a 100644 --- a/test/CodeGen/cleanup-stack.c +++ b/test/CodeGen/cleanup-stack.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple i386-unknown-unknown -O3 -emit-llvm %s -o %t -// RUN: grep "ret i32 9" %t +// RUN: %clang_cc1 -triple i386-unknown-unknown -O3 -emit-llvm %s -o - | FileCheck %s +// CHECK: ret i32 9 struct s0 { int *var; diff --git a/test/CodeGen/clear_cache.c b/test/CodeGen/clear_cache.c index f859d7fdc9a0..7bbcc03e21ca 100644 --- a/test/CodeGen/clear_cache.c +++ b/test/CodeGen/clear_cache.c @@ -7,6 +7,6 @@ char buffer[32] = "This is a largely unused buffer"; int main() { __builtin___clear_cache(buffer, buffer+32); -// CHECK: @llvm.clear_cache(i8* getelementptr {{.*}}, i8* getelementptr {{.*}} (i8* getelementptr {{.*}} 32)) +// CHECK: @llvm.clear_cache(i8* getelementptr inbounds ({{.*}}, i8* getelementptr inbounds (i8, i8* getelementptr inbounds ({{.*}} 32)) return 0; } diff --git a/test/CodeGen/complex-convert.c b/test/CodeGen/complex-convert.c index 6ecb884704c3..0db258840577 100644 --- a/test/CodeGen/complex-convert.c +++ b/test/CodeGen/complex-convert.c @@ -32,690 +32,690 @@ void foo(signed char sc, unsigned char uc, signed long long sll, // CHECK: alloca i[[LLSIZE]], align [[LLALIGN:[0-9]+]] sc1 = csc; - // CHECK: %[[VAR1:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR2:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR1]] + // CHECK: %[[VAR1:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR2:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR1]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR2]], i[[CHSIZE]]* %[[SC1:[A-Za-z0-9.]+]], align [[CHALIGN]] sc1 = cuc; - // CHECK-NEXT: %[[VAR3:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR4:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR3]] + // CHECK-NEXT: %[[VAR3:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR4:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR3]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR4]], i[[CHSIZE]]* %[[SC1]], align [[CHALIGN]] sc1 = csll; - // CHECK-NEXT: %[[VAR5:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR5]] + // CHECK-NEXT: %[[VAR5:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR5]] // CHECK-NEXT: %[[VAR7:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR6]] to i[[CHSIZE]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR7]], i[[CHSIZE]]* %[[SC1]], align [[CHALIGN]] sc1 = cull; - // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR8]] + // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR8]] // CHECK-NEXT: %[[VAR10:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR9]] to i[[CHSIZE]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR10]], i[[CHSIZE]]* %[[SC1]], align [[CHALIGN]] uc1 = csc; - // CHECK-NEXT: %[[VAR11:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR12:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR11]] + // CHECK-NEXT: %[[VAR11:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR12:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR11]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR12]], i[[CHSIZE]]* %[[UC1:[A-Za-z0-9.]+]], align [[CHALIGN]] uc1 = cuc; - // CHECK-NEXT: %[[VAR13:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR14:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR13]] + // CHECK-NEXT: %[[VAR13:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR14:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR13]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR14]], i[[CHSIZE]]* %[[UC1]], align [[CHALIGN]] uc1 = csll; - // CHECK-NEXT: %[[VAR15:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR16:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR15]] + // CHECK-NEXT: %[[VAR15:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR16:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR15]] // CHECK-NEXT: %[[VAR17:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR16]] to i[[CHSIZE]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR17]], i[[CHSIZE]]* %[[UC1]], align [[CHALIGN]] uc1 = cull; - // CHECK-NEXT: %[[VAR18:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR19:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR18]] + // CHECK-NEXT: %[[VAR18:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR19:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR18]] // CHECK-NEXT: %[[VAR20:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR19]] to i[[CHSIZE]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR20]], i[[CHSIZE]]* %[[UC1]], align [[CHALIGN]] sll1 = csc; - // CHECK-NEXT: %[[VAR21:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR22:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR21]] + // CHECK-NEXT: %[[VAR21:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR22:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR21]] // CHECK-NEXT: %[[VAR23:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR22]] to i[[LLSIZE]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR23]], i[[LLSIZE]]* %[[SLL1:[A-Za-z0-9]+]], align [[LLALIGN]] sll1 = cuc; - // CHECK-NEXT: %[[VAR24:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR25:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR24]] + // CHECK-NEXT: %[[VAR24:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR25:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR24]] // CHECK-NEXT: %[[VAR26:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR25]] to i[[LLSIZE]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR26]], i[[LLSIZE]]* %[[SLL1]], align [[LLALIGN]] sll1 = csll; - // CHECK-NEXT: %[[VAR27:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR28:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR27]] + // CHECK-NEXT: %[[VAR27:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR28:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR27]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR28]], i[[LLSIZE]]* %[[SLL1]], align [[LLALIGN]] sll1 = cull; - // CHECK-NEXT: %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR30:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR29]] + // CHECK-NEXT: %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR30:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR29]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR30]], i[[LLSIZE]]* %[[SLL1]], align [[LLALIGN]] ull1 = csc; - // CHECK-NEXT: %[[VAR31:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR32:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR31]] + // CHECK-NEXT: %[[VAR31:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR32:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR31]] // CHECK-NEXT: %[[VAR33:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR32]] to i[[LLSIZE]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR33]], i[[LLSIZE]]* %[[ULL1:[A-Za-z0-9]+]], align [[LLALIGN]] ull1 = cuc; - // CHECK-NEXT: %[[VAR34:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR35:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR34]] + // CHECK-NEXT: %[[VAR34:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR35:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR34]] // CHECK-NEXT: %[[VAR36:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR35]] to i[[LLSIZE]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR36]], i[[LLSIZE]]* %[[ULL1]], align [[LLALIGN]] ull1 = csll; - // CHECK-NEXT: %[[VAR37:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR38:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR37]] + // CHECK-NEXT: %[[VAR37:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR38:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR37]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR38]], i[[LLSIZE]]* %[[ULL1]], align [[LLALIGN]] ull1 = cull; - // CHECK-NEXT: %[[VAR39:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR40:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR39]] + // CHECK-NEXT: %[[VAR39:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR40:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR39]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR40]], i[[LLSIZE]]* %[[ULL1]], align [[LLALIGN]] csc1 = sc; - // CHECK-NEXT: %[[VAR41:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR:[A-Za-z0-9.]+]], align [[CHALIGN]] - // CHECK-NEXT: %[[VAR42:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR43:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR41:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR:[A-Za-z0-9.]+]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR42:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR43:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR41]], i[[CHSIZE]]* %[[VAR42]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR43]] csc1 = uc; - // CHECK-NEXT: %[[VAR44:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR:[A-Za-z0-9.]+]], align [[CHALIGN]] - // CHECK-NEXT: %[[VAR45:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR46:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR44:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR:[A-Za-z0-9.]+]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR45:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR46:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR44]], i[[CHSIZE]]* %[[VAR45]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR46]] csc1 = sll; - // CHECK-NEXT: %[[VAR47:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR:[A-Za-z0-9.]+]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR47:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR:[A-Za-z0-9.]+]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR48:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR47]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR49:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR50:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR49:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR50:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR48]], i[[CHSIZE]]* %[[VAR49]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR50]] csc1 = ull; - // CHECK-NEXT: %[[VAR51:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR:[A-Za-z0-9.]+]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR51:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR:[A-Za-z0-9.]+]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR52:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR51]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR53:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR54:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR53:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR54:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR52]], i[[CHSIZE]]* %[[VAR53]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR54]] cuc1 = sc; - // CHECK-NEXT: %[[VAR55:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] - // CHECK-NEXT: %[[VAR56:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR57:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR55:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR56:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR57:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR55]], i[[CHSIZE]]* %[[VAR56]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR57]] cuc1 = uc; - // CHECK-NEXT: %[[VAR58:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] - // CHECK-NEXT: %[[VAR59:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR60:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR58:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR59:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR60:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR58]], i[[CHSIZE]]* %[[VAR59]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR60]] cuc1 = sll; - // CHECK-NEXT: %[[VAR61:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR61:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR62:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR61]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR63:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR64:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR63:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR64:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR62]], i[[CHSIZE]]* %[[VAR63]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR64]] cuc1 = ull; - // CHECK-NEXT: %[[VAR65:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR65:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR66:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR65]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR67:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR68:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR67:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR68:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR66]], i[[CHSIZE]]* %[[VAR67]] // CHECK-NEXT: store i[[CHSIZE]] 0, i[[CHSIZE]]* %[[VAR68]] csll1 = sc; - // CHECK-NEXT: %[[VAR69:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR69:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR70:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR69]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR71:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR72:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR71:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR72:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR70]], i[[LLSIZE]]* %[[VAR71]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR72]] csll1 = uc; - // CHECK-NEXT: %[[VAR73:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR73:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR74:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR73]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR75:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR76:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR75:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR76:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR74]], i[[LLSIZE]]* %[[VAR75]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR76]] csll1 = sll; - // CHECK-NEXT: %[[VAR77:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR78:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR79:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR77:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR78:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR79:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR77]], i[[LLSIZE]]* %[[VAR78]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR79]] csll1 = ull; - // CHECK-NEXT: %[[VAR77:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR78:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR79:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR77:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR78:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR79:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR77]], i[[LLSIZE]]* %[[VAR78]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR79]] cull1 = sc; - // CHECK-NEXT: %[[VAR80:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR80:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR81:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR80]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR82:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR83:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR82:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR83:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR81]], i[[LLSIZE]]* %[[VAR82]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR83]] cull1 = uc; - // CHECK-NEXT: %[[VAR84:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR84:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR85:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR84]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR86:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR87:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR86:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR87:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR85]], i[[LLSIZE]]* %[[VAR86]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR87]] cull1 = sll; - // CHECK-NEXT: %[[VAR88:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR89:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR90:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR88:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR89:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR90:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR88]], i[[LLSIZE]]* %[[VAR89]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR90]] cull1 = ull; - // CHECK-NEXT: %[[VAR91:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR92:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR93:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR91:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR92:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR93:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR91]], i[[LLSIZE]]* %[[VAR92]] // CHECK-NEXT: store i[[LLSIZE]] 0, i[[LLSIZE]]* %[[VAR93]] csc1 = sc + csc; - // CHECK-NEXT: %[[VAR94:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR94:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR95:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR94]] to i[[ARSIZE:[0-9]+]] - // CHECK-NEXT: %[[VAR96:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR97:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR96]] - // CHECK-NEXT: %[[VAR98:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR99:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR98]] + // CHECK-NEXT: %[[VAR96:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR97:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR96]] + // CHECK-NEXT: %[[VAR98:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR99:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR98]] // CHECK-NEXT: %[[VAR100:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR97]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR101:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR99]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR102:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR95]], %[[VAR100]] // CHECK-NEXT: %[[VAR103:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR101]] // CHECK-NEXT: %[[VAR104:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR102]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR105:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR103]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR106:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR107:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR106:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR107:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR104]], i[[CHSIZE]]* %[[VAR106]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR105]], i[[CHSIZE]]* %[[VAR107]] cuc1 = sc + cuc; - // CHECK-NEXT: %[[VAR108:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR108:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR109:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR108]] to i[[ARSIZE]] - // CHECK-NEXT: %[[VAR110:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR111:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR110]] - // CHECK-NEXT: %[[VAR112:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR113:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR112]] + // CHECK-NEXT: %[[VAR110:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR111:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR110]] + // CHECK-NEXT: %[[VAR112:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR113:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR112]] // CHECK-NEXT: %[[VAR114:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR111]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR115:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR113]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR116:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR109]], %[[VAR114]] // CHECK-NEXT: %[[VAR117:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR115]] // CHECK-NEXT: %[[VAR118:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR116]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR119:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR117]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR120:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR121:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR120:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR121:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR118]], i[[CHSIZE]]* %[[VAR120]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR119]], i[[CHSIZE]]* %[[VAR121]] csll1 = sc + csll; - // CHECK-NEXT: %[[VAR122:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR122:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR123:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR122]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR124:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR125:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR124]] - // CHECK-NEXT: %[[VAR126:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR127:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR126]] + // CHECK-NEXT: %[[VAR124:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR125:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR124]] + // CHECK-NEXT: %[[VAR126:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR127:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR126]] // CHECK-NEXT: %[[VAR128:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR123]], %[[VAR125]] // CHECK-NEXT: %[[VAR129:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR127]] - // CHECK-NEXT: %[[VAR130:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR131:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR130:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR131:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR128]], i[[LLSIZE]]* %[[VAR130]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR129]], i[[LLSIZE]]* %[[VAR131]] cull1 = sc + cull; - // CHECK-NEXT: %[[VAR132:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR132:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR133:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR132]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR134:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR135:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR134]] - // CHECK-NEXT: %[[VAR136:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR137:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR136]] + // CHECK-NEXT: %[[VAR134:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR135:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR134]] + // CHECK-NEXT: %[[VAR136:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR137:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR136]] // CHECK-NEXT: %[[VAR138:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR133]], %[[VAR135]] // CHECK-NEXT: %[[VAR139:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR137]] - // CHECK-NEXT: %[[VAR140:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR141:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR140:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR141:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR138]], i[[LLSIZE]]* %[[VAR140]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR139]], i[[LLSIZE]]* %[[VAR141]] csc1 = uc + csc; - // CHECK-NEXT: %[[VAR142:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR142:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR143:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR142]] to i[[ARSIZE]] - // CHECK-NEXT: %[[VAR144:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR145:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR144]] - // CHECK-NEXT: %[[VAR146:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR147:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR146]] + // CHECK-NEXT: %[[VAR144:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR145:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR144]] + // CHECK-NEXT: %[[VAR146:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR147:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR146]] // CHECK-NEXT: %[[VAR148:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR145]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR149:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR147]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR150:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR143]], %[[VAR148]] // CHECK-NEXT: %[[VAR151:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR149]] // CHECK-NEXT: %[[VAR152:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR150]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR153:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR151]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR154:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR155:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR154:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR155:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR152]], i[[CHSIZE]]* %[[VAR154]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR153]], i[[CHSIZE]]* %[[VAR155]] cuc1 = uc + cuc; - // CHECK-NEXT: %[[VAR156:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR156:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR157:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR156]] to i[[ARSIZE]] - // CHECK-NEXT: %[[VAR158:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR159:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR158]] - // CHECK-NEXT: %[[VAR160:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR161:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR160]] + // CHECK-NEXT: %[[VAR158:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR159:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR158]] + // CHECK-NEXT: %[[VAR160:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR161:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR160]] // CHECK-NEXT: %[[VAR162:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR159]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR163:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR161]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR164:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR157]], %[[VAR162]] // CHECK-NEXT: %[[VAR165:[A-Za-z0-9.]+]] = add i[[ARSIZE]] 0, %[[VAR163]] // CHECK-NEXT: %[[VAR166:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR164]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR167:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR165]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR168:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR169:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR168:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR169:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR166]], i[[CHSIZE]]* %[[VAR168]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR167]], i[[CHSIZE]]* %[[VAR169]] csll1 = uc + csll; - // CHECK-NEXT: %[[VAR170:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR170:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR171:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR170]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR172:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR173:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR172]] - // CHECK-NEXT: %[[VAR174:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR175:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR174]] + // CHECK-NEXT: %[[VAR172:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR173:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR172]] + // CHECK-NEXT: %[[VAR174:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR175:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR174]] // CHECK-NEXT: %[[VAR176:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR171]], %[[VAR173]] // CHECK-NEXT: %[[VAR177:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR175]] - // CHECK-NEXT: %[[VAR178:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR179:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR178:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR179:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR176]], i[[LLSIZE]]* %[[VAR178]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR177]], i[[LLSIZE]]* %[[VAR179]] cull1 = uc + cull; - // CHECK-NEXT: %[[VAR180:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR180:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR181:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR180]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR182:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR183:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR182]] - // CHECK-NEXT: %[[VAR184:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR185:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR184]] + // CHECK-NEXT: %[[VAR182:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR183:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR182]] + // CHECK-NEXT: %[[VAR184:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR185:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR184]] // CHECK-NEXT: %[[VAR186:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR181]], %[[VAR183]] // CHECK-NEXT: %[[VAR187:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR185]] - // CHECK-NEXT: %[[VAR188:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR189:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR188:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR189:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR186]], i[[LLSIZE]]* %[[VAR188]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR187]], i[[LLSIZE]]* %[[VAR189]] csll1 = sll + csc; - // CHECK-NEXT: %[[VAR190:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR191:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR192:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR191]] - // CHECK-NEXT: %[[VAR193:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR194:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR193]] + // CHECK-NEXT: %[[VAR190:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR191:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR192:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR191]] + // CHECK-NEXT: %[[VAR193:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR194:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR193]] // CHECK-NEXT: %[[VAR195:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR192]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR196:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR194]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR197:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR190]], %[[VAR195]] // CHECK-NEXT: %[[VAR198:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR196]] - // CHECK-NEXT: %[[VAR199:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR200:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR199:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR200:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR197]], i[[LLSIZE]]* %[[VAR199]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR198]], i[[LLSIZE]]* %[[VAR200]] csll1 = sll + cuc; - // CHECK-NEXT: %[[VAR201:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR202:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR203:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR202]] - // CHECK-NEXT: %[[VAR204:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR205:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR204]] + // CHECK-NEXT: %[[VAR201:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR202:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR203:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR202]] + // CHECK-NEXT: %[[VAR204:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR205:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR204]] // CHECK-NEXT: %[[VAR206:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR203]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR207:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR205]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR208:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR201]], %[[VAR206]] // CHECK-NEXT: %[[VAR209:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR207]] - // CHECK-NEXT: %[[VAR210:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR211:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR210:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR211:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR208]], i[[LLSIZE]]* %[[VAR210]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR209]], i[[LLSIZE]]* %[[VAR211]] csll1 = sll + csll; - // CHECK-NEXT: %[[VAR212:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR213:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR214:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR213]] - // CHECK-NEXT: %[[VAR215:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR216:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR215]] + // CHECK-NEXT: %[[VAR212:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR213:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR214:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR213]] + // CHECK-NEXT: %[[VAR215:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR216:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR215]] // CHECK-NEXT: %[[VAR217:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR212]], %[[VAR214]] // CHECK-NEXT: %[[VAR218:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR216]] - // CHECK-NEXT: %[[VAR219:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR220:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR219:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR220:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR217]], i[[LLSIZE]]* %[[VAR219]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR218]], i[[LLSIZE]]* %[[VAR220]] csll1 = sll + cull; - // CHECK-NEXT: %[[VAR221:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR222:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR223:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR222]] - // CHECK-NEXT: %[[VAR224:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR225:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR224]] + // CHECK-NEXT: %[[VAR221:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR222:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR223:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR222]] + // CHECK-NEXT: %[[VAR224:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR225:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR224]] // CHECK-NEXT: %[[VAR226:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR221]], %[[VAR223]] // CHECK-NEXT: %[[VAR227:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR225]] - // CHECK-NEXT: %[[VAR228:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR229:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR228:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR229:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR226]], i[[LLSIZE]]* %[[VAR228]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR227]], i[[LLSIZE]]* %[[VAR229]] csll1 = ull + csc; - // CHECK-NEXT: %[[VAR230:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR231:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR232:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR231]] - // CHECK-NEXT: %[[VAR233:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR234:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR233]] + // CHECK-NEXT: %[[VAR230:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR231:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR232:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR231]] + // CHECK-NEXT: %[[VAR233:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR234:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR233]] // CHECK-NEXT: %[[VAR235:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR232]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR236:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR234]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR237:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR230]], %[[VAR235]] // CHECK-NEXT: %[[VAR238:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR236]] - // CHECK-NEXT: %[[VAR239:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR240:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR239:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR240:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR237]], i[[LLSIZE]]* %[[VAR239]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR238]], i[[LLSIZE]]* %[[VAR240]] cull1 = ull + cuc; - // CHECK-NEXT: %[[VAR241:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR242:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR243:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR242]] - // CHECK-NEXT: %[[VAR244:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR245:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR244]] + // CHECK-NEXT: %[[VAR241:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR242:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR243:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR242]] + // CHECK-NEXT: %[[VAR244:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR245:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR244]] // CHECK-NEXT: %[[VAR246:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR243]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR247:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR245]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR248:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR241]], %[[VAR246]] // CHECK-NEXT: %[[VAR249:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR247]] - // CHECK-NEXT: %[[VAR250:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR251:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR250:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR251:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR248]], i[[LLSIZE]]* %[[VAR250]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR249]], i[[LLSIZE]]* %[[VAR251]] csll1 = ull + csll; - // CHECK-NEXT: %[[VAR252:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR253:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR254:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR253]] - // CHECK-NEXT: %[[VAR255:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR256:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR255]] + // CHECK-NEXT: %[[VAR252:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR253:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR254:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR253]] + // CHECK-NEXT: %[[VAR255:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR256:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR255]] // CHECK-NEXT: %[[VAR257:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR252]], %[[VAR254]] // CHECK-NEXT: %[[VAR258:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR256]] - // CHECK-NEXT: %[[VAR259:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR260:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR259:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR260:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR257]], i[[LLSIZE]]* %[[VAR259]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR258]], i[[LLSIZE]]* %[[VAR260]] cull1 = ull + cull; - // CHECK-NEXT: %[[VAR261:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] - // CHECK-NEXT: %[[VAR262:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR263:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR262]] - // CHECK-NEXT: %[[VAR264:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR265:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR264]] + // CHECK-NEXT: %[[VAR261:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR262:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR263:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR262]] + // CHECK-NEXT: %[[VAR264:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR265:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR264]] // CHECK-NEXT: %[[VAR266:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR261]], %[[VAR263]] // CHECK-NEXT: %[[VAR267:[A-Za-z0-9.]+]] = add i[[LLSIZE]] 0, %[[VAR265]] - // CHECK-NEXT: %[[VAR268:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR269:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR268:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR269:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR266]], i[[LLSIZE]]* %[[VAR268]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR267]], i[[LLSIZE]]* %[[VAR269]] csc1 = csc + sc; - // CHECK-NEXT: %[[VAR270:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR271:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR270]] - // CHECK-NEXT: %[[VAR272:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR273:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR272]] + // CHECK-NEXT: %[[VAR270:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR271:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR270]] + // CHECK-NEXT: %[[VAR272:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR273:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR272]] // CHECK-NEXT: %[[VAR274:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR271]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR275:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR273]] to i[[ARSIZE]] - // CHECK-NEXT: %[[VAR276:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR276:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR277:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR276]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR278:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR274]], %[[VAR277]] // CHECK-NEXT: %[[VAR279:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR275]], 0 // CHECK-NEXT: %[[VAR280:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR278]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR281:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR279]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR282:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR283:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR282:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR283:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR280]], i[[CHSIZE]]* %[[VAR282]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR281]], i[[CHSIZE]]* %[[VAR283]] csc1 = csc + uc; - // CHECK-NEXT: %[[VAR284:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR285:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR284]] - // CHECK-NEXT: %[[VAR286:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR287:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR286]] + // CHECK-NEXT: %[[VAR284:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR285:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR284]] + // CHECK-NEXT: %[[VAR286:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR287:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR286]] // CHECK-NEXT: %[[VAR288:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR285]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR289:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR287]] to i[[ARSIZE]] - // CHECK-NEXT: %[[VAR290:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR290:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR291:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR290]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR292:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR288]], %[[VAR291]] // CHECK-NEXT: %[[VAR293:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR289]], 0 // CHECK-NEXT: %[[VAR294:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR292]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR295:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR293]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR296:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR297:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR296:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR297:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR294]], i[[CHSIZE]]* %[[VAR296]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR295]], i[[CHSIZE]]* %[[VAR297]] csll1 = csc + sll; - // CHECK-NEXT: %[[VAR298:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR299:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR298]] - // CHECK-NEXT: %[[VAR300:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR301:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR300]] + // CHECK-NEXT: %[[VAR298:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR299:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR298]] + // CHECK-NEXT: %[[VAR300:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR301:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR300]] // CHECK-NEXT: %[[VAR302:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR299]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR303:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR301]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR304:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR304:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR305:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR302]], %[[VAR304]] // CHECK-NEXT: %[[VAR306:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR303]], 0 - // CHECK-NEXT: %[[VAR307:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR308:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR307:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR308:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR305]], i[[LLSIZE]]* %[[VAR307]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR306]], i[[LLSIZE]]* %[[VAR308]] csll1 = csc + ull; - // CHECK-NEXT: %[[VAR309:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR310:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR309]] - // CHECK-NEXT: %[[VAR311:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR312:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR311]] + // CHECK-NEXT: %[[VAR309:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR310:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR309]] + // CHECK-NEXT: %[[VAR311:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR312:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR311]] // CHECK-NEXT: %[[VAR313:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR310]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR314:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR312]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR315:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR315:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR316:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR313]], %[[VAR315]] // CHECK-NEXT: %[[VAR317:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR314]], 0 - // CHECK-NEXT: %[[VAR318:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR319:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR318:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR319:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR316]], i[[LLSIZE]]* %[[VAR318]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR317]], i[[LLSIZE]]* %[[VAR319]] csc1 = cuc + sc; - // CHECK-NEXT: %[[VAR320:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR321:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR320]] - // CHECK-NEXT: %[[VAR322:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR323:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR322]] + // CHECK-NEXT: %[[VAR320:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR321:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR320]] + // CHECK-NEXT: %[[VAR322:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR323:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR322]] // CHECK-NEXT: %[[VAR324:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR321]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR325:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR323]] to i[[ARSIZE]] - // CHECK-NEXT: %[[VAR326:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR326:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR327:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR326]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR328:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR324]], %[[VAR327]] // CHECK-NEXT: %[[VAR329:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR325]], 0 // CHECK-NEXT: %[[VAR330:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR328]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR331:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR329]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR332:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR333:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR332:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR333:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CSC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR330]], i[[CHSIZE]]* %[[VAR332]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR331]], i[[CHSIZE]]* %[[VAR333]] cuc1 = cuc + uc; - // CHECK-NEXT: %[[VAR334:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR335:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR334]] - // CHECK-NEXT: %[[VAR336:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR337:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR336]] + // CHECK-NEXT: %[[VAR334:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR335:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR334]] + // CHECK-NEXT: %[[VAR336:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR337:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR336]] // CHECK-NEXT: %[[VAR338:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR335]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR339:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR337]] to i[[ARSIZE]] - // CHECK-NEXT: %[[VAR340:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR340:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR341:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR340]] to i[[ARSIZE]] // CHECK-NEXT: %[[VAR342:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR338]], %[[VAR341]] // CHECK-NEXT: %[[VAR343:[A-Za-z0-9.]+]] = add i[[ARSIZE]] %[[VAR339]], 0 // CHECK-NEXT: %[[VAR344:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR342]] to i[[CHSIZE]] // CHECK-NEXT: %[[VAR345:[A-Za-z0-9.]+]] = trunc i[[ARSIZE]] %[[VAR343]] to i[[CHSIZE]] - // CHECK-NEXT: %[[VAR346:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR347:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR346:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR347:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR344]], i[[CHSIZE]]* %[[VAR346]] // CHECK-NEXT: store i[[CHSIZE]] %[[VAR345]], i[[CHSIZE]]* %[[VAR347]] csll1 = cuc + sll; - // CHECK-NEXT: %[[VAR348:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR349:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR348]] - // CHECK-NEXT: %[[VAR350:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR351:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR350]] + // CHECK-NEXT: %[[VAR348:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR349:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR348]] + // CHECK-NEXT: %[[VAR350:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR351:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR350]] // CHECK-NEXT: %[[VAR352:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR349]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR353:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR351]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR354:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR354:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR355:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR352]], %[[VAR354]] // CHECK-NEXT: %[[VAR356:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR353]], 0 - // CHECK-NEXT: %[[VAR357:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR358:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR357:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR358:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR355]], i[[LLSIZE]]* %[[VAR357]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR356]], i[[LLSIZE]]* %[[VAR358]] cull1 = cuc + ull; - // CHECK-NEXT: %[[VAR357:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR358:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR357]] - // CHECK-NEXT: %[[VAR359:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR360:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[VAR359]] + // CHECK-NEXT: %[[VAR357:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR358:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR357]] + // CHECK-NEXT: %[[VAR359:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR360:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR359]] // CHECK-NEXT: %[[VAR361:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR358]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR362:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR360]] to i[[LLSIZE]] - // CHECK-NEXT: %[[VAR363:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR363:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR364:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR361]], %[[VAR363]] // CHECK-NEXT: %[[VAR365:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR362]], 0 - // CHECK-NEXT: %[[VAR366:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR367:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR366:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR367:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR364]], i[[LLSIZE]]* %[[VAR366]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR365]], i[[LLSIZE]]* %[[VAR367]] csll1 = csll + sc; - // CHECK-NEXT: %[[VAR368:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR369:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR368]] - // CHECK-NEXT: %[[VAR370:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR371:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR370]] - // CHECK-NEXT: %[[VAR372:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR368:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR369:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR368]] + // CHECK-NEXT: %[[VAR370:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR371:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR370]] + // CHECK-NEXT: %[[VAR372:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR373:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR372]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR374:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR369]], %[[VAR373]] // CHECK-NEXT: %[[VAR375:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR371]], 0 - // CHECK-NEXT: %[[VAR376:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR377:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR376:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR377:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR374]], i[[LLSIZE]]* %[[VAR376]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR375]], i[[LLSIZE]]* %[[VAR377]] csll1 = csll + uc; - // CHECK-NEXT: %[[VAR378:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR379:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR378]] - // CHECK-NEXT: %[[VAR380:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR381:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR380]] - // CHECK-NEXT: %[[VAR382:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR378:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR379:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR378]] + // CHECK-NEXT: %[[VAR380:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR381:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR380]] + // CHECK-NEXT: %[[VAR382:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR383:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR382]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR384:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR379]], %[[VAR383]] // CHECK-NEXT: %[[VAR385:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR381]], 0 - // CHECK-NEXT: %[[VAR386:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR387:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR386:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR387:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR384]], i[[LLSIZE]]* %[[VAR386]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR385]], i[[LLSIZE]]* %[[VAR387]] csll1 = csll + sll; - // CHECK-NEXT: %[[VAR388:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR389:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR388]] - // CHECK-NEXT: %[[VAR390:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR391:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR390]] - // CHECK-NEXT: %[[VAR392:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR388:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR389:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR388]] + // CHECK-NEXT: %[[VAR390:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR391:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR390]] + // CHECK-NEXT: %[[VAR392:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR393:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR389]], %[[VAR392]] // CHECK-NEXT: %[[VAR394:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR391]], 0 - // CHECK-NEXT: %[[VAR395:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR396:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR395:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR396:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR393]], i[[LLSIZE]]* %[[VAR395]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR394]], i[[LLSIZE]]* %[[VAR396]] csll1 = csll + ull; - // CHECK-NEXT: %[[VAR397:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR398:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR397]] - // CHECK-NEXT: %[[VAR399:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR400:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR399]] - // CHECK-NEXT: %[[VAR401:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR397:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR398:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR397]] + // CHECK-NEXT: %[[VAR399:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR400:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR399]] + // CHECK-NEXT: %[[VAR401:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR402:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR398]], %[[VAR401]] // CHECK-NEXT: %[[VAR403:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR400]], 0 - // CHECK-NEXT: %[[VAR404:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR405:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR404:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR405:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR402]], i[[LLSIZE]]* %[[VAR404]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR403]], i[[LLSIZE]]* %[[VAR405]] csll1 = cull + sc; - // CHECK-NEXT: %[[VAR406:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR407:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR406]] - // CHECK-NEXT: %[[VAR408:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR409:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR408]] - // CHECK-NEXT: %[[VAR410:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR406:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR407:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR406]] + // CHECK-NEXT: %[[VAR408:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR409:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR408]] + // CHECK-NEXT: %[[VAR410:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[SCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR411:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR410]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR412:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR407]], %[[VAR411]] // CHECK-NEXT: %[[VAR413:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR409]], 0 - // CHECK-NEXT: %[[VAR414:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR415:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR414:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR415:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR412]], i[[LLSIZE]]* %[[VAR414]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR413]], i[[LLSIZE]]* %[[VAR415]] cull1 = cull + uc; - // CHECK-NEXT: %[[VAR416:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR417:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR416]] - // CHECK-NEXT: %[[VAR418:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR419:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR418]] - // CHECK-NEXT: %[[VAR420:[A-Za-z0-9.]+]] = load i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] + // CHECK-NEXT: %[[VAR416:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR417:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR416]] + // CHECK-NEXT: %[[VAR418:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR419:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR418]] + // CHECK-NEXT: %[[VAR420:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[UCADDR]], align [[CHALIGN]] // CHECK-NEXT: %[[VAR421:[A-Za-z0-9.]+]] = zext i[[CHSIZE]] %[[VAR420]] to i[[LLSIZE]] // CHECK-NEXT: %[[VAR422:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR417]], %[[VAR421]] // CHECK-NEXT: %[[VAR423:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR419]], 0 - // CHECK-NEXT: %[[VAR424:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR425:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR424:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR425:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR422]], i[[LLSIZE]]* %[[VAR424]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR423]], i[[LLSIZE]]* %[[VAR425]] csll1 = cull + sll; - // CHECK-NEXT: %[[VAR426:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR427:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR426]] - // CHECK-NEXT: %[[VAR428:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR429:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR428]] - // CHECK-NEXT: %[[VAR430:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR426:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR427:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR426]] + // CHECK-NEXT: %[[VAR428:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR429:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR428]] + // CHECK-NEXT: %[[VAR430:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[SLLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR431:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR427]], %[[VAR430]] // CHECK-NEXT: %[[VAR432:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR429]], 0 - // CHECK-NEXT: %[[VAR433:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR434:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR433:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR434:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR431]], i[[LLSIZE]]* %[[VAR433]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR432]], i[[LLSIZE]]* %[[VAR434]] cull1 = cull + ull; - // CHECK-NEXT: %[[VAR435:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR436:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR435]] - // CHECK-NEXT: %[[VAR437:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // CHECK-NEXT: %[[VAR438:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[VAR437]] - // CHECK-NEXT: %[[VAR439:[A-Za-z0-9.]+]] = load i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] + // CHECK-NEXT: %[[VAR435:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR436:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR435]] + // CHECK-NEXT: %[[VAR437:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR438:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR437]] + // CHECK-NEXT: %[[VAR439:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[ULLADDR]], align [[LLALIGN]] // CHECK-NEXT: %[[VAR440:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR436]], %[[VAR439]] // CHECK-NEXT: %[[VAR441:[A-Za-z0-9.]+]] = add i[[LLSIZE]] %[[VAR438]], 0 - // CHECK-NEXT: %[[VAR442:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 - // CHECK-NEXT: %[[VAR443:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // CHECK-NEXT: %[[VAR442:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 + // CHECK-NEXT: %[[VAR443:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CULL1]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK-NEXT: store i[[LLSIZE]] %[[VAR440]], i[[LLSIZE]]* %[[VAR442]] // CHECK-NEXT: store i[[LLSIZE]] %[[VAR441]], i[[LLSIZE]]* %[[VAR443]] } diff --git a/test/CodeGen/compound-literal.c b/test/CodeGen/compound-literal.c index 458a78e1984b..85138bfaf5e0 100644 --- a/test/CodeGen/compound-literal.c +++ b/test/CodeGen/compound-literal.c @@ -18,13 +18,13 @@ void f() { // CHECK: [[S:%[a-zA-Z0-9.]+]] = alloca [[STRUCT:%[a-zA-Z0-9.]+]], struct S s; // CHECK-NEXT: [[COMPOUNDLIT:%[a-zA-Z0-9.]+]] = alloca [[STRUCT]] - // CHECK-NEXT: [[CX:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]]* [[COMPOUNDLIT]], i32 0, i32 0 - // CHECK-NEXT: [[SY:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]]* [[S]], i32 0, i32 1 - // CHECK-NEXT: [[TMP:%[a-zA-Z0-9.]+]] = load i32* [[SY]] + // CHECK-NEXT: [[CX:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]], [[STRUCT]]* [[COMPOUNDLIT]], i32 0, i32 0 + // CHECK-NEXT: [[SY:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]], [[STRUCT]]* [[S]], i32 0, i32 1 + // CHECK-NEXT: [[TMP:%[a-zA-Z0-9.]+]] = load i32, i32* [[SY]] // CHECK-NEXT: store i32 [[TMP]], i32* [[CX]] - // CHECK-NEXT: [[CY:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]]* [[COMPOUNDLIT]], i32 0, i32 1 - // CHECK-NEXT: [[SX:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]]* [[S]], i32 0, i32 0 - // CHECK-NEXT: [[TMP:%[a-zA-Z0-9.]+]] = load i32* [[SX]] + // CHECK-NEXT: [[CY:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]], [[STRUCT]]* [[COMPOUNDLIT]], i32 0, i32 1 + // CHECK-NEXT: [[SX:%[a-zA-Z0-9.]+]] = getelementptr inbounds [[STRUCT]], [[STRUCT]]* [[S]], i32 0, i32 0 + // CHECK-NEXT: [[TMP:%[a-zA-Z0-9.]+]] = load i32, i32* [[SX]] // CHECK-NEXT: store i32 [[TMP]], i32* [[CY]] // CHECK-NEXT: [[SI8:%[a-zA-Z0-9.]+]] = bitcast [[STRUCT]]* [[S]] to i8* // CHECK-NEXT: [[COMPOUNDLITI8:%[a-zA-Z0-9.]+]] = bitcast [[STRUCT]]* [[COMPOUNDLIT]] to i8* @@ -46,16 +46,16 @@ struct G g(int x, int y, int z) { // CHECK-NEXT: store i32 // Evaluate the compound literal directly in the result value slot. - // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[G]]* [[RESULT]], i32 0, i32 0 - // CHECK-NEXT: [[T1:%.*]] = load i32* [[X]], align 4 + // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[G]], [[G]]* [[RESULT]], i32 0, i32 0 + // CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[X]], align 4 // CHECK-NEXT: [[T2:%.*]] = trunc i32 [[T1]] to i16 // CHECK-NEXT: store i16 [[T2]], i16* [[T0]], align 2 - // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[G]]* [[RESULT]], i32 0, i32 1 - // CHECK-NEXT: [[T1:%.*]] = load i32* [[Y]], align 4 + // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[G]], [[G]]* [[RESULT]], i32 0, i32 1 + // CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[Y]], align 4 // CHECK-NEXT: [[T2:%.*]] = trunc i32 [[T1]] to i16 // CHECK-NEXT: store i16 [[T2]], i16* [[T0]], align 2 - // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[G]]* [[RESULT]], i32 0, i32 2 - // CHECK-NEXT: [[T1:%.*]] = load i32* [[Z]], align 4 + // CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[G]], [[G]]* [[RESULT]], i32 0, i32 2 + // CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[Z]], align 4 // CHECK-NEXT: [[T2:%.*]] = trunc i32 [[T1]] to i16 // CHECK-NEXT: store i16 [[T2]], i16* [[T0]], align 2 return (struct G) { x, y, z }; @@ -63,6 +63,6 @@ struct G g(int x, int y, int z) { // CHECK-NEXT: [[T0:%.*]] = bitcast i48* [[COERCE_TEMP]] to i8* // CHECK-NEXT: [[T1:%.*]] = bitcast [[G]]* [[RESULT]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[T0]], i8* [[T1]], i64 6 - // CHECK-NEXT: [[T0:%.*]] = load i48* [[COERCE_TEMP]] + // CHECK-NEXT: [[T0:%.*]] = load i48, i48* [[COERCE_TEMP]] // CHECK-NEXT: ret i48 [[T0]] } diff --git a/test/CodeGen/const-arithmetic.c b/test/CodeGen/const-arithmetic.c index a28f73f004e4..564ed9b356e4 100644 --- a/test/CodeGen/const-arithmetic.c +++ b/test/CodeGen/const-arithmetic.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s -// CHECK: @g1 = global [2 x i8*] [i8* getelementptr (i8* getelementptr inbounds ([0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -2), i8* getelementptr (i8* getelementptr inbounds ([0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -46)], align 16 -// CHECK: @g2 = global [2 x i8*] [i8* getelementptr (i8* getelementptr inbounds ([0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -2), i8* getelementptr (i8* getelementptr inbounds ([0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -46)], align 16 +// CHECK: @g1 = global [2 x i8*] [i8* getelementptr (i8, i8* getelementptr inbounds ([0 x %struct.anon], [0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -2), i8* getelementptr (i8, i8* getelementptr inbounds ([0 x %struct.anon], [0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -46)], align 16 +// CHECK: @g2 = global [2 x i8*] [i8* getelementptr (i8, i8* getelementptr inbounds ([0 x %struct.anon], [0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -2), i8* getelementptr (i8, i8* getelementptr inbounds ([0 x %struct.anon], [0 x %struct.anon]* @g0, i32 0, i32 0, i32 0), i64 -46)], align 16 extern struct { unsigned char a, b; } g0[]; void *g1[] = {g0 + -1, g0 + -23 }; diff --git a/test/CodeGen/const-init.c b/test/CodeGen/const-init.c index b86274fc8242..9434f1d1b24b 100644 --- a/test/CodeGen/const-init.c +++ b/test/CodeGen/const-init.c @@ -102,7 +102,7 @@ void g18(void) { static int *p[] = { &g19 }; } -// CHECK: @g20.l0 = internal global %struct.g20_s1 { %struct.g20_s0* null, %struct.g20_s0** getelementptr inbounds (%struct.g20_s1* @g20.l0, i32 0, i32 0) } +// CHECK: @g20.l0 = internal global %struct.g20_s1 { %struct.g20_s0* null, %struct.g20_s0** getelementptr inbounds (%struct.g20_s1, %struct.g20_s1* @g20.l0, i32 0, i32 0) } struct g20_s0; struct g20_s1 { struct g20_s0 *f0, **f1; @@ -121,7 +121,7 @@ struct g22 {int x;} __attribute((packed)); struct g23 {char a; short b; char c; struct g22 d;}; struct g23 g24 = {1,2,3,4}; -// CHECK: @g25.g26 = internal global i8* getelementptr inbounds ([4 x i8]* @__func__.g25, i32 0, i32 0) +// CHECK: @g25.g26 = internal global i8* getelementptr inbounds ([4 x i8], [4 x i8]* @__func__.g25, i32 0, i32 0) // CHECK: @__func__.g25 = private unnamed_addr constant [4 x i8] c"g25\00" int g25() { static const char *g26 = __func__; diff --git a/test/CodeGen/darwin-string-literals.c b/test/CodeGen/darwin-string-literals.c index 41e59cb14f5d..1cebbf6fbdd0 100644 --- a/test/CodeGen/darwin-string-literals.c +++ b/test/CodeGen/darwin-string-literals.c @@ -1,17 +1,17 @@ // RUN: %clang_cc1 -triple i386-apple-darwin9 -emit-llvm %s -o - | FileCheck -check-prefix CHECK-LSB %s // CHECK-LSB: @.str = private unnamed_addr constant [8 x i8] c"string0\00" -// CHECK-LSB: @.str1 = private unnamed_addr constant [8 x i8] c"string1\00" -// CHECK-LSB: @.str2 = private unnamed_addr constant [18 x i16] [i16 104, i16 101, i16 108, i16 108, i16 111, i16 32, i16 8594, i16 32, i16 9731, i16 32, i16 8592, i16 32, i16 119, i16 111, i16 114, i16 108, i16 100, i16 0], section "__TEXT,__ustring", align 2 -// CHECK-LSB: @.str4 = private unnamed_addr constant [6 x i16] [i16 116, i16 101, i16 115, i16 116, i16 8482, i16 0], section "__TEXT,__ustring", align 2 +// CHECK-LSB: @.str.1 = private unnamed_addr constant [8 x i8] c"string1\00" +// CHECK-LSB: @.str.2 = private unnamed_addr constant [18 x i16] [i16 104, i16 101, i16 108, i16 108, i16 111, i16 32, i16 8594, i16 32, i16 9731, i16 32, i16 8592, i16 32, i16 119, i16 111, i16 114, i16 108, i16 100, i16 0], section "__TEXT,__ustring", align 2 +// CHECK-LSB: @.str.4 = private unnamed_addr constant [6 x i16] [i16 116, i16 101, i16 115, i16 116, i16 8482, i16 0], section "__TEXT,__ustring", align 2 // RUN: %clang_cc1 -triple powerpc-apple-darwin9 -emit-llvm %s -o - | FileCheck -check-prefix CHECK-MSB %s // CHECK-MSB: @.str = private unnamed_addr constant [8 x i8] c"string0\00" -// CHECK-MSB: @.str1 = private unnamed_addr constant [8 x i8] c"string1\00" -// CHECK-MSB: @.str2 = private unnamed_addr constant [18 x i16] [i16 104, i16 101, i16 108, i16 108, i16 111, i16 32, i16 8594, i16 32, i16 9731, i16 32, i16 8592, i16 32, i16 119, i16 111, i16 114, i16 108, i16 100, i16 0], section "__TEXT,__ustring", align 2 -// CHECK-MSB: @.str4 = private unnamed_addr constant [6 x i16] [i16 116, i16 101, i16 115, i16 116, i16 8482, i16 0], section "__TEXT,__ustring", align 2 +// CHECK-MSB: @.str.1 = private unnamed_addr constant [8 x i8] c"string1\00" +// CHECK-MSB: @.str.2 = private unnamed_addr constant [18 x i16] [i16 104, i16 101, i16 108, i16 108, i16 111, i16 32, i16 8594, i16 32, i16 9731, i16 32, i16 8592, i16 32, i16 119, i16 111, i16 114, i16 108, i16 100, i16 0], section "__TEXT,__ustring", align 2 +// CHECK-MSB: @.str.4 = private unnamed_addr constant [6 x i16] [i16 116, i16 101, i16 115, i16 116, i16 8482, i16 0], section "__TEXT,__ustring", align 2 const char *g0 = "string0"; const void *g1 = __builtin___CFStringMakeConstantString("string1"); diff --git a/test/CodeGen/debug-info-257-args.c b/test/CodeGen/debug-info-257-args.c new file mode 100644 index 000000000000..c6ffa6e9bfb9 --- /dev/null +++ b/test/CodeGen/debug-info-257-args.c @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -x c++ -g -emit-llvm -triple x86_64-linux-gnu -o - %s | FileCheck %s +// PR23332 + +// CHECK: DILocalVariable(tag: DW_TAG_arg_variable, arg: 255 +// CHECK: DILocalVariable(tag: DW_TAG_arg_variable, arg: 256 +// CHECK: DILocalVariable(tag: DW_TAG_arg_variable, arg: 257 +void fn1(int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int, int, int, int, int, int, int, int, int, int, + int, int, int, int, int) {} diff --git a/test/CodeGen/debug-info-args.c b/test/CodeGen/debug-info-args.c index 33cf5bcbd06c..47c904b99951 100644 --- a/test/CodeGen/debug-info-args.c +++ b/test/CodeGen/debug-info-args.c @@ -2,7 +2,7 @@ int somefunc(char *x, int y, double z) { - // CHECK: ![[NUM:[^,]*]], null, null, null} ; [ DW_TAG_subroutine_type + // CHECK: !DISubroutineType(types: ![[NUM:[0-9]+]]) // CHECK: ![[NUM]] = {{!{![^,]*, ![^,]*, ![^,]*, ![^,]*}}} return y; diff --git a/test/CodeGen/debug-info-block-decl.c b/test/CodeGen/debug-info-block-decl.c index f3f5e6bd0a91..5476d8874bf4 100644 --- a/test/CodeGen/debug-info-block-decl.c +++ b/test/CodeGen/debug-info-block-decl.c @@ -9,8 +9,8 @@ int main() { -// CHECK: [[ASSIGNMENT]] = !MDLocation(line: [[@LINE+2]], -// CHECK: [[BLOCK_ENTRY]] = !MDLocation(line: [[@LINE+1]], +// CHECK: [[ASSIGNMENT]] = !DILocation(line: [[@LINE+2]], +// CHECK: [[BLOCK_ENTRY]] = !DILocation(line: [[@LINE+1]], int (^blockptr)(void) = ^(void) { return 0; }; diff --git a/test/CodeGen/debug-info-block-out-return.c b/test/CodeGen/debug-info-block-out-return.c index 47b90ce6882a..e0e5bd91249a 100644 --- a/test/CodeGen/debug-info-block-out-return.c +++ b/test/CodeGen/debug-info-block-out-return.c @@ -11,8 +11,8 @@ // out of order or not at all (the latter would occur if they were both assigned // the same argument number by mistake). -// CHECK: !"0x101\00.block_descriptor\0016777218\00{{[0-9]+}}", {{.*}} ; [ DW_TAG_arg_variable ] [.block_descriptor] -// CHECK: !"0x101\00param\0033554434\00{{[0-9]+}}", {{.*}} ; [ DW_TAG_arg_variable ] [param] +// CHECK: !DILocalVariable(tag: DW_TAG_arg_variable, name: ".block_descriptor", arg: 1,{{.*}}line: 2, +// CHECK: !DILocalVariable(tag: DW_TAG_arg_variable, name: "param", arg: 2,{{.*}}line: 2, // Line directive so we don't have to worry about how many lines preceed the // test code (as the line number is mangled in with the argument number as shown diff --git a/test/CodeGen/debug-info-block.c b/test/CodeGen/debug-info-block.c index 35ee0dd6e76d..c4930bfc3c86 100644 --- a/test/CodeGen/debug-info-block.c +++ b/test/CodeGen/debug-info-block.c @@ -2,8 +2,8 @@ // Verify that the desired debugging type is generated for a structure // member that is a pointer to a block. -// CHECK: __block_literal_generic{{.*}}DW_TAG_structure_type -// CHECK: __block_descriptor{{.*}}DW_TAG_structure_type +// CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "__block_literal_generic" +// CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "__block_descriptor" struct inStruct { void (^genericBlockPtr)(); } is; diff --git a/test/CodeGen/debug-info-enum.c b/test/CodeGen/debug-info-enum.c index 1f6b384d8527..4474e4000e95 100644 --- a/test/CodeGen/debug-info-enum.c +++ b/test/CodeGen/debug-info-enum.c @@ -1,8 +1,9 @@ // RUN: %clang_cc1 -emit-llvm -g %s -o - | FileCheck %s -// CHECK: [[TEST3_ENUMS:![0-9]*]], null, null, null} ; [ DW_TAG_enumeration_type ] [e] +// CHECK: !DICompositeType(tag: DW_TAG_enumeration_type, name: "e" +// CHECK-SAME: elements: [[TEST3_ENUMS:![0-9]*]] // CHECK: [[TEST3_ENUMS]] = !{[[TEST3_E:![0-9]*]]} -// CHECK: [[TEST3_E]] = !{!"0x28\00E\00-1"} ; [ DW_TAG_enumerator ] [E :: -1] +// CHECK: [[TEST3_E]] = !DIEnumerator(name: "E", value: -1) enum e; void func(enum e *p) { diff --git a/test/CodeGen/debug-info-file-change.c b/test/CodeGen/debug-info-file-change.c new file mode 100644 index 000000000000..abcffaf9bb40 --- /dev/null +++ b/test/CodeGen/debug-info-file-change.c @@ -0,0 +1,22 @@ +// RUN: %clang -emit-llvm -S -g %s -o - | FileCheck %s + +// Radar 8396182 +// There are no lexical blocks, but we need two DILexicalBlockFiles to +// correctly represent file info. + +int foo() { + int i = 1; +# 4 "m.c" +# 1 "m.h" 1 + int j = 2; +# 2 "m.h" +# 5 "m.c" 2 + return i + j; +} + +// CHECK-NOT: !DILexicalBlock +// CHECK: !DILexicalBlockFile({{.*}}file: ![[MH:[0-9]+]] +// CHECK: !DIFile(filename: "m.h" +// CHECK: !DILexicalBlockFile({{.*}}file: ![[MC:[0-9]+]] +// CHECK: !DIFile(filename: "m.c" +// CHECK-NOT: !DILexicalBlock diff --git a/test/CodeGen/debug-info-gline-tables-only2.c b/test/CodeGen/debug-info-gline-tables-only2.c index 8e9cc64e0d69..be457ab0b7ab 100644 --- a/test/CodeGen/debug-info-gline-tables-only2.c +++ b/test/CodeGen/debug-info-gline-tables-only2.c @@ -8,6 +8,6 @@ int main() { } // CHECK: !llvm.dbg.cu = !{!0} -// CHECK: DW_TAG_compile_unit -// CHECK: {{.*main.* DW_TAG_subprogram}} -// CHECK: DW_TAG_file_type +// CHECK: !DICompileUnit( +// CHECK: !DISubprogram( +// CHECK: !DIFile( diff --git a/test/CodeGen/debug-info-limited.c b/test/CodeGen/debug-info-limited.c index 7333452ee568..7c20ca4dd625 100644 --- a/test/CodeGen/debug-info-limited.c +++ b/test/CodeGen/debug-info-limited.c @@ -3,7 +3,9 @@ // Ensure we emit the full definition of 'foo' even though only its declaration // is needed, since C has no ODR to ensure that the definition will be the same // in whatever TU actually uses/requires the definition of 'foo'. -// CHECK: ; [ DW_TAG_structure_type ] [foo] {{.*}} [def] +// CHECK: !DICompositeType(tag: DW_TAG_structure_type, name: "foo", +// CHECK-NOT: DIFlagFwdDecl +// CHECK-SAME: ){{$}} struct foo { }; diff --git a/test/CodeGen/debug-info-line.c b/test/CodeGen/debug-info-line.c index 8f869d04f052..bc0d23a20003 100644 --- a/test/CodeGen/debug-info-line.c +++ b/test/CodeGen/debug-info-line.c @@ -1,21 +1,11 @@ -// RUN: %clang -emit-llvm -S -g %s -o - | FileCheck %s +// RUN: %clang_cc1 -w -gline-tables-only -fexceptions -fcxx-exceptions -S -emit-llvm %s -o - | FileCheck %s -// Radar 8396182 -// There are no lexical blocks, but we need two DILexicalBlockFiles to -// correctly represent file info. - -int foo() { - int i = 1; -# 4 "m.c" -# 1 "m.h" 1 - int j = 2; -# 2 "m.h" -# 5 "m.c" 2 - return i + j; +int f1(int a, int b) { + // CHECK: icmp {{.*}}, !dbg [[DBG_F1:!.*]] +#line 100 + return a // + && // + b; } -// CHECK: DW_TAG_lexical_block -// CHECK: !"m.h" -// CHECK: DW_TAG_lexical_block -// CHECK: !"m.c" -// CHECK-NOT: DW_TAG_lexical_block +// CHECK: [[DBG_F1]] = !DILocation(line: 100, diff --git a/test/CodeGen/debug-info-line3.c b/test/CodeGen/debug-info-line3.c index d2efcf724094..8ba57e208c04 100644 --- a/test/CodeGen/debug-info-line3.c +++ b/test/CodeGen/debug-info-line3.c @@ -13,4 +13,4 @@ void func(char c, char* d) } // CHECK: ret void, !dbg [[LINE:.*]] -// CHECK: [[LINE]] = !MDLocation(line: 6, +// CHECK: [[LINE]] = !DILocation(line: 6, diff --git a/test/CodeGen/debug-info-line4.c b/test/CodeGen/debug-info-line4.c index 2b3e0fe5bc65..3c99fc552117 100644 --- a/test/CodeGen/debug-info-line4.c +++ b/test/CodeGen/debug-info-line4.c @@ -8,4 +8,4 @@ int foo(int a, int b) { int c = a + b; } // Without column information we wouldn't change locations for b. -// CHECK: !MDLocation(line: 4, column: 20, +// CHECK: !DILocation(line: 4, column: 20, diff --git a/test/CodeGen/debug-info-same-line.c b/test/CodeGen/debug-info-same-line.c new file mode 100644 index 000000000000..7b71f57a682f --- /dev/null +++ b/test/CodeGen/debug-info-same-line.c @@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm %s -g -o - | FileCheck %s +// Here two temporary nodes are identical (but should not get uniqued) while +// building the full debug type. +typedef struct { long x; } foo; typedef struct { foo *x; } bar; +// CHECK: !DICompositeType(tag: DW_TAG_structure_type,{{.*}} line: 4, size: 64, +// CHECK: !DICompositeType(tag: DW_TAG_structure_type,{{.*}} line: 4, size: 64, +bar b; diff --git a/test/CodeGen/debug-info-scope-file.c b/test/CodeGen/debug-info-scope-file.c index 226fb27021eb..97063198a95c 100644 --- a/test/CodeGen/debug-info-scope-file.c +++ b/test/CodeGen/debug-info-scope-file.c @@ -5,10 +5,10 @@ // CHECK: ret void, !dbg [[F1_LINE:![0-9]*]] // CHECK: ret void, !dbg [[F2_LINE:![0-9]*]] -// CHECK: [[F1:![0-9]*]] = {{.*}} ; [ DW_TAG_subprogram ] {{.*}} [def] [f1] -// CHECK: [[F2:![0-9]*]] = {{.*}} ; [ DW_TAG_subprogram ] {{.*}} [def] [f2] -// CHECK: [[F1_LINE]] = !MDLocation({{.*}}, scope: [[F1]]) -// CHECK: [[F2_LINE]] = !MDLocation({{.*}}, scope: [[F2]]) +// CHECK: [[F1:![0-9]*]] = !DISubprogram(name: "f1",{{.*}} isDefinition: true +// CHECK: [[F2:![0-9]*]] = !DISubprogram(name: "f2",{{.*}} isDefinition: true +// CHECK: [[F1_LINE]] = !DILocation({{.*}}, scope: [[F1]]) +// CHECK: [[F2_LINE]] = !DILocation({{.*}}, scope: [[F2]]) void f1() { } diff --git a/test/CodeGen/debug-info-scope.c b/test/CodeGen/debug-info-scope.c index d84fafd018d2..aa6e5c1f2da0 100644 --- a/test/CodeGen/debug-info-scope.c +++ b/test/CodeGen/debug-info-scope.c @@ -5,23 +5,23 @@ int main() { int j = 0; int k = 0; -// CHECK: DW_TAG_auto_variable ] [i] -// CHECK-NEXT: DW_TAG_lexical_block +// CHECK: !DILocalVariable(tag: DW_TAG_auto_variable, name: "i" +// CHECK-NEXT: !DILexicalBlock( // FIXME: Looks like we don't actually need both these lexical blocks (disc 2 // just refers to disc 1, nothing actually uses disc 2). -// GMLT-NOT: DW_TAG_lexical_block -// GMLT: "0xb\002", {{.*}}} ; [ DW_TAG_lexical_block ] -// GMLT-NOT: DW_TAG_lexical_block -// GMLT: "0xb\001", {{.*}}} ; [ DW_TAG_lexical_block ] +// GMLT-NOT: !DILexicalBlock +// GMLT: !DILexicalBlockFile({{.*}}, discriminator: 2) +// GMLT-NOT: !DILexicalBlock +// GMLT: !DILexicalBlockFile({{.*}}, discriminator: 1) // Make sure we don't have any more lexical blocks because we don't need them in // -gmlt. -// GMLT-NOT: DW_TAG_lexical_block +// GMLT-NOT: !DILexicalBlock for (int i = 0; i < 10; i++) j++; -// CHECK: DW_TAG_auto_variable ] [i] -// CHECK-NEXT: DW_TAG_lexical_block -// GMLT-NOT: DW_TAG_lexical_block +// CHECK: !DILocalVariable(tag: DW_TAG_auto_variable, name: "i" +// CHECK-NEXT: !DILexicalBlock( +// GMLT-NOT: !DILexicalBlock for (int i = 0; i < 10; i++) k++; return 0; diff --git a/test/CodeGen/debug-info-static.c b/test/CodeGen/debug-info-static.c index 931c9e22afd0..115beaf84d40 100644 --- a/test/CodeGen/debug-info-static.c +++ b/test/CodeGen/debug-info-static.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -g -emit-llvm -o - %s | FileCheck %s -// CHECK: xyzzy, null} ; [ DW_TAG_variable ] +// CHECK: !DIGlobalVariable({{.*}}variable: i32* @f.xyzzy void f(void) { static int xyzzy; diff --git a/test/CodeGen/debug-info-typedef.c b/test/CodeGen/debug-info-typedef.c index 3db7d537890b..790e302984a9 100644 --- a/test/CodeGen/debug-info-typedef.c +++ b/test/CodeGen/debug-info-typedef.c @@ -7,5 +7,5 @@ typedef int MyType; MyType a; -// CHECK: !"0x16\00MyType\002\00{{.*}}", ![[HEADER:[0-9]+]], null{{.*}}} ; [ DW_TAG_typedef ] [MyType] [line 2, size 0, align 0, offset 0] [from int] -// CHECK: ![[HEADER]] = !{!"b.h", +// CHECK: !DIDerivedType(tag: DW_TAG_typedef, name: "MyType", file: ![[HEADER:[0-9]+]], line: 2, +// CHECK: ![[HEADER]] = !DIFile(filename: "b.h", diff --git a/test/CodeGen/debug-info-var-location.c b/test/CodeGen/debug-info-var-location.c deleted file mode 100644 index 41da7d382cb5..000000000000 --- a/test/CodeGen/debug-info-var-location.c +++ /dev/null @@ -1,22 +0,0 @@ -// FIXME: Check IR rather than asm, then triple is not needed. -// RUN: %clang -Xclang -triple=%itanium_abi_triple -S -g -fverbose-asm %s -o - | FileCheck %s -// Radar 8461032 -// CHECK: DW_AT_location -// CHECK-NEXT: byte 145 - -// 145 is DW_OP_fbreg -struct s { - int a; - struct s *next; -}; - -int foo(struct s *s) { - switch (s->a) { - case 1: - case 2: { - struct s *sp = s->next; - } - break; - } - return 1; -} diff --git a/test/CodeGen/debug-info-vector.c b/test/CodeGen/debug-info-vector.c index b7135afeeb8f..1075643cd602 100644 --- a/test/CodeGen/debug-info-vector.c +++ b/test/CodeGen/debug-info-vector.c @@ -4,4 +4,8 @@ typedef int v4si __attribute__((__vector_size__(16))); v4si a; // Test that we get an array type that's also a vector out of debug. -// CHECK: [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [vector] [from int] +// CHECK: !DICompositeType(tag: DW_TAG_array_type, +// CHECK-SAME: baseType: ![[INT:[0-9]+]] +// CHECK-SAME: size: 128, align: 128 +// CHECK-SAME: DIFlagVector +// CHECK: ![[INT]] = !DIBasicType(name: "int" diff --git a/test/CodeGen/debug-info-version.c b/test/CodeGen/debug-info-version.c index 5fe2e4eb570b..fa7e20e7f527 100644 --- a/test/CodeGen/debug-info-version.c +++ b/test/CodeGen/debug-info-version.c @@ -4,5 +4,5 @@ int main (void) { return 0; } -// CHECK: i32 2, !"Debug Info Version", i32 2} +// CHECK: i32 2, !"Debug Info Version", i32 3} // NO_DEBUG-NOT: !"Debug Info Version" diff --git a/test/CodeGen/debug-info-vla.c b/test/CodeGen/debug-info-vla.c index ac45dd0a7643..175c24cfb9dc 100644 --- a/test/CodeGen/debug-info-vla.c +++ b/test/CodeGen/debug-info-vla.c @@ -2,7 +2,10 @@ void testVLAwithSize(int s) { -// CHECK: !"0x100\00vla\00[[@LINE+1]]\008192", {{.*}}, {{.*}}, {{.*}}} ; [ DW_TAG_auto_variable ] [vla] [line [[@LINE+1]]] +// CHECK: dbg.declare +// CHECK: dbg.declare({{.*}}, metadata ![[VAR:.*]], metadata ![[EXPR:.*]]) +// CHECK: ![[VAR]] = !DILocalVariable(tag: DW_TAG_auto_variable, name: "vla",{{.*}} line: [[@LINE+2]] +// CHECK: ![[EXPR]] = !DIExpression(DW_OP_deref) int vla[s]; int i; for (i = 0; i < s; i++) { diff --git a/test/CodeGen/debug-info.c b/test/CodeGen/debug-info.c index bf08c589809c..1a505ee8bfb8 100644 --- a/test/CodeGen/debug-info.c +++ b/test/CodeGen/debug-info.c @@ -42,7 +42,7 @@ struct foo2 foo2; // Radar 7325611 -// CHECK: !"0x16\00barfoo\00{{.*}}" +// CHECK: !DIDerivedType(tag: DW_TAG_typedef, name: "barfoo" typedef int barfoo; barfoo foo() { } diff --git a/test/CodeGen/dllexport.c b/test/CodeGen/dllexport.c index 43899949437e..17c2ce9e2755 100644 --- a/test/CodeGen/dllexport.c +++ b/test/CodeGen/dllexport.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -triple i686-windows-msvc -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-windows-msvc -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple i686-windows-gnu -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-windows-gnu -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple i686-windows-gnu -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-windows-gnu -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck %s diff --git a/test/CodeGen/dllimport.c b/test/CodeGen/dllimport.c index 89dbb9f3461c..0dfecea43648 100644 --- a/test/CodeGen/dllimport.c +++ b/test/CodeGen/dllimport.c @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -triple i686-windows-msvc -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=MS %s -// RUN: %clang_cc1 -triple x86_64-windows-msvc -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=MS %s -// RUN: %clang_cc1 -triple i686-windows-gnu -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=GNU %s -// RUN: %clang_cc1 -triple x86_64-windows-gnu -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=GNU %s -// RUN: %clang_cc1 -triple i686-windows-msvc -emit-llvm -std=c11 -O1 -o - %s | FileCheck --check-prefix=O1 --check-prefix=MO1 %s -// RUN: %clang_cc1 -triple i686-windows-gnu -emit-llvm -std=c11 -O1 -o - %s | FileCheck --check-prefix=O1 --check-prefix=GO1 %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=MS %s +// RUN: %clang_cc1 -triple x86_64-windows-msvc -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=MS %s +// RUN: %clang_cc1 -triple i686-windows-gnu -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=GNU %s +// RUN: %clang_cc1 -triple x86_64-windows-gnu -fms-extensions -emit-llvm -std=c11 -O0 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=GNU %s +// RUN: %clang_cc1 -triple i686-windows-msvc -fms-extensions -emit-llvm -std=c11 -O1 -o - %s | FileCheck --check-prefix=O1 --check-prefix=MO1 %s +// RUN: %clang_cc1 -triple i686-windows-gnu -fms-extensions -emit-llvm -std=c11 -O1 -o - %s | FileCheck --check-prefix=O1 --check-prefix=GO1 %s #define JOIN2(x, y) x##y #define JOIN(x, y) JOIN2(x, y) diff --git a/test/CodeGen/enum.c b/test/CodeGen/enum.c index 0e239f1a8ee3..ef50f9eead64 100644 --- a/test/CodeGen/enum.c +++ b/test/CodeGen/enum.c @@ -1,5 +1,7 @@ -// RUN: %clang_cc1 -triple i386-unknown-unknown %s -O3 -emit-llvm -o - | grep 'ret i32 6' -// RUN: %clang_cc1 -triple i386-unknown-unknown -x c++ %s -O3 -emit-llvm -o - | grep 'ret i32 7' +// RUN: %clang_cc1 -triple i386-unknown-unknown %s -O3 -emit-llvm -o - | FileCheck -check-prefix=CHECK-C %s +// RUN: %clang_cc1 -triple i386-unknown-unknown -x c++ %s -O3 -emit-llvm -o - | FileCheck -check-prefix=CHECK-CXX %s +// CHECK-C: ret i32 6 +// CHECK-CXX: ret i32 7 // This test case illustrates a peculiarity of the promotion of // enumeration types in C and C++. In particular, the enumeration type @@ -19,4 +21,3 @@ int main (void) return r; } - diff --git a/test/CodeGen/exceptions-seh-finally.c b/test/CodeGen/exceptions-seh-finally.c new file mode 100644 index 000000000000..345d514611e3 --- /dev/null +++ b/test/CodeGen/exceptions-seh-finally.c @@ -0,0 +1,242 @@ +// RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s + +void abort(void) __attribute__((noreturn)); +void might_crash(void); +void cleanup(void); +int check_condition(void); +void basic_finally(void) { + __try { + might_crash(); + } __finally { + cleanup(); + } +} + +// CHECK-LABEL: define void @basic_finally() +// CHECK: invoke void @might_crash() +// CHECK: to label %[[invoke_cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[invoke_cont]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@basic_finally@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: ret void +// +// CHECK: [[lpad]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@basic_finally@@"(i8 1, i8* %[[fp]]) +// CHECK: resume { i8*, i32 } + +// CHECK: define internal void @"\01?fin$0@0@basic_finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: call void @cleanup() + +// Mostly check that we don't double emit 'r' which would crash. +void decl_in_finally(void) { + __try { + might_crash(); + } __finally { + int r; + } +} + +// Ditto, don't crash double emitting 'l'. +void label_in_finally(void) { + __try { + might_crash(); + } __finally { +l: + cleanup(); + if (check_condition()) + goto l; + } +} + +// CHECK-LABEL: define void @label_in_finally() +// CHECK: invoke void @might_crash() +// CHECK: to label %[[invoke_cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[invoke_cont]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@label_in_finally@@"(i8 0, i8* %[[fp]]) +// CHECK: ret void + +// CHECK: define internal void @"\01?fin$0@0@label_in_finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: br label %[[l:[^ ]*]] +// +// CHECK: [[l]] +// CHECK: call void @cleanup() +// CHECK: call i32 @check_condition() +// CHECK: br i1 {{.*}}, label +// CHECK: br label %[[l]] + +int crashed; +void use_abnormal_termination(void) { + __try { + might_crash(); + } __finally { + crashed = __abnormal_termination(); + } +} + +// CHECK-LABEL: define void @use_abnormal_termination() +// CHECK: invoke void @might_crash() +// CHECK: to label %[[invoke_cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[invoke_cont]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@use_abnormal_termination@@"(i8 0, i8* %[[fp]]) +// CHECK: ret void +// +// CHECK: [[lpad]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@use_abnormal_termination@@"(i8 1, i8* %[[fp]]) +// CHECK: resume { i8*, i32 } + +// CHECK: define internal void @"\01?fin$0@0@use_abnormal_termination@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: %[[abnormal_zext:[^ ]*]] = zext i8 %abnormal_termination to i32 +// CHECK: store i32 %[[abnormal_zext]], i32* @crashed +// CHECK-NEXT: ret void + +void noreturn_noop_finally() { + __try { + __noop(); + } __finally { + abort(); + } +} + +// CHECK-LABEL: define void @noreturn_noop_finally() +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@noreturn_noop_finally@@"(i8 0, i8* %[[fp]]) +// CHECK: ret void + +// CHECK: define internal void @"\01?fin$0@0@noreturn_noop_finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: call void @abort() +// CHECK: unreachable + +void noreturn_finally() { + __try { + might_crash(); + } __finally { + abort(); + } +} + +// CHECK-LABEL: define void @noreturn_finally() +// CHECK: invoke void @might_crash() +// CHECK: to label %[[cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[cont]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@noreturn_finally@@"(i8 0, i8* %[[fp]]) +// CHECK: ret void +// +// CHECK: [[lpad]] +// CHECK: landingpad +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@noreturn_finally@@"(i8 1, i8* %[[fp]]) +// CHECK: resume { i8*, i32 } + +// CHECK: define internal void @"\01?fin$0@0@noreturn_finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: call void @abort() +// CHECK: unreachable + +int finally_with_return() { + __try { + return 42; + } __finally { + } +} +// CHECK-LABEL: define i32 @finally_with_return() +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@finally_with_return@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: ret i32 42 + +// CHECK: define internal void @"\01?fin$0@0@finally_with_return@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK-NOT: br i1 +// CHECK-NOT: br label +// CHECK: ret void + +int nested___finally___finally() { + __try { + __try { + } __finally { + return 1; + } + } __finally { + // Intentionally no return here. + } + return 0; +} + +// CHECK-LABEL: define i32 @nested___finally___finally +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: invoke void @"\01?fin$1@0@nested___finally___finally@@"(i8 0, i8* %[[fp]]) +// CHECK: to label %[[outercont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[outercont]] +// CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@nested___finally___finally@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: ret i32 0 +// +// CHECK: [[lpad]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@nested___finally___finally@@"(i8 1, i8* %[[fp]]) + +// CHECK-LABEL: define internal void @"\01?fin$0@0@nested___finally___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: ret void + +// CHECK-LABEL: define internal void @"\01?fin$1@0@nested___finally___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: unreachable + +int nested___finally___finally_with_eh_edge() { + __try { + __try { + might_crash(); + } __finally { + return 899; + } + } __finally { + // Intentionally no return here. + } + return 912; +} +// CHECK-LABEL: define i32 @nested___finally___finally_with_eh_edge +// CHECK: invoke void @might_crash() +// CHECK-NEXT: to label %[[invokecont:[^ ]*]] unwind label %[[lpad1:[^ ]*]] +// +// [[invokecont]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: invoke void @"\01?fin$1@0@nested___finally___finally_with_eh_edge@@"(i8 0, i8* %[[fp]]) +// CHECK: to label %[[outercont:[^ ]*]] unwind label %[[lpad2:[^ ]*]] +// +// CHECK: [[outercont]] +// CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@nested___finally___finally_with_eh_edge@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: ret i32 912 +// +// CHECK: [[lpad1]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: invoke void @"\01?fin$1@0@nested___finally___finally_with_eh_edge@@"(i8 1, i8* %[[fp]]) +// CHECK: to label %[[outercont:[^ ]*]] unwind label %[[lpad2]] +// +// CHECK: [[lpad2]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@nested___finally___finally_with_eh_edge@@"(i8 1, i8* %[[fp]]) +// CHECK: resume + +// CHECK-LABEL: define internal void @"\01?fin$0@0@nested___finally___finally_with_eh_edge@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: ret void + +// CHECK-LABEL: define internal void @"\01?fin$1@0@nested___finally___finally_with_eh_edge@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: unreachable diff --git a/test/CodeGen/exceptions-seh-leave.c b/test/CodeGen/exceptions-seh-leave.c new file mode 100644 index 000000000000..36b896d06240 --- /dev/null +++ b/test/CodeGen/exceptions-seh-leave.c @@ -0,0 +1,349 @@ +// RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s + +void g(void); + +////////////////////////////////////////////////////////////////////////////// +// __leave with __except + +// Nothing in the __try block can trap, so __try.cont isn't created. +int __leave_with___except_simple() { + int myres = 0; + __try { + myres = 15; + __leave; + myres = 23; + } __except (1) { + return 0; + } + return 1; +} +// CHECK-LABEL: define i32 @__leave_with___except_simple() +// CHECK: store i32 15, i32* %myres +// CHECK-NEXT: br label %[[tryleave:[^ ]*]] +// CHECK-NOT: store i32 23 +// CHECK: [[tryleave]] +// CHECK-NEXT: ret i32 1 + + +// The "normal" case. +int __leave_with___except() { + int myres = 0; + __try { + g(); + __leave; + myres = 23; + } __except (1) { + return 0; + } + return 1; +} +// CHECK-LABEL: define i32 @__leave_with___except() +// CHECK: invoke void @g() +// CHECK-NEXT: to label %[[cont:.*]] unwind label %{{.*}} +// For __excepts, instead of an explicit __try.__leave label, we could use +// use invoke.cont as __leave jump target instead. However, not doing this +// keeps the CodeGen code simpler, __leave is very rare, and SimplifyCFG will +// simplify this anyways. +// CHECK: [[cont]] +// CHECK-NEXT: br label %[[tryleave:[^ ]*]] +// CHECK-NOT: store i32 23 +// CHECK: [[tryleave]] +// CHECK-NEXT: br label % + + +////////////////////////////////////////////////////////////////////////////// +// __leave with __finally + +void abort(void) __attribute__((noreturn)); + +// Nothing in the __try block can trap, so __finally.cont and friends aren't +// created. +int __leave_with___finally_simple() { + int myres = 0; + __try { + myres = 15; + __leave; + myres = 23; + } __finally { + return 0; + } + return 1; +} +// CHECK-LABEL: define i32 @__leave_with___finally_simple() +// CHECK: store i32 15, i32* %myres +// CHECK-NEXT: br label %[[tryleave:[^ ]*]] +// CHECK-NOT: store i32 23 +// CHECK: [[tryleave]] +// CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@__leave_with___finally_simple@@"(i8 0, i8* %[[fp]]) + +// __finally block doesn't return, __finally.cont doesn't exist. +int __leave_with___finally_noreturn() { + int myres = 0; + __try { + myres = 15; + __leave; + myres = 23; + } __finally { + abort(); + } + return 1; +} +// CHECK-LABEL: define i32 @__leave_with___finally_noreturn() +// CHECK: store i32 15, i32* %myres +// CHECK-NEXT: br label %[[tryleave:[^ ]*]] +// CHECK-NOT: store i32 23 +// CHECK: [[tryleave]] +// CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@__leave_with___finally_noreturn@@"(i8 0, i8* %[[fp]]) + +// The "normal" case. +int __leave_with___finally() { + int myres = 0; + __try { + g(); + __leave; + myres = 23; + } __finally { + return 0; + } + return 1; +} +// CHECK-LABEL: define i32 @__leave_with___finally() +// CHECK: invoke void @g() +// CHECK-NEXT: to label %[[cont:.*]] unwind label %{{.*}} +// For __finally, there needs to be an explicit __try.__leave, because +// abnormal.termination.slot needs to be set there. +// CHECK: [[cont]] +// CHECK-NEXT: br label %[[tryleave:[^ ]*]] +// CHECK-NOT: store i32 23 +// CHECK: [[tryleave]] +// CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@__leave_with___finally@@"(i8 0, i8* %[[fp]]) + + +////////////////////////////////////////////////////////////////////////////// +// Mixed, nested cases. + +int nested___except___finally() { + int myres = 0; + __try { + __try { + g(); + } __finally { + g(); + __leave; // Refers to the outer __try, not the __finally! + myres = 23; + return 0; + } + + myres = 51; + } __except (1) { + } + return 1; +} +// CHECK-LABEL: define i32 @nested___except___finally() + +// CHECK-LABEL: invoke void @g() +// CHECK-NEXT: to label %[[g1_cont1:.*]] unwind label %[[g1_lpad:.*]] + +// CHECK: [[g1_cont1]] +// CHECK-NEXT: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: invoke void @"\01?fin$0@0@nested___except___finally@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: to label %[[fin_cont:.*]] unwind label %[[g2_lpad:.*]] + +// CHECK: [[fin_cont]] +// CHECK: store i32 51, i32* % +// CHECK-NEXT: br label %[[trycont:[^ ]*]] + +// CHECK: [[g1_lpad]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: catch i8* null +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: invoke void @"\01?fin$0@0@nested___except___finally@@"(i8 1, i8* %[[fp]]) +// CHECK-NEXT: to label %[[g1_resume:.*]] unwind label %[[g2_lpad]] + +// CHECK: [[g2_lpad]] +// CHECK: br label %[[trycont]] + +// CHECK: [[trycont]] +// CHECK-NEXT: ret i32 1 + +// CHECK-LABEL: define internal void @"\01?fin$0@0@nested___except___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: call void @g() +// CHECK: unreachable + +int nested___except___except() { + int myres = 0; + __try { + __try { + g(); + myres = 16; + } __except (1) { + g(); + __leave; // Refers to the outer __try, not the __except we're in! + myres = 23; + return 0; + } + + myres = 51; + } __except (1) { + } + return 1; +} +// The order of basic blocks in the below doesn't matter. +// CHECK-LABEL: define i32 @nested___except___except() + +// CHECK-LABEL: invoke void @g() +// CHECK-NEXT: to label %[[g1_cont:.*]] unwind label %[[g1_lpad:.*]] + +// CHECK: [[g1_cont]] +// CHECK: store i32 16, i32* %myres +// CHECK-NEXT: br label %[[trycont:[^ ]*]] + +// CHECK: [[g1_lpad]] +// CHECK: br label %[[except:[^ ]*]] + +// CHECK: [[except]] +// CHECK-NEXT: invoke void @g() +// CHECK-NEXT: to label %[[g2_cont:.*]] unwind label %[[g2_lpad:.*]] + +// CHECK: [[g2_cont]] +// CHECK-NEXT: br label %[[tryleave:[^ ]*]] +// CHECK-NOT: store i32 23 + +// CHECK: [[g2_lpad]] +// CHECK: br label %[[outerexcept:[^ ]*]] + +// CHECK: [[outerexcept]] +// CHECK-NEXT: br label %[[trycont4:[^ ]*]] + +// CHECK: [[trycont4]] +// CHECK-NEXT: ret i32 1 + +// CHECK: [[trycont]] +// CHECK-NEXT: store i32 51, i32* %myres +// CHECK-NEXT: br label %[[tryleave]] + +// CHECK: [[tryleave]] +// CHECK-NEXT: br label %[[trycont4]] + +int nested___finally___except() { + int myres = 0; + __try { + __try { + g(); + } __except (1) { + g(); + __leave; // Refers to the outer __try, not the __except! + myres = 23; + return 0; + } + + myres = 51; + } __finally { + } + return 1; +} +// The order of basic blocks in the below doesn't matter. +// CHECK-LABEL: define i32 @nested___finally___except() + +// CHECK-LABEL: invoke void @g() +// CHECK-NEXT: to label %[[g1_cont:.*]] unwind label %[[g1_lpad:.*]] + +// CHECK: [[g1_cont]] +// CHECK-NEXT: br label %[[trycont:[^ ]*]] + +// CHECK: [[g1_lpad]] +// CHECK: br label %[[except:[^ ]*]] + +// CHECK: [[except]] +// CHECK-NEXT: invoke void @g() +// CHECK-NEXT: to label %[[g2_cont:.*]] unwind label %[[g2_lpad:.*]] + +// CHECK: [[g2_cont]] +// CHECK-NEXT: br label %[[tryleave:[^ ]*]] +// CHECK-NOT: 23 + +// CHECK: [[g2_lpad]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@nested___finally___except@@"(i8 1, i8* %[[fp]]) +// CHECK-NEXT: br label %[[ehresume:[^ ]*]] + +// CHECK: [[trycont]] +// CHECK: store i32 51, i32* % +// CHECK-NEXT: br label %[[tryleave]] + +// CHECK: [[tryleave]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@nested___finally___except@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: ret i32 1 + +// CHECK: [[ehresume]] +// CHECK: resume + +// CHECK-LABEL: define internal void @"\01?fin$0@0@nested___finally___except@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: ret void + +int nested___finally___finally() { + int myres = 0; + __try { + __try { + g(); + myres = 16; + } __finally { + g(); + __leave; // Refers to the outer __try, not the __finally we're in! + myres = 23; + return 0; + } + + myres = 51; + } __finally { + } + return 1; +} +// The order of basic blocks in the below doesn't matter. +// CHECK-LABEL: define i32 @nested___finally___finally() + +// CHECK-LABEL: invoke void @g() +// CHECK-NEXT: to label %[[g1_cont:.*]] unwind label %[[g1_lpad:.*]] + +// CHECK: [[g1_cont]] +// CHECK: store i32 16, i32* %[[myres:[^ ]*]], +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: invoke void @"\01?fin$1@0@nested___finally___finally@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: to label %[[finally_cont:.*]] unwind label %[[g2_lpad:.*]] + +// CHECK: [[finally_cont]] +// CHECK: store i32 51, i32* %[[myres]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@nested___finally___finally@@"(i8 0, i8* %[[fp]]) +// CHECK-NEXT: ret i32 1 + +// CHECK: [[g1_lpad]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: invoke void @"\01?fin$1@0@nested___finally___finally@@"(i8 1, i8* %[[fp]]) +// CHECK-NEXT: to label %[[finally_cont2:.*]] unwind label %[[g2_lpad]] + +// CHECK: [[g2_lpad]] +// CHECK-NEXT: landingpad +// CHECK-NEXT: cleanup +// CHECK: br label %[[ehcleanup:.*]] + +// CHECK: [[finally_cont2]] +// CHECK: br label %[[ehcleanup]] + +// CHECK: [[ehcleanup]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK-NEXT: call void @"\01?fin$0@0@nested___finally___finally@@"(i8 1, i8* %[[fp]]) +// CHECK: resume + +// CHECK-LABEL: define internal void @"\01?fin$0@0@nested___finally___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: ret void + +// CHECK-LABEL: define internal void @"\01?fin$1@0@nested___finally___finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: call void @g() +// CHECK: unreachable diff --git a/test/CodeGen/exceptions-seh.c b/test/CodeGen/exceptions-seh.c index 0a82e379b2cc..d8135e805c6b 100644 --- a/test/CodeGen/exceptions-seh.c +++ b/test/CodeGen/exceptions-seh.c @@ -1,19 +1,178 @@ -// RUN: not %clang_cc1 -triple i686-pc-win32 -fexceptions -fms-extensions -emit-llvm -o - %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s -// This is a codegen test because we only emit the diagnostic when we start -// generating code. +void try_body(int numerator, int denominator, int *myres) { + *myres = numerator / denominator; +} +// CHECK-LABEL: define void @try_body(i32 %numerator, i32 %denominator, i32* %myres) +// CHECK: sdiv i32 +// CHECK: store i32 %{{.*}}, i32* +// CHECK: ret void -int SaveDiv(int numerator, int denominator, int *res) { +int safe_div(int numerator, int denominator, int *res) { int myres = 0; + int success = 1; __try { - myres = numerator / denominator; - __leave; + try_body(numerator, denominator, &myres); } __except (1) { - return 0; + success = -42; } *res = myres; - return 1; + return success; +} +// CHECK-LABEL: define i32 @safe_div(i32 %numerator, i32 %denominator, i32* %res) +// CHECK: invoke void @try_body(i32 %{{.*}}, i32 %{{.*}}, i32* %{{.*}}) #[[NOINLINE:[0-9]+]] +// CHECK: to label %{{.*}} unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[lpad]] +// CHECK: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) +// CHECK-NEXT: catch i8* null +// CHECK-NOT: br i1 +// CHECK: br label %[[except:[^ ]*]] +// CHECK: [[except]] +// CHECK-NEXT: store i32 -42, i32* %[[success:[^ ]*]] +// +// CHECK: %[[res:[^ ]*]] = load i32, i32* %[[success]] +// CHECK: ret i32 %[[res]] + +void j(void); + +int filter_expr_capture(void) { + int r = 42; + __try { + j(); + } __except(r = -1) { + r = 13; + } + return r; +} + +// CHECK-LABEL: define i32 @filter_expr_capture() +// CHECK: call void (...) @llvm.frameescape(i32* %[[r:[^ ,]*]]) +// CHECK: store i32 42, i32* %[[r]] +// CHECK: invoke void @j() #[[NOINLINE]] +// +// CHECK: landingpad +// CHECK-NEXT: catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@filter_expr_capture@@" to i8*) +// CHECK: store i32 13, i32* %[[r]] +// +// CHECK: %[[rv:[^ ]*]] = load i32, i32* %[[r]] +// CHECK: ret i32 %[[rv]] + +// CHECK-LABEL: define internal i32 @"\01?filt$0@0@filter_expr_capture@@"(i8* %exception_pointers, i8* %frame_pointer) +// CHECK: call i8* @llvm.framerecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer, i32 0) +// CHECK: store i32 -1, i32* %{{.*}} +// CHECK: ret i32 -1 + +int nested_try(void) { + int r = 42; + __try { + __try { + j(); + r = 0; + } __except(_exception_code() == 123) { + r = 123; + } + } __except(_exception_code() == 456) { + r = 456; + } + return r; +} +// CHECK-LABEL: define i32 @nested_try() +// CHECK: store i32 42, i32* %[[r:[^ ,]*]] +// CHECK: invoke void @j() #[[NOINLINE]] +// CHECK: to label %[[cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[cont]] +// CHECK: store i32 0, i32* %[[r]] +// CHECK: br label %[[inner_try_cont:[^ ]*]] +// +// CHECK: [[lpad]] +// CHECK: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) +// CHECK: catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$1@0@nested_try@@" to i8*) +// CHECK: catch i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@nested_try@@" to i8*) +// CHECK: store i8* %{{.*}}, i8** %[[ehptr_slot:[^ ]*]] +// CHECK: store i32 %{{.*}}, i32* %[[sel_slot:[^ ]*]] +// +// CHECK: load i32, i32* %[[sel_slot]] +// CHECK: call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @"\01?filt$1@0@nested_try@@" to i8*)) +// CHECK: icmp eq i32 +// CHECK: br i1 +// +// CHECK: load i32, i32* %[[sel_slot]] +// CHECK: call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @"\01?filt$0@0@nested_try@@" to i8*)) +// CHECK: icmp eq i32 +// CHECK: br i1 +// +// CHECK: store i32 456, i32* %[[r]] +// CHECK: br label %[[outer_try_cont:[^ ]*]] +// +// CHECK: [[outer_try_cont]] +// CHECK: %[[r_load:[^ ]*]] = load i32, i32* %[[r]] +// CHECK: ret i32 %[[r_load]] +// +// CHECK: store i32 123, i32* %[[r]] +// CHECK: br label %[[inner_try_cont]] +// +// CHECK: [[inner_try_cont]] +// CHECK: br label %[[outer_try_cont]] + +static unsigned g = 0; +void basic_finally(void) { + ++g; + __try { + j(); + } __finally { + --g; + } } -// CHECK-NOT: error: -// CHECK: error: cannot compile this SEH __try yet -// CHECK-NOT: error: +// CHECK-LABEL: define void @basic_finally() +// CHECK: load i32, i32* @g +// CHECK: add i32 %{{.*}}, 1 +// CHECK: store i32 %{{.*}}, i32* @g +// +// CHECK: invoke void @j() +// CHECK: to label %[[cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[cont]] +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@basic_finally@@"(i8 0, i8* %[[fp]]) +// CHECK: ret void +// +// CHECK: [[lpad]] +// CHECK: landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) +// CHECK-NEXT: cleanup +// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.frameaddress(i32 0) +// CHECK: call void @"\01?fin$0@0@basic_finally@@"(i8 1, i8* %[[fp]]) +// CHECK: resume + +// CHECK: define internal void @"\01?fin$0@0@basic_finally@@"(i8 %abnormal_termination, i8* %frame_pointer) +// CHECK: load i32, i32* @g, align 4 +// CHECK: add i32 %{{.*}}, -1 +// CHECK: store i32 %{{.*}}, i32* @g, align 4 +// CHECK: ret void + +int returns_int(void); +int except_return(void) { + __try { + return returns_int(); + } __except(1) { + return 42; + } +} +// CHECK-LABEL: define i32 @except_return() +// CHECK: %[[tmp:[^ ]*]] = invoke i32 @returns_int() +// CHECK: to label %[[cont:[^ ]*]] unwind label %[[lpad:[^ ]*]] +// +// CHECK: [[cont]] +// CHECK: store i32 %[[tmp]], i32* %[[rv:[^ ]*]] +// CHECK: br label %[[retbb:[^ ]*]] +// +// CHECK: [[lpad]] +// CHECK: store i32 42, i32* %[[rv]] +// CHECK: br label %[[retbb]] +// +// CHECK: [[retbb]] +// CHECK: %[[r:[^ ]*]] = load i32, i32* %[[rv]] +// CHECK: ret i32 %[[r]] + +// CHECK: attributes #[[NOINLINE]] = { {{.*noinline.*}} } diff --git a/test/CodeGen/exprs.c b/test/CodeGen/exprs.c index 2a2216946b25..59afa802b183 100644 --- a/test/CodeGen/exprs.c +++ b/test/CodeGen/exprs.c @@ -127,9 +127,9 @@ int f11(long X) { return A[X]; // CHECK: [[Xaddr:%[^ ]+]] = alloca i64, align 8 -// CHECK: load {{.*}}* [[Xaddr]] -// CHECK-NEXT: getelementptr inbounds [100 x i32]* %A, i32 0, -// CHECK-NEXT: load i32* +// CHECK: load {{.*}}, {{.*}}* [[Xaddr]] +// CHECK-NEXT: getelementptr inbounds [100 x i32], [100 x i32]* %A, i32 0, +// CHECK-NEXT: load i32, i32* } int f12() { @@ -184,3 +184,14 @@ void f17() { extfunc(x); // CHECK: add nsw i128 %{{.}}, -1 } + +// PR23597: We should evaluate union cast operands even if the cast is unused. +typedef union u { + int i; +} strct; +int returns_int(void); +void f18() { + (strct)returns_int(); +} +// CHECK-LABEL: define void @f18() +// CHECK: call i32 @returns_int() diff --git a/test/CodeGen/ext-vector-indexing.c b/test/CodeGen/ext-vector-indexing.c index 28c0e1e9e25a..fff1fa45464c 100644 --- a/test/CodeGen/ext-vector-indexing.c +++ b/test/CodeGen/ext-vector-indexing.c @@ -8,7 +8,7 @@ void test() va.hi[0] = 3.0; // CHECK: [[VA:%.*]] = alloca <4 x float> // CHECK: [[CONV:%.*]] = bitcast <4 x float>* [[VA]] to float* -// CHECK: [[ADD:%.*]] = getelementptr inbounds float* [[CONV]], i64 2 -// CHECK: [[ARRIDX:%.*]] = getelementptr inbounds float* [[ADD]], i64 0 +// CHECK: [[ADD:%.*]] = getelementptr inbounds float, float* [[CONV]], i64 2 +// CHECK: [[ARRIDX:%.*]] = getelementptr inbounds float, float* [[ADD]], i64 0 // CHECK: store float 3.000000e+00, float* [[ARRIDX]] } diff --git a/test/CodeGen/ext-vector-member-alignment.c b/test/CodeGen/ext-vector-member-alignment.c index 49e69977fffd..5f044b8a28de 100644 --- a/test/CodeGen/ext-vector-member-alignment.c +++ b/test/CodeGen/ext-vector-member-alignment.c @@ -17,11 +17,11 @@ void func(struct struct1* p, float *a, float *b, float c) { // FIXME: We should be able to come up with a more aggressive alignment // estimate. // CHECK: @func - // CHECK: load <4 x float>* {{%.*}}, align 1 + // CHECK: load <4 x float>, <4 x float>* {{%.*}}, align 1 // CHECK: store <4 x float> {{%.*}}, <4 x float>* {{%.*}}, align 1 - // CHECK: load <4 x float>* {{%.*}}, align 1 - // CHECK: load <4 x float>* {{%.*}}, align 1 - // CHECK: load <4 x float>* {{%.*}}, align 1 + // CHECK: load <4 x float>, <4 x float>* {{%.*}}, align 1 + // CHECK: load <4 x float>, <4 x float>* {{%.*}}, align 1 + // CHECK: load <4 x float>, <4 x float>* {{%.*}}, align 1 // CHECK: store <4 x float> {{%.*}}, <4 x float>* {{%.*}}, align 1 // CHECK: ret void } diff --git a/test/CodeGen/extern-inline.c b/test/CodeGen/extern-inline.c index 77cb270191a0..2c0fde9f79bc 100644 --- a/test/CodeGen/extern-inline.c +++ b/test/CodeGen/extern-inline.c @@ -8,7 +8,7 @@ extern inline int f(int a) {return a;} int g(void) {return f(0);} // CHECK: call i32 @f int f(int b) {return 1+b;} -// CHECK: load i32* %{{.*}} +// CHECK: load i32, i32* %{{.*}} // CHECK: add nsw i32 1, %{{.*}} int h(void) {return f(1);} // CHECK: call i32 @f @@ -18,8 +18,8 @@ extern inline int f2(int a, int b) {return a+b;} int g2(void) {return f2(0,1);} // CHECK: call i32 @f2 static int f2(int a, int b) {return a*b;} -// CHECK: load i32* %{{.*}} -// CHECK: load i32* %{{.*}} +// CHECK: load i32, i32* %{{.*}} +// CHECK: load i32, i32* %{{.*}} // CHECK: mul nsw i32 %{{.*}}, %{{.*}} int h2(void) {return f2(1,2);} // CHECK: call i32 @f2 diff --git a/test/CodeGen/finite-math.c b/test/CodeGen/finite-math.c index b0ee15759a5d..8365b56fe56b 100644 --- a/test/CodeGen/finite-math.c +++ b/test/CodeGen/finite-math.c @@ -1,11 +1,17 @@ -// RUN: %clang_cc1 -ffinite-math-only -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -ffinite-math-only -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=FINITE +// RUN: %clang_cc1 -fno-signed-zeros -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=NSZ +// RUN: %clang_cc1 -freciprocal-math -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=RECIP + float f0, f1, f2; void foo(void) { // CHECK-LABEL: define void @foo() - // CHECK: fadd nnan ninf + // FINITE: fadd nnan ninf + // NSZ: fadd nsz + // RECIP: fadd arcp f0 = f1 + f2; // CHECK: ret } + diff --git a/test/CodeGen/fp16-ops.c b/test/CodeGen/fp16-ops.c index b269cf89fb0e..fe0fa2c2667e 100644 --- a/test/CodeGen/fp16-ops.c +++ b/test/CodeGen/fp16-ops.c @@ -1,284 +1,417 @@ // REQUIRES: arm-registered-target -// RUN: %clang_cc1 -emit-llvm -o - -triple arm-none-linux-gnueabi %s | FileCheck %s +// RUN: %clang_cc1 -emit-llvm -o - -triple arm-none-linux-gnueabi %s | FileCheck %s --check-prefix=NOHALF --check-prefix=CHECK +// RUN: %clang_cc1 -emit-llvm -o - -triple aarch64-none-linux-gnueabi %s | FileCheck %s --check-prefix=NOHALF --check-prefix=CHECK +// RUN: %clang_cc1 -emit-llvm -o - -triple arm-none-linux-gnueabi -fallow-half-arguments-and-returns %s | FileCheck %s --check-prefix=HALF --check-prefix=CHECK +// RUN: %clang_cc1 -emit-llvm -o - -triple aarch64-none-linux-gnueabi -fallow-half-arguments-and-returns %s | FileCheck %s --check-prefix=HALF --check-prefix=CHECK +// RUN: %clang_cc1 -emit-llvm -o - -triple arm-none-linux-gnueabi -fnative-half-type %s \ +// RUN: | FileCheck %s --check-prefix=NATIVE-HALF +// RUN: %clang_cc1 -emit-llvm -o - -triple aarch64-none-linux-gnueabi -fnative-half-type %s \ +// RUN: | FileCheck %s --check-prefix=NATIVE-HALF typedef unsigned cond_t; volatile cond_t test; volatile __fp16 h0 = 0.0, h1 = 1.0, h2; volatile float f0, f1, f2; +volatile double d0; void foo(void) { // CHECK-LABEL: define void @foo() // Check unary ops - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK fptoi float + // NOHALF: [[F16TOF32:call float @llvm.convert.from.fp16.f32]] + // HALF: [[F16TOF32:fpext half]] + // CHECK: fptoui float + // NATIVE-HALF: fptoui half test = (h0); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: uitofp i32 + // NOHALF: [[F32TOF16:call i16 @llvm.convert.to.fp16.f32]] + // HALF: [[F32TOF16:fptrunc float]] + // NATIVE-HALF: uitofp i32 {{.*}} to half + h0 = (test); + // CHECK: [[F16TOF32]] // CHECK: fcmp une float + // NATIVE-HALF: fcmp une half test = (!h1); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fsub float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // NOHALF: [[F32TOF16]] + // HALF: [[F32TOF16]] + // NATIVE-HALF: fsub half h1 = -h1; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F32TOF16]] + // NATIVE-HALF: load volatile half + // NATIVE-HALF-NEXT: store volatile half h1 = +h1; - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half h1++; - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half ++h1; - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half --h1; - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half h1--; // Check binary ops with various operands - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] // CHECK: fmul float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fmul half h1 = h0 * h2; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call i16 @llvm.convert.to.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F32TOF16]] + // NOHALF: [[F16TOF32]] // CHECK: fmul float - // CHECK: call i16 @llvm.convert.to.fp16.f32( - h1 = h0 * (__fp16) -2.0; - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fmul half + h1 = h0 * (__fp16) -2.0f; + // CHECK: [[F16TOF32]] // CHECK: fmul float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fmul float h1 = h0 * f2; - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fmul float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fmul float h1 = f0 * h2; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] // CHECK: fdiv float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fdiv half h1 = (h0 / h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] // CHECK: fdiv float - // CHECK: call i16 @llvm.convert.to.fp16.f32( - h1 = (h0 / (__fp16) -2.0); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fdiv half + h1 = (h0 / (__fp16) -2.0f); + // CHECK: [[F16TOF32]] // CHECK: fdiv float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fdiv float h1 = (h0 / f2); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fdiv float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fdiv float h1 = (f0 / h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half h1 = (h2 + h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half h1 = ((__fp16)-2.0 + h0); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fadd float h1 = (h2 + f0); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fadd float h1 = (f2 + h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] // CHECK: fsub float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fsub half h1 = (h2 - h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] // CHECK: fsub float - // CHECK: call i16 @llvm.convert.to.fp16.f32( - h1 = ((__fp16)-2.0 - h0); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fsub half + h1 = ((__fp16)-2.0f - h0); + // CHECK: [[F16TOF32]] // CHECK: fsub float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fsub float h1 = (h2 - f0); - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] // CHECK: fsub float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fsub float h1 = (f2 - h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp olt + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fcmp olt float + // NATIVE-HALF: fcmp olt half test = (h2 < h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp olt + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fcmp olt float + // NATIVE-HALF: fcmp olt half test = (h2 < (__fp16)42.0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp olt + // CHECK: [[F16TOF32]] + // CHECK: fcmp olt float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp olt float test = (h2 < f0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp olt + // CHECK: [[F16TOF32]] + // CHECK: fcmp olt float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp olt float test = (f2 < h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ogt + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fcmp ogt float + // NATIVE-HALF: fcmp ogt half test = (h0 > h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ogt + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fcmp ogt float + // NATIVE-HALF: fcmp ogt half test = ((__fp16)42.0 > h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ogt + // CHECK: [[F16TOF32]] + // CHECK: fcmp ogt float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp ogt float test = (h0 > f2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ogt + // CHECK: [[F16TOF32]] + // CHECK: fcmp ogt float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp ogt float test = (f0 > h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ole + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fcmp ole float + // NATIVE-HALF: fcmp ole half test = (h2 <= h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ole + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fcmp ole float + // NATIVE-HALF: fcmp ole half test = (h2 <= (__fp16)42.0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ole + // CHECK: [[F16TOF32]] + // CHECK: fcmp ole float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp ole float test = (h2 <= f0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp ole + // CHECK: [[F16TOF32]] + // CHECK: fcmp ole float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp ole float test = (f2 <= h0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oge + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fcmp oge float + // NATIVE-HALF: fcmp oge half test = (h0 >= h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oge + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fcmp oge float + // NATIVE-HALF: fcmp oge half test = (h0 >= (__fp16)-2.0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oge + // CHECK: [[F16TOF32]] + // CHECK: fcmp oge float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp oge float test = (h0 >= f2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oge + // CHECK: [[F16TOF32]] + // CHECK: fcmp oge float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp oge float test = (f0 >= h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oeq + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fcmp oeq float + // NATIVE-HALF: fcmp oeq half test = (h1 == h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oeq + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fcmp oeq float + // NATIVE-HALF: fcmp oeq half test = (h1 == (__fp16)1.0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oeq + // CHECK: [[F16TOF32]] + // CHECK: fcmp oeq float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp oeq float test = (h1 == f1); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp oeq + // CHECK: [[F16TOF32]] + // CHECK: fcmp oeq float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp oeq float test = (f1 == h1); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp une + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fcmp une float + // NATIVE-HALF: fcmp une half test = (h1 != h2); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp une + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fcmp une float + // NATIVE-HALF: fcmp une half test = (h1 != (__fp16)1.0); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp une + // CHECK: [[F16TOF32]] + // CHECK: fcmp une float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp une float test = (h1 != f1); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp une + // CHECK: [[F16TOF32]] + // CHECK: fcmp une float + // NATIVE-HALF: fpext half + // NATIVE-HALF: fcmp une float test = (f1 != h1); - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fcmp une - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: fcmp une float + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fcmp une half {{.*}}, 0xH0000 h1 = (h1 ? h2 : h0); // Check assignments (inc. compound) h0 = h1; - // CHECK: call i16 @llvm.convert.to.fp16.f32( - h0 = (__fp16)-2.0; - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // NOHALF: [[F32TOF16]] + // HALF: store {{.*}} half 0xHC000 + // NATIVE-HALF: store {{.*}} half 0xHC000 + h0 = (__fp16)-2.0f; + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fptrunc float h0 = f0; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] // CHECK: fadd float - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half h0 += h1; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fadd - // CHECK: call i16 @llvm.convert.to.fp16.f32( - h0 += (__fp16)1.0; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fadd - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fadd float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fadd half + h0 += (__fp16)1.0f; + // CHECK: [[F16TOF32]] + // CHECK: fadd float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fadd float + // NATIVE-HALF: fptrunc float h0 += f2; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fsub - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fsub float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fsub half h0 -= h1; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fsub - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fsub float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fsub half h0 -= (__fp16)1.0; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fsub - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: fsub float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fsub float + // NATIVE-HALF: fptrunc float h0 -= f2; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fmul - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fmul float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fmul half h0 *= h1; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fmul - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fmul float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fmul half h0 *= (__fp16)1.0; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fmul - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: fmul float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fmul float + // NATIVE-HALF: fptrunc float h0 *= f2; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fdiv - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: [[F16TOF32]] + // CHECK: fdiv float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fdiv half h0 /= h1; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fdiv - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // NOHALF: [[F16TOF32]] + // CHECK: fdiv float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fdiv half h0 /= (__fp16)1.0; - // CHECK: call float @llvm.convert.from.fp16.f32( - // CHECK: fdiv - // CHECK: call i16 @llvm.convert.to.fp16.f32( + // CHECK: [[F16TOF32]] + // CHECK: fdiv float + // CHECK: [[F32TOF16]] + // NATIVE-HALF: fpext half + // NATIVE-HALF: fdiv float + // NATIVE-HALF: fptrunc float h0 /= f2; + + // Check conversions to/from double + // NOHALF: call i16 @llvm.convert.to.fp16.f64( + // HALF: fptrunc double {{.*}} to half + // NATIVE-HALF: fptrunc double {{.*}} to half + h0 = d0; + + // CHECK: [[MID:%.*]] = fptrunc double {{%.*}} to float + // NOHALF: call i16 @llvm.convert.to.fp16.f32(float [[MID]]) + // HALF: fptrunc float [[MID]] to half + // NATIVE-HALF: [[MID:%.*]] = fptrunc double {{%.*}} to float + // NATIVE-HALF: fptrunc float {{.*}} to half + h0 = (float)d0; + + // NOHALF: call double @llvm.convert.from.fp16.f64( + // HALF: fpext half {{.*}} to double + // NATIVE-HALF: fpext half {{.*}} to double + d0 = h0; + + // NOHALF: [[MID:%.*]] = call float @llvm.convert.from.fp16.f32( + // HALF: [[MID:%.*]] = fpext half {{.*}} to float + // CHECK: fpext float [[MID]] to double + // NATIVE-HALF: [[MID:%.*]] = fpext half {{.*}} to float + // NATIVE-HALF: fpext float [[MID]] to double + d0 = (float)h0; } diff --git a/test/CodeGen/function-target-features.c b/test/CodeGen/function-target-features.c new file mode 100644 index 000000000000..351c7f102b12 --- /dev/null +++ b/test/CodeGen/function-target-features.c @@ -0,0 +1,26 @@ +// This test verifies that we produce target-cpu and target-features attributes +// on functions when they're different from the standard cpu and have written +// features. + +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | FileCheck %s -check-prefix=AVX-FEATURE +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | FileCheck %s -check-prefix=AVX-NO-CPU +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx512f -target-feature +avx512er | FileCheck %s -check-prefix=TWO-AVX +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu corei7 | FileCheck %s -check-prefix=CORE-CPU +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu corei7 -target-feature +avx | FileCheck %s -check-prefix=CORE-CPU-AND-FEATURES +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu x86-64 | FileCheck %s -check-prefix=X86-64-CPU +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-cpu corei7-avx -target-feature -avx | FileCheck %s -check-prefix=AVX-MINUS-FEATURE +// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm -o - %s -target-feature +soft-float | FileCheck %s -check-prefix=NO-SOFT-FLOAT +// RUN: %clang_cc1 -triple arm-unknown-unknown -emit-llvm -o - %s -target-feature +soft-float | FileCheck %s -check-prefix=SOFT-FLOAT +// RUN: %clang_cc1 -triple mips-unknown-unknown -emit-llvm -o - %s -target-feature +soft-float | FileCheck %s -check-prefix=SOFT-FLOAT + +void foo() {} + +// AVX-FEATURE: "target-features"{{.*}}+avx +// AVX-NO-CPU-NOT: target-cpu +// TWO-AVX: "target-features"={{.*}}+avx512er{{.*}}+avx512f +// CORE-CPU: "target-cpu"="corei7" +// CORE-CPU-AND-FEATURES: "target-cpu"="corei7" "target-features"={{.*}}+avx +// X86-64-CPU: "target-cpu"="x86-64" +// AVX-MINUS-FEATURE: "target-features"={{.*}}-avx +// SOFT-FLOAT: "target-features"={{.*}}+soft-float +// NO-SOFT-FLOAT-NOT: "target-features"={{.*}}+soft-float diff --git a/test/CodeGen/funique-sections.c b/test/CodeGen/funique-sections.c new file mode 100644 index 000000000000..1473fe57db01 --- /dev/null +++ b/test/CodeGen/funique-sections.c @@ -0,0 +1,13 @@ +// REQUIRES: x86-registered-target + +// RUN: %clang_cc1 -triple x86_64-pc-linux -S -ffunction-sections -fdata-sections -fno-unique-section-names -o - < %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-pc-linux -S -ffunction-sections -fdata-sections -o - < %s | FileCheck %s --check-prefix=UNIQUE + +const int hello = 123; +void world() {} + +// CHECK: .section .text,"ax",@progbits,unique +// CHECK: .section .rodata,"a",@progbits,unique + +// UNIQUE: .section .text.world,"ax",@progbits +// UNIQUE: .section .rodata.hello,"a",@progbits diff --git a/test/CodeGen/init.c b/test/CodeGen/init.c index b396c3be62fe..a2b492013d49 100644 --- a/test/CodeGen/init.c +++ b/test/CodeGen/init.c @@ -135,8 +135,8 @@ void test13(int x) { // CHECK-LABEL: @PR20473 void PR20473() { - // CHECK: memcpy{{.*}}([2 x i8]* @ + // CHECK: memcpy{{.*}}getelementptr inbounds ([2 x i8], [2 x i8]* @ bar((char[2]) {""}); - // CHECK: memcpy{{.*}}([3 x i8]* @ + // CHECK: memcpy{{.*}}getelementptr inbounds ([3 x i8], [3 x i8]* @ bar((char[3]) {""}); } diff --git a/test/CodeGen/inline-asm-matching-constraint.c b/test/CodeGen/inline-asm-matching-constraint.c new file mode 100644 index 000000000000..45c387f05ce2 --- /dev/null +++ b/test/CodeGen/inline-asm-matching-constraint.c @@ -0,0 +1,11 @@ +// RUN: %clang_cc1 -emit-llvm %s -o - -triple powerpc64le-linux-gnu | FileCheck %s +// Sadly since this requires a register constraint to trigger we have to set +// a target here. +void a(void) { + register unsigned long __sc_0 __asm__("r0"); + __asm__ __volatile__("mfcr %0" : "=&r"(__sc_0) : "0"(__sc_0)); +} + +// Check that we can generate code for this correctly. The matching input +// constraint should not have an early clobber on it. +// CHECK: call i64 asm sideeffect "mfcr $0", "=&{r0},{r0}" diff --git a/test/CodeGen/inline.c b/test/CodeGen/inline.c index 96c9a86baecb..a45bccc51328 100644 --- a/test/CodeGen/inline.c +++ b/test/CodeGen/inline.c @@ -17,8 +17,8 @@ // CHECK1-LABEL: define void @testA // CHECK1-LABEL: define void @testB // CHECK1-LABEL: define void @testC -// CHECK1-LABEL: define available_externally void @gnu_ei_inline() // CHECK1-LABEL: define available_externally i32 @ei() +// CHECK1-LABEL: define available_externally void @gnu_ei_inline() // RUN: echo "C99 tests:" // RUN: %clang_cc1 %s -triple i386-unknown-unknown -O1 -disable-llvm-optzns -emit-llvm -o - -std=gnu99 | FileCheck %s --check-prefix=CHECK2 @@ -39,8 +39,8 @@ // CHECK2-LABEL: define void @testA // CHECK2-LABEL: define void @testB // CHECK2-LABEL: define void @testC -// CHECK2-LABEL: define available_externally void @gnu_ei_inline() // CHECK2-LABEL: define available_externally i32 @foo() +// CHECK2-LABEL: define available_externally void @gnu_ei_inline() // RUN: echo "C++ tests:" // RUN: %clang_cc1 -x c++ %s -triple i386-unknown-unknown -O1 -disable-llvm-optzns -emit-llvm -o - -std=c++98 | FileCheck %s --check-prefix=CHECK3 @@ -49,6 +49,7 @@ // CHECK3-NOT: unreferenced // CHECK3-LABEL: define void @_Z10gnu_inlinev() // CHECK3-LABEL: define available_externally void @_Z13gnu_ei_inlinev() +// CHECK3-NOT: @_Z5testCv // CHECK3-LABEL: define linkonce_odr i32 @_Z2eiv() // RUN: echo "MS C Mode tests:" @@ -58,8 +59,8 @@ // CHECK4-NOT: unreferenced1 // CHECK4-LABEL: define weak_odr void @unreferenced2() // CHECK4-LABEL: define void @gnu_inline() -// CHECK4-LABEL: define available_externally void @gnu_ei_inline() // CHECK4-LABEL: define linkonce_odr i32 @foo() +// CHECK4-LABEL: define available_externally void @gnu_ei_inline() extern __inline int ei() { return 123; } diff --git a/test/CodeGen/integer-overflow.c b/test/CodeGen/integer-overflow.c index a007960dec83..de3b53f4b5b3 100644 --- a/test/CodeGen/integer-overflow.c +++ b/test/CodeGen/integer-overflow.c @@ -52,18 +52,18 @@ void test1() { // DEFAULT: add nsw i32 {{.*}}, -1 // WRAPV: add i32 {{.*}}, -1 - // TRAPV: llvm.sadd.with.overflow.i32({{.*}}, i32 -1) - // CATCH_UB: llvm.sadd.with.overflow.i32({{.*}}, i32 -1) + // TRAPV: llvm.ssub.with.overflow.i32({{.*}}, i32 1) + // CATCH_UB: llvm.ssub.with.overflow.i32({{.*}}, i32 1) // TRAPV_HANDLER: foo( --a; // -fwrapv should turn off inbounds for GEP's, PR9256 extern int* P; ++P; - // DEFAULT: getelementptr inbounds i32* - // WRAPV: getelementptr i32* - // TRAPV: getelementptr inbounds i32* - // CATCH_UB: getelementptr inbounds i32* + // DEFAULT: getelementptr inbounds i32, i32* + // WRAPV: getelementptr i32, i32* + // TRAPV: getelementptr inbounds i32, i32* + // CATCH_UB: getelementptr inbounds i32, i32* // PR9350: char increment never overflows. extern volatile signed char PR9350; diff --git a/test/CodeGen/kr-func-promote.c b/test/CodeGen/kr-func-promote.c index fcdbac3ee424..8e55dc91edf4 100644 --- a/test/CodeGen/kr-func-promote.c +++ b/test/CodeGen/kr-func-promote.c @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -triple i386-unknown-unknown %s -emit-llvm -o - | grep "i32 @a(i32)" +// RUN: %clang_cc1 -triple i386-unknown-unknown %s -emit-llvm -o - | FileCheck %s +// CHECK: i32 @a(i32) int a(); int a(x) short x; {return x;} diff --git a/test/CodeGen/lifetime-debuginfo-1.c b/test/CodeGen/lifetime-debuginfo-1.c new file mode 100644 index 000000000000..674346a031d2 --- /dev/null +++ b/test/CodeGen/lifetime-debuginfo-1.c @@ -0,0 +1,13 @@ +// RUN: %clang_cc1 -O1 -triple x86_64-none-linux-gnu -emit-llvm -gline-tables-only %s -o - | FileCheck %s + +// Inserting lifetime markers should not affect debuginfo + +extern int x; + +// CHECK-LABEL: define i32 @f +int f() { + int *p = &x; +// CHECK: ret i32 %{{.*}}, !dbg [[DI:![0-9]*]] +// CHECK: [[DI]] = !DILocation(line: [[@LINE+1]] + return *p; +} diff --git a/test/CodeGen/lifetime-debuginfo-2.c b/test/CodeGen/lifetime-debuginfo-2.c new file mode 100644 index 000000000000..03afbd8c18b7 --- /dev/null +++ b/test/CodeGen/lifetime-debuginfo-2.c @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -O1 -triple x86_64-none-linux-gnu -emit-llvm -gline-tables-only %s -o - | FileCheck %s + +// Inserting lifetime markers should not affect debuginfo: lifetime.end is not +// a destructor, but instrumentation for the compiler. Ensure the debug info for +// the return statement (in the IR) does not point to the function closing '}' +// which is used to show some destructors have been called before leaving the +// function. + +extern int f(int); +extern int g(int); + +// CHECK-LABEL: define i32 @test +int test(int a, int b) { + int res; + + if (a==2) { + int r = f(b); + res = r + b; + a += 2; + } else { + int r = f(a); + res = r + a; + b += 1; + } + + return res; +// CHECK: ret i32 %{{.*}}, !dbg [[DI:![0-9]+]] +// CHECK: [[DI]] = !DILocation(line: [[@LINE-2]] +} diff --git a/test/CodeGen/lineno-dbginfo.c b/test/CodeGen/lineno-dbginfo.c index 28c72438f542..ac61c8364949 100644 --- a/test/CodeGen/lineno-dbginfo.c +++ b/test/CodeGen/lineno-dbginfo.c @@ -1,6 +1,9 @@ // RUN: echo "#include <stddef.h>" > %t.h // RUN: %clang_cc1 -S -g -include %t.h %s -emit-llvm -o - | FileCheck %s -// CHECK: !"0x34\00outer\00outer\00\00[[@LINE+1]]\000\001" +// CHECK: !DIGlobalVariable(name: "outer", +// CHECK-NOT: linkageName: +// CHECK-SAME: line: [[@LINE+2]] +// CHECK-SAME: isDefinition: true int outer = 42; diff --git a/test/CodeGen/linetable-endscope.c b/test/CodeGen/linetable-endscope.c index 9a737cf79655..961eaec7dece 100644 --- a/test/CodeGen/linetable-endscope.c +++ b/test/CodeGen/linetable-endscope.c @@ -11,7 +11,7 @@ void foo(char c) { int i; - // CHECK: ![[CONV]] = !MDLocation(line: [[@LINE+1]], scope: !{{.*}}) + // CHECK: ![[CONV]] = !DILocation(line: [[@LINE+1]], scope: !{{.*}}) i = c; - // CHECK: ![[RET]] = !MDLocation(line: [[@LINE+1]], scope: !{{.*}}) + // CHECK: ![[RET]] = !DILocation(line: [[@LINE+1]], scope: !{{.*}}) } diff --git a/test/CodeGen/link-bitcode-file.c b/test/CodeGen/link-bitcode-file.c index fb97b4d1f585..92b1a88ffb2d 100644 --- a/test/CodeGen/link-bitcode-file.c +++ b/test/CodeGen/link-bitcode-file.c @@ -1,6 +1,9 @@ // RUN: %clang_cc1 -triple i386-pc-linux-gnu -DBITCODE -emit-llvm-bc -o %t.bc %s // RUN: %clang_cc1 -triple i386-pc-linux-gnu -mlink-bitcode-file %t.bc -O3 -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-NO-BC %s // RUN: not %clang_cc1 -triple i386-pc-linux-gnu -DBITCODE -mlink-bitcode-file %t.bc -O3 -emit-llvm -o - %s 2>&1 | FileCheck -check-prefix=CHECK-BC %s +// Make sure we deal with failure to load the file. +// RUN: not %clang_cc1 -triple i386-pc-linux-gnu -mlink-bitcode-file no-such-file.bc \ +// RUN: -emit-llvm -o - %s 2>&1 | FileCheck -check-prefix=CHECK-NO-FILE %s int f(void); @@ -22,3 +25,5 @@ int g(void) { // CHECK-NO-BC-LABEL: define i32 @f #endif + +// CHECK-NO-FILE: fatal error: cannot open file 'no-such-file.bc' diff --git a/test/CodeGen/mangle-blocks.c b/test/CodeGen/mangle-blocks.c index c5e08e9dd5b1..0023f53b3490 100644 --- a/test/CodeGen/mangle-blocks.c +++ b/test/CodeGen/mangle-blocks.c @@ -13,11 +13,11 @@ void (^mangle(void))(void) { // CHECK: @__func__.__mangle_block_invoke_2 = private unnamed_addr constant [24 x i8] c"__mangle_block_invoke_2\00", align 1 // CHECK: @.str = private unnamed_addr constant {{.*}}, align 1 -// CHECK: @.str1 = private unnamed_addr constant [7 x i8] c"mangle\00", align 1 +// CHECK: @.str.1 = private unnamed_addr constant [7 x i8] c"mangle\00", align 1 // CHECK: define internal void @__mangle_block_invoke(i8* %.block_descriptor) // CHECK: define internal void @__mangle_block_invoke_2(i8* %.block_descriptor){{.*}}{ -// CHECK: call void @__assert_rtn(i8* getelementptr inbounds ([24 x i8]* @__func__.__mangle_block_invoke_2, i32 0, i32 0), i8* getelementptr inbounds {{.*}}, i32 9, i8* getelementptr inbounds ([7 x i8]* @.str1, i32 0, i32 0)) +// CHECK: call void @__assert_rtn(i8* getelementptr inbounds ([24 x i8], [24 x i8]* @__func__.__mangle_block_invoke_2, i32 0, i32 0), i8* getelementptr inbounds {{.*}}, i32 9, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.1, i32 0, i32 0)) // CHECK: } diff --git a/test/CodeGen/mangle-windows.c b/test/CodeGen/mangle-windows.c index 594dbf09e9fa..db39425da827 100644 --- a/test/CodeGen/mangle-windows.c +++ b/test/CodeGen/mangle-windows.c @@ -5,8 +5,8 @@ // RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-mingw32 | FileCheck %s --check-prefix=X64 // RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-pc-windows-msvc-elf | FileCheck %s --check-prefix=ELF64 -// CHECK: target datalayout = "e-m:w-{{.*}}" -// X64: target datalayout = "e-m:e-{{.*}}" +// CHECK: target datalayout = "e-m:x-{{.*}}" +// X64: target datalayout = "e-m:w-{{.*}}" // ELF32: target datalayout = "e-m:e-{{.*}}" // ELF64: target datalayout = "e-m:e-{{.*}}" diff --git a/test/CodeGen/mips-inline-asm-modifiers.c b/test/CodeGen/mips-inline-asm-modifiers.c index 9437dbe5abe5..3116e764b213 100644 --- a/test/CodeGen/mips-inline-asm-modifiers.c +++ b/test/CodeGen/mips-inline-asm-modifiers.c @@ -7,8 +7,8 @@ int printf(const char*, ...); typedef int v4i32 __attribute__((vector_size(16))); - // CHECK: %{{[0-9]+}} = call i32 asm ".set noreorder;\0Alw $0,$1;\0A.set reorder;\0A", "=r,*m,~{$1}"(i32* getelementptr inbounds ([8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2, - // CHECK: %{{[0-9]+}} = call i32 asm "lw $0,${1:D};\0A", "=r,*m,~{$1}"(i32* getelementptr inbounds ([8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2, + // CHECK: %{{[0-9]+}} = call i32 asm ".set noreorder;\0Alw $0,$1;\0A.set reorder;\0A", "=r,*m,~{$1}"(i32* getelementptr inbounds ([8 x i32], [8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2, + // CHECK: %{{[0-9]+}} = call i32 asm "lw $0,${1:D};\0A", "=r,*m,~{$1}"(i32* getelementptr inbounds ([8 x i32], [8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2, // CHECK: %{{[0-9]+}} = call <4 x i32> asm "ldi.w ${0:w},1", "=f,~{$1}" int b[8] = {0,1,2,3,4,5,6,7}; int main() diff --git a/test/CodeGen/mips-inline-asm.c b/test/CodeGen/mips-inline-asm.c new file mode 100644 index 000000000000..2cfa41c98de7 --- /dev/null +++ b/test/CodeGen/mips-inline-asm.c @@ -0,0 +1,19 @@ +// REQUIRES: mips-registered-target +// RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm -o - %s | FileCheck %s + +int data; + +void m () { + asm("lw $1, %0" :: "m"(data)); + // CHECK: call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* @data) +} + +void ZC () { + asm("ll $1, %0" :: "ZC"(data)); + // CHECK: call void asm sideeffect "ll $$1, $0", "*^ZC,~{$1}"(i32* @data) +} + +void R () { + asm("lw $1, %0" :: "R"(data)); + // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data) +} diff --git a/test/CodeGen/mips-unsigned-ext-var.c b/test/CodeGen/mips-unsigned-ext-var.c new file mode 100644 index 000000000000..2e04792cf375 --- /dev/null +++ b/test/CodeGen/mips-unsigned-ext-var.c @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 -triple mips64-unknown-linux -O2 -target-abi n64 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=N64 +// RUN: %clang_cc1 -triple mips64-unknown-linux -O2 -target-abi n32 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=N32 +// RUN: %clang_cc1 -triple mips-unknown-linux -O2 -target-abi o32 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=O32 + +#include <stdarg.h> + +unsigned foo(int x, ...) { + va_list valist; + va_start(valist, x); + unsigned a; + a = va_arg(valist, unsigned); + return a; +} + +void foo1() { + unsigned f = 0xffffffe0; + foo(1,f); +} + +//N64: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32) +//N32: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32) +//O32: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32)
\ No newline at end of file diff --git a/test/CodeGen/mips-unsigned-extend.c b/test/CodeGen/mips-unsigned-extend.c new file mode 100644 index 000000000000..039d3800667e --- /dev/null +++ b/test/CodeGen/mips-unsigned-extend.c @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -triple mips64-unknown-linux -O0 -target-abi n64 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=N64 +// RUN: %clang_cc1 -triple mips64-unknown-linux -O0 -target-abi n32 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=N32 +// RUN: %clang_cc1 -triple mips-unknown-linux -O0 -target-abi o32 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=O32 + +void foo(unsigned a) { +} + +void foo1() { + unsigned f = 0xffffffe0; + foo(f); +} + +// N64: call void @foo(i32 signext %{{[0-9]+}}) +// N32: call void @foo(i32 signext %{{[0-9]+}}) +// O32: call void @foo(i32 signext %{{[0-9]+}}) diff --git a/test/CodeGen/mips-unsupported-nan.c b/test/CodeGen/mips-unsupported-nan.c new file mode 100644 index 000000000000..14a36fc0294a --- /dev/null +++ b/test/CodeGen/mips-unsupported-nan.c @@ -0,0 +1,25 @@ +// RUN: %clang -target mipsel-unknown-linux -mnan=2008 -march=mips2 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS2 -check-prefix=CHECK-NANLEGACY %s +// RUN: %clang -target mips64el-unknown-linux -mnan=2008 -march=mips3 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS3 -check-prefix=CHECK-NANLEGACY %s +// RUN: %clang -target mips64el-unknown-linux -mnan=2008 -march=mips4 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS4 -check-prefix=CHECK-NANLEGACY %s +// RUN: %clang -target mipsel-unknown-linux -mnan=2008 -march=mips32 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS32 -check-prefix=CHECK-NANLEGACY %s +// RUN: %clang -target mipsel-unknown-linux -mnan=2008 -march=mips32r2 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS32R2 -check-prefix=CHECK-NANLEGACY %s +// RUN: %clang -target mipsel-unknown-linux -mnan=2008 -march=mips32r3 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-NOT-MIPS32R3 -check-prefix=CHECK-NAN2008 %s +// RUN: %clang -target mipsel-unknown-linux -mnan=legacy -march=mips32r6 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS32R6 -check-prefix=CHECK-NAN2008 %s +// RUN: %clang -target mips64el-unknown-linux -mnan=2008 -march=mips64 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS64 -check-prefix=CHECK-NANLEGACY %s +// RUN: %clang -target mips64el-unknown-linux -mnan=2008 -march=mips64r2 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS64R2 -check-prefix=CHECK-NANLEGACY %s +// RUN: %clang -target mips64el-unknown-linux -mnan=legacy -march=mips64r6 -emit-llvm -S %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MIPS64R6 -check-prefix=CHECK-NAN2008 %s + +// CHECK-MIPS2: warning: ignoring '-mnan=2008' option because the 'mips2' architecture does not support it +// CHECK-MIPS3: warning: ignoring '-mnan=2008' option because the 'mips3' architecture does not support it +// CHECK-MIPS4: warning: ignoring '-mnan=2008' option because the 'mips4' architecture does not support it +// CHECK-MIPS32: warning: ignoring '-mnan=2008' option because the 'mips32' architecture does not support it +// CHECK-MIPS32R2: warning: ignoring '-mnan=2008' option because the 'mips32r2' architecture does not support it +// CHECK-MIPS32R3: warning: ignoring '-mnan=2008' option because the 'mips32r3' architecture does not support it +// CHECK-MIPS32R6: warning: ignoring '-mnan=legacy' option because the 'mips32r6' architecture does not support it +// CHECK-MIPS64: warning: ignoring '-mnan=2008' option because the 'mips64' architecture does not support it +// CHECK-MIPS64R2: warning: ignoring '-mnan=2008' option because the 'mips64r2' architecture does not support it +// CHECK-MIPS64R6: warning: ignoring '-mnan=legacy' option because the 'mips64r6' architecture does not support it +// CHECK-NANLEGACY: float 0x7FF4000000000000 +// CHECK-NAN2008: float 0x7FF8000000000000 + +float f = __builtin_nan(""); diff --git a/test/CodeGen/mips-varargs.c b/test/CodeGen/mips-varargs.c index 383831f2e824..8fd1df60b728 100644 --- a/test/CodeGen/mips-varargs.c +++ b/test/CodeGen/mips-varargs.c @@ -29,18 +29,18 @@ int test_i32(char *fmt, ...) { // ALL: call void @llvm.va_start(i8* [[VA1]]) // // O32: [[TMP0:%.+]] = bitcast i8** %va to i32** -// O32: [[AP_CUR:%.+]] = load i32** [[TMP0]], align [[PTRALIGN]] +// O32: [[AP_CUR:%.+]] = load i32*, i32** [[TMP0]], align [[PTRALIGN]] // NEW: [[TMP0:%.+]] = bitcast i8** %va to i64** -// NEW: [[AP_CUR:%.+]] = load i64** [[TMP0]], align [[PTRALIGN]] +// NEW: [[AP_CUR:%.+]] = load i64*, i64** [[TMP0]], align [[PTRALIGN]] // -// O32: [[AP_NEXT:%.+]] = getelementptr i32* [[AP_CUR]], i32 1 -// NEW: [[AP_NEXT:%.+]] = getelementptr i64* [[AP_CUR]], {{i32|i64}} 1 +// O32: [[AP_NEXT:%.+]] = getelementptr i32, i32* [[AP_CUR]], i32 1 +// NEW: [[AP_NEXT:%.+]] = getelementptr i64, i64* [[AP_CUR]], {{i32|i64}} 1 // // O32: store i32* [[AP_NEXT]], i32** [[TMP0]], align [[PTRALIGN]] // NEW: store i64* [[AP_NEXT]], i64** [[TMP0]], align [[PTRALIGN]] // -// O32: [[ARG1:%.+]] = load i32* [[AP_CUR]], align 4 -// NEW: [[TMP2:%.+]] = load i64* [[AP_CUR]], align 8 +// O32: [[ARG1:%.+]] = load i32, i32* [[AP_CUR]], align 4 +// NEW: [[TMP2:%.+]] = load i64, i64* [[AP_CUR]], align 8 // NEW: [[ARG1:%.+]] = trunc i64 [[TMP2]] to i32 // // ALL: call void @llvm.va_end(i8* [[VA1]]) @@ -65,29 +65,29 @@ int test_i32_2args(char *fmt, ...) { // ALL: call void @llvm.va_start(i8* [[VA1]]) // // O32: [[TMP0:%.+]] = bitcast i8** %va to i32** -// O32: [[AP_CUR:%.+]] = load i32** [[TMP0]], align [[PTRALIGN]] +// O32: [[AP_CUR:%.+]] = load i32*, i32** [[TMP0]], align [[PTRALIGN]] // NEW: [[TMP0:%.+]] = bitcast i8** %va to i64** -// NEW: [[AP_CUR:%.+]] = load i64** [[TMP0]], align [[PTRALIGN]] +// NEW: [[AP_CUR:%.+]] = load i64*, i64** [[TMP0]], align [[PTRALIGN]] // -// O32: [[AP_NEXT1:%.+]] = getelementptr i32* [[AP_CUR]], i32 1 -// NEW: [[AP_NEXT1:%.+]] = getelementptr i64* [[AP_CUR]], [[INTPTR_T:i32|i64]] 1 +// O32: [[AP_NEXT1:%.+]] = getelementptr i32, i32* [[AP_CUR]], i32 1 +// NEW: [[AP_NEXT1:%.+]] = getelementptr i64, i64* [[AP_CUR]], [[INTPTR_T:i32|i64]] 1 // // O32: store i32* [[AP_NEXT1]], i32** [[TMP0]], align [[PTRALIGN]] // FIXME: N32 optimised this store out. Why only for this ABI? // N64: store i64* [[AP_NEXT1]], i64** [[TMP0]], align [[PTRALIGN]] // -// O32: [[ARG1:%.+]] = load i32* [[AP_CUR]], align 4 -// NEW: [[TMP3:%.+]] = load i64* [[AP_CUR]], align 8 +// O32: [[ARG1:%.+]] = load i32, i32* [[AP_CUR]], align 4 +// NEW: [[TMP3:%.+]] = load i64, i64* [[AP_CUR]], align 8 // NEW: [[ARG1:%.+]] = trunc i64 [[TMP3]] to i32 // -// O32: [[AP_NEXT2:%.+]] = getelementptr i32* [[AP_CUR]], i32 2 -// NEW: [[AP_NEXT2:%.+]] = getelementptr i64* [[AP_CUR]], [[INTPTR_T]] 2 +// O32: [[AP_NEXT2:%.+]] = getelementptr i32, i32* [[AP_CUR]], i32 2 +// NEW: [[AP_NEXT2:%.+]] = getelementptr i64, i64* [[AP_CUR]], [[INTPTR_T]] 2 // // O32: store i32* [[AP_NEXT2]], i32** [[TMP0]], align [[PTRALIGN]] // NEW: store i64* [[AP_NEXT2]], i64** [[TMP0]], align [[PTRALIGN]] // -// O32: [[ARG2:%.+]] = load i32* [[AP_NEXT1]], align 4 -// NEW: [[TMP4:%.+]] = load i64* [[AP_NEXT1]], align 8 +// O32: [[ARG2:%.+]] = load i32, i32* [[AP_NEXT1]], align 4 +// NEW: [[TMP4:%.+]] = load i64, i64* [[AP_NEXT1]], align 8 // NEW: [[ARG2:%.+]] = trunc i64 [[TMP4]] to i32 // // ALL: call void @llvm.va_end(i8* [[VA1]]) @@ -111,9 +111,9 @@ long long test_i64(char *fmt, ...) { // ALL: [[VA1:%.+]] = bitcast i8** %va to i8* // ALL: call void @llvm.va_start(i8* [[VA1]]) // -// O32: [[AP_CUR:%.+]] = load i8** %va, align [[PTRALIGN]] +// O32: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]] // NEW: [[TMP0:%.+]] = bitcast i8** %va to i64** -// NEW: [[AP_CUR:%.+]] = load i64** [[TMP0]], align [[PTRALIGN]] +// NEW: [[AP_CUR:%.+]] = load i64*, i64** [[TMP0]], align [[PTRALIGN]] // // i64 is 8-byte aligned, while this is within O32's stack alignment there's no // guarantee that the offset is still 8-byte aligned after earlier reads. @@ -123,14 +123,14 @@ long long test_i64(char *fmt, ...) { // O32: [[PTR3:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i64* // O32: [[PTR4:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i8* // -// O32: [[AP_NEXT:%.+]] = getelementptr i8* [[PTR4]], [[INTPTR_T]] 8 -// NEW: [[AP_NEXT:%.+]] = getelementptr i64* [[AP_CUR]], [[INTPTR_T:i32|i64]] 1 +// O32: [[AP_NEXT:%.+]] = getelementptr i8, i8* [[PTR4]], [[INTPTR_T]] 8 +// NEW: [[AP_NEXT:%.+]] = getelementptr i64, i64* [[AP_CUR]], [[INTPTR_T:i32|i64]] 1 // // O32: store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]] // NEW: store i64* [[AP_NEXT]], i64** [[TMP0]], align [[PTRALIGN]] // -// O32: [[ARG1:%.+]] = load i64* [[PTR3]], align 8 -// NEW: [[ARG1:%.+]] = load i64* [[AP_CUR]], align 8 +// O32: [[ARG1:%.+]] = load i64, i64* [[PTR3]], align 8 +// NEW: [[ARG1:%.+]] = load i64, i64* [[AP_CUR]], align 8 // // ALL: call void @llvm.va_end(i8* [[VA1]]) // ALL: ret i64 [[ARG1]] @@ -156,30 +156,30 @@ char *test_ptr(char *fmt, ...) { // ALL: call void @llvm.va_start(i8* [[VA1]]) // // O32: [[TMP0:%.+]] = bitcast i8** %va to i8*** -// O32: [[AP_CUR:%.+]] = load i8*** [[TMP0]], align [[PTRALIGN]] +// O32: [[AP_CUR:%.+]] = load i8**, i8*** [[TMP0]], align [[PTRALIGN]] // N32 differs because the vararg is not a N32 pointer. It's been promoted to 64-bit. // N32: [[TMP0:%.+]] = bitcast i8** %va to i64** -// N32: [[AP_CUR:%.+]] = load i64** [[TMP0]], align [[PTRALIGN]] +// N32: [[AP_CUR:%.+]] = load i64*, i64** [[TMP0]], align [[PTRALIGN]] // N64: [[TMP0:%.+]] = bitcast i8** %va to i8*** -// N64: [[AP_CUR:%.+]] = load i8*** [[TMP0]], align [[PTRALIGN]] +// N64: [[AP_CUR:%.+]] = load i8**, i8*** [[TMP0]], align [[PTRALIGN]] // -// O32: [[AP_NEXT:%.+]] = getelementptr i8** [[AP_CUR]], i32 1 +// O32: [[AP_NEXT:%.+]] = getelementptr i8*, i8** [[AP_CUR]], i32 1 // N32 differs because the vararg is not a N32 pointer. It's been promoted to 64-bit. -// N32: [[AP_NEXT:%.+]] = getelementptr i64* [[AP_CUR]], {{i32|i64}} 1 -// N64: [[AP_NEXT:%.+]] = getelementptr i8** [[AP_CUR]], {{i32|i64}} 1 +// N32: [[AP_NEXT:%.+]] = getelementptr i64, i64* [[AP_CUR]], {{i32|i64}} 1 +// N64: [[AP_NEXT:%.+]] = getelementptr i8*, i8** [[AP_CUR]], {{i32|i64}} 1 // // O32: store i8** [[AP_NEXT]], i8*** [[TMP0]], align [[PTRALIGN]] // N32 differs because the vararg is not a N32 pointer. It's been promoted to 64-bit. // N32: store i64* [[AP_NEXT]], i64** [[TMP0]], align [[PTRALIGN]] // N64: store i8** [[AP_NEXT]], i8*** [[TMP0]], align [[PTRALIGN]] // -// O32: [[ARG1:%.+]] = load i8** [[AP_CUR]], align 4 +// O32: [[ARG1:%.+]] = load i8*, i8** [[AP_CUR]], align 4 // N32 differs because the vararg is not a N32 pointer. It's been promoted to // 64-bit so we must truncate the excess and bitcast to a N32 pointer. -// N32: [[TMP2:%.+]] = load i64* [[AP_CUR]], align 8 +// N32: [[TMP2:%.+]] = load i64, i64* [[AP_CUR]], align 8 // N32: [[TMP3:%.+]] = trunc i64 [[TMP2]] to i32 // N32: [[ARG1:%.+]] = inttoptr i32 [[TMP3]] to i8* -// N64: [[ARG1:%.+]] = load i8** [[AP_CUR]], align 8 +// N64: [[ARG1:%.+]] = load i8*, i8** [[AP_CUR]], align 8 // // ALL: call void @llvm.va_end(i8* [[VA1]]) // ALL: ret i8* [[ARG1]] @@ -200,7 +200,7 @@ int test_v4i32(char *fmt, ...) { // ALL: %va = alloca i8*, align [[PTRALIGN]] // ALL: [[VA1:%.+]] = bitcast i8** %va to i8* // ALL: call void @llvm.va_start(i8* [[VA1]]) -// ALL: [[AP_CUR:%.+]] = load i8** %va, align [[PTRALIGN]] +// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]] // // O32: [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]] // N32: [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]] @@ -216,9 +216,9 @@ int test_v4i32(char *fmt, ...) { // // ALL: [[PTR3:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to <4 x i32>* // ALL: [[PTR4:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i8* -// ALL: [[AP_NEXT:%.+]] = getelementptr i8* [[PTR4]], [[INTPTR_T]] 16 +// ALL: [[AP_NEXT:%.+]] = getelementptr i8, i8* [[PTR4]], [[INTPTR_T]] 16 // ALL: store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]] -// ALL: [[PTR5:%.+]] = load <4 x i32>* [[PTR3]], align 16 +// ALL: [[PTR5:%.+]] = load <4 x i32>, <4 x i32>* [[PTR3]], align 16 // ALL: call void @llvm.va_end(i8* [[VA1]]) // ALL: [[VECEXT:%.+]] = extractelement <4 x i32> [[PTR5]], i32 0 // ALL: ret i32 [[VECEXT]] diff --git a/test/CodeGen/mrtd.c b/test/CodeGen/mrtd.c index f929d4c26b28..8d2aeeec49df 100644 --- a/test/CodeGen/mrtd.c +++ b/test/CodeGen/mrtd.c @@ -23,6 +23,6 @@ void quux(int a1, int a2, int a3) { qux(a1, a2, a3); } // CHECK-LABEL: define x86_stdcallcc void @quux -// CHECK: call void (i32, ...)* @qux +// CHECK: call void (i32, ...) @qux // CHECK: attributes [[NUW]] = { nounwind{{.*}} } diff --git a/test/CodeGen/ms-align-tentative.c b/test/CodeGen/ms-align-tentative.c index ccd761616471..eb68e69f586b 100644 --- a/test/CodeGen/ms-align-tentative.c +++ b/test/CodeGen/ms-align-tentative.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple i386-pc-win32 %s -emit-llvm -fms-compatibility -o - | FileCheck %s +// RUN: %clang_cc1 -triple i386-pc-win32 -emit-llvm -fms-compatibility -o - < %s | FileCheck %s char __declspec(align(8192)) x; // CHECK-DAG: @x = global i8 0, align 8192 @@ -13,3 +13,13 @@ T __declspec(align(8192)) z; int __declspec(align(16)) redef; int __declspec(align(32)) redef = 8; // CHECK-DAG: @redef = global i32 8, align 32 + +struct __declspec(align(64)) S { + char fd; +} s; +// CHECK-DAG: @s = global %struct.S zeroinitializer, align 64 + +struct Wrap { + struct S x; +} w; +// CHECK-DAG: @w = global %struct.Wrap zeroinitializer, align 64 diff --git a/test/CodeGen/ms-anonymous-struct.c b/test/CodeGen/ms-anonymous-struct.c index b41caab0309e..bf33406d779c 100644 --- a/test/CodeGen/ms-anonymous-struct.c +++ b/test/CodeGen/ms-anonymous-struct.c @@ -26,34 +26,34 @@ void foo() // CHECK: %var = alloca %struct.test, align 4 struct test var; - // CHECK: getelementptr inbounds %struct.test* %var, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 0 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK: getelementptr inbounds %struct.test, %struct.test* %var, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 0 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var.a; - // CHECK-NEXT: getelementptr inbounds %struct.test* %var, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 2 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %var, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 2 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var.b; - // CHECK-NEXT: getelementptr inbounds %struct.test* %var, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested1* %{{.*}}, i32 0, i32 0 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %var, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested1, %struct.nested1* %{{.*}}, i32 0, i32 0 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var.a1; - // CHECK-NEXT: getelementptr inbounds %struct.test* %{{.*}}var, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested1* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %{{.*}}var, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested1, %struct.nested1* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var.b1; - // CHECK-NEXT: getelementptr inbounds %struct.test* %var, i32 0, i32 0 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %var, i32 0, i32 0 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var.x; - // CHECK-NEXT: getelementptr inbounds %struct.test* %var, i32 0, i32 2 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %var, i32 0, i32 2 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var.y; } @@ -61,39 +61,39 @@ void foo2(struct test* var) { // CHECK: alloca %struct.test*, align // CHECK-NEXT: store %struct.test* %var, %struct.test** %{{.*}}, align - // CHECK-NEXT: load %struct.test** %{{.*}}, align - // CHECK-NEXT: getelementptr inbounds %struct.test* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 0 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: load %struct.test*, %struct.test** %{{.*}}, align + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 0 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var->a; - // CHECK-NEXT: load %struct.test** %{{.*}}, align - // CHECK-NEXT: getelementptr inbounds %struct.test* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 2 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: load %struct.test*, %struct.test** %{{.*}}, align + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 2 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var->b; - // CHECK-NEXT: load %struct.test** %{{.*}}, align - // CHECK-NEXT: getelementptr inbounds %struct.test* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested1* %{{.*}}, i32 0, i32 0 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: load %struct.test*, %struct.test** %{{.*}}, align + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested1, %struct.nested1* %{{.*}}, i32 0, i32 0 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var->a1; - // CHECK-NEXT: load %struct.test** %{{.*}}, align - // CHECK-NEXT: getelementptr inbounds %struct.test* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested2* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: getelementptr inbounds %struct.nested1* %{{.*}}, i32 0, i32 1 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: load %struct.test*, %struct.test** %{{.*}}, align + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested2, %struct.nested2* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: getelementptr inbounds %struct.nested1, %struct.nested1* %{{.*}}, i32 0, i32 1 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var->b1; - // CHECK-NEXT: load %struct.test** %{{.*}}, align - // CHECK-NEXT: getelementptr inbounds %struct.test* %{{.*}}, i32 0, i32 0 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: load %struct.test*, %struct.test** %{{.*}}, align + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %{{.*}}, i32 0, i32 0 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var->x; - // CHECK-NEXT: load %struct.test** %{{.*}}, align - // CHECK-NEXT: getelementptr inbounds %struct.test* %{{.*}}, i32 0, i32 2 - // CHECK-NEXT: load i32* %{{.*}}, align 4 + // CHECK-NEXT: load %struct.test*, %struct.test** %{{.*}}, align + // CHECK-NEXT: getelementptr inbounds %struct.test, %struct.test* %{{.*}}, i32 0, i32 2 + // CHECK-NEXT: load i32, i32* %{{.*}}, align 4 var->y; } diff --git a/test/CodeGen/ms-declspecs.c b/test/CodeGen/ms-declspecs.c index 5dc7787b8fb9..c32733e65ff6 100644 --- a/test/CodeGen/ms-declspecs.c +++ b/test/CodeGen/ms-declspecs.c @@ -2,8 +2,14 @@ __declspec(selectany) int x1 = 1; const __declspec(selectany) int x2 = 2; -// CHECK: @x1 = weak_odr global i32 1, align 4 -// CHECK: @x2 = weak_odr constant i32 2, align 4 +// CHECK: @x1 = weak_odr global i32 1, comdat, align 4 +// CHECK: @x2 = weak_odr constant i32 2, comdat, align 4 + +// selectany turns extern variable declarations into definitions. +__declspec(selectany) int x3; +extern __declspec(selectany) int x4; +// CHECK: @x3 = weak_odr global i32 0, comdat, align 4 +// CHECK: @x4 = weak_odr global i32 0, comdat, align 4 struct __declspec(align(16)) S { char x; diff --git a/test/CodeGen/ms-declspecs.cpp b/test/CodeGen/ms-declspecs.cpp new file mode 100644 index 000000000000..decf5d6fcb22 --- /dev/null +++ b/test/CodeGen/ms-declspecs.cpp @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -triple i386-pc-win32 %s -emit-llvm -fms-compatibility -o - | FileCheck %s + +// selectany turns extern "C" variable declarations into definitions. +extern __declspec(selectany) int x1; +extern "C" __declspec(selectany) int x2; +extern "C++" __declspec(selectany) int x3; +extern "C" { +__declspec(selectany) int x4; +} +__declspec(selectany) int x5; +// CHECK: @"\01?x1@@3HA" = weak_odr global i32 0, comdat, align 4 +// CHECK: @x2 = weak_odr global i32 0, comdat, align 4 +// CHECK: @"\01?x3@@3HA" = weak_odr global i32 0, comdat, align 4 +// CHECK: @x4 = weak_odr global i32 0, comdat, align 4 +// CHECK: @"\01?x5@@3HA" = weak_odr global i32 0, comdat, align 4 diff --git a/test/CodeGen/ms-inline-asm.c b/test/CodeGen/ms-inline-asm.c index 59ff2023a465..a6f1b71b392b 100644 --- a/test/CodeGen/ms-inline-asm.c +++ b/test/CodeGen/ms-inline-asm.c @@ -93,7 +93,7 @@ unsigned t10(void) { // CHECK: [[J:%[a-zA-Z0-9]+]] = alloca i32, align 4 // CHECK: store i32 1, i32* [[I]], align 4 // CHECK: call i32 asm sideeffect inteldialect "mov eax, dword ptr $2\0A\09mov dword ptr $0, eax", "=*m,={eax},*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}) -// CHECK: [[RET:%[a-zA-Z0-9]+]] = load i32* [[J]], align 4 +// CHECK: [[RET:%[a-zA-Z0-9]+]] = load i32, i32* [[J]], align 4 // CHECK: ret i32 [[RET]] } diff --git a/test/CodeGen/ms-inline-asm.cpp b/test/CodeGen/ms-inline-asm.cpp index 03d971e698b5..123a0e3d6d3d 100644 --- a/test/CodeGen/ms-inline-asm.cpp +++ b/test/CodeGen/ms-inline-asm.cpp @@ -63,8 +63,8 @@ struct T4 { // CHECK-LABEL: define void @_ZN2T44testEv( void T4::test() { // CHECK: [[T0:%.*]] = alloca [[T4:%.*]]*, -// CHECK: [[THIS:%.*]] = load [[T4]]** [[T0]] -// CHECK: [[X:%.*]] = getelementptr inbounds [[T4]]* [[THIS]], i32 0, i32 0 +// CHECK: [[THIS:%.*]] = load [[T4]]*, [[T4]]** [[T0]] +// CHECK: [[X:%.*]] = getelementptr inbounds [[T4]], [[T4]]* [[THIS]], i32 0, i32 0 __asm mov eax, x; __asm mov y, eax; // CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $1\0A\09mov dword ptr $0, eax", "=*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* @_ZN2T41yE, i32* {{.*}}) diff --git a/test/CodeGen/ms-intrinsics.c b/test/CodeGen/ms-intrinsics.c index 4498b34bc48d..9103622197a9 100644 --- a/test/CodeGen/ms-intrinsics.c +++ b/test/CodeGen/ms-intrinsics.c @@ -57,7 +57,7 @@ long test__readfsdword(unsigned long Offset) { // CHECK-I386: define i32 @test__readfsdword(i32 %Offset){{.*}}{ // CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %Offset to i32 addrspace(257)* -// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i32 addrspace(257)* [[PTR]], align 4 +// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i32, i32 addrspace(257)* [[PTR]], align 4 // CHECK-I386: ret i32 [[VALUE:%[0-9]+]] // CHECK-I386: } #endif diff --git a/test/CodeGen/ms-setjmp.c b/test/CodeGen/ms-setjmp.c new file mode 100644 index 000000000000..675c8dda27de --- /dev/null +++ b/test/CodeGen/ms-setjmp.c @@ -0,0 +1,32 @@ +// RUN: %clang_cc1 -fms-extensions -DDECLARE_SETJMP -triple i686-windows-msvc -emit-llvm %s -o - | FileCheck --check-prefix=I386 %s +// RUN: %clang_cc1 -fms-extensions -DDECLARE_SETJMP -triple x86_64-windows-msvc -emit-llvm %s -o - | FileCheck --check-prefix=X64 %s +// RUN: %clang_cc1 -fms-extensions -triple i686-windows-msvc -emit-llvm %s -o - | FileCheck --check-prefix=I386 %s +// RUN: %clang_cc1 -fms-extensions -triple x86_64-windows-msvc -emit-llvm %s -o - | FileCheck --check-prefix=X64 %s +typedef char jmp_buf[1]; + +#ifdef DECLARE_SETJMP +int _setjmp(jmp_buf env); +int _setjmpex(jmp_buf env); +#endif + +jmp_buf jb; + +int test_setjmp() { + return _setjmp(jb); + // I386-LABEL: define i32 @test_setjmp + // I386: %[[call:.*]] = call i32 (i8*, i32, ...) @_setjmp3(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i32 0) + // I386-NEXT: ret i32 %[[call]] + + // X64-LABEL: define i32 @test_setjmp + // X64: %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0) + // X64: %[[call:.*]] = call i32 @_setjmp(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]]) + // X64-NEXT: ret i32 %[[call]] +} + +int test_setjmpex() { + return _setjmpex(jb); + // X64-LABEL: define i32 @test_setjmpex + // X64: %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0) + // X64: %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]]) + // X64-NEXT: ret i32 %[[call]] +} diff --git a/test/CodeGen/ms-volatile.c b/test/CodeGen/ms-volatile.c new file mode 100644 index 000000000000..87393e794f82 --- /dev/null +++ b/test/CodeGen/ms-volatile.c @@ -0,0 +1,62 @@ +// RUN: %clang_cc1 -triple i386-pc-win32 -fms-extensions -emit-llvm -fms-volatile -o - < %s | FileCheck %s +struct foo { + volatile int x; +}; +struct bar { + int x; +}; +typedef _Complex float __declspec(align(8)) baz; + +void test1(struct foo *p, struct foo *q) { + *p = *q; + // CHECK-LABEL: @test1 + // CHECK: load atomic volatile {{.*}} acquire + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} +void test2(volatile int *p, volatile int *q) { + *p = *q; + // CHECK-LABEL: @test2 + // CHECK: load atomic volatile {{.*}} acquire + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} +void test3(struct foo *p, struct foo *q) { + p->x = q->x; + // CHECK-LABEL: @test3 + // CHECK: load atomic volatile {{.*}} acquire + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} +void test4(volatile struct foo *p, volatile struct foo *q) { + p->x = q->x; + // CHECK-LABEL: @test4 + // CHECK: load atomic volatile {{.*}} acquire + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} +void test5(volatile struct foo *p, volatile struct foo *q) { + *p = *q; + // CHECK-LABEL: @test5 + // CHECK: load atomic volatile {{.*}} acquire + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} +void test6(struct bar *p, struct bar *q) { + *p = *q; + // CHECK-LABEL: @test6 + // CHECK-NOT: load atomic volatile {{.*}} + // CHECK-NOT: store atomic volatile {{.*}}, {{.*}} +} +void test7(volatile struct bar *p, volatile struct bar *q) { + *p = *q; + // CHECK-LABEL: @test7 + // CHECK: load atomic volatile {{.*}} acquire + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} +void test8(volatile double *p, volatile double *q) { + *p = *q; + // CHECK-LABEL: @test8 + // CHECK: load atomic volatile {{.*}} acquire + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} +void test9(volatile baz *p, baz *q) { + *p = *q; + // CHECK-LABEL: @test9 + // CHECK: store atomic volatile {{.*}}, {{.*}} release +} diff --git a/test/CodeGen/mult-alt-generic.c b/test/CodeGen/mult-alt-generic.c index 303edfcf3c42..6e7b11efe162 100644 --- a/test/CodeGen/mult-alt-generic.c +++ b/test/CodeGen/mult-alt-generic.c @@ -130,7 +130,7 @@ void single_X() asm("foo %1,%0" : "=r" (out0) : "X" (min1)); // CHECK: call i32 asm "foo $1,$0", "=r,X[[CLOBBERS]](i32 1) asm("foo %1,%0" : "=r" (out0) : "X" (1)); - // CHECK: call i32 asm "foo $1,$0", "=r,X[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) + // CHECK: call i32 asm "foo $1,$0", "=r,X[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32], [2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) asm("foo %1,%0" : "=r" (out0) : "X" (marray)); // CHECK: call i32 asm "foo $1,$0", "=r,X[[CLOBBERS]](double {{[0-9.eE+-]+}}) asm("foo %1,%0" : "=r" (out0) : "X" (1.0e+01)); @@ -143,7 +143,7 @@ void single_p() { register int out0 = 0; // Constraint converted differently on different platforms moved to platform-specific. - // : call i32 asm "foo $1,$0", "=r,im[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) + // : call i32 asm "foo $1,$0", "=r,im[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32], [2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) asm("foo %1,%0" : "=r" (out0) : "p" (marray)); } @@ -263,7 +263,7 @@ void multi_X() asm("foo %1,%0" : "=r,r" (out0) : "r,X" (min1)); // CHECK: call i32 asm "foo $1,$0", "=r|r,r|X[[CLOBBERS]](i32 1) asm("foo %1,%0" : "=r,r" (out0) : "r,X" (1)); - // CHECK: call i32 asm "foo $1,$0", "=r|r,r|X[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) + // CHECK: call i32 asm "foo $1,$0", "=r|r,r|X[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32], [2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) asm("foo %1,%0" : "=r,r" (out0) : "r,X" (marray)); // CHECK: call i32 asm "foo $1,$0", "=r|r,r|X[[CLOBBERS]](double {{[0-9.eE+-]+}}) asm("foo %1,%0" : "=r,r" (out0) : "r,X" (1.0e+01)); @@ -276,6 +276,6 @@ void multi_p() { register int out0 = 0; // Constraint converted differently on different platforms moved to platform-specific. - // : call i32 asm "foo $1,$0", "=r|r,r|im[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) + // : call i32 asm "foo $1,$0", "=r|r,r|im[[CLOBBERS]](i32* getelementptr inbounds ([2 x i32], [2 x i32]* {{[a-zA-Z0-9@%]+}}, i32 0, i32 0)) asm("foo %1,%0" : "=r,r" (out0) : "r,p" (marray)); } diff --git a/test/CodeGen/named_reg_global.c b/test/CodeGen/named_reg_global.c index d888a3ff1733..8f9a9c685d1f 100644 --- a/test/CodeGen/named_reg_global.c +++ b/test/CodeGen/named_reg_global.c @@ -21,7 +21,7 @@ unsigned long get_stack_pointer_addr() { // CHECK: declare{{.*}} i[[bits]] @llvm.read_register.i[[bits]](metadata) // CHECK: define{{.*}} void @set_stack_pointer_addr(i[[bits]] %addr) #0 { -// CHECK: [[sto:%[0-9]+]] = load i[[bits]]* % +// CHECK: [[sto:%[0-9]+]] = load i[[bits]], i[[bits]]* % // CHECK: call void @llvm.write_register.i[[bits]](metadata !0, i[[bits]] [[sto]]) // CHECK: ret void void set_stack_pointer_addr(unsigned long addr) { diff --git a/test/CodeGen/no-opt-volatile-memcpy.c b/test/CodeGen/no-opt-volatile-memcpy.c index 718d704a3338..bf98df39af16 100644 --- a/test/CodeGen/no-opt-volatile-memcpy.c +++ b/test/CodeGen/no-opt-volatile-memcpy.c @@ -19,9 +19,9 @@ void foo (void) { // CHECK-NEXT: %[[ZERO:.*]] = bitcast %struct.s* %[[LS]] to i8* // CHECK-NEXT: %[[ONE:.*]] = bitcast %struct.s* %[[LS]] to i8* // CHECK-NEXT: call void @llvm.memcpy.{{.*}}(i8* %[[ZERO]], i8* %[[ONE]], i64 132, i32 4, i1 true) -// CHECK-NEXT: call void @llvm.memcpy.{{.*}}(i8* getelementptr inbounds (%struct.s* @gs, i32 0, i32 0, i32 0), i8* getelementptr inbounds (%struct.s* @gs, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) +// CHECK-NEXT: call void @llvm.memcpy.{{.*}}(i8* getelementptr inbounds (%struct.s, %struct.s* @gs, i32 0, i32 0, i32 0), i8* getelementptr inbounds (%struct.s, %struct.s* @gs, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) // CHECK-NEXT: %[[TWO:.*]] = bitcast %struct.s* %[[LS]] to i8* -// CHECK-NEXT: call void @llvm.memcpy.{{.*}}(i8* %[[TWO]], i8* getelementptr inbounds (%struct.s* @gs, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) +// CHECK-NEXT: call void @llvm.memcpy.{{.*}}(i8* %[[TWO]], i8* getelementptr inbounds (%struct.s, %struct.s* @gs, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) struct s1 { @@ -35,6 +35,6 @@ void fee (void) { s.y = gs; } // CHECK-LABEL: define void @fee() -// CHECK: call void @llvm.memcpy.{{.*}}(i8* getelementptr inbounds (%struct.s1* @s, i32 0, i32 0, i32 0, i32 0), i8* getelementptr inbounds (%struct.s1* @s, i32 0, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) -// CHECK-NEXT: call void @llvm.memcpy.{{.*}}(i8* getelementptr inbounds (%struct.s1* @s, i32 0, i32 0, i32 0, i32 0), i8* getelementptr inbounds (%struct.s* @gs, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) +// CHECK: call void @llvm.memcpy.{{.*}}(i8* getelementptr inbounds (%struct.s1, %struct.s1* @s, i32 0, i32 0, i32 0, i32 0), i8* getelementptr inbounds (%struct.s1, %struct.s1* @s, i32 0, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) +// CHECK-NEXT: call void @llvm.memcpy.{{.*}}(i8* getelementptr inbounds (%struct.s1, %struct.s1* @s, i32 0, i32 0, i32 0, i32 0), i8* getelementptr inbounds (%struct.s, %struct.s* @gs, i32 0, i32 0, i32 0), i64 132, i32 4, i1 true) diff --git a/test/CodeGen/nvptx-cpus.c b/test/CodeGen/nvptx-cpus.c index c9c7680d6734..015f52946ef7 100644 --- a/test/CodeGen/nvptx-cpus.c +++ b/test/CodeGen/nvptx-cpus.c @@ -2,6 +2,7 @@ // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_21 -O3 -S -o %t %s -emit-llvm // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_30 -O3 -S -o %t %s -emit-llvm // RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_35 -O3 -S -o %t %s -emit-llvm +// RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_37 -O3 -S -o %t %s -emit-llvm // Make sure clang accepts all supported architectures. diff --git a/test/CodeGen/object-size.c b/test/CodeGen/object-size.c index 5a4dc99f3658..3fa038a0943b 100644 --- a/test/CodeGen/object-size.c +++ b/test/CodeGen/object-size.c @@ -15,31 +15,31 @@ int gi, gj; // CHECK-LABEL: define void @test1 void test1() { - // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8]* @gbuf, i32 0, i64 4), i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i64 59) + // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8], [63 x i8]* @gbuf, i32 0, i64 4), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i64 59) strcpy(&gbuf[4], "Hi there"); } // CHECK-LABEL: define void @test2 void test2() { - // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8]* @gbuf, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i64 63) + // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8], [63 x i8]* @gbuf, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i64 63) strcpy(gbuf, "Hi there"); } // CHECK-LABEL: define void @test3 void test3() { - // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8]* @gbuf, i64 1, i64 37), i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i64 0) + // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8], [63 x i8]* @gbuf, i64 1, i64 37), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i64 0) strcpy(&gbuf[100], "Hi there"); } // CHECK-LABEL: define void @test4 void test4() { - // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8]* @gbuf, i32 0, i64 -1), i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i64 0) + // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8], [63 x i8]* @gbuf, i32 0, i64 -1), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i64 0) strcpy((char*)(void*)&gbuf[-1], "Hi there"); } // CHECK-LABEL: define void @test5 void test5() { - // CHECK: = load i8** @gp + // CHECK: = load i8*, i8** @gp // CHECK-NEXT:= call i64 @llvm.objectsize.i64.p0i8(i8* %{{.*}}, i1 false) strcpy(gp, "Hi there"); } @@ -48,7 +48,7 @@ void test5() { void test6() { char buf[57]; - // CHECK: = call i8* @__strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i64 53) + // CHECK: = call i8* @__strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i64 53) strcpy(&buf[4], "Hi there"); } @@ -58,7 +58,7 @@ void test7() { // Ensure we only evaluate the side-effect once. // CHECK: = add // CHECK-NOT: = add - // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8]* @gbuf, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i64 63) + // CHECK: = call i8* @__strcpy_chk(i8* getelementptr inbounds ([63 x i8], [63 x i8]* @gbuf, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i64 63) strcpy((++i, gbuf), "Hi there"); } @@ -66,14 +66,14 @@ void test7() { void test8() { char *buf[50]; // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(buf[++gi], "Hi there"); } // CHECK-LABEL: define void @test9 void test9() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy((char *)((++gi) + gj), "Hi there"); } @@ -81,49 +81,49 @@ void test9() { char **p; void test10() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(*(++p), "Hi there"); } // CHECK-LABEL: define void @test11 void test11() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* getelementptr inbounds ([63 x i8]* @gbuf, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* getelementptr inbounds ([63 x i8], [63 x i8]* @gbuf, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(gp = gbuf, "Hi there"); } // CHECK-LABEL: define void @test12 void test12() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(++gp, "Hi there"); } // CHECK-LABEL: define void @test13 void test13() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(gp++, "Hi there"); } // CHECK-LABEL: define void @test14 void test14() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(--gp, "Hi there"); } // CHECK-LABEL: define void @test15 void test15() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{..*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{..*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(gp--, "Hi there"); } // CHECK-LABEL: define void @test16 void test16() { // CHECK-NOT: __strcpy_chk - // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) + // CHECK: = call i8* @__inline_strcpy_chk(i8* %{{.*}}, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0)) strcpy(gp += 1, "Hi there"); } diff --git a/test/CodeGen/packed-arrays.c b/test/CodeGen/packed-arrays.c index 8e748dfcfce7..993d88e2772d 100644 --- a/test/CodeGen/packed-arrays.c +++ b/test/CodeGen/packed-arrays.c @@ -52,10 +52,10 @@ int align2_x0 = __alignof(((struct s2*) 0)->x[0]); int align3_x0 = __alignof(((struct s3*) 0)->x[0]); // CHECK-LABEL: define i32 @f0_a -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } // CHECK-LABEL: define i32 @f0_b -// CHECK: load i32* %{{.*}}, align 4 +// CHECK: load i32, i32* %{{.*}}, align 4 // CHECK: } int f0_a(struct s0 *a) { return a->x[1]; @@ -67,19 +67,19 @@ int f0_b(struct s0 *a) { // Note that we are incompatible with GCC on this example. // // CHECK-LABEL: define i32 @f1_a -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } // CHECK-LABEL: define i32 @f1_b -// CHECK: load i32* %{{.*}}, align 4 +// CHECK: load i32, i32* %{{.*}}, align 4 // CHECK: } // Note that we are incompatible with GCC on this example. // // CHECK-LABEL: define i32 @f1_c -// CHECK: load i32* %{{.*}}, align 4 +// CHECK: load i32, i32* %{{.*}}, align 4 // CHECK: } // CHECK-LABEL: define i32 @f1_d -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } int f1_a(struct s1 *a) { return a->x[1]; @@ -95,16 +95,16 @@ int f1_d(struct s1 *a) { } // CHECK-LABEL: define i32 @f2_a -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } // CHECK-LABEL: define i32 @f2_b -// CHECK: load i32* %{{.*}}, align 4 +// CHECK: load i32, i32* %{{.*}}, align 4 // CHECK: } // CHECK-LABEL: define i32 @f2_c -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } // CHECK-LABEL: define i32 @f2_d -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } int f2_a(struct s2 *a) { return a->x[1]; @@ -120,16 +120,16 @@ int f2_d(struct s2 *a) { } // CHECK-LABEL: define i32 @f3_a -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } // CHECK-LABEL: define i32 @f3_b -// CHECK: load i32* %{{.*}}, align 4 +// CHECK: load i32, i32* %{{.*}}, align 4 // CHECK: } // CHECK-LABEL: define i32 @f3_c -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } // CHECK-LABEL: define i32 @f3_d -// CHECK: load i32* %{{.*}}, align 1 +// CHECK: load i32, i32* %{{.*}}, align 1 // CHECK: } int f3_a(struct s3 *a) { return a->x[1]; @@ -147,7 +147,7 @@ int f3_d(struct s3 *a) { // Verify we don't claim things are overaligned. // // CHECK-LABEL: define double @f4 -// CHECK: load double* {{.*}}, align 8 +// CHECK: load double, double* {{.*}}, align 8 // CHECK: } extern double g4[5] __attribute__((aligned(16))); double f4() { diff --git a/test/CodeGen/packed-nest-unpacked.c b/test/CodeGen/packed-nest-unpacked.c index ea45660b7a3c..1dcd2ec468d7 100644 --- a/test/CodeGen/packed-nest-unpacked.c +++ b/test/CodeGen/packed-nest-unpacked.c @@ -9,40 +9,40 @@ struct X foo(void); // <rdar://problem/10463337> struct X test1() { // CHECK: @test1 - // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y* @g, i32 0, i32 1) to i8*), i64 24, i32 1, i1 false) + // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y, %struct.Y* @g, i32 0, i32 1) to i8*), i64 24, i32 1, i1 false) return g.y; } struct X test2() { // CHECK: @test2 - // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y* @g, i32 0, i32 1) to i8*), i64 24, i32 1, i1 false) + // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y, %struct.Y* @g, i32 0, i32 1) to i8*), i64 24, i32 1, i1 false) struct X a = g.y; return a; } void test3(struct X a) { // CHECK: @test3 - // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y* @g, i32 0, i32 1) to i8*), i8* {{.*}}, i64 24, i32 1, i1 false) + // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y, %struct.Y* @g, i32 0, i32 1) to i8*), i8* {{.*}}, i64 24, i32 1, i1 false) g.y = a; } // <rdar://problem/10530444> void test4() { // CHECK: @test4 - // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y* @g, i32 0, i32 1) to i8*), i64 24, i32 1, i1 false) + // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y, %struct.Y* @g, i32 0, i32 1) to i8*), i64 24, i32 1, i1 false) f(g.y); } // PR12395 int test5() { // CHECK: @test5 - // CHECK: load i32* getelementptr inbounds (%struct.Y* @g, i32 0, i32 1, i32 0, i64 0), align 1 + // CHECK: load i32, i32* getelementptr inbounds (%struct.Y, %struct.Y* @g, i32 0, i32 1, i32 0, i64 0), align 1 return g.y.x[0]; } // <rdar://problem/11220251> void test6() { // CHECK: @test6 - // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y* @g, i32 0, i32 1) to i8*), i8* %{{.*}}, i64 24, i32 1, i1 false) + // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.X* getelementptr inbounds (%struct.Y, %struct.Y* @g, i32 0, i32 1) to i8*), i8* %{{.*}}, i64 24, i32 1, i1 false) g.y = foo(); } @@ -60,6 +60,6 @@ struct YBitfield gbitfield; unsigned test7() { // CHECK: @test7 - // CHECK: load i32* getelementptr inbounds (%struct.YBitfield* @gbitfield, i32 0, i32 1, i32 0), align 4 + // CHECK: load i32, i32* getelementptr inbounds (%struct.YBitfield, %struct.YBitfield* @gbitfield, i32 0, i32 1, i32 0), align 4 return gbitfield.y.b2; } diff --git a/test/CodeGen/packed-structure.c b/test/CodeGen/packed-structure.c index a915a544b9eb..8de31d6a81d0 100644 --- a/test/CodeGen/packed-structure.c +++ b/test/CodeGen/packed-structure.c @@ -17,7 +17,7 @@ int s0_align_y = __alignof(((struct s0*)0)->y); int s0_align = __alignof(struct s0); // CHECK-FUNCTIONS-LABEL: define i32 @s0_load_x -// CHECK-FUNCTIONS: [[s0_load_x:%.*]] = load i32* {{.*}}, align 4 +// CHECK-FUNCTIONS: [[s0_load_x:%.*]] = load i32, i32* {{.*}}, align 4 // CHECK-FUNCTIONS: ret i32 [[s0_load_x]] int s0_load_x(struct s0 *a) { return a->x; } // FIXME: This seems like it should be align 1. This is actually something which @@ -25,7 +25,7 @@ int s0_load_x(struct s0 *a) { return a->x; } // with align 1 (in 2363.1 at least). // // CHECK-FUNCTIONS-LABEL: define i32 @s0_load_y -// CHECK-FUNCTIONS: [[s0_load_y:%.*]] = load i32* {{.*}}, align 1 +// CHECK-FUNCTIONS: [[s0_load_y:%.*]] = load i32, i32* {{.*}}, align 1 // CHECK-FUNCTIONS: ret i32 [[s0_load_y]] int s0_load_y(struct s0 *a) { return a->y; } // CHECK-FUNCTIONS-LABEL: define void @s0_copy @@ -47,11 +47,11 @@ int s1_align_y = __alignof(((struct s1*)0)->y); int s1_align = __alignof(struct s1); // CHECK-FUNCTIONS-LABEL: define i32 @s1_load_x -// CHECK-FUNCTIONS: [[s1_load_x:%.*]] = load i32* {{.*}}, align 1 +// CHECK-FUNCTIONS: [[s1_load_x:%.*]] = load i32, i32* {{.*}}, align 1 // CHECK-FUNCTIONS: ret i32 [[s1_load_x]] int s1_load_x(struct s1 *a) { return a->x; } // CHECK-FUNCTIONS-LABEL: define i32 @s1_load_y -// CHECK-FUNCTIONS: [[s1_load_y:%.*]] = load i32* {{.*}}, align 1 +// CHECK-FUNCTIONS: [[s1_load_y:%.*]] = load i32, i32* {{.*}}, align 1 // CHECK-FUNCTIONS: ret i32 [[s1_load_y]] int s1_load_y(struct s1 *a) { return a->y; } // CHECK-FUNCTIONS-LABEL: define void @s1_copy @@ -75,11 +75,11 @@ int s2_align_y = __alignof(((struct s2*)0)->y); int s2_align = __alignof(struct s2); // CHECK-FUNCTIONS-LABEL: define i32 @s2_load_x -// CHECK-FUNCTIONS: [[s2_load_y:%.*]] = load i32* {{.*}}, align 2 +// CHECK-FUNCTIONS: [[s2_load_y:%.*]] = load i32, i32* {{.*}}, align 2 // CHECK-FUNCTIONS: ret i32 [[s2_load_y]] int s2_load_x(struct s2 *a) { return a->x; } // CHECK-FUNCTIONS-LABEL: define i32 @s2_load_y -// CHECK-FUNCTIONS: [[s2_load_y:%.*]] = load i32* {{.*}}, align 2 +// CHECK-FUNCTIONS: [[s2_load_y:%.*]] = load i32, i32* {{.*}}, align 2 // CHECK-FUNCTIONS: ret i32 [[s2_load_y]] int s2_load_y(struct s2 *a) { return a->y; } // CHECK-FUNCTIONS-LABEL: define void @s2_copy @@ -94,7 +94,7 @@ struct __attribute__((packed, aligned)) s3 { int s3_1 = __alignof(((struct s3*) 0)->anInt); // CHECK-FUNCTIONS-LABEL: define i32 @test3( int test3(struct s3 *ptr) { - // CHECK-FUNCTIONS: [[PTR:%.*]] = getelementptr inbounds {{%.*}}* {{%.*}}, i32 0, i32 1 - // CHECK-FUNCTIONS-NEXT: load i32* [[PTR]], align 1 + // CHECK-FUNCTIONS: [[PTR:%.*]] = getelementptr inbounds {{%.*}}, {{%.*}}* {{%.*}}, i32 0, i32 1 + // CHECK-FUNCTIONS-NEXT: load i32, i32* [[PTR]], align 1 return ptr->anInt; } diff --git a/test/CodeGen/pointer-signext.c b/test/CodeGen/pointer-signext.c index e809effb2b10..470411f95d5b 100644 --- a/test/CodeGen/pointer-signext.c +++ b/test/CodeGen/pointer-signext.c @@ -4,8 +4,8 @@ // cause any sign extensions. // CHECK: [[P:%.*]] = add i64 %param, -8 -// CHECK-NEXT: [[Q:%.*]] = inttoptr i64 [[P]] to [[R:%.*\*]] -// CHECK-NEXT: {{%.*}} = getelementptr inbounds [[R]] [[Q]], i64 0, i32 0 +// CHECK-NEXT: [[Q:%.*]] = inttoptr i64 [[P]] to [[R:%.*]]* +// CHECK-NEXT: {{%.*}} = getelementptr inbounds [[R]], [[R]]* [[Q]], i64 0, i32 0 #define CR(Record, TYPE, Field) \ ((TYPE *) ((unsigned char *) (Record) - (unsigned char *) &(((TYPE *) 0)->Field))) diff --git a/test/CodeGen/ppc-varargs-struct.c b/test/CodeGen/ppc-varargs-struct.c index f0e075b048d7..1c983c0e4349 100644 --- a/test/CodeGen/ppc-varargs-struct.c +++ b/test/CodeGen/ppc-varargs-struct.c @@ -19,7 +19,7 @@ void testva (int n, ...) // CHECK: bitcast %struct.x* %t to i8* // CHECK: bitcast %struct.x* %{{[0-9]+}} to i8* // CHECK: call void @llvm.memcpy -// CHECK-PPC: [[ARRAYDECAY:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0 +// CHECK-PPC: [[ARRAYDECAY:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0 // CHECK-PPC-NEXT: [[GPRPTR:%[a-z0-9]+]] = bitcast %struct.__va_list_tag* [[ARRAYDECAY]] to i8* // CHECK-PPC-NEXT: [[ZERO:%[0-9]+]] = ptrtoint i8* [[GPRPTR]] to i32 // CHECK-PPC-NEXT: [[ONE:%[0-9]+]] = add i32 [[ZERO]], 1 @@ -28,11 +28,11 @@ void testva (int n, ...) // CHECK-PPC-NEXT: [[FOUR:%[0-9]+]] = inttoptr i32 [[THREE]] to i8** // CHECK-PPC-NEXT: [[FIVE:%[0-9]+]] = add i32 [[THREE]], 4 // CHECK-PPC-NEXT: [[SIX:%[0-9]+]] = inttoptr i32 [[FIVE]] to i8** -// CHECK-PPC-NEXT: [[GPR:%[a-z0-9]+]] = load i8* [[GPRPTR]] -// CHECK-PPC-NEXT: [[FPR:%[a-z0-9]+]] = load i8* [[TWO]] -// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%[a-z_0-9]+]] = load i8** [[FOUR]] +// CHECK-PPC-NEXT: [[GPR:%[a-z0-9]+]] = load i8, i8* [[GPRPTR]] +// CHECK-PPC-NEXT: [[FPR:%[a-z0-9]+]] = load i8, i8* [[TWO]] +// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%[a-z_0-9]+]] = load i8*, i8** [[FOUR]] // CHECK-PPC-NEXT: [[SEVEN:%[0-9]+]] = ptrtoint i8* [[OVERFLOW_AREA]] to i32 -// CHECK-PPC-NEXT: [[REGSAVE_AREA:%[a-z_0-9]+]] = load i8** [[SIX]] +// CHECK-PPC-NEXT: [[REGSAVE_AREA:%[a-z_0-9]+]] = load i8*, i8** [[SIX]] // CHECK-PPC-NEXT: [[EIGHT:%[0-9]+]] = ptrtoint i8* [[REGSAVE_AREA]] to i32 // CHECK-PPC-NEXT: [[COND:%[a-z0-9]+]] = icmp ult i8 [[GPR]], 8 // CHECK-PPC-NEXT: [[NINE:%[0-9]+]] = mul i8 [[GPR]], 4 @@ -56,7 +56,7 @@ void testva (int n, ...) // CHECK-PPC1:[[CONT]] // CHECK-PPC: [[VAARG_ADDR:%[a-z.0-9]+]] = phi %struct.x* [ [[TWELVE]], [[USING_REGS]] ], [ [[FOURTEEN]], [[USING_OVERFLOW]] ] // CHECK-PPC-NEXT: [[AGGRPTR:%[a-z0-9]+]] = bitcast %struct.x* [[VAARG_ADDR]] to i8** -// CHECK-PPC-NEXT: [[AGGR:%[a-z0-9]+]] = load i8** [[AGGRPTR]] +// CHECK-PPC-NEXT: [[AGGR:%[a-z0-9]+]] = load i8*, i8** [[AGGRPTR]] // CHECK-PPC-NEXT: [[SEVENTEEN:%[0-9]+]] = bitcast %struct.x* %t to i8* // CHECK-PPC-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[SEVENTEEN]], i8* [[AGGR]], i32 16, i32 8, i1 false) @@ -65,7 +65,7 @@ void testva (int n, ...) // CHECK: add i64 %{{[0-9]+}}, 4 // CHECK: inttoptr i64 %{{[0-9]+}} to i8* // CHECK: bitcast i8* %{{[0-9]+}} to i32* -// CHECK-PPC: [[ARRAYDECAY1:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0 +// CHECK-PPC: [[ARRAYDECAY1:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0 // CHECK-PPC-NEXT: [[GPRPTR1:%[a-z0-9]+]] = bitcast %struct.__va_list_tag* [[ARRAYDECAY1]] to i8* // CHECK-PPC-NEXT: [[EIGHTEEN:%[0-9]+]] = ptrtoint i8* [[GPRPTR1]] to i32 // CHECK-PPC-NEXT: [[NINETEEN:%[0-9]+]] = add i32 [[EIGHTEEN]], 1 @@ -74,17 +74,17 @@ void testva (int n, ...) // CHECK-PPC-NEXT: [[TWENTYTWO:%[0-9]+]] = inttoptr i32 [[TWENTYONE]] to i8** // CHECK-PPC-NEXT: [[TWENTYTHREE:%[0-9]+]] = add i32 [[TWENTYONE]], 4 // CHECK-PPC-NEXT: [[TWENTYFOUR:%[0-9]+]] = inttoptr i32 [[TWENTYTHREE]] to i8** -// CHECK-PPC-NEXT: [[GPR1:%[a-z0-9]+]] = load i8* [[GPRPTR1]] -// CHECK-PPC-NEXT: [[FPR1:%[a-z0-9]+]] = load i8* [[TWENTY]] -// CHECK-PPC-NEXT: [[OVERFLOW_AREA1:%[a-z_0-9]+]] = load i8** [[TWENTYTWO]] +// CHECK-PPC-NEXT: [[GPR1:%[a-z0-9]+]] = load i8, i8* [[GPRPTR1]] +// CHECK-PPC-NEXT: [[FPR1:%[a-z0-9]+]] = load i8, i8* [[TWENTY]] +// CHECK-PPC-NEXT: [[OVERFLOW_AREA1:%[a-z_0-9]+]] = load i8*, i8** [[TWENTYTWO]] // CHECK-PPC-NEXT: [[TWENTYFIVE:%[0-9]+]] = ptrtoint i8* [[OVERFLOW_AREA1]] to i32 -// CHECK-PPC-NEXT: [[REGSAVE_AREA1:%[a-z_0-9]+]] = load i8** [[TWENTYFOUR]] +// CHECK-PPC-NEXT: [[REGSAVE_AREA1:%[a-z_0-9]+]] = load i8*, i8** [[TWENTYFOUR]] // CHECK-PPC-NEXT: [[TWENTYSIX:%[0-9]+]] = ptrtoint i8* [[REGSAVE_AREA1]] to i32 // CHECK-PPC-NEXT: [[COND1:%[a-z0-9]+]] = icmp ult i8 [[GPR1]], 8 // CHECK-PPC-NEXT: [[TWENTYSEVEN:%[0-9]+]] = mul i8 [[GPR1]], 4 // CHECK-PPC-NEXT: [[TWENTYEIGHT:%[0-9]+]] = sext i8 [[TWENTYSEVEN]] to i32 // CHECK-PPC-NEXT: [[TWENTYNINE:%[0-9]+]] = add i32 [[TWENTYSIX]], [[TWENTYEIGHT]] -// CHECK-PPC-NEXT: br i1 [[COND1]], label [[USING_REGS1:%[a-z_0-9]+]], label [[USING_OVERFLOW1:%[a-z_0-9]+]] +// CHECK-PPC-NEXT: br i1 [[COND1]], label [[USING_REGS1:%[.a-z_0-9]+]], label [[USING_OVERFLOW1:%[.a-z_0-9]+]] // // CHECK-PPC1:[[USING_REGS1]]: // CHECK-PPC: [[THIRTY:%[0-9]+]] = inttoptr i32 [[TWENTYNINE]] to i32* @@ -101,12 +101,12 @@ void testva (int n, ...) // // CHECK-PPC1:[[CONT1]]: // CHECK-PPC: [[VAARG_ADDR1:%[a-z.0-9]+]] = phi i32* [ [[THIRTY]], [[USING_REGS1]] ], [ [[THIRTYTWO]], [[USING_OVERFLOW1]] ] -// CHECK-PPC-NEXT: [[THIRTYFIVE:%[0-9]+]] = load i32* [[VAARG_ADDR1]] +// CHECK-PPC-NEXT: [[THIRTYFIVE:%[0-9]+]] = load i32, i32* [[VAARG_ADDR1]] // CHECK-PPC-NEXT: store i32 [[THIRTYFIVE]], i32* %v, align 4 #ifdef __powerpc64__ __int128_t u = va_arg (ap, __int128_t); #endif // CHECK: bitcast i8* %{{[a-z.0-9]+}} to i128* -// CHECK-NEXT: load i128* %{{[0-9]+}} +// CHECK-NEXT: load i128, i128* %{{[0-9]+}} } diff --git a/test/CodeGen/ppc64-align-long-double.c b/test/CodeGen/ppc64-align-long-double.c index 6d07f7039da6..2214e246205b 100644 --- a/test/CodeGen/ppc64-align-long-double.c +++ b/test/CodeGen/ppc64-align-long-double.c @@ -13,4 +13,4 @@ long double test (struct S x) return x.b; } -// CHECK: %{{[0-9]}} = load ppc_fp128* %{{[a-zA-Z0-9]+}}, align 16 +// CHECK: %{{[0-9]}} = load ppc_fp128, ppc_fp128* %{{[a-zA-Z0-9]+}}, align 16 diff --git a/test/CodeGen/ppc64-align-struct.c b/test/CodeGen/ppc64-align-struct.c index a50c849b4568..8c4437a38d0a 100644 --- a/test/CodeGen/ppc64-align-struct.c +++ b/test/CodeGen/ppc64-align-struct.c @@ -49,8 +49,8 @@ void test7 (int x, struct test7 y) } // CHECK: define void @test1va(%struct.test1* noalias sret %agg.result, i32 signext %x, ...) -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8* %[[CUR]], i64 8 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i64 8 // CHECK: store i8* %[[NEXT]], i8** %ap // CHECK: bitcast i8* %[[CUR]] to %struct.test1* struct test1 test1va (int x, ...) @@ -64,12 +64,12 @@ struct test1 test1va (int x, ...) } // CHECK: define void @test2va(%struct.test2* noalias sret %agg.result, i32 signext %x, ...) -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[TMP0:[^ ]+]] = ptrtoint i8* %[[CUR]] to i64 // CHECK: %[[TMP1:[^ ]+]] = add i64 %[[TMP0]], 15 // CHECK: %[[TMP2:[^ ]+]] = and i64 %[[TMP1]], -16 // CHECK: %[[ALIGN:[^ ]+]] = inttoptr i64 %[[TMP2]] to i8* -// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8* %[[ALIGN]], i64 16 +// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8, i8* %[[ALIGN]], i64 16 // CHECK: store i8* %[[NEXT]], i8** %ap // CHECK: bitcast i8* %[[ALIGN]] to %struct.test2* struct test2 test2va (int x, ...) @@ -83,12 +83,12 @@ struct test2 test2va (int x, ...) } // CHECK: define void @test3va(%struct.test3* noalias sret %agg.result, i32 signext %x, ...) -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[TMP0:[^ ]+]] = ptrtoint i8* %[[CUR]] to i64 // CHECK: %[[TMP1:[^ ]+]] = add i64 %[[TMP0]], 15 // CHECK: %[[TMP2:[^ ]+]] = and i64 %[[TMP1]], -16 // CHECK: %[[ALIGN:[^ ]+]] = inttoptr i64 %[[TMP2]] to i8* -// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8* %[[ALIGN]], i64 32 +// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8, i8* %[[ALIGN]], i64 32 // CHECK: store i8* %[[NEXT]], i8** %ap // CHECK: bitcast i8* %[[ALIGN]] to %struct.test3* struct test3 test3va (int x, ...) @@ -102,8 +102,8 @@ struct test3 test3va (int x, ...) } // CHECK: define void @test4va(%struct.test4* noalias sret %agg.result, i32 signext %x, ...) -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8* %[[CUR]], i64 16 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i64 16 // CHECK: store i8* %[[NEXT]], i8** %ap // CHECK: bitcast i8* %[[CUR]] to %struct.test4* struct test4 test4va (int x, ...) @@ -117,8 +117,8 @@ struct test4 test4va (int x, ...) } // CHECK: define void @testva_longdouble(%struct.test_longdouble* noalias sret %agg.result, i32 signext %x, ...) -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8* %[[CUR]], i64 16 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i64 16 // CHECK: store i8* %[[NEXT]], i8** %ap // CHECK: bitcast i8* %[[CUR]] to %struct.test_longdouble* struct test_longdouble { long double x; }; @@ -133,12 +133,12 @@ struct test_longdouble testva_longdouble (int x, ...) } // CHECK: define void @testva_vector(%struct.test_vector* noalias sret %agg.result, i32 signext %x, ...) -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap // CHECK: %[[TMP0:[^ ]+]] = ptrtoint i8* %[[CUR]] to i64 // CHECK: %[[TMP1:[^ ]+]] = add i64 %[[TMP0]], 15 // CHECK: %[[TMP2:[^ ]+]] = and i64 %[[TMP1]], -16 // CHECK: %[[ALIGN:[^ ]+]] = inttoptr i64 %[[TMP2]] to i8* -// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8* %[[ALIGN]], i64 16 +// CHECK: %[[NEXT:[^ ]+]] = getelementptr i8, i8* %[[ALIGN]], i64 16 // CHECK: store i8* %[[NEXT]], i8** %ap // CHECK: bitcast i8* %[[ALIGN]] to %struct.test_vector* struct test_vector { vector int x; }; diff --git a/test/CodeGen/ppc64-complex-parms.c b/test/CodeGen/ppc64-complex-parms.c index fe3025a711b1..f5583a0742d9 100644 --- a/test/CodeGen/ppc64-complex-parms.c +++ b/test/CodeGen/ppc64-complex-parms.c @@ -58,14 +58,14 @@ void bar_float(void) { // CHECK: define void @bar_float() [[NUW]] { // CHECK: %[[VAR1:[A-Za-z0-9.]+]] = alloca { float, float }, align 4 -// CHECK: %[[VAR2:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }* %[[VAR1]], i32 0, i32 0 -// CHECK: %[[VAR3:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }* %[[VAR1]], i32 0, i32 1 +// CHECK: %[[VAR2:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR1]], i32 0, i32 0 +// CHECK: %[[VAR3:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR1]], i32 0, i32 1 // CHECK: store float 2.000000e+00, float* %[[VAR2]] // CHECK: store float -2.500000e+00, float* %[[VAR3]] -// CHECK: %[[VAR4:[A-Za-z0-9.]+]] = getelementptr { float, float }* %[[VAR1]], i32 0, i32 0 -// CHECK: %[[VAR5:[A-Za-z0-9.]+]] = load float* %[[VAR4]], align 1 -// CHECK: %[[VAR6:[A-Za-z0-9.]+]] = getelementptr { float, float }* %[[VAR1]], i32 0, i32 1 -// CHECK: %[[VAR7:[A-Za-z0-9.]+]] = load float* %[[VAR6]], align 1 +// CHECK: %[[VAR4:[A-Za-z0-9.]+]] = getelementptr { float, float }, { float, float }* %[[VAR1]], i32 0, i32 0 +// CHECK: %[[VAR5:[A-Za-z0-9.]+]] = load float, float* %[[VAR4]], align 1 +// CHECK: %[[VAR6:[A-Za-z0-9.]+]] = getelementptr { float, float }, { float, float }* %[[VAR1]], i32 0, i32 1 +// CHECK: %[[VAR7:[A-Za-z0-9.]+]] = load float, float* %[[VAR6]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call float @foo_float(float %[[VAR5]], float %[[VAR7]]) void bar_double(void) { @@ -74,14 +74,14 @@ void bar_double(void) { // CHECK: define void @bar_double() [[NUW]] { // CHECK: %[[VAR11:[A-Za-z0-9.]+]] = alloca { double, double }, align 8 -// CHECK: %[[VAR12:[A-Za-z0-9.]+]] = getelementptr inbounds { double, double }* %[[VAR11]], i32 0, i32 0 -// CHECK: %[[VAR13:[A-Za-z0-9.]+]] = getelementptr inbounds { double, double }* %[[VAR11]], i32 0, i32 1 +// CHECK: %[[VAR12:[A-Za-z0-9.]+]] = getelementptr inbounds { double, double }, { double, double }* %[[VAR11]], i32 0, i32 0 +// CHECK: %[[VAR13:[A-Za-z0-9.]+]] = getelementptr inbounds { double, double }, { double, double }* %[[VAR11]], i32 0, i32 1 // CHECK: store double 2.000000e+00, double* %[[VAR12]] // CHECK: store double -2.500000e+00, double* %[[VAR13]] -// CHECK: %[[VAR14:[A-Za-z0-9.]+]] = getelementptr { double, double }* %[[VAR11]], i32 0, i32 0 -// CHECK: %[[VAR15:[A-Za-z0-9.]+]] = load double* %[[VAR14]], align 1 -// CHECK: %[[VAR16:[A-Za-z0-9.]+]] = getelementptr { double, double }* %[[VAR11]], i32 0, i32 1 -// CHECK: %[[VAR17:[A-Za-z0-9.]+]] = load double* %[[VAR16]], align 1 +// CHECK: %[[VAR14:[A-Za-z0-9.]+]] = getelementptr { double, double }, { double, double }* %[[VAR11]], i32 0, i32 0 +// CHECK: %[[VAR15:[A-Za-z0-9.]+]] = load double, double* %[[VAR14]], align 1 +// CHECK: %[[VAR16:[A-Za-z0-9.]+]] = getelementptr { double, double }, { double, double }* %[[VAR11]], i32 0, i32 1 +// CHECK: %[[VAR17:[A-Za-z0-9.]+]] = load double, double* %[[VAR16]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call double @foo_double(double %[[VAR15]], double %[[VAR17]]) void bar_long_double(void) { @@ -90,14 +90,14 @@ void bar_long_double(void) { // CHECK: define void @bar_long_double() [[NUW]] { // CHECK: %[[VAR21:[A-Za-z0-9.]+]] = alloca { ppc_fp128, ppc_fp128 }, align 16 -// CHECK: %[[VAR22:[A-Za-z0-9.]+]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 0 -// CHECK: %[[VAR23:[A-Za-z0-9.]+]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 1 +// CHECK: %[[VAR22:[A-Za-z0-9.]+]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 0 +// CHECK: %[[VAR23:[A-Za-z0-9.]+]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 1 // CHECK: store ppc_fp128 0xM40000000000000000000000000000000, ppc_fp128* %[[VAR22]] // CHECK: store ppc_fp128 0xMC0040000000000000000000000000000, ppc_fp128* %[[VAR23]] -// CHECK: %[[VAR24:[A-Za-z0-9.]+]] = getelementptr { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 0 -// CHECK: %[[VAR25:[A-Za-z0-9.]+]] = load ppc_fp128* %[[VAR24]], align 1 -// CHECK: %[[VAR26:[A-Za-z0-9.]+]] = getelementptr { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 1 -// CHECK: %[[VAR27:[A-Za-z0-9.]+]] = load ppc_fp128* %[[VAR26]], align 1 +// CHECK: %[[VAR24:[A-Za-z0-9.]+]] = getelementptr { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 0 +// CHECK: %[[VAR25:[A-Za-z0-9.]+]] = load ppc_fp128, ppc_fp128* %[[VAR24]], align 1 +// CHECK: %[[VAR26:[A-Za-z0-9.]+]] = getelementptr { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %[[VAR21]], i32 0, i32 1 +// CHECK: %[[VAR27:[A-Za-z0-9.]+]] = load ppc_fp128, ppc_fp128* %[[VAR26]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call ppc_fp128 @foo_long_double(ppc_fp128 %[[VAR25]], ppc_fp128 %[[VAR27]]) void bar_int(void) { @@ -106,14 +106,14 @@ void bar_int(void) { // CHECK: define void @bar_int() [[NUW]] { // CHECK: %[[VAR31:[A-Za-z0-9.]+]] = alloca { i32, i32 }, align 4 -// CHECK: %[[VAR32:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }* %[[VAR31]], i32 0, i32 0 -// CHECK: %[[VAR33:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }* %[[VAR31]], i32 0, i32 1 +// CHECK: %[[VAR32:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR31]], i32 0, i32 0 +// CHECK: %[[VAR33:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR31]], i32 0, i32 1 // CHECK: store i32 2, i32* %[[VAR32]] // CHECK: store i32 -3, i32* %[[VAR33]] -// CHECK: %[[VAR34:[A-Za-z0-9.]+]] = getelementptr { i32, i32 }* %[[VAR31]], i32 0, i32 0 -// CHECK: %[[VAR35:[A-Za-z0-9.]+]] = load i32* %[[VAR34]], align 1 -// CHECK: %[[VAR36:[A-Za-z0-9.]+]] = getelementptr { i32, i32 }* %[[VAR31]], i32 0, i32 1 -// CHECK: %[[VAR37:[A-Za-z0-9.]+]] = load i32* %[[VAR36]], align 1 +// CHECK: %[[VAR34:[A-Za-z0-9.]+]] = getelementptr { i32, i32 }, { i32, i32 }* %[[VAR31]], i32 0, i32 0 +// CHECK: %[[VAR35:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR34]], align 1 +// CHECK: %[[VAR36:[A-Za-z0-9.]+]] = getelementptr { i32, i32 }, { i32, i32 }* %[[VAR31]], i32 0, i32 1 +// CHECK: %[[VAR37:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR36]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call signext i32 @foo_int(i32 %[[VAR35]], i32 %[[VAR37]]) void bar_short(void) { @@ -122,14 +122,14 @@ void bar_short(void) { // CHECK: define void @bar_short() [[NUW]] { // CHECK: %[[VAR41:[A-Za-z0-9.]+]] = alloca { i16, i16 }, align 2 -// CHECK: %[[VAR42:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }* %[[VAR41]], i32 0, i32 0 -// CHECK: %[[VAR43:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }* %[[VAR41]], i32 0, i32 1 +// CHECK: %[[VAR42:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR41]], i32 0, i32 0 +// CHECK: %[[VAR43:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR41]], i32 0, i32 1 // CHECK: store i16 2, i16* %[[VAR42]] // CHECK: store i16 -3, i16* %[[VAR43]] -// CHECK: %[[VAR44:[A-Za-z0-9.]+]] = getelementptr { i16, i16 }* %[[VAR41]], i32 0, i32 0 -// CHECK: %[[VAR45:[A-Za-z0-9.]+]] = load i16* %[[VAR44]], align 1 -// CHECK: %[[VAR46:[A-Za-z0-9.]+]] = getelementptr { i16, i16 }* %[[VAR41]], i32 0, i32 1 -// CHECK: %[[VAR47:[A-Za-z0-9.]+]] = load i16* %[[VAR46]], align 1 +// CHECK: %[[VAR44:[A-Za-z0-9.]+]] = getelementptr { i16, i16 }, { i16, i16 }* %[[VAR41]], i32 0, i32 0 +// CHECK: %[[VAR45:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR44]], align 1 +// CHECK: %[[VAR46:[A-Za-z0-9.]+]] = getelementptr { i16, i16 }, { i16, i16 }* %[[VAR41]], i32 0, i32 1 +// CHECK: %[[VAR47:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR46]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call signext i16 @foo_short(i16 %[[VAR45]], i16 %[[VAR47]]) void bar_char(void) { @@ -138,14 +138,14 @@ void bar_char(void) { // CHECK: define void @bar_char() [[NUW]] { // CHECK: %[[VAR51:[A-Za-z0-9.]+]] = alloca { i8, i8 }, align 1 -// CHECK: %[[VAR52:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }* %[[VAR51]], i32 0, i32 0 -// CHECK: %[[VAR53:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }* %[[VAR51]], i32 0, i32 1 +// CHECK: %[[VAR52:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR51]], i32 0, i32 0 +// CHECK: %[[VAR53:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR51]], i32 0, i32 1 // CHECK: store i8 2, i8* %[[VAR52]] // CHECK: store i8 -3, i8* %[[VAR53]] -// CHECK: %[[VAR54:[A-Za-z0-9.]+]] = getelementptr { i8, i8 }* %[[VAR51]], i32 0, i32 0 -// CHECK: %[[VAR55:[A-Za-z0-9.]+]] = load i8* %[[VAR54]], align 1 -// CHECK: %[[VAR56:[A-Za-z0-9.]+]] = getelementptr { i8, i8 }* %[[VAR51]], i32 0, i32 1 -// CHECK: %[[VAR57:[A-Za-z0-9.]+]] = load i8* %[[VAR56]], align 1 +// CHECK: %[[VAR54:[A-Za-z0-9.]+]] = getelementptr { i8, i8 }, { i8, i8 }* %[[VAR51]], i32 0, i32 0 +// CHECK: %[[VAR55:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR54]], align 1 +// CHECK: %[[VAR56:[A-Za-z0-9.]+]] = getelementptr { i8, i8 }, { i8, i8 }* %[[VAR51]], i32 0, i32 1 +// CHECK: %[[VAR57:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR56]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call signext i8 @foo_char(i8 %[[VAR55]], i8 %[[VAR57]]) void bar_long(void) { @@ -154,14 +154,14 @@ void bar_long(void) { // CHECK: define void @bar_long() [[NUW]] { // CHECK: %[[VAR61:[A-Za-z0-9.]+]] = alloca { i64, i64 }, align 8 -// CHECK: %[[VAR62:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }* %[[VAR61]], i32 0, i32 0 -// CHECK: %[[VAR63:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }* %[[VAR61]], i32 0, i32 1 +// CHECK: %[[VAR62:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* %[[VAR61]], i32 0, i32 0 +// CHECK: %[[VAR63:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* %[[VAR61]], i32 0, i32 1 // CHECK: store i64 2, i64* %[[VAR62]] // CHECK: store i64 -3, i64* %[[VAR63]] -// CHECK: %[[VAR64:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }* %[[VAR61]], i32 0, i32 0 -// CHECK: %[[VAR65:[A-Za-z0-9.]+]] = load i64* %[[VAR64]], align 1 -// CHECK: %[[VAR66:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }* %[[VAR61]], i32 0, i32 1 -// CHECK: %[[VAR67:[A-Za-z0-9.]+]] = load i64* %[[VAR66]], align 1 +// CHECK: %[[VAR64:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }, { i64, i64 }* %[[VAR61]], i32 0, i32 0 +// CHECK: %[[VAR65:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR64]], align 1 +// CHECK: %[[VAR66:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }, { i64, i64 }* %[[VAR61]], i32 0, i32 1 +// CHECK: %[[VAR67:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR66]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call i64 @foo_long(i64 %[[VAR65]], i64 %[[VAR67]]) void bar_long_long(void) { @@ -170,14 +170,14 @@ void bar_long_long(void) { // CHECK: define void @bar_long_long() [[NUW]] { // CHECK: %[[VAR71:[A-Za-z0-9.]+]] = alloca { i64, i64 }, align 8 -// CHECK: %[[VAR72:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }* %[[VAR71]], i32 0, i32 0 -// CHECK: %[[VAR73:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }* %[[VAR71]], i32 0, i32 1 +// CHECK: %[[VAR72:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* %[[VAR71]], i32 0, i32 0 +// CHECK: %[[VAR73:[A-Za-z0-9.]+]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* %[[VAR71]], i32 0, i32 1 // CHECK: store i64 2, i64* %[[VAR72]] // CHECK: store i64 -3, i64* %[[VAR73]] -// CHECK: %[[VAR74:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }* %[[VAR71]], i32 0, i32 0 -// CHECK: %[[VAR75:[A-Za-z0-9.]+]] = load i64* %[[VAR74]], align 1 -// CHECK: %[[VAR76:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }* %[[VAR71]], i32 0, i32 1 -// CHECK: %[[VAR77:[A-Za-z0-9.]+]] = load i64* %[[VAR76]], align 1 +// CHECK: %[[VAR74:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }, { i64, i64 }* %[[VAR71]], i32 0, i32 0 +// CHECK: %[[VAR75:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR74]], align 1 +// CHECK: %[[VAR76:[A-Za-z0-9.]+]] = getelementptr { i64, i64 }, { i64, i64 }* %[[VAR71]], i32 0, i32 1 +// CHECK: %[[VAR77:[A-Za-z0-9.]+]] = load i64, i64* %[[VAR76]], align 1 // CHECK: %{{[A-Za-z0-9.]+}} = call i64 @foo_long_long(i64 %[[VAR75]], i64 %[[VAR77]]) // CHECK: attributes [[NUW]] = { nounwind{{.*}} } diff --git a/test/CodeGen/ppc64-elf-abi.c b/test/CodeGen/ppc64-elf-abi.c index 0dd183e2a6da..59112a0baf4a 100644 --- a/test/CodeGen/ppc64-elf-abi.c +++ b/test/CodeGen/ppc64-elf-abi.c @@ -7,6 +7,8 @@ // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s \ // RUN: -target-abi elfv1 | FileCheck %s --check-prefix=CHECK-ELFv1 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s \ +// RUN: -target-abi elfv1-qpx | FileCheck %s --check-prefix=CHECK-ELFv1 +// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s \ // RUN: -target-abi elfv2 | FileCheck %s --check-prefix=CHECK-ELFv2 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm -o - %s \ // RUN: | FileCheck %s --check-prefix=CHECK-ELFv2 @@ -19,22 +21,3 @@ // CHECK-ELFv2: define [2 x float] @func_fab([2 x float] %x.coerce) struct fab { float a; float b; }; struct fab func_fab(struct fab x) { return x; } - -// Verify ABI choice is passed on to the back end - -// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -S -o - %s \ -// RUN: | FileCheck %s --check-prefix=CHECK-ASM-ELFv1 -// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -S -o - %s \ -// RUN: -target-abi elfv1 | FileCheck %s --check-prefix=CHECK-ASM-ELFv1 -// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -S -o - %s \ -// RUN: -target-abi elfv2 | FileCheck %s --check-prefix=CHECK-ASM-ELFv2 -// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -S -o - %s \ -// RUN: | FileCheck %s --check-prefix=CHECK-ASM-ELFv2 -// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -S -o - %s \ -// RUN: -target-abi elfv1 | FileCheck %s --check-prefix=CHECK-ASM-ELFv1 -// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -S -o - %s \ -// RUN: -target-abi elfv2 | FileCheck %s --check-prefix=CHECK-ASM-ELFv2 - -// CHECK-ASM-ELFv2: .abiversion 2 -// CHECK-ASM-ELFv1-NOT: .abiversion 2 - diff --git a/test/CodeGen/ppc64-qpx-vector.c b/test/CodeGen/ppc64-qpx-vector.c new file mode 100644 index 000000000000..c42d4b36a830 --- /dev/null +++ b/test/CodeGen/ppc64-qpx-vector.c @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=ALL -check-prefix=NORMAL +// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - -target-abi elfv1-qpx %s | FileCheck %s -check-prefix=ALL -check-prefix=QPX + +typedef float v4sf __attribute__((vector_size(16))); +typedef double v4df __attribute__((vector_size(32))); + +struct ssf { v4sf v; }; +struct sdf { v4df v; }; + +struct ssf2 { v4sf v[2]; }; +struct sdf2 { v4df v[2]; }; + +v4sf foo1(struct ssf a, v4sf b, struct ssf2 c) { + return a.v + b; +} + +// ALL-LABEL: define <4 x float> @foo1(<4 x float> inreg %a.coerce, <4 x float> %b, [2 x i128] %c.coerce) +// ALL: ret <4 x float> + +v4df foo2(struct sdf a, v4df b, struct sdf2 c) { + return a.v + b; +} + +// QPX-LABEL: define <4 x double> @foo2(<4 x double> inreg %a.coerce, <4 x double> %b, [2 x i256] %c.coerce) +// QPX: ret <4 x double> + +// NORMAL-LABEL: define void @foo2(<4 x double>* noalias sret %agg.result, [2 x i128] %a.coerce, <4 x double>*, [4 x i128] %c.coerce) +// NORMAL: ret void + diff --git a/test/CodeGen/ppc64-struct-onefloat.c b/test/CodeGen/ppc64-struct-onefloat.c index 11b16a4c5081..d0ccfbe34a44 100644 --- a/test/CodeGen/ppc64-struct-onefloat.c +++ b/test/CodeGen/ppc64-struct-onefloat.c @@ -13,15 +13,15 @@ void bar(Sf a, Sd b, SSf d, SSd e) {} // CHECK: %b = alloca %struct.s2, align 8 // CHECK: %d = alloca %struct.s4, align 4 // CHECK: %e = alloca %struct.s5, align 8 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1* %a, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1, %struct.s1* %a, i32 0, i32 0 // CHECK: store float %a.coerce, float* %{{[a-zA-Z0-9.]+}}, align 1 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2* %b, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2, %struct.s2* %b, i32 0, i32 0 // CHECK: store double %b.coerce, double* %{{[a-zA-Z0-9.]+}}, align 1 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s4* %d, i32 0, i32 0 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s4, %struct.s4* %d, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1, %struct.s1* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 // CHECK: store float %d.coerce, float* %{{[a-zA-Z0-9.]+}}, align 1 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s5* %e, i32 0, i32 0 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s5, %struct.s5* %e, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2, %struct.s2* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 // CHECK: store double %e.coerce, double* %{{[a-zA-Z0-9.]+}}, align 1 // CHECK: ret void @@ -35,15 +35,15 @@ void foo(void) } // CHECK-LABEL: define void @foo -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1* %p1, i32 0, i32 0 -// CHECK: %{{[0-9]+}} = load float* %{{[a-zA-Z0-9.]+}}, align 1 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2* %p2, i32 0, i32 0 -// CHECK: %{{[0-9]+}} = load double* %{{[a-zA-Z0-9.]+}}, align 1 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s4* %p4, i32 0, i32 0 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 -// CHECK: %{{[0-9]+}} = load float* %{{[a-zA-Z0-9.]+}}, align 1 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s5* %p5, i32 0, i32 0 -// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 -// CHECK: %{{[0-9]+}} = load double* %{{[a-zA-Z0-9.]+}}, align 1 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1, %struct.s1* %p1, i32 0, i32 0 +// CHECK: %{{[0-9]+}} = load float, float* %{{[a-zA-Z0-9.]+}}, align 1 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2, %struct.s2* %p2, i32 0, i32 0 +// CHECK: %{{[0-9]+}} = load double, double* %{{[a-zA-Z0-9.]+}}, align 1 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s4, %struct.s4* %p4, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s1, %struct.s1* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 +// CHECK: %{{[0-9]+}} = load float, float* %{{[a-zA-Z0-9.]+}}, align 1 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s5, %struct.s5* %p5, i32 0, i32 0 +// CHECK: %{{[a-zA-Z0-9.]+}} = getelementptr %struct.s2, %struct.s2* %{{[a-zA-Z0-9.]+}}, i32 0, i32 0 +// CHECK: %{{[0-9]+}} = load double, double* %{{[a-zA-Z0-9.]+}}, align 1 // CHECK: call void @bar(float inreg %{{[0-9]+}}, double inreg %{{[0-9]+}}, float inreg %{{[0-9]+}}, double inreg %{{[0-9]+}}) // CHECK: ret void diff --git a/test/CodeGen/ppc64-varargs-complex.c b/test/CodeGen/ppc64-varargs-complex.c index 8fc88395bc39..f79062934572 100644 --- a/test/CodeGen/ppc64-varargs-complex.c +++ b/test/CodeGen/ppc64-varargs-complex.c @@ -8,66 +8,66 @@ void testva (int n, ...) va_list ap; _Complex int i = va_arg(ap, _Complex int); - // CHECK: %[[VAR40:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR41:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR40]], i64 16 + // CHECK: %[[VAR40:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR41:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR40]], i64 16 // CHECK-NEXT: store i8* %[[VAR41]], i8** %[[VAR100]] // CHECK-NEXT: %[[VAR1:[A-Za-z0-9.]+]] = ptrtoint i8* %[[VAR40]] to i64 // CHECK-NEXT: %[[VAR2:[A-Za-z0-9.]+]] = add i64 %[[VAR1]], 4 // CHECK-NEXT: %[[VAR3:[A-Za-z0-9.]+]] = add i64 %[[VAR1]], 12 // CHECK-NEXT: %[[VAR4:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR2]] to i32* // CHECK-NEXT: %[[VAR5:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR3]] to i32* - // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i32* %[[VAR4]] - // CHECK-NEXT: %[[VAR7:[A-Za-z0-9.]+]] = load i32* %[[VAR5]] - // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }* %[[VAR0:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }* %[[VAR0]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR4]] + // CHECK-NEXT: %[[VAR7:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR5]] + // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR0:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR0]], i32 0, i32 1 // CHECK-NEXT: store i32 %[[VAR6]], i32* %[[VAR8]] // CHECK-NEXT: store i32 %[[VAR7]], i32* %[[VAR9]] _Complex short s = va_arg(ap, _Complex short); - // CHECK: %[[VAR50:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR51:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR50]], i64 16 + // CHECK: %[[VAR50:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR51:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR50]], i64 16 // CHECK-NEXT: store i8* %[[VAR51]], i8** %[[VAR100]] // CHECK: %[[VAR11:[A-Za-z0-9.]+]] = ptrtoint i8* %{{[A-Za-z0-9.]+}} to i64 // CHECK-NEXT: %[[VAR12:[A-Za-z0-9.]+]] = add i64 %[[VAR11]], 6 // CHECK-NEXT: %[[VAR13:[A-Za-z0-9.]+]] = add i64 %[[VAR11]], 14 // CHECK-NEXT: %[[VAR14:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR12]] to i16* // CHECK-NEXT: %[[VAR15:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR13]] to i16* - // CHECK-NEXT: %[[VAR16:[A-Za-z0-9.]+]] = load i16* %[[VAR14]] - // CHECK-NEXT: %[[VAR17:[A-Za-z0-9.]+]] = load i16* %[[VAR15]] - // CHECK-NEXT: %[[VAR18:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }* %[[VAR10:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR19:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }* %[[VAR10]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR16:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR14]] + // CHECK-NEXT: %[[VAR17:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR15]] + // CHECK-NEXT: %[[VAR18:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR10:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR19:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR10]], i32 0, i32 1 // CHECK-NEXT: store i16 %[[VAR16]], i16* %[[VAR18]] // CHECK-NEXT: store i16 %[[VAR17]], i16* %[[VAR19]] _Complex char c = va_arg(ap, _Complex char); - // CHECK: %[[VAR60:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR61:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR60]], i64 16 + // CHECK: %[[VAR60:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR61:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR60]], i64 16 // CHECK-NEXT: store i8* %[[VAR61]], i8** %[[VAR100]] // CHECK: %[[VAR21:[A-Za-z0-9.]+]] = ptrtoint i8* %{{[A-Za-z0-9.]+}} to i64 // CHECK-NEXT: %[[VAR22:[A-Za-z0-9.]+]] = add i64 %[[VAR21]], 7 // CHECK-NEXT: %[[VAR23:[A-Za-z0-9.]+]] = add i64 %[[VAR21]], 15 // CHECK-NEXT: %[[VAR24:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR22]] to i8* // CHECK-NEXT: %[[VAR25:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR23]] to i8* - // CHECK-NEXT: %[[VAR26:[A-Za-z0-9.]+]] = load i8* %[[VAR24]] - // CHECK-NEXT: %[[VAR27:[A-Za-z0-9.]+]] = load i8* %[[VAR25]] - // CHECK-NEXT: %[[VAR28:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }* %[[VAR20:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }* %[[VAR20]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR26:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR24]] + // CHECK-NEXT: %[[VAR27:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR25]] + // CHECK-NEXT: %[[VAR28:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR20:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR20]], i32 0, i32 1 // CHECK-NEXT: store i8 %[[VAR26]], i8* %[[VAR28]] // CHECK-NEXT: store i8 %[[VAR27]], i8* %[[VAR29]] _Complex float f = va_arg(ap, _Complex float); - // CHECK: %[[VAR70:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR71:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR70]], i64 16 + // CHECK: %[[VAR70:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR71:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR70]], i64 16 // CHECK-NEXT: store i8* %[[VAR71]], i8** %[[VAR100]] // CHECK: %[[VAR31:[A-Za-z0-9.]+]] = ptrtoint i8* %{{[A-Za-z0-9.]+}} to i64 // CHECK-NEXT: %[[VAR32:[A-Za-z0-9.]+]] = add i64 %[[VAR31]], 4 // CHECK-NEXT: %[[VAR33:[A-Za-z0-9.]+]] = add i64 %[[VAR31]], 12 // CHECK-NEXT: %[[VAR34:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR32]] to float* // CHECK-NEXT: %[[VAR35:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR33]] to float* - // CHECK-NEXT: %[[VAR36:[A-Za-z0-9.]+]] = load float* %[[VAR34]] - // CHECK-NEXT: %[[VAR37:[A-Za-z0-9.]+]] = load float* %[[VAR35]] - // CHECK-NEXT: %[[VAR38:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }* %[[VAR30:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR39:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }* %[[VAR30]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR36:[A-Za-z0-9.]+]] = load float, float* %[[VAR34]] + // CHECK-NEXT: %[[VAR37:[A-Za-z0-9.]+]] = load float, float* %[[VAR35]] + // CHECK-NEXT: %[[VAR38:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR30:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR39:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR30]], i32 0, i32 1 // CHECK-NEXT: store float %[[VAR36]], float* %[[VAR38]] // CHECK-NEXT: store float %[[VAR37]], float* %[[VAR39]] } diff --git a/test/CodeGen/ppc64le-aggregates.c b/test/CodeGen/ppc64le-aggregates.c index e193dcc3faef..76798c132734 100644 --- a/test/CodeGen/ppc64le-aggregates.c +++ b/test/CodeGen/ppc64le-aggregates.c @@ -54,49 +54,49 @@ struct fabc func_fabc(struct fabc x) { return x; } struct f2a2b func_f2a2b(struct f2a2b x) { return x; } // CHECK-LABEL: @call_f1 -// CHECK: %[[TMP:[^ ]+]] = load float* getelementptr inbounds (%struct.f1* @global_f1, i32 0, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load float, float* getelementptr inbounds (%struct.f1, %struct.f1* @global_f1, i32 0, i32 0, i32 0), align 1 // CHECK: call [1 x float] @func_f1(float inreg %[[TMP]]) struct f1 global_f1; void call_f1(void) { global_f1 = func_f1(global_f1); } // CHECK-LABEL: @call_f2 -// CHECK: %[[TMP:[^ ]+]] = load [2 x float]* getelementptr inbounds (%struct.f2* @global_f2, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [2 x float], [2 x float]* getelementptr inbounds (%struct.f2, %struct.f2* @global_f2, i32 0, i32 0), align 1 // CHECK: call [2 x float] @func_f2([2 x float] %[[TMP]]) struct f2 global_f2; void call_f2(void) { global_f2 = func_f2(global_f2); } // CHECK-LABEL: @call_f3 -// CHECK: %[[TMP:[^ ]+]] = load [3 x float]* getelementptr inbounds (%struct.f3* @global_f3, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [3 x float], [3 x float]* getelementptr inbounds (%struct.f3, %struct.f3* @global_f3, i32 0, i32 0), align 1 // CHECK: call [3 x float] @func_f3([3 x float] %[[TMP]]) struct f3 global_f3; void call_f3(void) { global_f3 = func_f3(global_f3); } // CHECK-LABEL: @call_f4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x float]* getelementptr inbounds (%struct.f4* @global_f4, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [4 x float], [4 x float]* getelementptr inbounds (%struct.f4, %struct.f4* @global_f4, i32 0, i32 0), align 1 // CHECK: call [4 x float] @func_f4([4 x float] %[[TMP]]) struct f4 global_f4; void call_f4(void) { global_f4 = func_f4(global_f4); } // CHECK-LABEL: @call_f5 -// CHECK: %[[TMP:[^ ]+]] = load [5 x float]* getelementptr inbounds (%struct.f5* @global_f5, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [5 x float], [5 x float]* getelementptr inbounds (%struct.f5, %struct.f5* @global_f5, i32 0, i32 0), align 1 // CHECK: call [5 x float] @func_f5([5 x float] %[[TMP]]) struct f5 global_f5; void call_f5(void) { global_f5 = func_f5(global_f5); } // CHECK-LABEL: @call_f6 -// CHECK: %[[TMP:[^ ]+]] = load [6 x float]* getelementptr inbounds (%struct.f6* @global_f6, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [6 x float], [6 x float]* getelementptr inbounds (%struct.f6, %struct.f6* @global_f6, i32 0, i32 0), align 1 // CHECK: call [6 x float] @func_f6([6 x float] %[[TMP]]) struct f6 global_f6; void call_f6(void) { global_f6 = func_f6(global_f6); } // CHECK-LABEL: @call_f7 -// CHECK: %[[TMP:[^ ]+]] = load [7 x float]* getelementptr inbounds (%struct.f7* @global_f7, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [7 x float], [7 x float]* getelementptr inbounds (%struct.f7, %struct.f7* @global_f7, i32 0, i32 0), align 1 // CHECK: call [7 x float] @func_f7([7 x float] %[[TMP]]) struct f7 global_f7; void call_f7(void) { global_f7 = func_f7(global_f7); } // CHECK-LABEL: @call_f8 -// CHECK: %[[TMP:[^ ]+]] = load [8 x float]* getelementptr inbounds (%struct.f8* @global_f8, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [8 x float], [8 x float]* getelementptr inbounds (%struct.f8, %struct.f8* @global_f8, i32 0, i32 0), align 1 // CHECK: call [8 x float] @func_f8([8 x float] %[[TMP]]) struct f8 global_f8; void call_f8(void) { global_f8 = func_f8(global_f8); } @@ -105,19 +105,19 @@ void call_f8(void) { global_f8 = func_f8(global_f8); } // CHECK: %[[TMP1:[^ ]+]] = alloca [5 x i64] // CHECK: %[[TMP2:[^ ]+]] = bitcast [5 x i64]* %[[TMP1]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %[[TMP2]], i8* bitcast (%struct.f9* @global_f9 to i8*), i64 36, i32 1, i1 false) -// CHECK: %[[TMP3:[^ ]+]] = load [5 x i64]* %[[TMP1]] +// CHECK: %[[TMP3:[^ ]+]] = load [5 x i64], [5 x i64]* %[[TMP1]] // CHECK: call void @func_f9(%struct.f9* sret %{{[^ ]+}}, [5 x i64] %[[TMP3]]) struct f9 global_f9; void call_f9(void) { global_f9 = func_f9(global_f9); } // CHECK-LABEL: @call_fab -// CHECK: %[[TMP:[^ ]+]] = load [2 x float]* bitcast (%struct.fab* @global_fab to [2 x float]*) +// CHECK: %[[TMP:[^ ]+]] = load [2 x float], [2 x float]* bitcast (%struct.fab* @global_fab to [2 x float]*) // CHECK: call [2 x float] @func_fab([2 x float] %[[TMP]]) struct fab global_fab; void call_fab(void) { global_fab = func_fab(global_fab); } // CHECK-LABEL: @call_fabc -// CHECK: %[[TMP:[^ ]+]] = load [3 x float]* bitcast (%struct.fabc* @global_fabc to [3 x float]*) +// CHECK: %[[TMP:[^ ]+]] = load [3 x float], [3 x float]* bitcast (%struct.fabc* @global_fabc to [3 x float]*) // CHECK: call [3 x float] @func_fabc([3 x float] %[[TMP]]) struct fabc global_fabc; void call_fabc(void) { global_fabc = func_fabc(global_fabc); } @@ -172,49 +172,49 @@ struct vab func_vab(struct vab x) { return x; } struct vabc func_vabc(struct vabc x) { return x; } // CHECK-LABEL: @call_v1 -// CHECK: %[[TMP:[^ ]+]] = load <4 x i32>* getelementptr inbounds (%struct.v1* @global_v1, i32 0, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load <4 x i32>, <4 x i32>* getelementptr inbounds (%struct.v1, %struct.v1* @global_v1, i32 0, i32 0, i32 0), align 1 // CHECK: call [1 x <4 x i32>] @func_v1(<4 x i32> inreg %[[TMP]]) struct v1 global_v1; void call_v1(void) { global_v1 = func_v1(global_v1); } // CHECK-LABEL: @call_v2 -// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>]* getelementptr inbounds (%struct.v2* @global_v2, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>], [2 x <4 x i32>]* getelementptr inbounds (%struct.v2, %struct.v2* @global_v2, i32 0, i32 0), align 1 // CHECK: call [2 x <4 x i32>] @func_v2([2 x <4 x i32>] %[[TMP]]) struct v2 global_v2; void call_v2(void) { global_v2 = func_v2(global_v2); } // CHECK-LABEL: @call_v3 -// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>]* getelementptr inbounds (%struct.v3* @global_v3, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>], [3 x <4 x i32>]* getelementptr inbounds (%struct.v3, %struct.v3* @global_v3, i32 0, i32 0), align 1 // CHECK: call [3 x <4 x i32>] @func_v3([3 x <4 x i32>] %[[TMP]]) struct v3 global_v3; void call_v3(void) { global_v3 = func_v3(global_v3); } // CHECK-LABEL: @call_v4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x <4 x i32>]* getelementptr inbounds (%struct.v4* @global_v4, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [4 x <4 x i32>], [4 x <4 x i32>]* getelementptr inbounds (%struct.v4, %struct.v4* @global_v4, i32 0, i32 0), align 1 // CHECK: call [4 x <4 x i32>] @func_v4([4 x <4 x i32>] %[[TMP]]) struct v4 global_v4; void call_v4(void) { global_v4 = func_v4(global_v4); } // CHECK-LABEL: @call_v5 -// CHECK: %[[TMP:[^ ]+]] = load [5 x <4 x i32>]* getelementptr inbounds (%struct.v5* @global_v5, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [5 x <4 x i32>], [5 x <4 x i32>]* getelementptr inbounds (%struct.v5, %struct.v5* @global_v5, i32 0, i32 0), align 1 // CHECK: call [5 x <4 x i32>] @func_v5([5 x <4 x i32>] %[[TMP]]) struct v5 global_v5; void call_v5(void) { global_v5 = func_v5(global_v5); } // CHECK-LABEL: @call_v6 -// CHECK: %[[TMP:[^ ]+]] = load [6 x <4 x i32>]* getelementptr inbounds (%struct.v6* @global_v6, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [6 x <4 x i32>], [6 x <4 x i32>]* getelementptr inbounds (%struct.v6, %struct.v6* @global_v6, i32 0, i32 0), align 1 // CHECK: call [6 x <4 x i32>] @func_v6([6 x <4 x i32>] %[[TMP]]) struct v6 global_v6; void call_v6(void) { global_v6 = func_v6(global_v6); } // CHECK-LABEL: @call_v7 -// CHECK: %[[TMP:[^ ]+]] = load [7 x <4 x i32>]* getelementptr inbounds (%struct.v7* @global_v7, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [7 x <4 x i32>], [7 x <4 x i32>]* getelementptr inbounds (%struct.v7, %struct.v7* @global_v7, i32 0, i32 0), align 1 // CHECK: call [7 x <4 x i32>] @func_v7([7 x <4 x i32>] %[[TMP]]) struct v7 global_v7; void call_v7(void) { global_v7 = func_v7(global_v7); } // CHECK-LABEL: @call_v8 -// CHECK: %[[TMP:[^ ]+]] = load [8 x <4 x i32>]* getelementptr inbounds (%struct.v8* @global_v8, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [8 x <4 x i32>], [8 x <4 x i32>]* getelementptr inbounds (%struct.v8, %struct.v8* @global_v8, i32 0, i32 0), align 1 // CHECK: call [8 x <4 x i32>] @func_v8([8 x <4 x i32>] %[[TMP]]) struct v8 global_v8; void call_v8(void) { global_v8 = func_v8(global_v8); } @@ -225,13 +225,13 @@ struct v9 global_v9; void call_v9(void) { global_v9 = func_v9(global_v9); } // CHECK-LABEL: @call_vab -// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>]* bitcast (%struct.vab* @global_vab to [2 x <4 x i32>]*) +// CHECK: %[[TMP:[^ ]+]] = load [2 x <4 x i32>], [2 x <4 x i32>]* bitcast (%struct.vab* @global_vab to [2 x <4 x i32>]*) // CHECK: call [2 x <4 x i32>] @func_vab([2 x <4 x i32>] %[[TMP]]) struct vab global_vab; void call_vab(void) { global_vab = func_vab(global_vab); } // CHECK-LABEL: @call_vabc -// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>]* bitcast (%struct.vabc* @global_vabc to [3 x <4 x i32>]*) +// CHECK: %[[TMP:[^ ]+]] = load [3 x <4 x i32>], [3 x <4 x i32>]* bitcast (%struct.vabc* @global_vabc to [3 x <4 x i32>]*) // CHECK: call [3 x <4 x i32>] @func_vabc([3 x <4 x i32>] %[[TMP]]) struct vabc global_vabc; void call_vabc(void) { global_vabc = func_vabc(global_vabc); } @@ -289,49 +289,49 @@ struct v3fab func_v3fab(struct v3fab x) { return x; } struct v3fabc func_v3fabc(struct v3fabc x) { return x; } // CHECK-LABEL: @call_v3f1 -// CHECK: %[[TMP:[^ ]+]] = load <3 x float>* getelementptr inbounds (%struct.v3f1* @global_v3f1, i32 0, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load <3 x float>, <3 x float>* getelementptr inbounds (%struct.v3f1, %struct.v3f1* @global_v3f1, i32 0, i32 0, i32 0), align 1 // CHECK: call [1 x <3 x float>] @func_v3f1(<3 x float> inreg %[[TMP]]) struct v3f1 global_v3f1; void call_v3f1(void) { global_v3f1 = func_v3f1(global_v3f1); } // CHECK-LABEL: @call_v3f2 -// CHECK: %[[TMP:[^ ]+]] = load [2 x <3 x float>]* getelementptr inbounds (%struct.v3f2* @global_v3f2, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [2 x <3 x float>], [2 x <3 x float>]* getelementptr inbounds (%struct.v3f2, %struct.v3f2* @global_v3f2, i32 0, i32 0), align 1 // CHECK: call [2 x <3 x float>] @func_v3f2([2 x <3 x float>] %[[TMP]]) struct v3f2 global_v3f2; void call_v3f2(void) { global_v3f2 = func_v3f2(global_v3f2); } // CHECK-LABEL: @call_v3f3 -// CHECK: %[[TMP:[^ ]+]] = load [3 x <3 x float>]* getelementptr inbounds (%struct.v3f3* @global_v3f3, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [3 x <3 x float>], [3 x <3 x float>]* getelementptr inbounds (%struct.v3f3, %struct.v3f3* @global_v3f3, i32 0, i32 0), align 1 // CHECK: call [3 x <3 x float>] @func_v3f3([3 x <3 x float>] %[[TMP]]) struct v3f3 global_v3f3; void call_v3f3(void) { global_v3f3 = func_v3f3(global_v3f3); } // CHECK-LABEL: @call_v3f4 -// CHECK: %[[TMP:[^ ]+]] = load [4 x <3 x float>]* getelementptr inbounds (%struct.v3f4* @global_v3f4, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [4 x <3 x float>], [4 x <3 x float>]* getelementptr inbounds (%struct.v3f4, %struct.v3f4* @global_v3f4, i32 0, i32 0), align 1 // CHECK: call [4 x <3 x float>] @func_v3f4([4 x <3 x float>] %[[TMP]]) struct v3f4 global_v3f4; void call_v3f4(void) { global_v3f4 = func_v3f4(global_v3f4); } // CHECK-LABEL: @call_v3f5 -// CHECK: %[[TMP:[^ ]+]] = load [5 x <3 x float>]* getelementptr inbounds (%struct.v3f5* @global_v3f5, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [5 x <3 x float>], [5 x <3 x float>]* getelementptr inbounds (%struct.v3f5, %struct.v3f5* @global_v3f5, i32 0, i32 0), align 1 // CHECK: call [5 x <3 x float>] @func_v3f5([5 x <3 x float>] %[[TMP]]) struct v3f5 global_v3f5; void call_v3f5(void) { global_v3f5 = func_v3f5(global_v3f5); } // CHECK-LABEL: @call_v3f6 -// CHECK: %[[TMP:[^ ]+]] = load [6 x <3 x float>]* getelementptr inbounds (%struct.v3f6* @global_v3f6, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [6 x <3 x float>], [6 x <3 x float>]* getelementptr inbounds (%struct.v3f6, %struct.v3f6* @global_v3f6, i32 0, i32 0), align 1 // CHECK: call [6 x <3 x float>] @func_v3f6([6 x <3 x float>] %[[TMP]]) struct v3f6 global_v3f6; void call_v3f6(void) { global_v3f6 = func_v3f6(global_v3f6); } // CHECK-LABEL: @call_v3f7 -// CHECK: %[[TMP:[^ ]+]] = load [7 x <3 x float>]* getelementptr inbounds (%struct.v3f7* @global_v3f7, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [7 x <3 x float>], [7 x <3 x float>]* getelementptr inbounds (%struct.v3f7, %struct.v3f7* @global_v3f7, i32 0, i32 0), align 1 // CHECK: call [7 x <3 x float>] @func_v3f7([7 x <3 x float>] %[[TMP]]) struct v3f7 global_v3f7; void call_v3f7(void) { global_v3f7 = func_v3f7(global_v3f7); } // CHECK-LABEL: @call_v3f8 -// CHECK: %[[TMP:[^ ]+]] = load [8 x <3 x float>]* getelementptr inbounds (%struct.v3f8* @global_v3f8, i32 0, i32 0), align 1 +// CHECK: %[[TMP:[^ ]+]] = load [8 x <3 x float>], [8 x <3 x float>]* getelementptr inbounds (%struct.v3f8, %struct.v3f8* @global_v3f8, i32 0, i32 0), align 1 // CHECK: call [8 x <3 x float>] @func_v3f8([8 x <3 x float>] %[[TMP]]) struct v3f8 global_v3f8; void call_v3f8(void) { global_v3f8 = func_v3f8(global_v3f8); } @@ -342,13 +342,13 @@ struct v3f9 global_v3f9; void call_v3f9(void) { global_v3f9 = func_v3f9(global_v3f9); } // CHECK-LABEL: @call_v3fab -// CHECK: %[[TMP:[^ ]+]] = load [2 x <3 x float>]* bitcast (%struct.v3fab* @global_v3fab to [2 x <3 x float>]*) +// CHECK: %[[TMP:[^ ]+]] = load [2 x <3 x float>], [2 x <3 x float>]* bitcast (%struct.v3fab* @global_v3fab to [2 x <3 x float>]*) // CHECK: call [2 x <3 x float>] @func_v3fab([2 x <3 x float>] %[[TMP]]) struct v3fab global_v3fab; void call_v3fab(void) { global_v3fab = func_v3fab(global_v3fab); } // CHECK-LABEL: @call_v3fabc -// CHECK: %[[TMP:[^ ]+]] = load [3 x <3 x float>]* bitcast (%struct.v3fabc* @global_v3fabc to [3 x <3 x float>]*) +// CHECK: %[[TMP:[^ ]+]] = load [3 x <3 x float>], [3 x <3 x float>]* bitcast (%struct.v3fabc* @global_v3fabc to [3 x <3 x float>]*) // CHECK: call [3 x <3 x float>] @func_v3fabc([3 x <3 x float>] %[[TMP]]) struct v3fabc global_v3fabc; void call_v3fabc(void) { global_v3fabc = func_v3fabc(global_v3fabc); } diff --git a/test/CodeGen/ppc64le-varargs-complex.c b/test/CodeGen/ppc64le-varargs-complex.c index b89f462c380a..68dfa0b69f35 100644 --- a/test/CodeGen/ppc64le-varargs-complex.c +++ b/test/CodeGen/ppc64le-varargs-complex.c @@ -8,62 +8,62 @@ void testva (int n, ...) va_list ap; _Complex int i = va_arg(ap, _Complex int); - // CHECK: %[[VAR40:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR41:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR40]], i64 16 + // CHECK: %[[VAR40:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR41:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR40]], i64 16 // CHECK-NEXT: store i8* %[[VAR41]], i8** %[[VAR100]] // CHECK-NEXT: %[[VAR1:[A-Za-z0-9.]+]] = ptrtoint i8* %[[VAR40]] to i64 // CHECK-NEXT: %[[VAR3:[A-Za-z0-9.]+]] = add i64 %[[VAR1]], 8 // CHECK-NEXT: %[[VAR4:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR1]] to i32* // CHECK-NEXT: %[[VAR5:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR3]] to i32* - // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i32* %[[VAR4]] - // CHECK-NEXT: %[[VAR7:[A-Za-z0-9.]+]] = load i32* %[[VAR5]] - // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }* %[[VAR0:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }* %[[VAR0]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR4]] + // CHECK-NEXT: %[[VAR7:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR5]] + // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR0:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR0]], i32 0, i32 1 // CHECK-NEXT: store i32 %[[VAR6]], i32* %[[VAR8]] // CHECK-NEXT: store i32 %[[VAR7]], i32* %[[VAR9]] _Complex short s = va_arg(ap, _Complex short); - // CHECK: %[[VAR50:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR51:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR50]], i64 16 + // CHECK: %[[VAR50:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR51:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR50]], i64 16 // CHECK-NEXT: store i8* %[[VAR51]], i8** %[[VAR100]] // CHECK: %[[VAR11:[A-Za-z0-9.]+]] = ptrtoint i8* %{{[A-Za-z0-9.]+}} to i64 // CHECK-NEXT: %[[VAR13:[A-Za-z0-9.]+]] = add i64 %[[VAR11]], 8 // CHECK-NEXT: %[[VAR14:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR11]] to i16* // CHECK-NEXT: %[[VAR15:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR13]] to i16* - // CHECK-NEXT: %[[VAR16:[A-Za-z0-9.]+]] = load i16* %[[VAR14]] - // CHECK-NEXT: %[[VAR17:[A-Za-z0-9.]+]] = load i16* %[[VAR15]] - // CHECK-NEXT: %[[VAR18:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }* %[[VAR10:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR19:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }* %[[VAR10]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR16:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR14]] + // CHECK-NEXT: %[[VAR17:[A-Za-z0-9.]+]] = load i16, i16* %[[VAR15]] + // CHECK-NEXT: %[[VAR18:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR10:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR19:[A-Za-z0-9.]+]] = getelementptr inbounds { i16, i16 }, { i16, i16 }* %[[VAR10]], i32 0, i32 1 // CHECK-NEXT: store i16 %[[VAR16]], i16* %[[VAR18]] // CHECK-NEXT: store i16 %[[VAR17]], i16* %[[VAR19]] _Complex char c = va_arg(ap, _Complex char); - // CHECK: %[[VAR60:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR61:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR60]], i64 16 + // CHECK: %[[VAR60:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR61:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR60]], i64 16 // CHECK-NEXT: store i8* %[[VAR61]], i8** %[[VAR100]] // CHECK: %[[VAR21:[A-Za-z0-9.]+]] = ptrtoint i8* %{{[A-Za-z0-9.]+}} to i64 // CHECK-NEXT: %[[VAR23:[A-Za-z0-9.]+]] = add i64 %[[VAR21]], 8 // CHECK-NEXT: %[[VAR24:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR21]] to i8* // CHECK-NEXT: %[[VAR25:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR23]] to i8* - // CHECK-NEXT: %[[VAR26:[A-Za-z0-9.]+]] = load i8* %[[VAR24]] - // CHECK-NEXT: %[[VAR27:[A-Za-z0-9.]+]] = load i8* %[[VAR25]] - // CHECK-NEXT: %[[VAR28:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }* %[[VAR20:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }* %[[VAR20]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR26:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR24]] + // CHECK-NEXT: %[[VAR27:[A-Za-z0-9.]+]] = load i8, i8* %[[VAR25]] + // CHECK-NEXT: %[[VAR28:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR20:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR29:[A-Za-z0-9.]+]] = getelementptr inbounds { i8, i8 }, { i8, i8 }* %[[VAR20]], i32 0, i32 1 // CHECK-NEXT: store i8 %[[VAR26]], i8* %[[VAR28]] // CHECK-NEXT: store i8 %[[VAR27]], i8* %[[VAR29]] _Complex float f = va_arg(ap, _Complex float); - // CHECK: %[[VAR70:[A-Za-z0-9.]+]] = load i8** %[[VAR100:[A-Za-z0-9.]+]] - // CHECK-NEXT: %[[VAR71:[A-Za-z0-9.]+]] = getelementptr i8* %[[VAR70]], i64 16 + // CHECK: %[[VAR70:[A-Za-z0-9.]+]] = load i8*, i8** %[[VAR100:[A-Za-z0-9.]+]] + // CHECK-NEXT: %[[VAR71:[A-Za-z0-9.]+]] = getelementptr i8, i8* %[[VAR70]], i64 16 // CHECK-NEXT: store i8* %[[VAR71]], i8** %[[VAR100]] // CHECK: %[[VAR31:[A-Za-z0-9.]+]] = ptrtoint i8* %{{[A-Za-z0-9.]+}} to i64 // CHECK-NEXT: %[[VAR33:[A-Za-z0-9.]+]] = add i64 %[[VAR31]], 8 // CHECK-NEXT: %[[VAR34:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR31]] to float* // CHECK-NEXT: %[[VAR35:[A-Za-z0-9.]+]] = inttoptr i64 %[[VAR33]] to float* - // CHECK-NEXT: %[[VAR36:[A-Za-z0-9.]+]] = load float* %[[VAR34]] - // CHECK-NEXT: %[[VAR37:[A-Za-z0-9.]+]] = load float* %[[VAR35]] - // CHECK-NEXT: %[[VAR38:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }* %[[VAR30:[A-Za-z0-9.]+]], i32 0, i32 0 - // CHECK-NEXT: %[[VAR39:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }* %[[VAR30]], i32 0, i32 1 + // CHECK-NEXT: %[[VAR36:[A-Za-z0-9.]+]] = load float, float* %[[VAR34]] + // CHECK-NEXT: %[[VAR37:[A-Za-z0-9.]+]] = load float, float* %[[VAR35]] + // CHECK-NEXT: %[[VAR38:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR30:[A-Za-z0-9.]+]], i32 0, i32 0 + // CHECK-NEXT: %[[VAR39:[A-Za-z0-9.]+]] = getelementptr inbounds { float, float }, { float, float }* %[[VAR30]], i32 0, i32 1 // CHECK-NEXT: store float %[[VAR36]], float* %[[VAR38]] // CHECK-NEXT: store float %[[VAR37]], float* %[[VAR39]] } diff --git a/test/CodeGen/pr12251.c b/test/CodeGen/pr12251.c index ea74cc6a594d..dd5e4a1f92dd 100644 --- a/test/CodeGen/pr12251.c +++ b/test/CodeGen/pr12251.c @@ -6,6 +6,6 @@ enum e1 g1(enum e1 *x) { } // CHECK-LABEL: define i32 @g1 -// CHECK: load i32* %x, align 4 +// CHECK: load i32, i32* %x, align 4 // CHECK-NOT: range // CHECK: ret diff --git a/test/CodeGen/pr3518.c b/test/CodeGen/pr3518.c index ff8d75e7b90c..5ce6a6570564 100644 --- a/test/CodeGen/pr3518.c +++ b/test/CodeGen/pr3518.c @@ -7,9 +7,9 @@ extern void abort (void); // CHECK: @.compoundliteral = internal global %struct.A { i32 1, i32 2 } -// CHECK: @.compoundliteral1 = internal global %struct.A { i32 3, i32 4 } -// CHECK: @.compoundliteral2 = internal global %struct.B { %struct.A* @.compoundliteral, %struct.A* @.compoundliteral1 } -// CHECK: @.compoundliteral3 = internal global %struct.A { i32 5, i32 6 } +// CHECK: @.compoundliteral.1 = internal global %struct.A { i32 3, i32 4 } +// CHECK: @.compoundliteral.2 = internal global %struct.B { %struct.A* @.compoundliteral, %struct.A* @.compoundliteral.1 } +// CHECK: @.compoundliteral.3 = internal global %struct.A { i32 5, i32 6 } struct A { int i; int j; }; struct B { struct A *a; struct A *b; }; diff --git a/test/CodeGen/pr4349.c b/test/CodeGen/pr4349.c index 016995871a49..e39dc2c517f4 100644 --- a/test/CodeGen/pr4349.c +++ b/test/CodeGen/pr4349.c @@ -21,17 +21,17 @@ struct svar svars1[] = { { &((cpu.pc).w[0]) } }; -// CHECK: @svars2 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr (i8* bitcast (%struct.cpu* @cpu to i8*), i64 1) }] +// CHECK: @svars2 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr (i8, i8* bitcast (%struct.cpu* @cpu to i8*), i64 1) }] struct svar svars2[] = { { &((cpu.pc).b[0][1]) } }; -// CHECK: @svars3 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr (i8* bitcast (%struct.cpu* @cpu to i8*), i64 2) }] +// CHECK: @svars3 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr (i8, i8* bitcast (%struct.cpu* @cpu to i8*), i64 2) }] struct svar svars3[] = { { &((cpu.pc).w[1]) } }; -// CHECK: @svars4 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr (i8* bitcast (%struct.cpu* @cpu to i8*), i64 3) }] +// CHECK: @svars4 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr (i8, i8* bitcast (%struct.cpu* @cpu to i8*), i64 3) }] struct svar svars4[] = { { &((cpu.pc).b[1][1]) } diff --git a/test/CodeGen/pr5406.c b/test/CodeGen/pr5406.c index 0f04a8e069cd..69038ac07f5e 100644 --- a/test/CodeGen/pr5406.c +++ b/test/CodeGen/pr5406.c @@ -6,7 +6,7 @@ typedef struct { char x[3]; } A0; void foo (int i, ...); -// CHECK: call void (i32, ...)* @foo(i32 1, [1 x i32] {{.*}}) +// CHECK: call void (i32, ...) @foo(i32 1, [1 x i32] {{.*}}) int main (void) { A0 a3; diff --git a/test/CodeGen/pragma-comment.c b/test/CodeGen/pragma-comment.c index 221cfc87f919..fbae9d532357 100644 --- a/test/CodeGen/pragma-comment.c +++ b/test/CodeGen/pragma-comment.c @@ -1,23 +1,32 @@ // RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 %s -triple i686-pc-linux -fms-extensions -emit-llvm -o - | FileCheck -check-prefix LINUX %s +// RUN: %clang_cc1 %s -triple x86_64-scei-ps4 -fms-extensions -emit-llvm -o - | FileCheck -check-prefix PS4 %s #pragma comment(lib, "msvcrt.lib") #pragma comment(lib, "kernel32") #pragma comment(lib, "USER32.LIB") +#pragma comment(lib, "with space") #define BAR "2" #pragma comment(linker," /bar=" BAR) +#pragma comment(linker," /foo=\"foo bar\"") // CHECK: !llvm.module.flags = !{{{.*}}} // CHECK: !{{[0-9]+}} = !{i32 6, !"Linker Options", ![[link_opts:[0-9]+]]} -// CHECK: ![[link_opts]] = !{![[msvcrt:[0-9]+]], ![[kernel32:[0-9]+]], ![[USER32:[0-9]+]], ![[bar:[0-9]+]]} +// CHECK: ![[link_opts]] = !{![[msvcrt:[0-9]+]], ![[kernel32:[0-9]+]], ![[USER32:[0-9]+]], ![[space:[0-9]+]], ![[bar:[0-9]+]], ![[foo:[0-9]+]]} // CHECK: ![[msvcrt]] = !{!"/DEFAULTLIB:msvcrt.lib"} // CHECK: ![[kernel32]] = !{!"/DEFAULTLIB:kernel32.lib"} // CHECK: ![[USER32]] = !{!"/DEFAULTLIB:USER32.LIB"} +// CHECK: ![[space]] = !{!"/DEFAULTLIB:\22with space.lib\22"} // CHECK: ![[bar]] = !{!" /bar=2"} +// CHECK: ![[foo]] = !{!" /foo=\22foo bar\22"} // LINUX: !{!"-lmsvcrt.lib"} // LINUX: !{!"-lkernel32"} // LINUX: !{!"-lUSER32.LIB"} // LINUX: !{!" /bar=2"} + +// PS4: !{!"\01msvcrt.lib"} +// PS4: !{!"\01kernel32"} +// PS4: !{!"\01USER32.LIB"} diff --git a/test/CodeGen/private-extern.c b/test/CodeGen/private-extern.c index 2d34d543213d..26b3fcede5ab 100644 --- a/test/CodeGen/private-extern.c +++ b/test/CodeGen/private-extern.c @@ -1,6 +1,7 @@ -// RUN: %clang_cc1 -emit-llvm -o %t %s -// RUN: grep '@g0 = external hidden constant i32' %t -// RUN: grep '@g1 = hidden constant i32 1' %t +// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s + +// CHECK-DAG: @g0 = external hidden constant i32 +// CHECK-DAG: @g1 = hidden constant i32 1 __private_extern__ const int g0; __private_extern__ const int g1 = 1; diff --git a/test/CodeGen/redefine_extname.c b/test/CodeGen/redefine_extname.c index e73a3ad8dfce..a91e5b836ae6 100644 --- a/test/CodeGen/redefine_extname.c +++ b/test/CodeGen/redefine_extname.c @@ -12,4 +12,4 @@ int fish() { return fake() + __PRAGMA_REDEFINE_EXTNAME + name; } // Check that the call to fake() is emitted as a call to real() // CHECK: call i32 @real() // Check that this also works with variables names -// CHECK: load i32* @alias +// CHECK: load i32, i32* @alias diff --git a/test/CodeGen/sanitize-thread-attr.cpp b/test/CodeGen/sanitize-thread-attr.cpp index fe5d81026db2..46cab4dbf92f 100644 --- a/test/CodeGen/sanitize-thread-attr.cpp +++ b/test/CodeGen/sanitize-thread-attr.cpp @@ -22,6 +22,12 @@ __attribute__((no_sanitize_thread)) int NoTSAN2(int *a); int NoTSAN2(int *a) { return *a; } +// WITHOUT: NoTSAN3{{.*}}) [[NOATTR:#[0-9]+]] +// BL: NoTSAN3{{.*}}) [[NOATTR:#[0-9]+]] +// TSAN: NoTSAN3{{.*}}) [[NOATTR:#[0-9]+]] +__attribute__((no_sanitize("thread"))) +int NoTSAN3(int *a) { return *a; } + // WITHOUT: TSANOk{{.*}}) [[NOATTR]] // BL: TSANOk{{.*}}) [[NOATTR]] // TSAN: TSANOk{{.*}}) [[WITH:#[0-9]+]] @@ -46,16 +52,13 @@ int force_instance = TemplateTSANOk<42>() // Check that __cxx_global_var_init* get the sanitize_thread attribute. int global1 = 0; int global2 = *(int*)((char*)&global1+1); -// WITHOUT: @__cxx_global_var_init{{.*}}[[NOATTR_NO_TF:#[0-9]+]] -// BL: @__cxx_global_var_init{{.*}}[[NOATTR_NO_TF:#[0-9]+]] -// TSAN: @__cxx_global_var_init{{.*}}[[WITH_NO_TF:#[0-9]+]] +// WITHOUT: @__cxx_global_var_init{{.*}}[[NOATTR:#[0-9]+]] +// BL: @__cxx_global_var_init{{.*}}[[NOATTR:#[0-9]+]] +// TSAN: @__cxx_global_var_init{{.*}}[[WITH:#[0-9]+]] // WITHOUT: attributes [[NOATTR]] = { nounwind{{.*}} } -// WITHOUT: attributes [[NOATTR_NO_TF]] = { nounwind } // BL: attributes [[NOATTR]] = { nounwind{{.*}} } -// BL: attributes [[NOATTR_NO_TF]] = { nounwind{{.*}} } // TSAN: attributes [[NOATTR]] = { nounwind{{.*}} } // TSAN: attributes [[WITH]] = { nounwind sanitize_thread{{.*}} } -// TSAN: attributes [[WITH_NO_TF]] = { nounwind sanitize_thread } diff --git a/test/CodeGen/sha-builtins.c b/test/CodeGen/sha-builtins.c index 181dba15b539..2b11dedd3451 100644 --- a/test/CodeGen/sha-builtins.c +++ b/test/CodeGen/sha-builtins.c @@ -7,7 +7,7 @@ __m128i test_sha1rnds4(__m128i a, __m128i b) { // CHECK: call <4 x i32> @llvm.x86.sha1rnds4 - return _mm_sha1rnds4_epu32(a, b, 8); + return _mm_sha1rnds4_epu32(a, b, 3); } __m128i test_sha1nexte(__m128i a, __m128i b) { // CHECK: call <4 x i32> @llvm.x86.sha1nexte diff --git a/test/CodeGen/sparcv9-abi.c b/test/CodeGen/sparcv9-abi.c index d4fff81ab6ef..bf447198cdfc 100644 --- a/test/CodeGen/sparcv9-abi.c +++ b/test/CodeGen/sparcv9-abi.c @@ -131,29 +131,29 @@ int f_variable(char *f, ...) { va_start(ap, f); while ((c = *f++)) switch (c) { -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8* %[[CUR]], i32 8 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i32 8 // CHECK-DAG: store i8* %[[NXT]], i8** %ap -// CHECK-DAG: %[[EXT:[^ ]+]] = getelementptr i8* %[[CUR]], i32 4 +// CHECK-DAG: %[[EXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i32 4 // CHECK-DAG: %[[ADR:[^ ]+]] = bitcast i8* %[[EXT]] to i32* -// CHECK-DAG: load i32* %[[ADR]] +// CHECK-DAG: load i32, i32* %[[ADR]] // CHECK: br case 'i': s += va_arg(ap, int); break; -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8* %[[CUR]], i32 8 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i32 8 // CHECK-DAG: store i8* %[[NXT]], i8** %ap // CHECK-DAG: %[[ADR:[^ ]+]] = bitcast i8* %[[CUR]] to i64* -// CHECK-DAG: load i64* %[[ADR]] +// CHECK-DAG: load i64, i64* %[[ADR]] // CHECK: br case 'l': s += va_arg(ap, long); break; -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8* %[[CUR]], i32 8 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i32 8 // CHECK-DAG: store i8* %[[NXT]], i8** %ap // CHECK-DAG: %[[ADR:[^ ]+]] = bitcast i8* %[[CUR]] to %struct.tiny* // CHECK: br @@ -161,8 +161,8 @@ int f_variable(char *f, ...) { s += va_arg(ap, struct tiny).a; break; -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8* %[[CUR]], i32 16 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i32 16 // CHECK-DAG: store i8* %[[NXT]], i8** %ap // CHECK-DAG: %[[ADR:[^ ]+]] = bitcast i8* %[[CUR]] to %struct.small* // CHECK: br @@ -170,11 +170,11 @@ int f_variable(char *f, ...) { s += *va_arg(ap, struct small).a; break; -// CHECK: %[[CUR:[^ ]+]] = load i8** %ap -// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8* %[[CUR]], i32 8 +// CHECK: %[[CUR:[^ ]+]] = load i8*, i8** %ap +// CHECK-DAG: %[[NXT:[^ ]+]] = getelementptr i8, i8* %[[CUR]], i32 8 // CHECK-DAG: store i8* %[[NXT]], i8** %ap // CHECK-DAG: %[[IND:[^ ]+]] = bitcast i8* %[[CUR]] to %struct.medium** -// CHECK-DAG: %[[ADR:[^ ]+]] = load %struct.medium** %[[IND]] +// CHECK-DAG: %[[ADR:[^ ]+]] = load %struct.medium*, %struct.medium** %[[IND]] // CHECK: br case 'm': s += *va_arg(ap, struct medium).a; diff --git a/test/CodeGen/sparcv9-dwarf.c b/test/CodeGen/sparcv9-dwarf.c index 11ac28c31e3b..c75b09fb7d91 100644 --- a/test/CodeGen/sparcv9-dwarf.c +++ b/test/CodeGen/sparcv9-dwarf.c @@ -8,92 +8,92 @@ int test() { } // CHECK-LABEL: define signext i32 @test() -// CHECK: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 0) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 1) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 2) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 3) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 4) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 5) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 6) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 7) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 8) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 9) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 10) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 11) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 12) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 13) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 14) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 15) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 16) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 17) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 18) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 19) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 20) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 21) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 22) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 23) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 24) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 25) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 26) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 27) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 28) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 29) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 30) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 31) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 32) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 33) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 34) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 35) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 36) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 37) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 38) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 39) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 40) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 41) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 42) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 43) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 44) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 45) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 46) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 47) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 48) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 49) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 50) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 51) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 52) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 53) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 54) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 55) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 56) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 57) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 58) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 59) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 60) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 61) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 62) -// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 63) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 64) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 65) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 66) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 67) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 68) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 69) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 70) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 71) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 72) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 73) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 74) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 75) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 76) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 77) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 78) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 79) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 80) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 81) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 82) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 83) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 84) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 85) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 86) -// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8]* @dwarf_reg_size_table, i32 0, i32 87) +// CHECK: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 0) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 1) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 2) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 3) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 4) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 5) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 6) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 7) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 8) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 9) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 10) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 11) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 12) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 13) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 14) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 15) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 16) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 17) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 18) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 19) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 20) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 21) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 22) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 23) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 24) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 25) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 26) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 27) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 28) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 29) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 30) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 31) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 32) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 33) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 34) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 35) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 36) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 37) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 38) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 39) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 40) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 41) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 42) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 43) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 44) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 45) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 46) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 47) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 48) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 49) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 50) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 51) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 52) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 53) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 54) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 55) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 56) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 57) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 58) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 59) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 60) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 61) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 62) +// CHECK-NEXT: store i8 4, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 63) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 64) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 65) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 66) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 67) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 68) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 69) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 70) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 71) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 72) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 73) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 74) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 75) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 76) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 77) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 78) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 79) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 80) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 81) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 82) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 83) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 84) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 85) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 86) +// CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 87) // CHECK-NEXT: ret i32 14 diff --git a/test/CodeGen/sse-builtins.c b/test/CodeGen/sse-builtins.c index 34c2de7d331b..6d66cca24f31 100644 --- a/test/CodeGen/sse-builtins.c +++ b/test/CodeGen/sse-builtins.c @@ -36,7 +36,7 @@ __m128 test_sqrt_ss(__m128 x) { __m128 test_loadl_pi(__m128 x, void* y) { // CHECK: define {{.*}} @test_loadl_pi - // CHECK: load <2 x float>* {{.*}}, align 1{{$}} + // CHECK: load <2 x float>, <2 x float>* {{.*}}, align 1{{$}} // CHECK: shufflevector {{.*}} <4 x i32> <i32 0, i32 1 // CHECK: shufflevector {{.*}} <4 x i32> <i32 4, i32 5, i32 2, i32 3> return _mm_loadl_pi(x,y); @@ -44,7 +44,7 @@ __m128 test_loadl_pi(__m128 x, void* y) { __m128 test_loadh_pi(__m128 x, void* y) { // CHECK: define {{.*}} @test_loadh_pi - // CHECK: load <2 x float>* {{.*}}, align 1{{$}} + // CHECK: load <2 x float>, <2 x float>* {{.*}}, align 1{{$}} // CHECK: shufflevector {{.*}} <4 x i32> <i32 0, i32 1 // CHECK: shufflevector {{.*}} <4 x i32> <i32 0, i32 1, i32 4, i32 5> return _mm_loadh_pi(x,y); @@ -52,13 +52,13 @@ __m128 test_loadh_pi(__m128 x, void* y) { __m128 test_load_ss(void* y) { // CHECK: define {{.*}} @test_load_ss - // CHECK: load float* {{.*}}, align 1{{$}} + // CHECK: load float, float* {{.*}}, align 1{{$}} return _mm_load_ss(y); } __m128 test_load1_ps(void* y) { // CHECK: define {{.*}} @test_load1_ps - // CHECK: load float* {{.*}}, align 1{{$}} + // CHECK: load float, float* {{.*}}, align 1{{$}} return _mm_load1_ps(y); } @@ -70,31 +70,31 @@ void test_store_ss(__m128 x, void* y) { __m128d test_load1_pd(__m128 x, void* y) { // CHECK: define {{.*}} @test_load1_pd - // CHECK: load double* {{.*}}, align 1{{$}} + // CHECK: load double, double* {{.*}}, align 1{{$}} return _mm_load1_pd(y); } __m128d test_loadr_pd(__m128 x, void* y) { // CHECK: define {{.*}} @test_loadr_pd - // CHECK: load <2 x double>* {{.*}}, align 16{{$}} + // CHECK: load <2 x double>, <2 x double>* {{.*}}, align 16{{$}} return _mm_loadr_pd(y); } __m128d test_load_sd(void* y) { // CHECK: define {{.*}} @test_load_sd - // CHECK: load double* {{.*}}, align 1{{$}} + // CHECK: load double, double* {{.*}}, align 1{{$}} return _mm_load_sd(y); } __m128d test_loadh_pd(__m128d x, void* y) { // CHECK: define {{.*}} @test_loadh_pd - // CHECK: load double* {{.*}}, align 1{{$}} + // CHECK: load double, double* {{.*}}, align 1{{$}} return _mm_loadh_pd(x, y); } __m128d test_loadl_pd(__m128d x, void* y) { // CHECK: define {{.*}} @test_loadl_pd - // CHECK: load double* {{.*}}, align 1{{$}} + // CHECK: load double, double* {{.*}}, align 1{{$}} return _mm_loadl_pd(x, y); } @@ -131,7 +131,7 @@ void test_storel_pd(__m128d x, void* y) { __m128i test_loadl_epi64(void* y) { // CHECK: define {{.*}} @test_loadl_epi64 - // CHECK: load i64* {{.*}}, align 1{{$}} + // CHECK: load i64, i64* {{.*}}, align 1{{$}} return _mm_loadl_epi64(y); } @@ -543,3 +543,37 @@ __m128d test_mm_cmpnge_pd(__m128d __a, __m128d __b) { // CHECK: @llvm.x86.sse2.cmp.pd(<2 x double> %{{.*}}, <2 x double> %{{.*}}, i8 6) return _mm_cmpnge_pd(__a, __b); } + +__m128 test_mm_slli_si128(__m128 a) { + // CHECK-LABEL: @test_mm_slli_si128 + // CHECK: shufflevector <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26> + return _mm_slli_si128(a, 5); +} + +__m128 test_mm_bslli_si128(__m128 a) { + // CHECK-LABEL: @test_mm_bslli_si128 + // CHECK: shufflevector <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26> + return _mm_bslli_si128(a, 5); +} + +__m128 test_mm_srli_si128(__m128 a) { + // CHECK-LABEL: @test_mm_srli_si128 + // CHECK: shufflevector <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20> + return _mm_srli_si128(a, 5); +} + +__m128 test_mm_bsrli_si128(__m128 a) { + // CHECK-LABEL: @test_mm_bsrli_si128 + // CHECK: shufflevector <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20> + return _mm_bsrli_si128(a, 5); +} + +__m128i test_mm_alignr_epi8(__m128i a, __m128i b) { + // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17> + return _mm_alignr_epi8(a, b, 2); +} + +__m128i test2_mm_alignr_epi8(__m128i a, __m128i b) { + // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16> + return _mm_alignr_epi8(a, b, 17); +} diff --git a/test/CodeGen/sse.c b/test/CodeGen/sse.c new file mode 100644 index 000000000000..17cce69d8466 --- /dev/null +++ b/test/CodeGen/sse.c @@ -0,0 +1,40 @@ +// RUN: %clang_cc1 -O3 -ffreestanding -triple x86_64-apple-macosx10.8.0 -target-feature +sse4.1 -emit-llvm %s -o - | FileCheck %s + +#include <emmintrin.h> + +// Byte-shifts look reversed due to xmm register layout +__m128 test_mm_slli_si128(__m128 a) { + // CHECK-LABEL: @test_mm_slli_si128 + // CHECK: shufflevector <16 x i8> <{{.*}}, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> {{.*}}, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26> + return _mm_slli_si128(a, 5); +} + +__m128 test_mm_slli_si128_0(__m128 a) { + // CHECK-LABEL: @test_mm_slli_si128_0 + // CHECK-NOT: shufflevector + return _mm_slli_si128(a, 0); +} + +__m128 test_mm_slli_si128_16(__m128 a) { + // CHECK-LABEL: @test_mm_slli_si128_16 + // CHECK-NOT: shufflevector + return _mm_slli_si128(a, 16); +} + +__m128 test_mm_srli_si128(__m128 a) { + // CHECK-LABEL: @test_mm_srli_si128 + // CHECK: shufflevector <16 x i8> {{.*}}, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, {{.*}}>, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20> + return _mm_srli_si128(a, 5); +} + +__m128 test_mm_srli_si128_0(__m128 a) { + // CHECK-LABEL: @test_mm_srli_si128_0 + // CHECK-NOT: shufflevector + return _mm_srli_si128(a, 0); +} + +__m128 test_mm_srli_si128_16(__m128 a) { + // CHECK-LABEL: @test_mm_srli_si128_16 + // CHECK-NOT: shufflevector + return _mm_srli_si128(a, 16); +} diff --git a/test/CodeGen/systemz-abi-vector.c b/test/CodeGen/systemz-abi-vector.c new file mode 100644 index 000000000000..1d1f302e6324 --- /dev/null +++ b/test/CodeGen/systemz-abi-vector.c @@ -0,0 +1,590 @@ +// RUN: %clang_cc1 -triple s390x-linux-gnu \ +// RUN: -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-feature +vector \ +// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 \ +// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s + +// Vector types + +typedef __attribute__((vector_size(1))) char v1i8; + +typedef __attribute__((vector_size(2))) char v2i8; +typedef __attribute__((vector_size(2))) short v1i16; + +typedef __attribute__((vector_size(4))) char v4i8; +typedef __attribute__((vector_size(4))) short v2i16; +typedef __attribute__((vector_size(4))) int v1i32; +typedef __attribute__((vector_size(4))) float v1f32; + +typedef __attribute__((vector_size(8))) char v8i8; +typedef __attribute__((vector_size(8))) short v4i16; +typedef __attribute__((vector_size(8))) int v2i32; +typedef __attribute__((vector_size(8))) long long v1i64; +typedef __attribute__((vector_size(8))) float v2f32; +typedef __attribute__((vector_size(8))) double v1f64; + +typedef __attribute__((vector_size(16))) char v16i8; +typedef __attribute__((vector_size(16))) short v8i16; +typedef __attribute__((vector_size(16))) int v4i32; +typedef __attribute__((vector_size(16))) long long v2i64; +typedef __attribute__((vector_size(16))) __int128 v1i128; +typedef __attribute__((vector_size(16))) float v4f32; +typedef __attribute__((vector_size(16))) double v2f64; +typedef __attribute__((vector_size(16))) long double v1f128; + +typedef __attribute__((vector_size(32))) char v32i8; + +unsigned int align = __alignof__ (v16i8); +// CHECK: @align = global i32 16 +// CHECK-VECTOR: @align = global i32 8 + +v1i8 pass_v1i8(v1i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1i8(<1 x i8>* noalias sret %{{.*}}, <1 x i8>*) +// CHECK-VECTOR-LABEL: define <1 x i8> @pass_v1i8(<1 x i8> %{{.*}}) + +v2i8 pass_v2i8(v2i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_v2i8(<2 x i8>* noalias sret %{{.*}}, <2 x i8>*) +// CHECK-VECTOR-LABEL: define <2 x i8> @pass_v2i8(<2 x i8> %{{.*}}) + +v4i8 pass_v4i8(v4i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_v4i8(<4 x i8>* noalias sret %{{.*}}, <4 x i8>*) +// CHECK-VECTOR-LABEL: define <4 x i8> @pass_v4i8(<4 x i8> %{{.*}}) + +v8i8 pass_v8i8(v8i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_v8i8(<8 x i8>* noalias sret %{{.*}}, <8 x i8>*) +// CHECK-VECTOR-LABEL: define <8 x i8> @pass_v8i8(<8 x i8> %{{.*}}) + +v16i8 pass_v16i8(v16i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_v16i8(<16 x i8>* noalias sret %{{.*}}, <16 x i8>*) +// CHECK-VECTOR-LABEL: define <16 x i8> @pass_v16i8(<16 x i8> %{{.*}}) + +v32i8 pass_v32i8(v32i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_v32i8(<32 x i8>* noalias sret %{{.*}}, <32 x i8>*) +// CHECK-VECTOR-LABEL: define void @pass_v32i8(<32 x i8>* noalias sret %{{.*}}, <32 x i8>*) + +v1i16 pass_v1i16(v1i16 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1i16(<1 x i16>* noalias sret %{{.*}}, <1 x i16>*) +// CHECK-VECTOR-LABEL: define <1 x i16> @pass_v1i16(<1 x i16> %{{.*}}) + +v2i16 pass_v2i16(v2i16 arg) { return arg; } +// CHECK-LABEL: define void @pass_v2i16(<2 x i16>* noalias sret %{{.*}}, <2 x i16>*) +// CHECK-VECTOR-LABEL: define <2 x i16> @pass_v2i16(<2 x i16> %{{.*}}) + +v4i16 pass_v4i16(v4i16 arg) { return arg; } +// CHECK-LABEL: define void @pass_v4i16(<4 x i16>* noalias sret %{{.*}}, <4 x i16>*) +// CHECK-VECTOR-LABEL: define <4 x i16> @pass_v4i16(<4 x i16> %{{.*}}) + +v8i16 pass_v8i16(v8i16 arg) { return arg; } +// CHECK-LABEL: define void @pass_v8i16(<8 x i16>* noalias sret %{{.*}}, <8 x i16>*) +// CHECK-VECTOR-LABEL: define <8 x i16> @pass_v8i16(<8 x i16> %{{.*}}) + +v1i32 pass_v1i32(v1i32 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1i32(<1 x i32>* noalias sret %{{.*}}, <1 x i32>*) +// CHECK-VECTOR-LABEL: define <1 x i32> @pass_v1i32(<1 x i32> %{{.*}}) + +v2i32 pass_v2i32(v2i32 arg) { return arg; } +// CHECK-LABEL: define void @pass_v2i32(<2 x i32>* noalias sret %{{.*}}, <2 x i32>*) +// CHECK-VECTOR-LABEL: define <2 x i32> @pass_v2i32(<2 x i32> %{{.*}}) + +v4i32 pass_v4i32(v4i32 arg) { return arg; } +// CHECK-LABEL: define void @pass_v4i32(<4 x i32>* noalias sret %{{.*}}, <4 x i32>*) +// CHECK-VECTOR-LABEL: define <4 x i32> @pass_v4i32(<4 x i32> %{{.*}}) + +v1i64 pass_v1i64(v1i64 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1i64(<1 x i64>* noalias sret %{{.*}}, <1 x i64>*) +// CHECK-VECTOR-LABEL: define <1 x i64> @pass_v1i64(<1 x i64> %{{.*}}) + +v2i64 pass_v2i64(v2i64 arg) { return arg; } +// CHECK-LABEL: define void @pass_v2i64(<2 x i64>* noalias sret %{{.*}}, <2 x i64>*) +// CHECK-VECTOR-LABEL: define <2 x i64> @pass_v2i64(<2 x i64> %{{.*}}) + +v1i128 pass_v1i128(v1i128 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1i128(<1 x i128>* noalias sret %{{.*}}, <1 x i128>*) +// CHECK-VECTOR-LABEL: define <1 x i128> @pass_v1i128(<1 x i128> %{{.*}}) + +v1f32 pass_v1f32(v1f32 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1f32(<1 x float>* noalias sret %{{.*}}, <1 x float>*) +// CHECK-VECTOR-LABEL: define <1 x float> @pass_v1f32(<1 x float> %{{.*}}) + +v2f32 pass_v2f32(v2f32 arg) { return arg; } +// CHECK-LABEL: define void @pass_v2f32(<2 x float>* noalias sret %{{.*}}, <2 x float>*) +// CHECK-VECTOR-LABEL: define <2 x float> @pass_v2f32(<2 x float> %{{.*}}) + +v4f32 pass_v4f32(v4f32 arg) { return arg; } +// CHECK-LABEL: define void @pass_v4f32(<4 x float>* noalias sret %{{.*}}, <4 x float>*) +// CHECK-VECTOR-LABEL: define <4 x float> @pass_v4f32(<4 x float> %{{.*}}) + +v1f64 pass_v1f64(v1f64 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1f64(<1 x double>* noalias sret %{{.*}}, <1 x double>*) +// CHECK-VECTOR-LABEL: define <1 x double> @pass_v1f64(<1 x double> %{{.*}}) + +v2f64 pass_v2f64(v2f64 arg) { return arg; } +// CHECK-LABEL: define void @pass_v2f64(<2 x double>* noalias sret %{{.*}}, <2 x double>*) +// CHECK-VECTOR-LABEL: define <2 x double> @pass_v2f64(<2 x double> %{{.*}}) + +v1f128 pass_v1f128(v1f128 arg) { return arg; } +// CHECK-LABEL: define void @pass_v1f128(<1 x fp128>* noalias sret %{{.*}}, <1 x fp128>*) +// CHECK-VECTOR-LABEL: define <1 x fp128> @pass_v1f128(<1 x fp128> %{{.*}}) + + +// Vector-like aggregate types + +struct agg_v1i8 { v1i8 a; }; +struct agg_v1i8 pass_agg_v1i8(struct agg_v1i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret %{{.*}}, i8 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_v1i8(%struct.agg_v1i8* noalias sret %{{.*}}, <1 x i8> %{{.*}}) + +struct agg_v2i8 { v2i8 a; }; +struct agg_v2i8 pass_agg_v2i8(struct agg_v2i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret %{{.*}}, i16 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_v2i8(%struct.agg_v2i8* noalias sret %{{.*}}, <2 x i8> %{{.*}}) + +struct agg_v4i8 { v4i8 a; }; +struct agg_v4i8 pass_agg_v4i8(struct agg_v4i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret %{{.*}}, i32 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_v4i8(%struct.agg_v4i8* noalias sret %{{.*}}, <4 x i8> %{{.*}}) + +struct agg_v8i8 { v8i8 a; }; +struct agg_v8i8 pass_agg_v8i8(struct agg_v8i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_v8i8(%struct.agg_v8i8* noalias sret %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_v8i8(%struct.agg_v8i8* noalias sret %{{.*}}, <8 x i8> %{{.*}}) + +struct agg_v16i8 { v16i8 a; }; +struct agg_v16i8 pass_agg_v16i8(struct agg_v16i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_v16i8(%struct.agg_v16i8* noalias sret %{{.*}}, %struct.agg_v16i8* %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_v16i8(%struct.agg_v16i8* noalias sret %{{.*}}, <16 x i8> %{{.*}}) + +struct agg_v32i8 { v32i8 a; }; +struct agg_v32i8 pass_agg_v32i8(struct agg_v32i8 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_v32i8(%struct.agg_v32i8* noalias sret %{{.*}}, %struct.agg_v32i8* %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_v32i8(%struct.agg_v32i8* noalias sret %{{.*}}, %struct.agg_v32i8* %{{.*}}) + + +// Verify that the following are *not* vector-like aggregate types + +struct agg_novector1 { v4i8 a; v4i8 b; }; +struct agg_novector1 pass_agg_novector1(struct agg_novector1 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_novector1(%struct.agg_novector1* noalias sret %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_novector1(%struct.agg_novector1* noalias sret %{{.*}}, i64 %{{.*}}) + +struct agg_novector2 { v4i8 a; float b; }; +struct agg_novector2 pass_agg_novector2(struct agg_novector2 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_novector2(%struct.agg_novector2* noalias sret %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_novector2(%struct.agg_novector2* noalias sret %{{.*}}, i64 %{{.*}}) + +struct agg_novector3 { v4i8 a; int : 0; }; +struct agg_novector3 pass_agg_novector3(struct agg_novector3 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_novector3(%struct.agg_novector3* noalias sret %{{.*}}, i32 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_novector3(%struct.agg_novector3* noalias sret %{{.*}}, i32 %{{.*}}) + +struct agg_novector4 { v4i8 a __attribute__((aligned (8))); }; +struct agg_novector4 pass_agg_novector4(struct agg_novector4 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_novector4(%struct.agg_novector4* noalias sret %{{.*}}, i64 %{{.*}}) +// CHECK-VECTOR-LABEL: define void @pass_agg_novector4(%struct.agg_novector4* noalias sret %{{.*}}, i64 %{{.*}}) + + +// Accessing variable argument lists + +v1i8 va_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, v1i8); } +// CHECK-LABEL: define void @va_v1i8(<1 x i8>* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to <1 x i8>** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to <1 x i8>** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi <1 x i8>** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load <1 x i8>*, <1 x i8>** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define <1 x i8> @va_v1i8(%struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to <1 x i8>* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[RET:%[^ ]+]] = load <1 x i8>, <1 x i8>* [[MEM_ADDR]] +// CHECK-VECTOR: ret <1 x i8> [[RET]] + +v2i8 va_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, v2i8); } +// CHECK-LABEL: define void @va_v2i8(<2 x i8>* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to <2 x i8>** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to <2 x i8>** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi <2 x i8>** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load <2 x i8>*, <2 x i8>** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define <2 x i8> @va_v2i8(%struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to <2 x i8>* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[RET:%[^ ]+]] = load <2 x i8>, <2 x i8>* [[MEM_ADDR]] +// CHECK-VECTOR: ret <2 x i8> [[RET]] + +v4i8 va_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, v4i8); } +// CHECK-LABEL: define void @va_v4i8(<4 x i8>* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to <4 x i8>** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to <4 x i8>** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi <4 x i8>** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load <4 x i8>*, <4 x i8>** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define <4 x i8> @va_v4i8(%struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to <4 x i8>* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[RET:%[^ ]+]] = load <4 x i8>, <4 x i8>* [[MEM_ADDR]] +// CHECK-VECTOR: ret <4 x i8> [[RET]] + +v8i8 va_v8i8(__builtin_va_list l) { return __builtin_va_arg(l, v8i8); } +// CHECK-LABEL: define void @va_v8i8(<8 x i8>* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to <8 x i8>** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to <8 x i8>** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi <8 x i8>** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load <8 x i8>*, <8 x i8>** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define <8 x i8> @va_v8i8(%struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to <8 x i8>* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[RET:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[MEM_ADDR]] +// CHECK-VECTOR: ret <8 x i8> [[RET]] + +v16i8 va_v16i8(__builtin_va_list l) { return __builtin_va_arg(l, v16i8); } +// CHECK-LABEL: define void @va_v16i8(<16 x i8>* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to <16 x i8>** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to <16 x i8>** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi <16 x i8>** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load <16 x i8>*, <16 x i8>** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define <16 x i8> @va_v16i8(%struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to <16 x i8>* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 16 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[RET:%[^ ]+]] = load <16 x i8>, <16 x i8>* [[MEM_ADDR]] +// CHECK-VECTOR: ret <16 x i8> [[RET]] + +v32i8 va_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, v32i8); } +// CHECK-LABEL: define void @va_v32i8(<32 x i8>* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to <32 x i8>** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to <32 x i8>** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi <32 x i8>** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load <32 x i8>*, <32 x i8>** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define void @va_v32i8(<32 x i8>* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK-VECTOR: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK-VECTOR: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK-VECTOR: br i1 [[FITS_IN_REGS]], +// CHECK-VECTOR: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK-VECTOR: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK-VECTOR: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK-VECTOR: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK-VECTOR: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK-VECTOR: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to <32 x i8>** +// CHECK-VECTOR: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK-VECTOR: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to <32 x i8>** +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[VA_ARG_ADDR:%[^ ]+]] = phi <32 x i8>** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK-VECTOR: [[INDIRECT_ARG:%[^ ]+]] = load <32 x i8>*, <32 x i8>** [[VA_ARG_ADDR]] +// CHECK-VECTOR: ret void + +struct agg_v1i8 va_agg_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v1i8); } +// CHECK-LABEL: define void @va_agg_v1i8(%struct.agg_v1i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 23 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_v1i8* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 7 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_v1i8* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_v1i8* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define void @va_agg_v1i8(%struct.agg_v1i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to %struct.agg_v1i8* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: ret void + +struct agg_v2i8 va_agg_v2i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v2i8); } +// CHECK-LABEL: define void @va_agg_v2i8(%struct.agg_v2i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 22 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_v2i8* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 6 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_v2i8* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_v2i8* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define void @va_agg_v2i8(%struct.agg_v2i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to %struct.agg_v2i8* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: ret void + +struct agg_v4i8 va_agg_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v4i8); } +// CHECK-LABEL: define void @va_agg_v4i8(%struct.agg_v4i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 20 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_v4i8* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 4 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_v4i8* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_v4i8* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define void @va_agg_v4i8(%struct.agg_v4i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to %struct.agg_v4i8* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: ret void + +struct agg_v8i8 va_agg_v8i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v8i8); } +// CHECK-LABEL: define void @va_agg_v8i8(%struct.agg_v8i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_v8i8* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_v8i8* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_v8i8* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define void @va_agg_v8i8(%struct.agg_v8i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to %struct.agg_v8i8* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: ret void + +struct agg_v16i8 va_agg_v16i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v16i8); } +// CHECK-LABEL: define void @va_agg_v16i8(%struct.agg_v16i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_v16i8** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_v16i8** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_v16i8** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load %struct.agg_v16i8*, %struct.agg_v16i8** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define void @va_agg_v16i8(%struct.agg_v16i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[OVERFLOW_ARG_AREA]] to %struct.agg_v16i8* +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA1:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 16 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA1]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: ret void + +struct agg_v32i8 va_agg_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_v32i8); } +// CHECK-LABEL: define void @va_agg_v32i8(%struct.agg_v32i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_v32i8** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_v32i8** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_v32i8** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load %struct.agg_v32i8*, %struct.agg_v32i8** [[VA_ARG_ADDR]] +// CHECK: ret void +// CHECK-VECTOR-LABEL: define void @va_agg_v32i8(%struct.agg_v32i8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK-VECTOR: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK-VECTOR: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK-VECTOR: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK-VECTOR: br i1 [[FITS_IN_REGS]], +// CHECK-VECTOR: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK-VECTOR: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK-VECTOR: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK-VECTOR: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK-VECTOR: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK-VECTOR: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_v32i8** +// CHECK-VECTOR: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK-VECTOR: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK-VECTOR: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_v32i8** +// CHECK-VECTOR: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK-VECTOR: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK-VECTOR: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_v32i8** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK-VECTOR: [[INDIRECT_ARG:%[^ ]+]] = load %struct.agg_v32i8*, %struct.agg_v32i8** [[VA_ARG_ADDR]] +// CHECK-VECTOR: ret void diff --git a/test/CodeGen/systemz-abi.c b/test/CodeGen/systemz-abi.c new file mode 100644 index 000000000000..375d02a35889 --- /dev/null +++ b/test/CodeGen/systemz-abi.c @@ -0,0 +1,591 @@ +// RUN: %clang_cc1 -triple s390x-linux-gnu \ +// RUN: -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-feature +vector \ +// RUN: -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 \ +// RUN: -emit-llvm -o - %s | FileCheck %s + +// Scalar types + +char pass_char(char arg) { return arg; } +// CHECK-LABEL: define signext i8 @pass_char(i8 signext %{{.*}}) + +short pass_short(short arg) { return arg; } +// CHECK-LABEL: define signext i16 @pass_short(i16 signext %{{.*}}) + +int pass_int(int arg) { return arg; } +// CHECK-LABEL: define signext i32 @pass_int(i32 signext %{{.*}}) + +long pass_long(long arg) { return arg; } +// CHECK-LABEL: define i64 @pass_long(i64 %{{.*}}) + +long long pass_longlong(long long arg) { return arg; } +// CHECK-LABEL: define i64 @pass_longlong(i64 %{{.*}}) + +__int128 pass_int128(__int128 arg) { return arg; } +// CHECK-LABEL: define void @pass_int128(i128* noalias sret %{{.*}}, i128*) + +float pass_float(float arg) { return arg; } +// CHECK-LABEL: define float @pass_float(float %{{.*}}) + +double pass_double(double arg) { return arg; } +// CHECK-LABEL: define double @pass_double(double %{{.*}}) + +long double pass_longdouble(long double arg) { return arg; } +// CHECK-LABEL: define void @pass_longdouble(fp128* noalias sret %{{.*}}, fp128*) + + +// Complex types + +_Complex char pass_complex_char(_Complex char arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_char({ i8, i8 }* noalias sret %{{.*}}, { i8, i8 }* %{{.*}}arg) + +_Complex short pass_complex_short(_Complex short arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_short({ i16, i16 }* noalias sret %{{.*}}, { i16, i16 }* %{{.*}}arg) + +_Complex int pass_complex_int(_Complex int arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_int({ i32, i32 }* noalias sret %{{.*}}, { i32, i32 }* %{{.*}}arg) + +_Complex long pass_complex_long(_Complex long arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_long({ i64, i64 }* noalias sret %{{.*}}, { i64, i64 }* %{{.*}}arg) + +_Complex long long pass_complex_longlong(_Complex long long arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_longlong({ i64, i64 }* noalias sret %{{.*}}, { i64, i64 }* %{{.*}}arg) + +_Complex float pass_complex_float(_Complex float arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_float({ float, float }* noalias sret %{{.*}}, { float, float }* %{{.*}}arg) + +_Complex double pass_complex_double(_Complex double arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_double({ double, double }* noalias sret %{{.*}}, { double, double }* %{{.*}}arg) + +_Complex long double pass_complex_longdouble(_Complex long double arg) { return arg; } +// CHECK-LABEL: define void @pass_complex_longdouble({ fp128, fp128 }* noalias sret %{{.*}}, { fp128, fp128 }* %{{.*}}arg) + + +// Aggregate types + +struct agg_1byte { char a[1]; }; +struct agg_1byte pass_agg_1byte(struct agg_1byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_1byte(%struct.agg_1byte* noalias sret %{{.*}}, i8 %{{.*}}) + +struct agg_2byte { char a[2]; }; +struct agg_2byte pass_agg_2byte(struct agg_2byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_2byte(%struct.agg_2byte* noalias sret %{{.*}}, i16 %{{.*}}) + +struct agg_3byte { char a[3]; }; +struct agg_3byte pass_agg_3byte(struct agg_3byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_3byte(%struct.agg_3byte* noalias sret %{{.*}}, %struct.agg_3byte* %{{.*}}) + +struct agg_4byte { char a[4]; }; +struct agg_4byte pass_agg_4byte(struct agg_4byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_4byte(%struct.agg_4byte* noalias sret %{{.*}}, i32 %{{.*}}) + +struct agg_5byte { char a[5]; }; +struct agg_5byte pass_agg_5byte(struct agg_5byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_5byte(%struct.agg_5byte* noalias sret %{{.*}}, %struct.agg_5byte* %{{.*}}) + +struct agg_6byte { char a[6]; }; +struct agg_6byte pass_agg_6byte(struct agg_6byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_6byte(%struct.agg_6byte* noalias sret %{{.*}}, %struct.agg_6byte* %{{.*}}) + +struct agg_7byte { char a[7]; }; +struct agg_7byte pass_agg_7byte(struct agg_7byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_7byte(%struct.agg_7byte* noalias sret %{{.*}}, %struct.agg_7byte* %{{.*}}) + +struct agg_8byte { char a[8]; }; +struct agg_8byte pass_agg_8byte(struct agg_8byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_8byte(%struct.agg_8byte* noalias sret %{{.*}}, i64 %{{.*}}) + +struct agg_16byte { char a[16]; }; +struct agg_16byte pass_agg_16byte(struct agg_16byte arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_16byte(%struct.agg_16byte* noalias sret %{{.*}}, %struct.agg_16byte* %{{.*}}) + + +// Float-like aggregate types + +struct agg_float { float a; }; +struct agg_float pass_agg_float(struct agg_float arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_float(%struct.agg_float* noalias sret %{{.*}}, float %{{.*}}) + +struct agg_double { double a; }; +struct agg_double pass_agg_double(struct agg_double arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_double(%struct.agg_double* noalias sret %{{.*}}, double %{{.*}}) + +struct agg_longdouble { long double a; }; +struct agg_longdouble pass_agg_longdouble(struct agg_longdouble arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_longdouble(%struct.agg_longdouble* noalias sret %{{.*}}, %struct.agg_longdouble* %{{.*}}) + +struct agg_float_a8 { float a __attribute__((aligned (8))); }; +struct agg_float_a8 pass_agg_float_a8(struct agg_float_a8 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_float_a8(%struct.agg_float_a8* noalias sret %{{.*}}, double %{{.*}}) + +struct agg_float_a16 { float a __attribute__((aligned (16))); }; +struct agg_float_a16 pass_agg_float_a16(struct agg_float_a16 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_float_a16(%struct.agg_float_a16* noalias sret %{{.*}}, %struct.agg_float_a16* %{{.*}}) + + +// Verify that the following are *not* float-like aggregate types + +struct agg_nofloat1 { float a; float b; }; +struct agg_nofloat1 pass_agg_nofloat1(struct agg_nofloat1 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_nofloat1(%struct.agg_nofloat1* noalias sret %{{.*}}, i64 %{{.*}}) + +struct agg_nofloat2 { float a; int b; }; +struct agg_nofloat2 pass_agg_nofloat2(struct agg_nofloat2 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_nofloat2(%struct.agg_nofloat2* noalias sret %{{.*}}, i64 %{{.*}}) + +struct agg_nofloat3 { float a; int : 0; }; +struct agg_nofloat3 pass_agg_nofloat3(struct agg_nofloat3 arg) { return arg; } +// CHECK-LABEL: define void @pass_agg_nofloat3(%struct.agg_nofloat3* noalias sret %{{.*}}, i32 %{{.*}}) + + +// Accessing variable argument lists + +int va_int(__builtin_va_list l) { return __builtin_va_arg(l, int); } +// CHECK-LABEL: define signext i32 @va_int(%struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 20 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to i32* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 4 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to i32* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi i32* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[RET:%[^ ]+]] = load i32, i32* [[VA_ARG_ADDR]] +// CHECK: ret i32 [[RET]] + +long va_long(__builtin_va_list l) { return __builtin_va_arg(l, long); } +// CHECK-LABEL: define i64 @va_long(%struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to i64* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to i64* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi i64* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[RET:%[^ ]+]] = load i64, i64* [[VA_ARG_ADDR]] +// CHECK: ret i64 [[RET]] + +long long va_longlong(__builtin_va_list l) { return __builtin_va_arg(l, long long); } +// CHECK-LABEL: define i64 @va_longlong(%struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to i64* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to i64* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi i64* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[RET:%[^ ]+]] = load i64, i64* [[VA_ARG_ADDR]] +// CHECK: ret i64 [[RET]] + +double va_double(__builtin_va_list l) { return __builtin_va_arg(l, double); } +// CHECK-LABEL: define double @va_double(%struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 1 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 4 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 128 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to double* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to double* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi double* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[RET:%[^ ]+]] = load double, double* [[VA_ARG_ADDR]] +// CHECK: ret double [[RET]] + +long double va_longdouble(__builtin_va_list l) { return __builtin_va_arg(l, long double); } +// CHECK-LABEL: define void @va_longdouble(fp128* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}}) +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to fp128** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to fp128** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi fp128** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load fp128*, fp128** [[VA_ARG_ADDR]] +// CHECK: [[RET:%[^ ]+]] = load fp128, fp128* [[INDIRECT_ARG]] +// CHECK: store fp128 [[RET]], fp128* %{{.*}} +// CHECK: ret void + +_Complex char va_complex_char(__builtin_va_list l) { return __builtin_va_arg(l, _Complex char); } +// CHECK-LABEL: define void @va_complex_char({ i8, i8 }* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to { i8, i8 }** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to { i8, i8 }** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi { i8, i8 }** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load { i8, i8 }*, { i8, i8 }** [[VA_ARG_ADDR]] +// CHECK: ret void + +struct agg_1byte va_agg_1byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_1byte); } +// CHECK-LABEL: define void @va_agg_1byte(%struct.agg_1byte* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 23 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_1byte* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 7 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_1byte* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_1byte* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_2byte va_agg_2byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_2byte); } +// CHECK-LABEL: define void @va_agg_2byte(%struct.agg_2byte* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 22 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_2byte* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 6 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_2byte* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_2byte* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_3byte va_agg_3byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_3byte); } +// CHECK-LABEL: define void @va_agg_3byte(%struct.agg_3byte* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_3byte** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_3byte** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_3byte** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load %struct.agg_3byte*, %struct.agg_3byte** [[VA_ARG_ADDR]] +// CHECK: ret void + +struct agg_4byte va_agg_4byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_4byte); } +// CHECK-LABEL: define void @va_agg_4byte(%struct.agg_4byte* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 20 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_4byte* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 4 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_4byte* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_4byte* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_8byte va_agg_8byte(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_8byte); } +// CHECK-LABEL: define void @va_agg_8byte(%struct.agg_8byte* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_8byte* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_8byte* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_8byte* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_float va_agg_float(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_float); } +// CHECK-LABEL: define void @va_agg_float(%struct.agg_float* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 1 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 4 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 128 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_float* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 4 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_float* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_float* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_double va_agg_double(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_double); } +// CHECK-LABEL: define void @va_agg_double(%struct.agg_double* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 1 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 4 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 128 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_double* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_double* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_double* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_longdouble va_agg_longdouble(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_longdouble); } +// CHECK-LABEL: define void @va_agg_longdouble(%struct.agg_longdouble* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_longdouble** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_longdouble** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_longdouble** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load %struct.agg_longdouble*, %struct.agg_longdouble** [[VA_ARG_ADDR]] +// CHECK: ret void + +struct agg_float_a8 va_agg_float_a8(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_float_a8); } +// CHECK-LABEL: define void @va_agg_float_a8(%struct.agg_float_a8* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 1 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 4 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 128 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_float_a8* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_float_a8* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_float_a8* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_float_a16 va_agg_float_a16(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_float_a16); } +// CHECK-LABEL: define void @va_agg_float_a16(%struct.agg_float_a16* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_float_a16** +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_float_a16** +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_float_a16** [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: [[INDIRECT_ARG:%[^ ]+]] = load %struct.agg_float_a16*, %struct.agg_float_a16** [[VA_ARG_ADDR]] +// CHECK: ret void + +struct agg_nofloat1 va_agg_nofloat1(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_nofloat1); } +// CHECK-LABEL: define void @va_agg_nofloat1(%struct.agg_nofloat1* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_nofloat1* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_nofloat1* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_nofloat1* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_nofloat2 va_agg_nofloat2(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_nofloat2); } +// CHECK-LABEL: define void @va_agg_nofloat2(%struct.agg_nofloat2* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 16 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_nofloat2* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 0 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_nofloat2* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_nofloat2* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + +struct agg_nofloat3 va_agg_nofloat3(__builtin_va_list l) { return __builtin_va_arg(l, struct agg_nofloat3); } +// CHECK-LABEL: define void @va_agg_nofloat3(%struct.agg_nofloat3* noalias sret %{{.*}}, %struct.__va_list_tag* %{{.*}} +// CHECK: [[REG_COUNT_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 0 +// CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]] +// CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5 +// CHECK: br i1 [[FITS_IN_REGS]], +// CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8 +// CHECK: [[REG_OFFSET:%[^ ]+]] = add i64 [[SCALED_REG_COUNT]], 20 +// CHECK: [[REG_SAVE_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 3 +// CHECK: [[REG_SAVE_AREA:%[^ ]+]] = load i8*, i8** [[REG_SAVE_AREA_PTR:[^ ]+]] +// CHECK: [[RAW_REG_ADDR:%[^ ]+]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i64 [[REG_OFFSET]] +// CHECK: [[REG_ADDR:%[^ ]+]] = bitcast i8* [[RAW_REG_ADDR]] to %struct.agg_nofloat3* +// CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1 +// CHECK: store i64 [[REG_COUNT1]], i64* [[REG_COUNT_PTR]] +// CHECK: [[OVERFLOW_ARG_AREA_PTR:%[^ ]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* %{{.*}}, i32 0, i32 2 +// CHECK: [[OVERFLOW_ARG_AREA:%[^ ]+]] = load i8*, i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[RAW_MEM_ADDR:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 4 +// CHECK: [[MEM_ADDR:%[^ ]+]] = bitcast i8* [[RAW_MEM_ADDR]] to %struct.agg_nofloat3* +// CHECK: [[OVERFLOW_ARG_AREA2:%[^ ]+]] = getelementptr i8, i8* [[OVERFLOW_ARG_AREA]], i64 8 +// CHECK: store i8* [[OVERFLOW_ARG_AREA2]], i8** [[OVERFLOW_ARG_AREA_PTR]] +// CHECK: [[VA_ARG_ADDR:%[^ ]+]] = phi %struct.agg_nofloat3* [ [[REG_ADDR]], %{{.*}} ], [ [[MEM_ADDR]], %{{.*}} ] +// CHECK: ret void + diff --git a/test/CodeGen/systemz-abi.cpp b/test/CodeGen/systemz-abi.cpp new file mode 100644 index 000000000000..0249e9f63c9b --- /dev/null +++ b/test/CodeGen/systemz-abi.cpp @@ -0,0 +1,9 @@ +// RUN: %clang_cc1 -triple s390x-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s + +// For compatibility with GCC, this structure is passed in an FPR in C++, +// but passed in a GPR in C (checked in systemz-abi.c). + +struct agg_float_cpp { float a; int : 0; }; +struct agg_float_cpp pass_agg_float_cpp(struct agg_float_cpp arg) { return arg; } +// CHECK-LABEL: define void @_Z18pass_agg_float_cpp13agg_float_cpp(%struct.agg_float_cpp* noalias sret %{{.*}}, float %{{.*}}) + diff --git a/test/CodeGen/systemz-inline-asm.c b/test/CodeGen/systemz-inline-asm.c index c9372333b1f2..92ed4bb03243 100644 --- a/test/CodeGen/systemz-inline-asm.c +++ b/test/CodeGen/systemz-inline-asm.c @@ -124,8 +124,8 @@ long double test_f128(long double f, long double g) { asm("axbr %0, %2" : "=f" (f) : "0" (f), "f" (g)); return f; // CHECK: define void @test_f128(fp128* noalias nocapture sret [[DEST:%.*]], fp128* nocapture readonly, fp128* nocapture readonly) -// CHECK: %f = load fp128* %0 -// CHECK: %g = load fp128* %1 +// CHECK: %f = load fp128, fp128* %0 +// CHECK: %g = load fp128, fp128* %1 // CHECK: [[RESULT:%.*]] = tail call fp128 asm "axbr $0, $2", "=f,0,f"(fp128 %f, fp128 %g) // CHECK: store fp128 [[RESULT]], fp128* [[DEST]] } diff --git a/test/CodeGen/target-data.c b/test/CodeGen/target-data.c index d8e77c5352c2..d601158af63a 100644 --- a/test/CodeGen/target-data.c +++ b/test/CodeGen/target-data.c @@ -8,11 +8,11 @@ // RUN: %clang_cc1 -triple i686-unknown-win32 -emit-llvm -o - %s | \ // RUN: FileCheck --check-prefix=I686-WIN32 %s -// I686-WIN32: target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32" +// I686-WIN32: target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" // RUN: %clang_cc1 -triple i686-unknown-cygwin -emit-llvm -o - %s | \ // RUN: FileCheck --check-prefix=I686-CYGWIN %s -// I686-CYGWIN: target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32" +// I686-CYGWIN: target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | \ // RUN: FileCheck --check-prefix=X86_64 %s @@ -66,7 +66,7 @@ // RUN: FileCheck %s -check-prefix=X86_64-NACL // X86_64-NACL: target datalayout = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128" -// RUN: %clang_cc1 -triple arm-nacl-gnueabi -o - -emit-llvm %s | \ +// RUN: %clang_cc1 -triple arm-nacl -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=ARM-NACL // ARM-NACL: target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128" @@ -122,6 +122,11 @@ // RUN: | FileCheck %s -check-prefix=R600SI // R600SI: target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" +// Test default -target-cpu +// RUN: %clang_cc1 -triple amdgcn-unknown -o - -emit-llvm %s \ +// RUN: | FileCheck %s -check-prefix=R600SIDefault +// R600SIDefault: target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" + // RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=AARCH64 // AARCH64: target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" @@ -150,6 +155,10 @@ // RUN: FileCheck %s -check-prefix=SYSTEMZ // SYSTEMZ: target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64" +// RUN: %clang_cc1 -triple s390x-unknown -target-cpu z13 -o - -emit-llvm %s | \ +// RUN: FileCheck %s -check-prefix=SYSTEMZ-VECTOR +// SYSTEMZ-VECTOR: target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" + // RUN: %clang_cc1 -triple msp430-unknown -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=MSP430 // MSP430: target datalayout = "e-m:e-p:16:16-i32:16:32-a:16-n8:16" diff --git a/test/CodeGen/tbaa.cpp b/test/CodeGen/tbaa.cpp index 4a723f100ecf..2bff5d0ba070 100644 --- a/test/CodeGen/tbaa.cpp +++ b/test/CodeGen/tbaa.cpp @@ -203,9 +203,9 @@ struct five { char g13(struct five *a, struct five *b) { return a->b; // CHECK: define signext i8 @{{.*}}( -// CHECK: load i8* %{{.*}}, align 1, !tbaa [[TAG_char:!.*]] +// CHECK: load i8, i8* %{{.*}}, align 1, !tbaa [[TAG_char:!.*]] // PATH: define signext i8 @{{.*}}( -// PATH: load i8* %{{.*}}, align 1, !tbaa [[TAG_five_b:!.*]] +// PATH: load i8, i8* %{{.*}}, align 1, !tbaa [[TAG_five_b:!.*]] } struct six { @@ -216,9 +216,9 @@ struct six { }; char g14(struct six *a, struct six *b) { // CHECK: define signext i8 @{{.*}}( -// CHECK: load i8* %{{.*}}, align 1, !tbaa [[TAG_char]] +// CHECK: load i8, i8* %{{.*}}, align 1, !tbaa [[TAG_char]] // PATH: define signext i8 @{{.*}}( -// PATH: load i8* %{{.*}}, align 1, !tbaa [[TAG_six_b:!.*]] +// PATH: load i8, i8* %{{.*}}, align 1, !tbaa [[TAG_six_b:!.*]] return a->b; } diff --git a/test/CodeGen/trapv.c b/test/CodeGen/trapv.c index 51034108ee43..04842408a019 100644 --- a/test/CodeGen/trapv.c +++ b/test/CodeGen/trapv.c @@ -6,14 +6,14 @@ int i, j, k; // CHECK-LABEL: define void @test0() void test0() { // -ftrapv doesn't affect unsigned arithmetic. - // CHECK: [[T1:%.*]] = load i32* @uj - // CHECK-NEXT: [[T2:%.*]] = load i32* @uk + // CHECK: [[T1:%.*]] = load i32, i32* @uj + // CHECK-NEXT: [[T2:%.*]] = load i32, i32* @uk // CHECK-NEXT: [[T3:%.*]] = add i32 [[T1]], [[T2]] // CHECK-NEXT: store i32 [[T3]], i32* @ui ui = uj + uk; - // CHECK: [[T1:%.*]] = load i32* @j - // CHECK-NEXT: [[T2:%.*]] = load i32* @k + // CHECK: [[T1:%.*]] = load i32, i32* @j + // CHECK-NEXT: [[T2:%.*]] = load i32, i32* @k // CHECK-NEXT: [[T3:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T1]], i32 [[T2]]) // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T3]], 0 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T3]], 1 @@ -28,7 +28,7 @@ void test1() { extern void opaque(int); opaque(i++); - // CHECK: [[T1:%.*]] = load i32* @i + // CHECK: [[T1:%.*]] = load i32, i32* @i // CHECK-NEXT: [[T2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T1]], i32 1) // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 0 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T2]], 1 @@ -42,7 +42,7 @@ void test2() { extern void opaque(int); opaque(++i); - // CHECK: [[T1:%.*]] = load i32* @i + // CHECK: [[T1:%.*]] = load i32, i32* @i // CHECK-NEXT: [[T2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T1]], i32 1) // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 0 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T2]], 1 diff --git a/test/CodeGen/unsigned-overflow.c b/test/CodeGen/unsigned-overflow.c index 01ed0bf8cb5e..c91be3356edd 100644 --- a/test/CodeGen/unsigned-overflow.c +++ b/test/CodeGen/unsigned-overflow.c @@ -11,8 +11,8 @@ extern void opaqueint(unsigned int); // CHECK-LABEL: define void @testlongadd() void testlongadd() { - // CHECK: [[T1:%.*]] = load i64* @lj - // CHECK-NEXT: [[T2:%.*]] = load i64* @lk + // CHECK: [[T1:%.*]] = load i64, i64* @lj + // CHECK-NEXT: [[T2:%.*]] = load i64, i64* @lk // CHECK-NEXT: [[T3:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[T1]], i64 [[T2]]) // CHECK-NEXT: [[T4:%.*]] = extractvalue { i64, i1 } [[T3]], 0 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i64, i1 } [[T3]], 1 @@ -23,8 +23,8 @@ void testlongadd() { // CHECK-LABEL: define void @testlongsub() void testlongsub() { - // CHECK: [[T1:%.*]] = load i64* @lj - // CHECK-NEXT: [[T2:%.*]] = load i64* @lk + // CHECK: [[T1:%.*]] = load i64, i64* @lj + // CHECK-NEXT: [[T2:%.*]] = load i64, i64* @lk // CHECK-NEXT: [[T3:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[T1]], i64 [[T2]]) // CHECK-NEXT: [[T4:%.*]] = extractvalue { i64, i1 } [[T3]], 0 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i64, i1 } [[T3]], 1 @@ -35,8 +35,8 @@ void testlongsub() { // CHECK-LABEL: define void @testlongmul() void testlongmul() { - // CHECK: [[T1:%.*]] = load i64* @lj - // CHECK-NEXT: [[T2:%.*]] = load i64* @lk + // CHECK: [[T1:%.*]] = load i64, i64* @lj + // CHECK-NEXT: [[T2:%.*]] = load i64, i64* @lk // CHECK-NEXT: [[T3:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[T1]], i64 [[T2]]) // CHECK-NEXT: [[T4:%.*]] = extractvalue { i64, i1 } [[T3]], 0 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i64, i1 } [[T3]], 1 @@ -48,7 +48,7 @@ void testlongmul() { void testlongpostinc() { opaquelong(li++); - // CHECK: [[T1:%.*]] = load i64* @li + // CHECK: [[T1:%.*]] = load i64, i64* @li // CHECK-NEXT: [[T2:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[T1]], i64 1) // CHECK-NEXT: [[T3:%.*]] = extractvalue { i64, i1 } [[T2]], 0 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i64, i1 } [[T2]], 1 @@ -59,7 +59,7 @@ void testlongpostinc() { void testlongpreinc() { opaquelong(++li); - // CHECK: [[T1:%.*]] = load i64* @li + // CHECK: [[T1:%.*]] = load i64, i64* @li // CHECK-NEXT: [[T2:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[T1]], i64 1) // CHECK-NEXT: [[T3:%.*]] = extractvalue { i64, i1 } [[T2]], 0 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i64, i1 } [[T2]], 1 @@ -69,8 +69,8 @@ void testlongpreinc() { // CHECK-LABEL: define void @testintadd() void testintadd() { - // CHECK: [[T1:%.*]] = load i32* @ij - // CHECK-NEXT: [[T2:%.*]] = load i32* @ik + // CHECK: [[T1:%.*]] = load i32, i32* @ij + // CHECK-NEXT: [[T2:%.*]] = load i32, i32* @ik // CHECK-NEXT: [[T3:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[T1]], i32 [[T2]]) // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T3]], 0 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T3]], 1 @@ -81,8 +81,8 @@ void testintadd() { // CHECK-LABEL: define void @testintsub() void testintsub() { - // CHECK: [[T1:%.*]] = load i32* @ij - // CHECK-NEXT: [[T2:%.*]] = load i32* @ik + // CHECK: [[T1:%.*]] = load i32, i32* @ij + // CHECK-NEXT: [[T2:%.*]] = load i32, i32* @ik // CHECK-NEXT: [[T3:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[T1]], i32 [[T2]]) // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T3]], 0 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T3]], 1 @@ -93,8 +93,8 @@ void testintsub() { // CHECK-LABEL: define void @testintmul() void testintmul() { - // CHECK: [[T1:%.*]] = load i32* @ij - // CHECK-NEXT: [[T2:%.*]] = load i32* @ik + // CHECK: [[T1:%.*]] = load i32, i32* @ij + // CHECK-NEXT: [[T2:%.*]] = load i32, i32* @ik // CHECK-NEXT: [[T3:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[T1]], i32 [[T2]]) // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T3]], 0 // CHECK-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T3]], 1 @@ -106,7 +106,7 @@ void testintmul() { void testintpostinc() { opaqueint(ii++); - // CHECK: [[T1:%.*]] = load i32* @ii + // CHECK: [[T1:%.*]] = load i32, i32* @ii // CHECK-NEXT: [[T2:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[T1]], i32 1) // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 0 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T2]], 1 @@ -117,7 +117,7 @@ void testintpostinc() { void testintpreinc() { opaqueint(++ii); - // CHECK: [[T1:%.*]] = load i32* @ii + // CHECK: [[T1:%.*]] = load i32, i32* @ii // CHECK-NEXT: [[T2:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[T1]], i32 1) // CHECK-NEXT: [[T3:%.*]] = extractvalue { i32, i1 } [[T2]], 0 // CHECK-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T2]], 1 diff --git a/test/CodeGen/unsigned-promotion.c b/test/CodeGen/unsigned-promotion.c index 2c3415201ce7..4e7a4426a03e 100644 --- a/test/CodeGen/unsigned-promotion.c +++ b/test/CodeGen/unsigned-promotion.c @@ -15,16 +15,16 @@ extern void opaquechar(unsigned char); // CHECKS-LABEL: define void @testshortadd() // CHECKU-LABEL: define void @testshortadd() void testshortadd() { - // CHECKS: load i16* @sj - // CHECKS: load i16* @sk + // CHECKS: load i16, i16* @sj + // CHECKS: load i16, i16* @sk // CHECKS: [[T1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T2:%.*]], i32 [[T3:%.*]]) // CHECKS-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T1]], 0 // CHECKS-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T1]], 1 // CHECKS: call void @__ubsan_handle_add_overflow // - // CHECKU: [[T1:%.*]] = load i16* @sj + // CHECKU: [[T1:%.*]] = load i16, i16* @sj // CHECKU: [[T2:%.*]] = zext i16 [[T1]] - // CHECKU: [[T3:%.*]] = load i16* @sk + // CHECKU: [[T3:%.*]] = load i16, i16* @sk // CHECKU: [[T4:%.*]] = zext i16 [[T3]] // CHECKU-NOT: llvm.sadd // CHECKU-NOT: llvm.uadd @@ -37,16 +37,16 @@ void testshortadd() { // CHECKU-LABEL: define void @testshortsub() void testshortsub() { - // CHECKS: load i16* @sj - // CHECKS: load i16* @sk + // CHECKS: load i16, i16* @sj + // CHECKS: load i16, i16* @sk // CHECKS: [[T1:%.*]] = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 [[T2:%.*]], i32 [[T3:%.*]]) // CHECKS-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T1]], 0 // CHECKS-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T1]], 1 // CHECKS: call void @__ubsan_handle_sub_overflow // - // CHECKU: [[T1:%.*]] = load i16* @sj + // CHECKU: [[T1:%.*]] = load i16, i16* @sj // CHECKU: [[T2:%.*]] = zext i16 [[T1]] - // CHECKU: [[T3:%.*]] = load i16* @sk + // CHECKU: [[T3:%.*]] = load i16, i16* @sk // CHECKU: [[T4:%.*]] = zext i16 [[T3]] // CHECKU-NOT: llvm.ssub // CHECKU-NOT: llvm.usub @@ -59,16 +59,16 @@ void testshortsub() { // CHECKU-LABEL: define void @testshortmul() void testshortmul() { - // CHECKS: load i16* @sj - // CHECKS: load i16* @sk + // CHECKS: load i16, i16* @sj + // CHECKS: load i16, i16* @sk // CHECKS: [[T1:%.*]] = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 [[T2:%.*]], i32 [[T3:%.*]]) // CHECKS-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T1]], 0 // CHECKS-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T1]], 1 // CHECKS: call void @__ubsan_handle_mul_overflow // - // CHECKU: [[T1:%.*]] = load i16* @sj + // CHECKU: [[T1:%.*]] = load i16, i16* @sj // CHECKU: [[T2:%.*]] = zext i16 [[T1]] - // CHECKU: [[T3:%.*]] = load i16* @sk + // CHECKU: [[T3:%.*]] = load i16, i16* @sk // CHECKU: [[T4:%.*]] = zext i16 [[T3]] // CHECKU-NOT: llvm.smul // CHECKU-NOT: llvm.umul @@ -80,16 +80,16 @@ void testshortmul() { // CHECKU-LABEL: define void @testcharadd() void testcharadd() { - // CHECKS: load i8* @cj - // CHECKS: load i8* @ck + // CHECKS: load i8, i8* @cj + // CHECKS: load i8, i8* @ck // CHECKS: [[T1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[T2:%.*]], i32 [[T3:%.*]]) // CHECKS-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T1]], 0 // CHECKS-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T1]], 1 // CHECKS: call void @__ubsan_handle_add_overflow // - // CHECKU: [[T1:%.*]] = load i8* @cj + // CHECKU: [[T1:%.*]] = load i8, i8* @cj // CHECKU: [[T2:%.*]] = zext i8 [[T1]] - // CHECKU: [[T3:%.*]] = load i8* @ck + // CHECKU: [[T3:%.*]] = load i8, i8* @ck // CHECKU: [[T4:%.*]] = zext i8 [[T3]] // CHECKU-NOT: llvm.sadd // CHECKU-NOT: llvm.uadd @@ -102,16 +102,16 @@ void testcharadd() { // CHECKU-LABEL: define void @testcharsub() void testcharsub() { - // CHECKS: load i8* @cj - // CHECKS: load i8* @ck + // CHECKS: load i8, i8* @cj + // CHECKS: load i8, i8* @ck // CHECKS: [[T1:%.*]] = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 [[T2:%.*]], i32 [[T3:%.*]]) // CHECKS-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T1]], 0 // CHECKS-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T1]], 1 // CHECKS: call void @__ubsan_handle_sub_overflow // - // CHECKU: [[T1:%.*]] = load i8* @cj + // CHECKU: [[T1:%.*]] = load i8, i8* @cj // CHECKU: [[T2:%.*]] = zext i8 [[T1]] - // CHECKU: [[T3:%.*]] = load i8* @ck + // CHECKU: [[T3:%.*]] = load i8, i8* @ck // CHECKU: [[T4:%.*]] = zext i8 [[T3]] // CHECKU-NOT: llvm.ssub // CHECKU-NOT: llvm.usub @@ -124,16 +124,16 @@ void testcharsub() { // CHECKU-LABEL: define void @testcharmul() void testcharmul() { - // CHECKS: load i8* @cj - // CHECKS: load i8* @ck + // CHECKS: load i8, i8* @cj + // CHECKS: load i8, i8* @ck // CHECKS: [[T1:%.*]] = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 [[T2:%.*]], i32 [[T3:%.*]]) // CHECKS-NEXT: [[T4:%.*]] = extractvalue { i32, i1 } [[T1]], 0 // CHECKS-NEXT: [[T5:%.*]] = extractvalue { i32, i1 } [[T1]], 1 // CHECKS: call void @__ubsan_handle_mul_overflow // - // CHECKU: [[T1:%.*]] = load i8* @cj + // CHECKU: [[T1:%.*]] = load i8, i8* @cj // CHECKU: [[T2:%.*]] = zext i8 [[T1]] - // CHECKU: [[T3:%.*]] = load i8* @ck + // CHECKU: [[T3:%.*]] = load i8, i8* @ck // CHECKU: [[T4:%.*]] = zext i8 [[T3]] // CHECKU-NOT: llvm.smul // CHECKU-NOT: llvm.umul diff --git a/test/CodeGen/variadic-gpfp-x86.c b/test/CodeGen/variadic-gpfp-x86.c index 735c4beea03a..854899b6a341 100644 --- a/test/CodeGen/variadic-gpfp-x86.c +++ b/test/CodeGen/variadic-gpfp-x86.c @@ -8,8 +8,8 @@ struct Bar { struct Bar foo(__builtin_va_list ap) { return __builtin_va_arg(ap, struct Bar); -// CHECK: [[FPOP:%.*]] = getelementptr inbounds %struct.__va_list_tag* {{.*}}, i32 0, i32 1 -// CHECK: [[FPO:%.*]] = load i32* [[FPOP]] -// CHECK: [[FPVEC:%.*]] = getelementptr i8* {{.*}}, i32 [[FPO]] +// CHECK: [[FPOP:%.*]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* {{.*}}, i32 0, i32 1 +// CHECK: [[FPO:%.*]] = load i32, i32* [[FPOP]] +// CHECK: [[FPVEC:%.*]] = getelementptr i8, i8* {{.*}}, i32 [[FPO]] // CHECK: bitcast i8* [[FPVEC]] to <2 x float>* } diff --git a/test/CodeGen/variadic-null-win64.c b/test/CodeGen/variadic-null-win64.c index 4f57e7b39f9f..3e079cbf8e51 100644 --- a/test/CodeGen/variadic-null-win64.c +++ b/test/CodeGen/variadic-null-win64.c @@ -12,6 +12,6 @@ void f(const char *f) { v(f, 1, 2, 3, NULL); } // WINDOWS: define void @f(i8* %f) -// WINDOWS: call void (i8*, ...)* @v(i8* {{.*}}, i32 1, i32 2, i32 3, i64 0) +// WINDOWS: call void (i8*, ...) @v(i8* {{.*}}, i32 1, i32 2, i32 3, i64 0) // LINUX: define void @f(i8* %f) -// LINUX: call void (i8*, ...)* @v(i8* {{.*}}, i32 1, i32 2, i32 3, i32 0) +// LINUX: call void (i8*, ...) @v(i8* {{.*}}, i32 1, i32 2, i32 3, i32 0) diff --git a/test/CodeGen/vla-2.c b/test/CodeGen/vla-2.c index 0a74907f7b2d..894913da3ec7 100644 --- a/test/CodeGen/vla-2.c +++ b/test/CodeGen/vla-2.c @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -std=gnu99 %s -emit-llvm -o - | grep ".*alloca.*align 16" +// RUN: %clang_cc1 -std=gnu99 %s -emit-llvm -o - | FileCheck %s +// CHECK: alloca {{.*}}, align 16 extern void bar(int[]); diff --git a/test/CodeGen/vla-3.c b/test/CodeGen/vla-3.c index 4927b464231f..66acf58c1feb 100644 --- a/test/CodeGen/vla-3.c +++ b/test/CodeGen/vla-3.c @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -std=gnu99 %s -emit-llvm -o - | grep ".*alloca.*align 16" +// RUN: %clang_cc1 -std=gnu99 %s -emit-llvm -o - | FileCheck %s +// CHECK: alloca {{.*}}, align 16 void adr(char *); diff --git a/test/CodeGen/vla.c b/test/CodeGen/vla.c index e6cdd5d2a32a..0f2e2cdc669d 100644 --- a/test/CodeGen/vla.c +++ b/test/CodeGen/vla.c @@ -79,7 +79,7 @@ int test2(int n) { GLOB = 0; char b[1][n+3]; /* Variable length array. */ - // CHECK: [[tmp_1:%.*]] = load i32* @GLOB, align 4 + // CHECK: [[tmp_1:%.*]] = load i32, i32* @GLOB, align 4 // CHECK-NEXT: add nsw i32 [[tmp_1]], 1 __typeof__(b[GLOB++]) c; return GLOB; @@ -92,13 +92,13 @@ double test_PR8567(int n, double (*p)[n][5]) { // CHECK-NEXT: [[PV:%.*]] = alloca [5 x double]*, align 4 // CHECK-NEXT: store // CHECK-NEXT: store - // CHECK-NEXT: [[N:%.*]] = load i32* [[NV]], align 4 - // CHECK-NEXT: [[P:%.*]] = load [5 x double]** [[PV]], align 4 + // CHECK-NEXT: [[N:%.*]] = load i32, i32* [[NV]], align 4 + // CHECK-NEXT: [[P:%.*]] = load [5 x double]*, [5 x double]** [[PV]], align 4 // CHECK-NEXT: [[T0:%.*]] = mul nsw i32 1, [[N]] - // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [5 x double]* [[P]], i32 [[T0]] - // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds [5 x double]* [[T1]], i32 2 - // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [5 x double]* [[T2]], i32 0, i32 3 - // CHECK-NEXT: [[T4:%.*]] = load double* [[T3]] + // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [5 x double], [5 x double]* [[P]], i32 [[T0]] + // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds [5 x double], [5 x double]* [[T1]], i32 2 + // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [5 x double], [5 x double]* [[T2]], i32 0, i32 3 + // CHECK-NEXT: [[T4:%.*]] = load double, double* [[T3]] // CHECK-NEXT: ret double [[T4]] return p[1][2][3]; } @@ -112,27 +112,27 @@ int test4(unsigned n, char (*p)[n][n+1][6]) { // CHECK-NEXT: store [6 x i8]* // VLA captures. - // CHECK-NEXT: [[DIM0:%.*]] = load i32* [[N]], align 4 - // CHECK-NEXT: [[T0:%.*]] = load i32* [[N]], align 4 + // CHECK-NEXT: [[DIM0:%.*]] = load i32, i32* [[N]], align 4 + // CHECK-NEXT: [[T0:%.*]] = load i32, i32* [[N]], align 4 // CHECK-NEXT: [[DIM1:%.*]] = add i32 [[T0]], 1 - // CHECK-NEXT: [[T0:%.*]] = load [6 x i8]** [[P]], align 4 - // CHECK-NEXT: [[T1:%.*]] = load i32* [[N]], align 4 + // CHECK-NEXT: [[T0:%.*]] = load [6 x i8]*, [6 x i8]** [[P]], align 4 + // CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[N]], align 4 // CHECK-NEXT: [[T2:%.*]] = udiv i32 [[T1]], 2 // CHECK-NEXT: [[T3:%.*]] = mul nuw i32 [[DIM0]], [[DIM1]] // CHECK-NEXT: [[T4:%.*]] = mul nsw i32 [[T2]], [[T3]] - // CHECK-NEXT: [[T5:%.*]] = getelementptr inbounds [6 x i8]* [[T0]], i32 [[T4]] - // CHECK-NEXT: [[T6:%.*]] = load i32* [[N]], align 4 + // CHECK-NEXT: [[T5:%.*]] = getelementptr inbounds [6 x i8], [6 x i8]* [[T0]], i32 [[T4]] + // CHECK-NEXT: [[T6:%.*]] = load i32, i32* [[N]], align 4 // CHECK-NEXT: [[T7:%.*]] = udiv i32 [[T6]], 4 // CHECK-NEXT: [[T8:%.*]] = sub i32 0, [[T7]] // CHECK-NEXT: [[T9:%.*]] = mul nuw i32 [[DIM0]], [[DIM1]] // CHECK-NEXT: [[T10:%.*]] = mul nsw i32 [[T8]], [[T9]] - // CHECK-NEXT: [[T11:%.*]] = getelementptr inbounds [6 x i8]* [[T5]], i32 [[T10]] + // CHECK-NEXT: [[T11:%.*]] = getelementptr inbounds [6 x i8], [6 x i8]* [[T5]], i32 [[T10]] // CHECK-NEXT: store [6 x i8]* [[T11]], [6 x i8]** [[P2]], align 4 __typeof(p) p2 = (p + n/2) - n/4; - // CHECK-NEXT: [[T0:%.*]] = load [6 x i8]** [[P2]], align 4 - // CHECK-NEXT: [[T1:%.*]] = load [6 x i8]** [[P]], align 4 + // CHECK-NEXT: [[T0:%.*]] = load [6 x i8]*, [6 x i8]** [[P2]], align 4 + // CHECK-NEXT: [[T1:%.*]] = load [6 x i8]*, [6 x i8]** [[P]], align 4 // CHECK-NEXT: [[T2:%.*]] = ptrtoint [6 x i8]* [[T0]] to i32 // CHECK-NEXT: [[T3:%.*]] = ptrtoint [6 x i8]* [[T1]] to i32 // CHECK-NEXT: [[T4:%.*]] = sub i32 [[T2]], [[T3]] @@ -154,16 +154,16 @@ void test5(void) // CHECK-NEXT: store i32 0, i32* [[I]], align 4 (typeof(++i, (int (*)[i])a)){&a} += 0; - // CHECK-NEXT: [[Z:%.*]] = load i32* [[I]], align 4 + // CHECK-NEXT: [[Z:%.*]] = load i32, i32* [[I]], align 4 // CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[Z]], 1 // CHECK-NEXT: store i32 [[INC]], i32* [[I]], align 4 - // CHECK-NEXT: [[O:%.*]] = load i32* [[I]], align 4 - // CHECK-NEXT: [[AR:%.*]] = getelementptr inbounds [5 x i32]* [[A]], i32 0, i32 0 + // CHECK-NEXT: [[O:%.*]] = load i32, i32* [[I]], align 4 + // CHECK-NEXT: [[AR:%.*]] = getelementptr inbounds [5 x i32], [5 x i32]* [[A]], i32 0, i32 0 // CHECK-NEXT: [[T:%.*]] = bitcast [5 x i32]* [[A]] to i32* // CHECK-NEXT: store i32* [[T]], i32** [[CL]] - // CHECK-NEXT: [[TH:%.*]] = load i32** [[CL]] + // CHECK-NEXT: [[TH:%.*]] = load i32*, i32** [[CL]] // CHECK-NEXT: [[VLAIX:%.*]] = mul nsw i32 0, [[O]] - // CHECK-NEXT: [[ADDPTR:%.*]] = getelementptr inbounds i32* [[TH]], i32 [[VLAIX]] + // CHECK-NEXT: [[ADDPTR:%.*]] = getelementptr inbounds i32, i32* [[TH]], i32 [[VLAIX]] // CHECK-NEXT: store i32* [[ADDPTR]], i32** [[CL]] } @@ -178,15 +178,15 @@ void test6(void) // CHECK-NEXT: [[CL:%.*]] = alloca i32**, align 4 // CHECK-NEXT: store i32 20, i32* [[N]], align 4 // CHECK-NEXT: store i32 0, i32* [[I]], align 4 - // CHECK-NEXT: [[Z:%.*]] = load i32* [[I]], align 4 + // CHECK-NEXT: [[Z:%.*]] = load i32, i32* [[I]], align 4 // CHECK-NEXT: [[O:%.*]] = bitcast i32*** [[A]] to i32** // CHECK-NEXT: store i32** [[O]], i32*** [[CL]] - // CHECK-NEXT: [[T:%.*]] = load i32*** [[CL]] - // CHECK-NEXT: [[IX:%.*]] = getelementptr inbounds i32** [[T]], i32 0 - // CHECK-NEXT: [[TH:%.*]] = load i32** [[IX]], align 4 + // CHECK-NEXT: [[T:%.*]] = load i32**, i32*** [[CL]] + // CHECK-NEXT: [[IX:%.*]] = getelementptr inbounds i32*, i32** [[T]], i32 0 + // CHECK-NEXT: [[TH:%.*]] = load i32*, i32** [[IX]], align 4 // CHECK-NEXT: [[F:%.*]] = mul nsw i32 1, [[Z]] - // CHECK-NEXT: [[IX1:%.*]] = getelementptr inbounds i32* [[TH]], i32 [[F]] - // CHECK-NEXT: [[IX2:%.*]] = getelementptr inbounds i32* [[IX1]], i32 5 + // CHECK-NEXT: [[IX1:%.*]] = getelementptr inbounds i32, i32* [[TH]], i32 [[F]] + // CHECK-NEXT: [[IX2:%.*]] = getelementptr inbounds i32, i32* [[IX1]], i32 5 // CHECK-NEXT: store i32 0, i32* [[IX2]], align 4 } diff --git a/test/CodeGen/volatile-1.c b/test/CodeGen/volatile-1.c index d1861d545899..71cd5f8d1b24 100644 --- a/test/CodeGen/volatile-1.c +++ b/test/CodeGen/volatile-1.c @@ -24,47 +24,47 @@ int printf(const char *, ...); // CHECK-LABEL: define void @test() void test() { - // CHECK: load volatile [[INT]]* @i + // CHECK: load volatile [[INT]], [[INT]]* @i i; - // CHECK-NEXT: load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 // CHECK-NEXT: sitofp [[INT]] (float)(ci); - // CHECK-NEXT: load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 (void)ci; // CHECK-NEXT: bitcast // CHECK-NEXT: memcpy (void)a; - // CHECK-NEXT: [[R:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: [[I:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 - // CHECK-NEXT: store volatile [[INT]] [[R]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: store volatile [[INT]] [[I]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: [[I:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: store volatile [[INT]] [[R]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: store volatile [[INT]] [[I]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 (void)(ci=ci); - // CHECK-NEXT: [[T:%.*]] = load volatile [[INT]]* @j + // CHECK-NEXT: [[T:%.*]] = load volatile [[INT]], [[INT]]* @j // CHECK-NEXT: store volatile [[INT]] [[T]], [[INT]]* @i (void)(i=j); - // CHECK-NEXT: [[R1:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: [[I1:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 - // CHECK-NEXT: [[R2:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: [[I2:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R1:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: [[I1:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R2:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: [[I2:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 // Not sure why they're ordered this way. // CHECK-NEXT: [[R:%.*]] = add [[INT]] [[R2]], [[R1]] // CHECK-NEXT: [[I:%.*]] = add [[INT]] [[I2]], [[I1]] - // CHECK-NEXT: store volatile [[INT]] [[R]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: store volatile [[INT]] [[I]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: store volatile [[INT]] [[R]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: store volatile [[INT]] [[I]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 ci+=ci; - // CHECK-NEXT: [[R1:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: [[I1:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 - // CHECK-NEXT: [[R2:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: [[I2:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R1:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: [[I1:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R2:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: [[I2:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 // CHECK-NEXT: [[R:%.*]] = add [[INT]] [[R2]], [[R1]] // CHECK-NEXT: [[I:%.*]] = add [[INT]] [[I2]], [[I1]] - // CHECK-NEXT: store volatile [[INT]] [[R]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: store volatile [[INT]] [[I]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 - // CHECK-NEXT: [[R2:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 0), align 4 - // CHECK-NEXT: [[I2:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: store volatile [[INT]] [[R]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: store volatile [[INT]] [[I]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R2:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 0), align 4 + // CHECK-NEXT: [[I2:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1), align 4 // These additions can be elided // CHECK-NEXT: add [[INT]] [[R]], [[R2]] // CHECK-NEXT: add [[INT]] [[I]], [[I2]] @@ -192,9 +192,9 @@ void test() { // CHECK-NEXT: store volatile // CHECK-NEXT: store volatile ci=ci=ci; - // CHECK-NEXT: [[T:%.*]] = load volatile [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1) - // CHECK-NEXT: store volatile [[INT]] [[T]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1) - // CHECK-NEXT: store volatile [[INT]] [[T]], [[INT]]* getelementptr inbounds ([[CINT]]* @ci, i32 0, i32 1) + // CHECK-NEXT: [[T:%.*]] = load volatile [[INT]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1) + // CHECK-NEXT: store volatile [[INT]] [[T]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1) + // CHECK-NEXT: store volatile [[INT]] [[T]], [[INT]]* getelementptr inbounds ([[CINT]], [[CINT]]* @ci, i32 0, i32 1) __imag ci = __imag ci = __imag ci; // CHECK-NEXT: load volatile // CHECK-NEXT: store volatile @@ -316,9 +316,9 @@ void test1() { // CHECK: define {{.*}} @test2() int test2() { - // CHECK: load volatile i32* - // CHECK-NEXT: load volatile i32* - // CHECK-NEXT: load volatile i32* + // CHECK: load volatile i32, i32* + // CHECK-NEXT: load volatile i32, i32* + // CHECK-NEXT: load volatile i32, i32* // CHECK-NEXT: add i32 // CHECK-NEXT: add i32 // CHECK-NEXT: store volatile i32 diff --git a/test/CodeGen/volatile-2.c b/test/CodeGen/volatile-2.c index 18d0d318ef82..84cbc1edc470 100644 --- a/test/CodeGen/volatile-2.c +++ b/test/CodeGen/volatile-2.c @@ -3,8 +3,8 @@ void test0() { // CHECK-LABEL: define void @test0() // CHECK: [[F:%.*]] = alloca float - // CHECK-NEXT: [[REAL:%.*]] = load volatile float* getelementptr inbounds ({ float, float }* @test0_v, i32 0, i32 0), align 4 - // CHECK-NEXT: load volatile float* getelementptr inbounds ({{.*}} @test0_v, i32 0, i32 1), align 4 + // CHECK-NEXT: [[REAL:%.*]] = load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @test0_v, i32 0, i32 0), align 4 + // CHECK-NEXT: load volatile float, float* getelementptr inbounds ({{.*}} @test0_v, i32 0, i32 1), align 4 // CHECK-NEXT: store float [[REAL]], float* [[F]], align 4 // CHECK-NEXT: ret void extern volatile _Complex float test0_v; @@ -13,8 +13,8 @@ void test0() { void test1() { // CHECK-LABEL: define void @test1() - // CHECK: [[REAL:%.*]] = load volatile float* getelementptr inbounds ({{.*}} @test1_v, i32 0, i32 0), align 4 - // CHECK-NEXT: [[IMAG:%.*]] = load volatile float* getelementptr inbounds ({{.*}} @test1_v, i32 0, i32 1), align 4 + // CHECK: [[REAL:%.*]] = load volatile float, float* getelementptr inbounds ({{.*}} @test1_v, i32 0, i32 0), align 4 + // CHECK-NEXT: [[IMAG:%.*]] = load volatile float, float* getelementptr inbounds ({{.*}} @test1_v, i32 0, i32 1), align 4 // CHECK-NEXT: store volatile float [[REAL]], float* getelementptr inbounds ({{.*}} @test1_v, i32 0, i32 0), align 4 // CHECK-NEXT: store volatile float [[IMAG]], float* getelementptr inbounds ({{.*}} @test1_v, i32 0, i32 1), align 4 // CHECK-NEXT: ret void diff --git a/test/CodeGen/volatile-complex.c b/test/CodeGen/volatile-complex.c index fd5e52b8d7e3..cd8f72d28669 100644 --- a/test/CodeGen/volatile-complex.c +++ b/test/CodeGen/volatile-complex.c @@ -14,52 +14,52 @@ volatile _Complex double cd32 __attribute__((aligned(32))); // CHECK-LABEL: define void @test_cf() void test_cf() { - // CHECK: load volatile float* getelementptr inbounds ({ float, float }* @cf, i32 0, i32 0), align 4 - // CHECK-NEXT: load volatile float* getelementptr inbounds ({ float, float }* @cf, i32 0, i32 1), align 4 + // CHECK: load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 + // CHECK-NEXT: load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 (void)(cf); - // CHECK-NEXT: [[R:%.*]] = load volatile float* getelementptr inbounds ({ float, float }* @cf, i32 0, i32 0), align 4 - // CHECK-NEXT: [[I:%.*]] = load volatile float* getelementptr inbounds ({ float, float }* @cf, i32 0, i32 1), align 4 - // CHECK-NEXT: store volatile float [[R]], float* getelementptr inbounds ({ float, float }* @cf, i32 0, i32 0), align 4 - // CHECK-NEXT: store volatile float [[I]], float* getelementptr inbounds ({ float, float }* @cf, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R:%.*]] = load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 + // CHECK-NEXT: [[I:%.*]] = load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 + // CHECK-NEXT: store volatile float [[R]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 0), align 4 + // CHECK-NEXT: store volatile float [[I]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf, i32 0, i32 1), align 4 (void)(cf=cf); // CHECK-NEXT: ret void } // CHECK-LABEL: define void @test_cd() void test_cd() { - // CHECK: load volatile double* getelementptr inbounds ({ double, double }* @cd, i32 0, i32 0), align 8 - // CHECK-NEXT: load volatile double* getelementptr inbounds ({ double, double }* @cd, i32 0, i32 1), align 8 + // CHECK: load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd, i32 0, i32 0), align 8 + // CHECK-NEXT: load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd, i32 0, i32 1), align 8 (void)(cd); - // CHECK-NEXT: [[R:%.*]] = load volatile double* getelementptr inbounds ({ double, double }* @cd, i32 0, i32 0), align 8 - // CHECK-NEXT: [[I:%.*]] = load volatile double* getelementptr inbounds ({ double, double }* @cd, i32 0, i32 1), align 8 - // CHECK-NEXT: store volatile double [[R]], double* getelementptr inbounds ({ double, double }* @cd, i32 0, i32 0), align 8 - // CHECK-NEXT: store volatile double [[I]], double* getelementptr inbounds ({ double, double }* @cd, i32 0, i32 1), align 8 + // CHECK-NEXT: [[R:%.*]] = load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd, i32 0, i32 0), align 8 + // CHECK-NEXT: [[I:%.*]] = load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd, i32 0, i32 1), align 8 + // CHECK-NEXT: store volatile double [[R]], double* getelementptr inbounds ({ double, double }, { double, double }* @cd, i32 0, i32 0), align 8 + // CHECK-NEXT: store volatile double [[I]], double* getelementptr inbounds ({ double, double }, { double, double }* @cd, i32 0, i32 1), align 8 (void)(cd=cd); // CHECK-NEXT: ret void } // CHECK-LABEL: define void @test_cf32() void test_cf32() { - // CHECK: load volatile float* getelementptr inbounds ({ float, float }* @cf32, i32 0, i32 0), align 32 - // CHECK-NEXT: load volatile float* getelementptr inbounds ({ float, float }* @cf32, i32 0, i32 1), align 4 + // CHECK: load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf32, i32 0, i32 0), align 32 + // CHECK-NEXT: load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf32, i32 0, i32 1), align 4 (void)(cf32); - // CHECK-NEXT: [[R:%.*]] = load volatile float* getelementptr inbounds ({ float, float }* @cf32, i32 0, i32 0), align 32 - // CHECK-NEXT: [[I:%.*]] = load volatile float* getelementptr inbounds ({ float, float }* @cf32, i32 0, i32 1), align 4 - // CHECK-NEXT: store volatile float [[R]], float* getelementptr inbounds ({ float, float }* @cf32, i32 0, i32 0), align 32 - // CHECK-NEXT: store volatile float [[I]], float* getelementptr inbounds ({ float, float }* @cf32, i32 0, i32 1), align 4 + // CHECK-NEXT: [[R:%.*]] = load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf32, i32 0, i32 0), align 32 + // CHECK-NEXT: [[I:%.*]] = load volatile float, float* getelementptr inbounds ({ float, float }, { float, float }* @cf32, i32 0, i32 1), align 4 + // CHECK-NEXT: store volatile float [[R]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf32, i32 0, i32 0), align 32 + // CHECK-NEXT: store volatile float [[I]], float* getelementptr inbounds ({ float, float }, { float, float }* @cf32, i32 0, i32 1), align 4 (void)(cf32=cf32); // CHECK-NEXT: ret void } // CHECK-LABEL: define void @test_cd32() void test_cd32() { - // CHECK: load volatile double* getelementptr inbounds ({ double, double }* @cd32, i32 0, i32 0), align 32 - // CHECK-NEXT: load volatile double* getelementptr inbounds ({ double, double }* @cd32, i32 0, i32 1), align 8 + // CHECK: load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd32, i32 0, i32 0), align 32 + // CHECK-NEXT: load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd32, i32 0, i32 1), align 8 (void)(cd32); - // CHECK-NEXT: [[R:%.*]] = load volatile double* getelementptr inbounds ({ double, double }* @cd32, i32 0, i32 0), align 32 - // CHECK-NEXT: [[I:%.*]] = load volatile double* getelementptr inbounds ({ double, double }* @cd32, i32 0, i32 1), align 8 - // CHECK-NEXT: store volatile double [[R]], double* getelementptr inbounds ({ double, double }* @cd32, i32 0, i32 0), align 32 - // CHECK-NEXT: store volatile double [[I]], double* getelementptr inbounds ({ double, double }* @cd32, i32 0, i32 1), align 8 + // CHECK-NEXT: [[R:%.*]] = load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd32, i32 0, i32 0), align 32 + // CHECK-NEXT: [[I:%.*]] = load volatile double, double* getelementptr inbounds ({ double, double }, { double, double }* @cd32, i32 0, i32 1), align 8 + // CHECK-NEXT: store volatile double [[R]], double* getelementptr inbounds ({ double, double }, { double, double }* @cd32, i32 0, i32 0), align 32 + // CHECK-NEXT: store volatile double [[I]], double* getelementptr inbounds ({ double, double }, { double, double }* @cd32, i32 0, i32 1), align 8 (void)(cd32=cd32); // CHECK-NEXT: ret void } diff --git a/test/CodeGen/volatile.c b/test/CodeGen/volatile.c index 3e891aa32c77..52915f6f4d5b 100644 --- a/test/CodeGen/volatile.c +++ b/test/CodeGen/volatile.c @@ -41,67 +41,67 @@ int main() { // CHECK: [[I:%[a-zA-Z0-9_.]+]] = alloca i32 // load i=S; -// CHECK: load i32* @S +// CHECK: load i32, i32* @S // CHECK: store i32 {{.*}}, i32* [[I]] i=vS; -// CHECK: load volatile i32* @vS +// CHECK: load volatile i32, i32* @vS // CHECK: store i32 {{.*}}, i32* [[I]] i=*pS; -// CHECK: [[PS_VAL:%[a-zA-Z0-9_.]+]] = load i32** @pS -// CHECK: load i32* [[PS_VAL]] +// CHECK: [[PS_VAL:%[a-zA-Z0-9_.]+]] = load i32*, i32** @pS +// CHECK: load i32, i32* [[PS_VAL]] // CHECK: store i32 {{.*}}, i32* [[I]] i=*pvS; -// CHECK: [[PVS_VAL:%[a-zA-Z0-9_.]+]] = load i32** @pvS -// CHECK: load volatile i32* [[PVS_VAL]] +// CHECK: [[PVS_VAL:%[a-zA-Z0-9_.]+]] = load i32*, i32** @pvS +// CHECK: load volatile i32, i32* [[PVS_VAL]] // CHECK: store i32 {{.*}}, i32* [[I]] i=A[2]; -// CHECK: load i32* getelementptr {{.*}} @A +// CHECK: load i32, i32* getelementptr {{.*}} @A // CHECK: store i32 {{.*}}, i32* [[I]] i=vA[2]; -// CHECK: load volatile i32* getelementptr {{.*}} @vA +// CHECK: load volatile i32, i32* getelementptr {{.*}} @vA // CHECK: store i32 {{.*}}, i32* [[I]] i=F.x; -// CHECK: load i32* getelementptr {{.*}} @F +// CHECK: load i32, i32* getelementptr {{.*}} @F // CHECK: store i32 {{.*}}, i32* [[I]] i=vF.x; -// CHECK: load volatile i32* getelementptr {{.*}} @vF +// CHECK: load volatile i32, i32* getelementptr {{.*}} @vF // CHECK: store i32 {{.*}}, i32* [[I]] i=F2.x; -// CHECK: load i32* getelementptr {{.*}} @F2 +// CHECK: load i32, i32* getelementptr {{.*}} @F2 // CHECK: store i32 {{.*}}, i32* [[I]] i=vF2.x; -// CHECK: load volatile i32* getelementptr {{.*}} @vF2 +// CHECK: load volatile i32, i32* getelementptr {{.*}} @vF2 // CHECK: store i32 {{.*}}, i32* [[I]] i=vpF2->x; -// CHECK: [[VPF2_VAL:%[a-zA-Z0-9_.]+]] = load {{%[a-zA-Z0-9_.]+}}** @vpF2 +// CHECK: [[VPF2_VAL:%[a-zA-Z0-9_.]+]] = load {{%[a-zA-Z0-9_.]+}}*, {{%[a-zA-Z0-9_.]+}}** @vpF2 // CHECK: [[ELT:%[a-zA-Z0-9_.]+]] = getelementptr {{.*}} [[VPF2_VAL]] -// CHECK: load volatile i32* [[ELT]] +// CHECK: load volatile i32, i32* [[ELT]] // CHECK: store i32 {{.*}}, i32* [[I]] i=F3.x.y; -// CHECK: load i32* getelementptr {{.*}} @F3 +// CHECK: load i32, i32* getelementptr {{.*}} @F3 // CHECK: store i32 {{.*}}, i32* [[I]] i=vF3.x.y; -// CHECK: load volatile i32* getelementptr {{.*}} @vF3 +// CHECK: load volatile i32, i32* getelementptr {{.*}} @vF3 // CHECK: store i32 {{.*}}, i32* [[I]] i=BF.x; -// CHECK-IT: load i8* getelementptr {{.*}} @BF -// CHECK-MS: load i32* getelementptr {{.*}} @BF +// CHECK-IT: load i8, i8* getelementptr {{.*}} @BF +// CHECK-MS: load i32, i32* getelementptr {{.*}} @BF // CHECK: store i32 {{.*}}, i32* [[I]] i=vBF.x; -// CHECK-IT: load volatile i8* getelementptr {{.*}} @vBF -// CHECK-MS: load volatile i32* getelementptr {{.*}} @vBF +// CHECK-IT: load volatile i8, i8* getelementptr {{.*}} @vBF +// CHECK-MS: load volatile i32, i32* getelementptr {{.*}} @vBF // CHECK: store i32 {{.*}}, i32* [[I]] i=V[3]; -// CHECK: load <4 x i32>* @V +// CHECK: load <4 x i32>, <4 x i32>* @V // CHECK: store i32 {{.*}}, i32* [[I]] i=vV[3]; -// CHECK: load volatile <4 x i32>* @vV +// CHECK: load volatile <4 x i32>, <4 x i32>* @vV // CHECK: store i32 {{.*}}, i32* [[I]] i=VE.yx[1]; -// CHECK: load <4 x i32>* @VE +// CHECK: load <4 x i32>, <4 x i32>* @VE // CHECK: store i32 {{.*}}, i32* [[I]] i=vVE.zy[1]; -// CHECK: load volatile <4 x i32>* @vVE +// CHECK: load volatile <4 x i32>, <4 x i32>* @vVE // CHECK: store i32 {{.*}}, i32* [[I]] i = aggFct().x; // Note: not volatile // N.b. Aggregate return is extremely target specific, all we can @@ -110,92 +110,92 @@ int main() { // CHECK-NOT: load volatile // CHECK: store i32 {{.*}}, i32* [[I]] i=vtS; -// CHECK: load volatile i32* @vtS +// CHECK: load volatile i32, i32* @vtS // CHECK: store i32 {{.*}}, i32* [[I]] // store S=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store i32 {{.*}}, i32* @S vS=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store volatile i32 {{.*}}, i32* @vS *pS=i; -// CHECK: load i32* [[I]] -// CHECK: [[PS_VAL:%[a-zA-Z0-9_.]+]] = load i32** @pS +// CHECK: load i32, i32* [[I]] +// CHECK: [[PS_VAL:%[a-zA-Z0-9_.]+]] = load i32*, i32** @pS // CHECK: store i32 {{.*}}, i32* [[PS_VAL]] *pvS=i; -// CHECK: load i32* [[I]] -// CHECK: [[PVS_VAL:%[a-zA-Z0-9_.]+]] = load i32** @pvS +// CHECK: load i32, i32* [[I]] +// CHECK: [[PVS_VAL:%[a-zA-Z0-9_.]+]] = load i32*, i32** @pvS // CHECK: store volatile i32 {{.*}}, i32* [[PVS_VAL]] A[2]=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store i32 {{.*}}, i32* getelementptr {{.*}} @A vA[2]=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store volatile i32 {{.*}}, i32* getelementptr {{.*}} @vA F.x=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store i32 {{.*}}, i32* getelementptr {{.*}} @F vF.x=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store volatile i32 {{.*}}, i32* getelementptr {{.*}} @vF F2.x=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store i32 {{.*}}, i32* getelementptr {{.*}} @F2 vF2.x=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store volatile i32 {{.*}}, i32* getelementptr {{.*}} @vF2 vpF2->x=i; -// CHECK: load i32* [[I]] -// CHECK: [[VPF2_VAL:%[a-zA-Z0-9_.]+]] = load {{%[a-zA-Z0-9._]+}}** @vpF2 +// CHECK: load i32, i32* [[I]] +// CHECK: [[VPF2_VAL:%[a-zA-Z0-9_.]+]] = load {{%[a-zA-Z0-9._]+}}*, {{%[a-zA-Z0-9._]+}}** @vpF2 // CHECK: [[ELT:%[a-zA-Z0-9_.]+]] = getelementptr {{.*}} [[VPF2_VAL]] // CHECK: store volatile i32 {{.*}}, i32* [[ELT]] vF3.x.y=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store volatile i32 {{.*}}, i32* getelementptr {{.*}} @vF3 BF.x=i; -// CHECK: load i32* [[I]] -// CHECK-IT: load i8* getelementptr {{.*}} @BF -// CHECK-MS: load i32* getelementptr {{.*}} @BF +// CHECK: load i32, i32* [[I]] +// CHECK-IT: load i8, i8* getelementptr {{.*}} @BF +// CHECK-MS: load i32, i32* getelementptr {{.*}} @BF // CHECK-IT: store i8 {{.*}}, i8* getelementptr {{.*}} @BF // CHECK-MS: store i32 {{.*}}, i32* getelementptr {{.*}} @BF vBF.x=i; -// CHECK: load i32* [[I]] -// CHECK-IT: load volatile i8* getelementptr {{.*}} @vBF -// CHECK-MS: load volatile i32* getelementptr {{.*}} @vBF +// CHECK: load i32, i32* [[I]] +// CHECK-IT: load volatile i8, i8* getelementptr {{.*}} @vBF +// CHECK-MS: load volatile i32, i32* getelementptr {{.*}} @vBF // CHECK-IT: store volatile i8 {{.*}}, i8* getelementptr {{.*}} @vBF // CHECK-MS: store volatile i32 {{.*}}, i32* getelementptr {{.*}} @vBF V[3]=i; -// CHECK: load i32* [[I]] -// CHECK: load <4 x i32>* @V +// CHECK: load i32, i32* [[I]] +// CHECK: load <4 x i32>, <4 x i32>* @V // CHECK: store <4 x i32> {{.*}}, <4 x i32>* @V vV[3]=i; -// CHECK: load i32* [[I]] -// CHECK: load volatile <4 x i32>* @vV +// CHECK: load i32, i32* [[I]] +// CHECK: load volatile <4 x i32>, <4 x i32>* @vV // CHECK: store volatile <4 x i32> {{.*}}, <4 x i32>* @vV vtS=i; -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* [[I]] // CHECK: store volatile i32 {{.*}}, i32* @vtS // other ops: ++S; -// CHECK: load i32* @S +// CHECK: load i32, i32* @S // CHECK: store i32 {{.*}}, i32* @S ++vS; -// CHECK: load volatile i32* @vS +// CHECK: load volatile i32, i32* @vS // CHECK: store volatile i32 {{.*}}, i32* @vS i+=S; -// CHECK: load i32* @S -// CHECK: load i32* [[I]] +// CHECK: load i32, i32* @S +// CHECK: load i32, i32* [[I]] // CHECK: store i32 {{.*}}, i32* [[I]] i+=vS; -// CHECK: load volatile i32* @vS -// CHECK: load i32* [[I]] +// CHECK: load volatile i32, i32* @vS +// CHECK: load i32, i32* [[I]] // CHECK: store i32 {{.*}}, i32* [[I]] ++vtS; -// CHECK: load volatile i32* @vtS +// CHECK: load volatile i32, i32* @vtS // CHECK: store volatile i32 {{.*}}, i32* @vtS (void)vF2; // From vF2 to a temporary diff --git a/test/CodeGen/windows-on-arm-dllimport-dllexport.c b/test/CodeGen/windows-on-arm-dllimport-dllexport.c index 897d06a729d6..4b2e29e430c6 100644 --- a/test/CodeGen/windows-on-arm-dllimport-dllexport.c +++ b/test/CodeGen/windows-on-arm-dllimport-dllexport.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -Werror -triple thumbv7-windows-itanium -mfloat-abi hard -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -Werror -triple thumbv7-windows-itanium -mfloat-abi hard -fms-extensions -emit-llvm %s -o - | FileCheck %s __declspec(dllexport) int export_int; diff --git a/test/CodeGen/windows-on-arm-stack-probe-size.c b/test/CodeGen/windows-on-arm-stack-probe-size.c new file mode 100644 index 000000000000..c072566d7125 --- /dev/null +++ b/test/CodeGen/windows-on-arm-stack-probe-size.c @@ -0,0 +1,28 @@ +// RUN: %clang_cc1 -triple thumbv7-windows-itanium -mstack-probe-size=8096 -fms-extensions -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix CHECK-8096 + +// RUN: %clang_cc1 -triple thumbv7-windows-itanium -mstack-probe-size=4096 -fms-extensions -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix CHECK-4096 + +// RUN: %clang_cc1 -triple thumbv7-windows-itanium -fms-extensions -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix CHECK + +__declspec(dllimport) void initialise(signed char buffer[4096]); + +__declspec(dllexport) signed char function(unsigned index) { + signed char buffer[4096]; + initialise(buffer); + return buffer[index]; +} + +// CHECK-8096: attributes #0 = { +// CHECK-8096: "stack-probe-size"="8096" +// CHECK-8096: } + +// CHECK-4096: attributes #0 = { +// CHECK-4096-NOT: "stack-probe-size"= +// CHECK-4096: } + +// CHECK: attributes #0 = { +// CHECK-NOT: "stack-probe-size"= +// CHECK: } diff --git a/test/CodeGen/x86-atomic-long_double.c b/test/CodeGen/x86-atomic-long_double.c index 22c7bd4b89c5..9857c67592f2 100644 --- a/test/CodeGen/x86-atomic-long_double.c +++ b/test/CodeGen/x86-atomic-long_double.c @@ -4,12 +4,12 @@ long double testinc(_Atomic long double *addr) { // CHECK-LABEL: @testinc // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VALUE:%.+]] = load atomic i128* [[INT_ADDR]] seq_cst, align 16 + // CHECK: [[INT_VALUE:%.+]] = load atomic i128, i128* [[INT_ADDR]] seq_cst, align 16 // CHECK: [[INT_LOAD_ADDR:%.+]] = bitcast x86_fp80* [[LD_ADDR:%.+]] to i128* // CHECK: store i128 [[INT_VALUE]], i128* [[INT_LOAD_ADDR]], align 16 - // CHECK: [[LD_VALUE:%.+]] = load x86_fp80* [[LD_ADDR]], align 16 + // CHECK: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[LD_ADDR]], align 16 // CHECK: br label %[[ATOMIC_OP:.+]] // CHECK: [[ATOMIC_OP]] // CHECK: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -18,29 +18,29 @@ long double testinc(_Atomic long double *addr) { // CHECK: call void @llvm.memset.p0i8.i64(i8* [[OLD_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 16 // CHECK: [[OLD_INT_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i128* - // CHECK: [[OLD_INT:%.+]] = load i128* [[OLD_INT_ADDR]], align 16 + // CHECK: [[OLD_INT:%.+]] = load i128, i128* [[OLD_INT_ADDR]], align 16 // CHECK: [[NEW_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[NEW_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[INC_VALUE]], x86_fp80* [[NEW_VALUE_ADDR]], align 16 // CHECK: [[NEW_INT_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR]] to i128* - // CHECK: [[NEW_INT:%.+]] = load i128* [[NEW_INT_ADDR]], align 16 + // CHECK: [[NEW_INT:%.+]] = load i128, i128* [[NEW_INT_ADDR]], align 16 // CHECK: [[OBJ_INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[RES:%.+]] = cmpxchg i128* [[OBJ_INT_ADDR]], i128 [[OLD_INT]], i128 [[NEW_INT]] seq_cst seq_cst // CHECK: [[OLD_VALUE:%.+]] = extractvalue { i128, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1 // CHECK: [[OLD_VALUE_RES_INT_PTR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_RES_PTR:%.+]] to i128* // CHECK: store i128 [[OLD_VALUE]], i128* [[OLD_VALUE_RES_INT_PTR]], align 16 - // CHECK: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 + // CHECK: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK: [[ATOMIC_CONT]] // CHECK: ret x86_fp80 [[INC_VALUE]] // CHECK32-LABEL: @testinc // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) - // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80* [[TEMP_LD_ADDR]], align 4 + // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -54,8 +54,8 @@ long double testinc(_Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 7, i32 7) - // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80* [[OLD_VALUE_ADDR]], align 4 + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) + // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] // CHECK32: ret x86_fp80 [[INC_VALUE]] @@ -66,12 +66,12 @@ long double testinc(_Atomic long double *addr) { long double testdec(_Atomic long double *addr) { // CHECK-LABEL: @testdec // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VALUE:%.+]] = load atomic i128* [[INT_ADDR]] seq_cst, align 16 + // CHECK: [[INT_VALUE:%.+]] = load atomic i128, i128* [[INT_ADDR]] seq_cst, align 16 // CHECK: [[INT_LOAD_ADDR:%.+]] = bitcast x86_fp80* [[LD_ADDR:%.+]] to i128* // CHECK: store i128 [[INT_VALUE]], i128* [[INT_LOAD_ADDR]], align 16 - // CHECK: [[ORIG_LD_VALUE:%.+]] = load x86_fp80* [[LD_ADDR]], align 16 + // CHECK: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[LD_ADDR]], align 16 // CHECK: br label %[[ATOMIC_OP:.+]] // CHECK: [[ATOMIC_OP]] // CHECK: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -80,29 +80,29 @@ long double testdec(_Atomic long double *addr) { // CHECK: call void @llvm.memset.p0i8.i64(i8* [[OLD_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 16 // CHECK: [[OLD_INT_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i128* - // CHECK: [[OLD_INT:%.+]] = load i128* [[OLD_INT_ADDR]], align 16 + // CHECK: [[OLD_INT:%.+]] = load i128, i128* [[OLD_INT_ADDR]], align 16 // CHECK: [[NEW_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[NEW_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[DEC_VALUE]], x86_fp80* [[NEW_VALUE_ADDR]], align 16 // CHECK: [[NEW_INT_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR]] to i128* - // CHECK: [[NEW_INT:%.+]] = load i128* [[NEW_INT_ADDR]], align 16 + // CHECK: [[NEW_INT:%.+]] = load i128, i128* [[NEW_INT_ADDR]], align 16 // CHECK: [[OBJ_INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[RES:%.+]] = cmpxchg i128* [[OBJ_INT_ADDR]], i128 [[OLD_INT]], i128 [[NEW_INT]] seq_cst seq_cst // CHECK: [[OLD_VALUE:%.+]] = extractvalue { i128, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1 // CHECK: [[OLD_VALUE_RES_INT_PTR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_RES_PTR:%.+]] to i128* // CHECK: store i128 [[OLD_VALUE]], i128* [[OLD_VALUE_RES_INT_PTR]], align 16 - // CHECK: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 + // CHECK: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK: [[ATOMIC_CONT]] // CHECK: ret x86_fp80 [[ORIG_LD_VALUE]] // CHECK32-LABEL: @testdec // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) - // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80* [[TEMP_LD_ADDR]], align 4 + // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -116,8 +116,8 @@ long double testdec(_Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 7, i32 7) - // CHECK32: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_ADDR]], align 4 + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) + // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] // CHECK32: ret x86_fp80 [[ORIG_LD_VALUE]] @@ -129,12 +129,12 @@ long double testcompassign(_Atomic long double *addr) { *addr -= 25; // CHECK-LABEL: @testcompassign // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VALUE:%.+]] = load atomic i128* [[INT_ADDR]] seq_cst, align 16 + // CHECK: [[INT_VALUE:%.+]] = load atomic i128, i128* [[INT_ADDR]] seq_cst, align 16 // CHECK: [[INT_LOAD_ADDR:%.+]] = bitcast x86_fp80* [[LD_ADDR:%.+]] to i128* // CHECK: store i128 [[INT_VALUE]], i128* [[INT_LOAD_ADDR]], align 16 - // CHECK: [[LD_VALUE:%.+]] = load x86_fp80* [[LD_ADDR]], align 16 + // CHECK: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[LD_ADDR]], align 16 // CHECK: br label %[[ATOMIC_OP:.+]] // CHECK: [[ATOMIC_OP]] // CHECK: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -143,35 +143,35 @@ long double testcompassign(_Atomic long double *addr) { // CHECK: call void @llvm.memset.p0i8.i64(i8* [[OLD_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 16 // CHECK: [[OLD_INT_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i128* - // CHECK: [[OLD_INT:%.+]] = load i128* [[OLD_INT_ADDR]], align 16 + // CHECK: [[OLD_INT:%.+]] = load i128, i128* [[OLD_INT_ADDR]], align 16 // CHECK: [[NEW_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[NEW_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[SUB_VALUE]], x86_fp80* [[NEW_VALUE_ADDR]], align 16 // CHECK: [[NEW_INT_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR]] to i128* - // CHECK: [[NEW_INT:%.+]] = load i128* [[NEW_INT_ADDR]], align 16 + // CHECK: [[NEW_INT:%.+]] = load i128, i128* [[NEW_INT_ADDR]], align 16 // CHECK: [[OBJ_INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[RES:%.+]] = cmpxchg i128* [[OBJ_INT_ADDR]], i128 [[OLD_INT]], i128 [[NEW_INT]] seq_cst seq_cst // CHECK: [[OLD_VALUE:%.+]] = extractvalue { i128, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1 // CHECK: [[OLD_VALUE_RES_INT_PTR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_RES_PTR:%.+]] to i128* // CHECK: store i128 [[OLD_VALUE]], i128* [[OLD_VALUE_RES_INT_PTR]], align 16 - // CHECK: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 + // CHECK: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK: [[ATOMIC_CONT]] - // CHECK: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VAL:%.+]] = load atomic i128* [[ADDR_INT]] seq_cst, align 16 + // CHECK: [[INT_VAL:%.+]] = load atomic i128, i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: [[INT_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i128* // CHECK: store i128 [[INT_VAL]], i128* [[INT_LD_TEMP:%.+]], align 16 - // CHECK: [[RET_VAL:%.+]] = load x86_fp80* [[LD_TEMP]], align 16 + // CHECK: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 16 // CHECK: ret x86_fp80 [[RET_VAL]] // CHECK32-LABEL: @testcompassign // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) - // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80* [[TEMP_LD_ADDR]], align 4 + // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -185,15 +185,15 @@ long double testcompassign(_Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 7, i32 7) - // CHECK32: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_ADDR]], align 4 + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) + // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] - // CHECK32: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_GET_ADDR:%.+]] = bitcast x86_fp80* [[GET_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_GET_ADDR]], i32 5) - // CHECK32: [[RET_VAL:%.+]] = load x86_fp80* [[GET_ADDR]], align 4 + // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[GET_ADDR]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] return *addr; } @@ -201,17 +201,17 @@ long double testcompassign(_Atomic long double *addr) { long double testassign(_Atomic long double *addr) { // CHECK-LABEL: @testassign // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[STORE_TEMP_VOID_PTR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 16 // CHECK: [[STORE_TEMP_INT_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i128* - // CHECK: [[STORE_TEMP_INT:%.+]] = load i128* [[STORE_TEMP_INT_PTR]], align 16 + // CHECK: [[STORE_TEMP_INT:%.+]] = load i128, i128* [[STORE_TEMP_INT_PTR]], align 16 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: store atomic i128 [[STORE_TEMP_INT]], i128* [[ADDR_INT]] seq_cst, align 16 // CHECK32-LABEL: @testassign // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8* // CHECK32: call void @llvm.memset.p0i8.i64(i8* [[STORE_TEMP_VOID_PTR]], i8 0, i64 12, i32 4, i1 false) // CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4 @@ -219,18 +219,18 @@ long double testassign(_Atomic long double *addr) { // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8* // CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5) *addr = 115; - // CHECK: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VAL:%.+]] = load atomic i128* [[ADDR_INT]] seq_cst, align 16 + // CHECK: [[INT_VAL:%.+]] = load atomic i128, i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: [[INT_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i128* // CHECK: store i128 [[INT_VAL]], i128* [[INT_LD_TEMP:%.+]], align 16 - // CHECK: [[RET_VAL:%.+]] = load x86_fp80* [[LD_TEMP]], align 16 + // CHECK: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 16 // CHECK: ret x86_fp80 [[RET_VAL]] - // CHECK32: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_LD_TEMP]], i32 5) - // CHECK32: [[RET_VAL:%.+]] = load x86_fp80* [[LD_TEMP]], align 4 + // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] return *addr; @@ -239,12 +239,12 @@ long double testassign(_Atomic long double *addr) { long double test_volatile_inc(volatile _Atomic long double *addr) { // CHECK-LABEL: @test_volatile_inc // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VALUE:%.+]] = load atomic volatile i128* [[INT_ADDR]] seq_cst, align 16 + // CHECK: [[INT_VALUE:%.+]] = load atomic volatile i128, i128* [[INT_ADDR]] seq_cst, align 16 // CHECK: [[INT_LOAD_ADDR:%.+]] = bitcast x86_fp80* [[LD_ADDR:%.+]] to i128* // CHECK: store i128 [[INT_VALUE]], i128* [[INT_LOAD_ADDR]], align 16 - // CHECK: [[LD_VALUE:%.+]] = load x86_fp80* [[LD_ADDR]], align 16 + // CHECK: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[LD_ADDR]], align 16 // CHECK: br label %[[ATOMIC_OP:.+]] // CHECK: [[ATOMIC_OP]] // CHECK: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -253,29 +253,29 @@ long double test_volatile_inc(volatile _Atomic long double *addr) { // CHECK: call void @llvm.memset.p0i8.i64(i8* [[OLD_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 16 // CHECK: [[OLD_INT_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i128* - // CHECK: [[OLD_INT:%.+]] = load i128* [[OLD_INT_ADDR]], align 16 + // CHECK: [[OLD_INT:%.+]] = load i128, i128* [[OLD_INT_ADDR]], align 16 // CHECK: [[NEW_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[NEW_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[INC_VALUE]], x86_fp80* [[NEW_VALUE_ADDR]], align 16 // CHECK: [[NEW_INT_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR]] to i128* - // CHECK: [[NEW_INT:%.+]] = load i128* [[NEW_INT_ADDR]], align 16 + // CHECK: [[NEW_INT:%.+]] = load i128, i128* [[NEW_INT_ADDR]], align 16 // CHECK: [[OBJ_INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[RES:%.+]] = cmpxchg volatile i128* [[OBJ_INT_ADDR]], i128 [[OLD_INT]], i128 [[NEW_INT]] seq_cst seq_cst // CHECK: [[OLD_VALUE:%.+]] = extractvalue { i128, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1 // CHECK: [[OLD_VALUE_RES_INT_PTR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_RES_PTR:%.+]] to i128* // CHECK: store i128 [[OLD_VALUE]], i128* [[OLD_VALUE_RES_INT_PTR]], align 16 - // CHECK: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 + // CHECK: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK: [[ATOMIC_CONT]] // CHECK: ret x86_fp80 [[INC_VALUE]] // CHECK32-LABEL: @test_volatile_inc // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) - // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80* [[TEMP_LD_ADDR]], align 4 + // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -289,8 +289,8 @@ long double test_volatile_inc(volatile _Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 7, i32 7) - // CHECK32: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_ADDR]], align 4 + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) + // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] // CHECK32: ret x86_fp80 [[INC_VALUE]] @@ -300,12 +300,12 @@ long double test_volatile_inc(volatile _Atomic long double *addr) { long double test_volatile_dec(volatile _Atomic long double *addr) { // CHECK-LABEL: @test_volatile_dec // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VALUE:%.+]] = load atomic volatile i128* [[INT_ADDR]] seq_cst, align 16 + // CHECK: [[INT_VALUE:%.+]] = load atomic volatile i128, i128* [[INT_ADDR]] seq_cst, align 16 // CHECK: [[INT_LOAD_ADDR:%.+]] = bitcast x86_fp80* [[LD_ADDR:%.+]] to i128* // CHECK: store i128 [[INT_VALUE]], i128* [[INT_LOAD_ADDR]], align 16 - // CHECK: [[ORIG_LD_VALUE:%.+]] = load x86_fp80* [[LD_ADDR]], align 16 + // CHECK: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[LD_ADDR]], align 16 // CHECK: br label %[[ATOMIC_OP:.+]] // CHECK: [[ATOMIC_OP]] // CHECK: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -314,29 +314,29 @@ long double test_volatile_dec(volatile _Atomic long double *addr) { // CHECK: call void @llvm.memset.p0i8.i64(i8* [[OLD_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 16 // CHECK: [[OLD_INT_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i128* - // CHECK: [[OLD_INT:%.+]] = load i128* [[OLD_INT_ADDR]], align 16 + // CHECK: [[OLD_INT:%.+]] = load i128, i128* [[OLD_INT_ADDR]], align 16 // CHECK: [[NEW_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[NEW_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[DEC_VALUE]], x86_fp80* [[NEW_VALUE_ADDR]], align 16 // CHECK: [[NEW_INT_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR]] to i128* - // CHECK: [[NEW_INT:%.+]] = load i128* [[NEW_INT_ADDR]], align 16 + // CHECK: [[NEW_INT:%.+]] = load i128, i128* [[NEW_INT_ADDR]], align 16 // CHECK: [[OBJ_INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[RES:%.+]] = cmpxchg volatile i128* [[OBJ_INT_ADDR]], i128 [[OLD_INT]], i128 [[NEW_INT]] seq_cst seq_cst // CHECK: [[OLD_VALUE:%.+]] = extractvalue { i128, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1 // CHECK: [[OLD_VALUE_RES_INT_PTR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_RES_PTR:%.+]] to i128* // CHECK: store i128 [[OLD_VALUE]], i128* [[OLD_VALUE_RES_INT_PTR]], align 16 - // CHECK: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 + // CHECK: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK: [[ATOMIC_CONT]] // CHECK: ret x86_fp80 [[ORIG_LD_VALUE]] // CHECK32-LABEL: @test_volatile_dec // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) - // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80* [[TEMP_LD_ADDR]], align 4 + // CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[ORIG_LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -350,8 +350,8 @@ long double test_volatile_dec(volatile _Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 7, i32 7) - // CHECK32: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_ADDR]], align 4 + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) + // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] // CHECK32: ret x86_fp80 [[ORIG_LD_VALUE]] @@ -362,12 +362,12 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) { *addr -= 25; // CHECK-LABEL: @test_volatile_compassign // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VALUE:%.+]] = load atomic volatile i128* [[INT_ADDR]] seq_cst, align 16 + // CHECK: [[INT_VALUE:%.+]] = load atomic volatile i128, i128* [[INT_ADDR]] seq_cst, align 16 // CHECK: [[INT_LOAD_ADDR:%.+]] = bitcast x86_fp80* [[LD_ADDR:%.+]] to i128* // CHECK: store i128 [[INT_VALUE]], i128* [[INT_LOAD_ADDR]], align 16 - // CHECK: [[LD_VALUE:%.+]] = load x86_fp80* [[LD_ADDR]], align 16 + // CHECK: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[LD_ADDR]], align 16 // CHECK: br label %[[ATOMIC_OP:.+]] // CHECK: [[ATOMIC_OP]] // CHECK: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -376,34 +376,34 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) { // CHECK: call void @llvm.memset.p0i8.i64(i8* [[OLD_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[OLD_VALUE]], x86_fp80* [[OLD_VALUE_ADDR]], align 16 // CHECK: [[OLD_INT_ADDR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i128* - // CHECK: [[OLD_INT:%.+]] = load i128* [[OLD_INT_ADDR]], align 16 + // CHECK: [[OLD_INT:%.+]] = load i128, i128* [[OLD_INT_ADDR]], align 16 // CHECK: [[NEW_VALUE_VOID_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[NEW_VALUE_VOID_ADDR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 [[SUB_VALUE]], x86_fp80* [[NEW_VALUE_ADDR]], align 16 // CHECK: [[NEW_INT_ADDR:%.+]] = bitcast x86_fp80* [[NEW_VALUE_ADDR]] to i128* - // CHECK: [[NEW_INT:%.+]] = load i128* [[NEW_INT_ADDR]], align 16 + // CHECK: [[NEW_INT:%.+]] = load i128, i128* [[NEW_INT_ADDR]], align 16 // CHECK: [[OBJ_INT_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: [[RES:%.+]] = cmpxchg volatile i128* [[OBJ_INT_ADDR]], i128 [[OLD_INT]], i128 [[NEW_INT]] seq_cst seq_cst // CHECK: [[OLD_VALUE:%.+]] = extractvalue { i128, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i128, i1 } [[RES]], 1 // CHECK: [[OLD_VALUE_RES_INT_PTR:%.+]] = bitcast x86_fp80* [[OLD_VALUE_RES_PTR:%.+]] to i128* // CHECK: store i128 [[OLD_VALUE]], i128* [[OLD_VALUE_RES_INT_PTR]], align 16 - // CHECK: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 + // CHECK: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_RES_PTR]], align 16 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK: [[ATOMIC_CONT]] - // CHECK: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VAL:%.+]] = load atomic volatile i128* [[ADDR_INT]] seq_cst, align 16 + // CHECK: [[INT_VAL:%.+]] = load atomic volatile i128, i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: [[INT_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i128* // CHECK: store i128 [[INT_VAL]], i128* [[INT_LD_TEMP:%.+]], align 16 - // CHECK: [[RET_VAL:%.+]] = load x86_fp80* [[LD_TEMP]], align 16 + // CHECK: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 16 // CHECK32-LABEL: @test_volatile_compassign // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5) - // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80* [[TEMP_LD_ADDR]], align 4 + // CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4 // CHECK32: br label %[[ATOMIC_OP:.+]] // CHECK32: [[ATOMIC_OP]] // CHECK32: [[OLD_VALUE:%.+]] = phi x86_fp80 [ [[LD_VALUE]], %{{.+}} ], [ [[LD_VALUE:%.+]], %[[ATOMIC_OP]] ] @@ -417,15 +417,15 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) { // CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8* // CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8* - // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 7, i32 7) - // CHECK32: [[LD_VALUE]] = load x86_fp80* [[OLD_VALUE_ADDR]], align 4 + // CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5) + // CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4 // CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]] // CHECK32: [[ATOMIC_CONT]] - // CHECK32: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_GET_ADDR:%.+]] = bitcast x86_fp80* [[GET_ADDR:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_GET_ADDR]], i32 5) - // CHECK32: [[RET_VAL:%.+]] = load x86_fp80* [[GET_ADDR]], align 4 + // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[GET_ADDR]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] return *addr; } @@ -433,17 +433,17 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) { long double test_volatile_assign(volatile _Atomic long double *addr) { // CHECK-LABEL: @test_volatile_assign // CHECK: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 8 - // CHECK: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 8 // CHECK: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8* // CHECK: call void @llvm.memset.p0i8.i64(i8* [[STORE_TEMP_VOID_PTR]], i8 0, i64 16, i32 16, i1 false) // CHECK: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 16 // CHECK: [[STORE_TEMP_INT_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i128* - // CHECK: [[STORE_TEMP_INT:%.+]] = load i128* [[STORE_TEMP_INT_PTR]], align 16 + // CHECK: [[STORE_TEMP_INT:%.+]] = load i128, i128* [[STORE_TEMP_INT_PTR]], align 16 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* // CHECK: store atomic volatile i128 [[STORE_TEMP_INT]], i128* [[ADDR_INT]] seq_cst, align 16 // CHECK32-LABEL: @test_volatile_assign // CHECK32: store x86_fp80* %{{.+}}, x86_fp80** [[ADDR_ADDR:%.+]], align 4 - // CHECK32: [[ADDR:%.+]] = load x86_fp80** [[ADDR_ADDR]], align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4 // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR:%.+]] to i8* // CHECK32: call void @llvm.memset.p0i8.i64(i8* [[STORE_TEMP_VOID_PTR]], i8 0, i64 12, i32 4, i1 false) // CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4 @@ -451,18 +451,18 @@ long double test_volatile_assign(volatile _Atomic long double *addr) { // CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8* // CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5) *addr = 115; - // CHECK: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 8 + // CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8 // CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128* - // CHECK: [[INT_VAL:%.+]] = load atomic volatile i128* [[ADDR_INT]] seq_cst, align 16 + // CHECK: [[INT_VAL:%.+]] = load atomic volatile i128, i128* [[ADDR_INT]] seq_cst, align 16 // CHECK: [[INT_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i128* // CHECK: store i128 [[INT_VAL]], i128* [[INT_LD_TEMP:%.+]], align 16 - // CHECK: [[RET_VAL:%.+]] = load x86_fp80* [[LD_TEMP]], align 16 + // CHECK: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 16 // CHECK: ret x86_fp80 [[RET_VAL]] - // CHECK32: [[ADDR:%.+]] = load x86_fp80** %{{.+}}, align 4 + // CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4 // CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8* // CHECK32: [[VOID_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i8* // CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_LD_TEMP]], i32 5) - // CHECK32: [[RET_VAL:%.+]] = load x86_fp80* [[LD_TEMP]], align 4 + // CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 4 // CHECK32: ret x86_fp80 [[RET_VAL]] return *addr; diff --git a/test/CodeGen/x86_32-arguments-darwin.c b/test/CodeGen/x86_32-arguments-darwin.c index 422e030537e0..1536631fb0f3 100644 --- a/test/CodeGen/x86_32-arguments-darwin.c +++ b/test/CodeGen/x86_32-arguments-darwin.c @@ -236,7 +236,7 @@ v4i32 f55(v4i32 arg) { return arg+arg; } // CHECK: <8 x i32> %a10, %struct.s56_5* byval align 4, // CHECK: <4 x double> %a12, %struct.s56_6* byval align 4) -// CHECK: call void (i32, ...)* @f56_0(i32 1, +// CHECK: call void (i32, ...) @f56_0(i32 1, // CHECK: i32 %{{[^ ]*}}, %struct.s56_0* byval align 4 %{{[^ ]*}}, // CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval align 4 %{{[^ ]*}}, // CHECK: i64 %{{[^ ]*}}, %struct.s56_2* byval align 4 %{{[^ ]*}}, diff --git a/test/CodeGen/x86_32-arguments-linux.c b/test/CodeGen/x86_32-arguments-linux.c index 1a8c6001292b..02eac51216af 100644 --- a/test/CodeGen/x86_32-arguments-linux.c +++ b/test/CodeGen/x86_32-arguments-linux.c @@ -10,7 +10,7 @@ // CHECK: <8 x i32> %a10, %struct.s56_5* byval align 4, // CHECK: <4 x double> %a12, %struct.s56_6* byval align 4) -// CHECK: call void (i32, ...)* @f56_0(i32 1, +// CHECK: call void (i32, ...) @f56_0(i32 1, // CHECK: i32 %{{.*}}, %struct.s56_0* byval align 4 %{{[^ ]*}}, // CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval align 4 %{{[^ ]*}}, // CHECK: <1 x double> %{{[^ ]*}}, %struct.s56_2* byval align 4 %{{[^ ]*}}, diff --git a/test/CodeGen/x86_64-arguments-nacl.c b/test/CodeGen/x86_64-arguments-nacl.c index 1c3f5b0c4a2f..cbfad1a1cb57 100644 --- a/test/CodeGen/x86_64-arguments-nacl.c +++ b/test/CodeGen/x86_64-arguments-nacl.c @@ -90,31 +90,3 @@ void f9122143() { func(ss); } - - -typedef struct { - int a; - int b; -} s1; -// CHECK-LABEL: define i32 @f48(%struct.s1* byval %s) -int __attribute__((pnaclcall)) f48(s1 s) { return s.a; } - -// CHECK-LABEL: define void @f49(%struct.s1* noalias sret %agg.result) -s1 __attribute__((pnaclcall)) f49() { s1 s; s.a = s.b = 1; return s; } - -union simple_union { - int a; - char b; -}; -// Unions should be passed as byval structs -// CHECK-LABEL: define void @f50(%union.simple_union* byval %s) -void __attribute__((pnaclcall)) f50(union simple_union s) {} - -typedef struct { - int b4 : 4; - int b3 : 3; - int b8 : 8; -} bitfield1; -// Bitfields should be passed as byval structs -// CHECK-LABEL: define void @f51(%struct.bitfield1* byval %bf1) -void __attribute__((pnaclcall)) f51(bitfield1 bf1) {} diff --git a/test/CodeGen/x86_64-arguments-win32.c b/test/CodeGen/x86_64-arguments-win32.c index 5aea7fc62368..7731eadd01ea 100644 --- a/test/CodeGen/x86_64-arguments-win32.c +++ b/test/CodeGen/x86_64-arguments-win32.c @@ -14,3 +14,18 @@ void f3(short a) {} // CHECK-LABEL: define void @f4(i16 %a) void f4(unsigned short a) {} + +// For ABI compatibility with ICC, _Complex should be passed/returned +// as if it were a struct with two elements. + +// CHECK-LABEL: define void @f5(i64 %a.coerce) +void f5(_Complex float a) {} + +// CHECK-LABEL: define void @f6({ double, double }* %a) +void f6(_Complex double a) {} + +// CHECK-LABEL: define i64 @f7() +_Complex float f7() { return 1.0; } + +// CHECK-LABEL: define void @f8({ double, double }* noalias sret %agg.result) +_Complex double f8() { return 1.0; } diff --git a/test/CodeGen/x86_64-arguments.c b/test/CodeGen/x86_64-arguments.c index e82e7b067ada..c412e3c06e86 100644 --- a/test/CodeGen/x86_64-arguments.c +++ b/test/CodeGen/x86_64-arguments.c @@ -1,5 +1,7 @@ -// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s| FileCheck %s -// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | FileCheck %s -check-prefix=AVX +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | \ +// RUN: FileCheck %s -check-prefix=CHECK -check-prefix=SSE +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s -target-feature +avx | \ +// RUN: FileCheck %s -check-prefix=CHECK -check-prefix=AVX #include <stdarg.h> // CHECK-LABEL: define signext i8 @f0() @@ -288,8 +290,8 @@ v2i32 f36(v2i32 arg) { return arg; } // AVX: declare void @f38(<8 x float>) // AVX: declare void @f37(<8 x float>) -// CHECK: declare void @f38(%struct.s256* byval align 32) -// CHECK: declare void @f37(<8 x float>* byval align 32) +// SSE: declare void @f38(%struct.s256* byval align 32) +// SSE: declare void @f37(<8 x float>* byval align 32) typedef float __m256 __attribute__ ((__vector_size__ (32))); typedef struct { __m256 m; @@ -402,18 +404,18 @@ void test49(double d, double e) { test49_helper(d, e); } // CHECK-LABEL: define void @test49( -// CHECK: [[T0:%.*]] = load double* -// CHECK-NEXT: [[T1:%.*]] = load double* -// CHECK-NEXT: call void (double, ...)* @test49_helper(double [[T0]], double [[T1]]) +// CHECK: [[T0:%.*]] = load double, double* +// CHECK-NEXT: [[T1:%.*]] = load double, double* +// CHECK-NEXT: call void (double, ...) @test49_helper(double [[T0]], double [[T1]]) void test50_helper(); void test50(double d, double e) { test50_helper(d, e); } // CHECK-LABEL: define void @test50( -// CHECK: [[T0:%.*]] = load double* -// CHECK-NEXT: [[T1:%.*]] = load double* -// CHECK-NEXT: call void (double, double, ...)* bitcast (void (...)* @test50_helper to void (double, double, ...)*)(double [[T0]], double [[T1]]) +// CHECK: [[T0:%.*]] = load double, double* +// CHECK-NEXT: [[T1:%.*]] = load double, double* +// CHECK-NEXT: call void (double, double, ...) bitcast (void (...)* @test50_helper to void (double, double, ...)*)(double [[T0]], double [[T1]]) struct test51_s { __uint128_t intval; }; void test51(struct test51_s *s, __builtin_va_list argList) { @@ -424,8 +426,8 @@ void test51(struct test51_s *s, __builtin_va_list argList) { // CHECK: [[TMP_ADDR:%.*]] = alloca [[STRUCT_TEST51:%.*]], align 16 // CHECK: br i1 // CHECK: [[REG_SAVE_AREA_PTR:%.*]] = getelementptr inbounds {{.*}}, i32 0, i32 3 -// CHECK-NEXT: [[REG_SAVE_AREA:%.*]] = load i8** [[REG_SAVE_AREA_PTR]] -// CHECK-NEXT: [[VALUE_ADDR:%.*]] = getelementptr i8* [[REG_SAVE_AREA]], i32 {{.*}} +// CHECK-NEXT: [[REG_SAVE_AREA:%.*]] = load i8*, i8** [[REG_SAVE_AREA_PTR]] +// CHECK-NEXT: [[VALUE_ADDR:%.*]] = getelementptr i8, i8* [[REG_SAVE_AREA]], i32 {{.*}} // CHECK-NEXT: [[CASTED_VALUE_ADDR:%.*]] = bitcast i8* [[VALUE_ADDR]] to [[STRUCT_TEST51]] // CHECK-NEXT: [[CASTED_TMP_ADDR:%.*]] = bitcast [[STRUCT_TEST51]]* [[TMP_ADDR]] to i8* // CHECK-NEXT: [[RECASTED_VALUE_ADDR:%.*]] = bitcast [[STRUCT_TEST51]]* [[CASTED_VALUE_ADDR]] to i8* diff --git a/test/CodeGen/xcore-abi.c b/test/CodeGen/xcore-abi.c index 6dbc44b5595d..23fb44146945 100644 --- a/test/CodeGen/xcore-abi.c +++ b/test/CodeGen/xcore-abi.c @@ -31,52 +31,52 @@ void testva (int n, ...) { char* v1 = va_arg (ap, char*); f(v1); - // CHECK: [[I:%[a-z0-9]+]] = load i8** [[AP]] + // CHECK: [[I:%[a-z0-9]+]] = load i8*, i8** [[AP]] // CHECK: [[P:%[a-z0-9]+]] = bitcast i8* [[I]] to i8** - // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8* [[I]], i32 4 + // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8, i8* [[I]], i32 4 // CHECK: store i8* [[IN]], i8** [[AP]] - // CHECK: [[V1:%[a-z0-9]+]] = load i8** [[P]] + // CHECK: [[V1:%[a-z0-9]+]] = load i8*, i8** [[P]] // CHECK: store i8* [[V1]], i8** [[V:%[a-z0-9]+]], align 4 - // CHECK: [[V2:%[a-z0-9]+]] = load i8** [[V]], align 4 + // CHECK: [[V2:%[a-z0-9]+]] = load i8*, i8** [[V]], align 4 // CHECK: call void @f(i8* [[V2]]) char v2 = va_arg (ap, char); // expected-warning{{second argument to 'va_arg' is of promotable type 'char'}} f(&v2); - // CHECK: [[I:%[a-z0-9]+]] = load i8** [[AP]] - // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8* [[I]], i32 4 + // CHECK: [[I:%[a-z0-9]+]] = load i8*, i8** [[AP]] + // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8, i8* [[I]], i32 4 // CHECK: store i8* [[IN]], i8** [[AP]] - // CHECK: [[V1:%[a-z0-9]+]] = load i8* [[I]] + // CHECK: [[V1:%[a-z0-9]+]] = load i8, i8* [[I]] // CHECK: store i8 [[V1]], i8* [[V:%[a-z0-9]+]], align 1 // CHECK: call void @f(i8* [[V]]) int v3 = va_arg (ap, int); f(&v3); - // CHECK: [[I:%[a-z0-9]+]] = load i8** [[AP]] + // CHECK: [[I:%[a-z0-9]+]] = load i8*, i8** [[AP]] // CHECK: [[P:%[a-z0-9]+]] = bitcast i8* [[I]] to i32* - // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8* [[I]], i32 4 + // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8, i8* [[I]], i32 4 // CHECK: store i8* [[IN]], i8** [[AP]] - // CHECK: [[V1:%[a-z0-9]+]] = load i32* [[P]] + // CHECK: [[V1:%[a-z0-9]+]] = load i32, i32* [[P]] // CHECK: store i32 [[V1]], i32* [[V:%[a-z0-9]+]], align 4 // CHECK: [[V2:%[a-z0-9]+]] = bitcast i32* [[V]] to i8* // CHECK: call void @f(i8* [[V2]]) long long int v4 = va_arg (ap, long long int); f(&v4); - // CHECK: [[I:%[a-z0-9]+]] = load i8** [[AP]] + // CHECK: [[I:%[a-z0-9]+]] = load i8*, i8** [[AP]] // CHECK: [[P:%[a-z0-9]+]] = bitcast i8* [[I]] to i64* - // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8* [[I]], i32 8 + // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8, i8* [[I]], i32 8 // CHECK: store i8* [[IN]], i8** [[AP]] - // CHECK: [[V1:%[a-z0-9]+]] = load i64* [[P]] + // CHECK: [[V1:%[a-z0-9]+]] = load i64, i64* [[P]] // CHECK: store i64 [[V1]], i64* [[V:%[a-z0-9]+]], align 4 // CHECK:[[V2:%[a-z0-9]+]] = bitcast i64* [[V]] to i8* // CHECK: call void @f(i8* [[V2]]) struct x v5 = va_arg (ap, struct x); // typical aggregate type f(&v5); - // CHECK: [[I:%[a-z0-9]+]] = load i8** [[AP]] + // CHECK: [[I:%[a-z0-9]+]] = load i8*, i8** [[AP]] // CHECK: [[I2:%[a-z0-9]+]] = bitcast i8* [[I]] to %struct.x** - // CHECK: [[P:%[a-z0-9]+]] = load %struct.x** [[I2]] - // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8* [[I]], i32 4 + // CHECK: [[P:%[a-z0-9]+]] = load %struct.x*, %struct.x** [[I2]] + // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8, i8* [[I]], i32 4 // CHECK: store i8* [[IN]], i8** [[AP]] // CHECK: [[V1:%[a-z0-9]+]] = bitcast %struct.x* [[V:%[a-z0-9]+]] to i8* // CHECK: [[P1:%[a-z0-9]+]] = bitcast %struct.x* [[P]] to i8* @@ -86,27 +86,27 @@ void testva (int n, ...) { int* v6 = va_arg (ap, int[4]); // an unusual aggregate type f(v6); - // CHECK: [[I:%[a-z0-9]+]] = load i8** [[AP]] + // CHECK: [[I:%[a-z0-9]+]] = load i8*, i8** [[AP]] // CHECK: [[I2:%[a-z0-9]+]] = bitcast i8* [[I]] to [4 x i32]** - // CHECK: [[P:%[a-z0-9]+]] = load [4 x i32]** [[I2]] - // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8* [[I]], i32 4 + // CHECK: [[P:%[a-z0-9]+]] = load [4 x i32]*, [4 x i32]** [[I2]] + // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8, i8* [[I]], i32 4 // CHECK: store i8* [[IN]], i8** [[AP]] // CHECK: [[V1:%[a-z0-9]+]] = bitcast [4 x i32]* [[V0:%[a-z0-9]+]] to i8* // CHECK: [[P1:%[a-z0-9]+]] = bitcast [4 x i32]* [[P]] to i8* // CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[V1]], i8* [[P1]], i32 16, i32 4, i1 false) - // CHECK: [[V2:%[a-z0-9]+]] = getelementptr inbounds [4 x i32]* [[V0]], i32 0, i32 0 + // CHECK: [[V2:%[a-z0-9]+]] = getelementptr inbounds [4 x i32], [4 x i32]* [[V0]], i32 0, i32 0 // CHECK: store i32* [[V2]], i32** [[V:%[a-z0-9]+]], align 4 - // CHECK: [[V3:%[a-z0-9]+]] = load i32** [[V]], align 4 + // CHECK: [[V3:%[a-z0-9]+]] = load i32*, i32** [[V]], align 4 // CHECK: [[V4:%[a-z0-9]+]] = bitcast i32* [[V3]] to i8* // CHECK: call void @f(i8* [[V4]]) double v7 = va_arg (ap, double); f(&v7); - // CHECK: [[I:%[a-z0-9]+]] = load i8** [[AP]] + // CHECK: [[I:%[a-z0-9]+]] = load i8*, i8** [[AP]] // CHECK: [[P:%[a-z0-9]+]] = bitcast i8* [[I]] to double* - // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8* [[I]], i32 8 + // CHECK: [[IN:%[a-z0-9]+]] = getelementptr i8, i8* [[I]], i32 8 // CHECK: store i8* [[IN]], i8** [[AP]] - // CHECK: [[V1:%[a-z0-9]+]] = load double* [[P]] + // CHECK: [[V1:%[a-z0-9]+]] = load double, double* [[P]] // CHECK: store double [[V1]], double* [[V:%[a-z0-9]+]], align 4 // CHECK: [[V2:%[a-z0-9]+]] = bitcast double* [[V]] to i8* // CHECK: call void @f(i8* [[V2]]) |