diff options
Diffstat (limited to 'test/MC/AArch64/SVE/trn2-diagnostics.s')
| -rw-r--r-- | test/MC/AArch64/SVE/trn2-diagnostics.s | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/test/MC/AArch64/SVE/trn2-diagnostics.s b/test/MC/AArch64/SVE/trn2-diagnostics.s new file mode 100644 index 000000000000..48b37bf3a181 --- /dev/null +++ b/test/MC/AArch64/SVE/trn2-diagnostics.s @@ -0,0 +1,43 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Invalid element kind. +trn2 z6.h, z23.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: trn2 z6.h, z23.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +trn2 z0.h, z30.h, z24.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: trn2 z0.h, z30.h, z24.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Too few operands +trn2 z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction +// CHECK-NEXT: trn2 z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// z32 is not a valid SVE data register +trn2 z1.s, z2.s, z32.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 z1.s, z2.s, z32.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// p16 is not a valid SVE predicate register +trn2 p1.s, p2.s, p16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 p1.s, p2.s, p16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining data and predicate registers as operands +trn2 z1.s, z2.s, p3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 z1.s, z2.s, p3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining predicate and data registers as operands +trn2 p1.s, p2.s, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 p1.s, p2.s, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |