diff options
Diffstat (limited to 'test/MC/AArch64/SVE')
362 files changed, 8856 insertions, 19 deletions
diff --git a/test/MC/AArch64/SVE/abs.s b/test/MC/AArch64/SVE/abs.s index 6341c4f4885d..460f846cdc03 100644 --- a/test/MC/AArch64/SVE/abs.s +++ b/test/MC/AArch64/SVE/abs.s @@ -54,3 +54,31 @@ abs z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd6,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d6 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +abs z4.d, p7/m, z31.d +// CHECK-INST: abs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d6 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +abs z4.d, p7/m, z31.d +// CHECK-INST: abs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d6 04 <unknown> diff --git a/test/MC/AArch64/SVE/add-diagnostics.s b/test/MC/AArch64/SVE/add-diagnostics.s index 23042b6708c0..6d95a645f068 100644 --- a/test/MC/AArch64/SVE/add-diagnostics.s +++ b/test/MC/AArch64/SVE/add-diagnostics.s @@ -144,3 +144,25 @@ add z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: add z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +add z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: add z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.s, p0/z, z30.s +add z23.s, z13.s, z8.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: add z23.s, z13.s, z8.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +add z23.s, z13.s, z8.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: add z23.s, z13.s, z8.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/add.s b/test/MC/AArch64/SVE/add.s index f477eb956871..2064181d18d2 100644 --- a/test/MC/AArch64/SVE/add.s +++ b/test/MC/AArch64/SVE/add.s @@ -283,3 +283,43 @@ add z31.d, z31.d, #65280 // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e0 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.b, p7/z, z6.b +// CHECK-INST: movprfx z4.b, p7/z, z6.b +// CHECK-ENCODING: [0xc4,0x3c,0x10,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 10 04 <unknown> + +add z4.b, p7/m, z4.b, z31.b +// CHECK-INST: add z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 00 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +add z4.b, p7/m, z4.b, z31.b +// CHECK-INST: add z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 00 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +add z31.d, z31.d, #65280 +// CHECK-INST: add z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe0,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e0 25 <unknown> diff --git a/test/MC/AArch64/SVE/adr-diagnostics.s b/test/MC/AArch64/SVE/adr-diagnostics.s index 99890ff79304..2bab1f7faeaa 100644 --- a/test/MC/AArch64/SVE/adr-diagnostics.s +++ b/test/MC/AArch64/SVE/adr-diagnostics.s @@ -57,3 +57,19 @@ adr z0.d, [z0.d, z0.d, sxtw #4] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/and-diagnostics.s b/test/MC/AArch64/SVE/and-diagnostics.s index 2ea6b3eb2721..ff7332e60e70 100644 --- a/test/MC/AArch64/SVE/and-diagnostics.s +++ b/test/MC/AArch64/SVE/and-diagnostics.s @@ -92,3 +92,25 @@ and p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: and p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +and z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: and z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +and z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: and z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +and z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: and z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/and.s b/test/MC/AArch64/SVE/and.s index 88e2439c44ed..0d0edc73e8f5 100644 --- a/test/MC/AArch64/SVE/and.s +++ b/test/MC/AArch64/SVE/and.s @@ -108,3 +108,43 @@ and p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7d 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +and z4.d, p7/m, z4.d, z31.d +// CHECK-INST: and z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f da 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +and z4.d, p7/m, z4.d, z31.d +// CHECK-INST: and z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f da 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +and z0.d, z0.d, #0x6 +// CHECK-INST: and z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x83,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 83 05 <unknown> diff --git a/test/MC/AArch64/SVE/andv-diagnostics.s b/test/MC/AArch64/SVE/andv-diagnostics.s index 60a42f826049..2048d77ff900 100644 --- a/test/MC/AArch64/SVE/andv-diagnostics.s +++ b/test/MC/AArch64/SVE/andv-diagnostics.s @@ -31,4 +31,19 @@ andv v0.2d, p7, z31.d andv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: andv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +andv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: andv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +andv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: andv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/asr-diagnostics.s b/test/MC/AArch64/SVE/asr-diagnostics.s index a4811324d264..9cec835dbe2f 100644 --- a/test/MC/AArch64/SVE/asr-diagnostics.s +++ b/test/MC/AArch64/SVE/asr-diagnostics.s @@ -122,3 +122,31 @@ asr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: asr z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +asr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +asr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +asr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +asr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/asr.s b/test/MC/AArch64/SVE/asr.s index 7204a27155d4..d514eda2af13 100644 --- a/test/MC/AArch64/SVE/asr.s +++ b/test/MC/AArch64/SVE/asr.s @@ -162,3 +162,55 @@ asr z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x80,0xa2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 80 a2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +asr z31.d, p0/m, z31.d, #64 +// CHECK-INST: asr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x80,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 80 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +asr z31.d, p0/m, z31.d, #64 +// CHECK-INST: asr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x80,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 80 04 <unknown> + +movprfx z0.s, p0/z, z7.s +// CHECK-INST: movprfx z0.s, p0/z, z7.s +// CHECK-ENCODING: [0xe0,0x20,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 90 04 <unknown> + +asr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: asr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x98,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 98 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +asr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: asr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x98,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 98 04 <unknown> diff --git a/test/MC/AArch64/SVE/asrd.s b/test/MC/AArch64/SVE/asrd.s index 69805517c1cb..78fbbba5b338 100644 --- a/test/MC/AArch64/SVE/asrd.s +++ b/test/MC/AArch64/SVE/asrd.s @@ -54,3 +54,31 @@ asrd z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 1f 80 84 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +asrd z31.d, p0/m, z31.d, #64 +// CHECK-INST: asrd z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x84,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 84 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +asrd z31.d, p0/m, z31.d, #64 +// CHECK-INST: asrd z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x84,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 84 04 <unknown> diff --git a/test/MC/AArch64/SVE/asrr.s b/test/MC/AArch64/SVE/asrr.s index e7f7cc5afa2c..f9cc7ea6f8ee 100644 --- a/test/MC/AArch64/SVE/asrr.s +++ b/test/MC/AArch64/SVE/asrr.s @@ -30,3 +30,31 @@ asrr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd4,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d4 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +asrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d4 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +asrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d4 04 <unknown> diff --git a/test/MC/AArch64/SVE/bic-diagnostics.s b/test/MC/AArch64/SVE/bic-diagnostics.s index 61d0231e4cf4..abdd52028d01 100644 --- a/test/MC/AArch64/SVE/bic-diagnostics.s +++ b/test/MC/AArch64/SVE/bic-diagnostics.s @@ -92,3 +92,25 @@ bic p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: bic p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +bic z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: bic z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +bic z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bic z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +bic z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bic z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/bic.s b/test/MC/AArch64/SVE/bic.s index bd19fcd9fcfd..c9e6d9b82665 100644 --- a/test/MC/AArch64/SVE/bic.s +++ b/test/MC/AArch64/SVE/bic.s @@ -102,3 +102,43 @@ bic p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x40,0x00,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 10 40 00 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +bic z4.d, p7/m, z4.d, z31.d +// CHECK-INST: bic z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f db 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +bic z4.d, p7/m, z4.d, z31.d +// CHECK-INST: bic z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f db 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +bic z0.d, z0.d, #0x6 +// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x83,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 83 05 <unknown> diff --git a/test/MC/AArch64/SVE/brka-diagnostics.s b/test/MC/AArch64/SVE/brka-diagnostics.s new file mode 100644 index 000000000000..140ac004fe07 --- /dev/null +++ b/test/MC/AArch64/SVE/brka-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brka p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brka p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brka.s b/test/MC/AArch64/SVE/brka.s new file mode 100644 index 000000000000..d87e7632e3fd --- /dev/null +++ b/test/MC/AArch64/SVE/brka.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brka p0.b, p15/m, p15.b +// CHECK-INST: brka p0.b, p15/m, p15.b +// CHECK-ENCODING: [0xf0,0x7d,0x10,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 7d 10 25 <unknown> + +brka p0.b, p15/z, p15.b +// CHECK-INST: brka p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0x10,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d 10 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkas-diagnostics.s b/test/MC/AArch64/SVE/brkas-diagnostics.s new file mode 100644 index 000000000000..14fe7cf6ba6d --- /dev/null +++ b/test/MC/AArch64/SVE/brkas-diagnostics.s @@ -0,0 +1,19 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkas p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkas p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// flag-setting variant does not have merging predication + +brkas p0.b, p15/m, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkas p0.b, p15/m, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkas.s b/test/MC/AArch64/SVE/brkas.s new file mode 100644 index 000000000000..f75c5bc8069d --- /dev/null +++ b/test/MC/AArch64/SVE/brkas.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkas p0.b, p15/z, p15.b +// CHECK-INST: brkas p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d 50 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkb-diagnostics.s b/test/MC/AArch64/SVE/brkb-diagnostics.s new file mode 100644 index 000000000000..7f87f15d3885 --- /dev/null +++ b/test/MC/AArch64/SVE/brkb-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkb p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkb p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkb.s b/test/MC/AArch64/SVE/brkb.s new file mode 100644 index 000000000000..393d29449588 --- /dev/null +++ b/test/MC/AArch64/SVE/brkb.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkb p0.b, p15/m, p15.b +// CHECK-INST: brkb p0.b, p15/m, p15.b +// CHECK-ENCODING: [0xf0,0x7d,0x90,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 7d 90 25 <unknown> + +brkb p0.b, p15/z, p15.b +// CHECK-INST: brkb p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0x90,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d 90 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkbs-diagnostics.s b/test/MC/AArch64/SVE/brkbs-diagnostics.s new file mode 100644 index 000000000000..bcb9a6464b1e --- /dev/null +++ b/test/MC/AArch64/SVE/brkbs-diagnostics.s @@ -0,0 +1,19 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkbs p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkbs p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// flag-setting variant does not have merging predication + +brkbs p0.b, p15/m, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkbs p0.b, p15/m, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkbs.s b/test/MC/AArch64/SVE/brkbs.s new file mode 100644 index 000000000000..708ec91345c3 --- /dev/null +++ b/test/MC/AArch64/SVE/brkbs.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkbs p0.b, p15/z, p15.b +// CHECK-INST: brkbs p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0xd0,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d d0 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkn-diagnostics.s b/test/MC/AArch64/SVE/brkn-diagnostics.s new file mode 100644 index 000000000000..87587fbe373c --- /dev/null +++ b/test/MC/AArch64/SVE/brkn-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// BRKN only supports merging predication + +brkn p0.b, p15/m, p1.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkn p0.b, p15/m, p1.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Check tied operand constraints + +brkn p0.b, p15/z, p1.b, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: brkn p0.b, p15/z, p1.b, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkn p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkn p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkn.s b/test/MC/AArch64/SVE/brkn.s new file mode 100644 index 000000000000..8494e547732f --- /dev/null +++ b/test/MC/AArch64/SVE/brkn.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkn p0.b, p15/z, p1.b, p0.b +// CHECK-INST: brkn p0.b, p15/z, p1.b, p0.b +// CHECK-ENCODING: [0x20,0x7c,0x18,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c 18 25 <unknown> + +brkn p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkn p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x7d,0x18,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 7d 18 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkns-diagnostics.s b/test/MC/AArch64/SVE/brkns-diagnostics.s new file mode 100644 index 000000000000..c22d4cdb0d8d --- /dev/null +++ b/test/MC/AArch64/SVE/brkns-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// BRKN only supports merging predication + +brkns p0.b, p15/m, p1.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkns p0.b, p15/m, p1.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Check tied operand constraints + +brkns p0.b, p15/z, p1.b, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: brkns p0.b, p15/z, p1.b, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkns p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkns p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkns.s b/test/MC/AArch64/SVE/brkns.s new file mode 100644 index 000000000000..6fd47f69c91f --- /dev/null +++ b/test/MC/AArch64/SVE/brkns.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkns p0.b, p15/z, p1.b, p0.b +// CHECK-INST: brkns p0.b, p15/z, p1.b, p0.b +// CHECK-ENCODING: [0x20,0x7c,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c 58 25 <unknown> + +brkns p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkns p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x7d,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 7d 58 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpa-diagnostics.s b/test/MC/AArch64/SVE/brkpa-diagnostics.s new file mode 100644 index 000000000000..d7693c62a279 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpa-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpa p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpa p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpa p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpa p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpa.s b/test/MC/AArch64/SVE/brkpa.s new file mode 100644 index 000000000000..c283ee2fdea6 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpa.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpa p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpa p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x20,0xfc,0x02,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc 02 25 <unknown> + +brkpa p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpa p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0xfd,0x0f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef fd 0f 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpas-diagnostics.s b/test/MC/AArch64/SVE/brkpas-diagnostics.s new file mode 100644 index 000000000000..a88e11075c74 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpas-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpas p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpas p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpas p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpas p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpas.s b/test/MC/AArch64/SVE/brkpas.s new file mode 100644 index 000000000000..81d590096681 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpas.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpas p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpas p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x20,0xfc,0x42,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc 42 25 <unknown> + +brkpas p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpas p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0xfd,0x4f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef fd 4f 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpb-diagnostics.s b/test/MC/AArch64/SVE/brkpb-diagnostics.s new file mode 100644 index 000000000000..e03f0bfbf93d --- /dev/null +++ b/test/MC/AArch64/SVE/brkpb-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpb p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpb p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpb p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpb p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpb.s b/test/MC/AArch64/SVE/brkpb.s new file mode 100644 index 000000000000..039e71f5e322 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpb.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpb p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpb p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x30,0xfc,0x02,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 30 fc 02 25 <unknown> + +brkpb p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpb p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xff,0xfd,0x0f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff fd 0f 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpbs-diagnostics.s b/test/MC/AArch64/SVE/brkpbs-diagnostics.s new file mode 100644 index 000000000000..25e230e2e63c --- /dev/null +++ b/test/MC/AArch64/SVE/brkpbs-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpbs p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpbs p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpbs p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpbs p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpbs.s b/test/MC/AArch64/SVE/brkpbs.s new file mode 100644 index 000000000000..1d44178659dd --- /dev/null +++ b/test/MC/AArch64/SVE/brkpbs.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpbs p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpbs p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x30,0xfc,0x42,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 30 fc 42 25 <unknown> + +brkpbs p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpbs p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xff,0xfd,0x4f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff fd 4f 25 <unknown> diff --git a/test/MC/AArch64/SVE/clasta-diagnostics.s b/test/MC/AArch64/SVE/clasta-diagnostics.s index cfc1db15b2cd..c0924bf689c7 100644 --- a/test/MC/AArch64/SVE/clasta-diagnostics.s +++ b/test/MC/AArch64/SVE/clasta-diagnostics.s @@ -77,3 +77,37 @@ clasta z0.d, p7, z0.d, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: clasta z0.d, p7, z0.d, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +clasta x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clasta x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +clasta d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clasta d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p7/z, z7.d +clasta z0.d, p7, z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: clasta z0.d, p7, z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/clasta.s b/test/MC/AArch64/SVE/clasta.s index 3e120310298b..05f6f92afac9 100644 --- a/test/MC/AArch64/SVE/clasta.s +++ b/test/MC/AArch64/SVE/clasta.s @@ -78,3 +78,19 @@ clasta z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e8 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +clasta z0.d, p7, z0.d, z31.d +// CHECK-INST: clasta z0.d, p7, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e8 05 <unknown> diff --git a/test/MC/AArch64/SVE/clastb-diagnostics.s b/test/MC/AArch64/SVE/clastb-diagnostics.s index 62f696458c3e..0f0f677ec225 100644 --- a/test/MC/AArch64/SVE/clastb-diagnostics.s +++ b/test/MC/AArch64/SVE/clastb-diagnostics.s @@ -77,3 +77,37 @@ clastb z0.d, p7, z0.d, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: clastb z0.d, p7, z0.d, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +clastb x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clastb x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +clastb d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clastb d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p7/z, z7.d +clastb z0.d, p7, z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: clastb z0.d, p7, z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/clastb.s b/test/MC/AArch64/SVE/clastb.s index 654ab1133e78..6785edb87cee 100644 --- a/test/MC/AArch64/SVE/clastb.s +++ b/test/MC/AArch64/SVE/clastb.s @@ -78,3 +78,19 @@ clastb z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e9 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +clastb z0.d, p7, z0.d, z31.d +// CHECK-INST: clastb z0.d, p7, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e9 05 <unknown> diff --git a/test/MC/AArch64/SVE/cls.s b/test/MC/AArch64/SVE/cls.s index db1c0b2a7cea..e860a7b40401 100644 --- a/test/MC/AArch64/SVE/cls.s +++ b/test/MC/AArch64/SVE/cls.s @@ -30,3 +30,31 @@ cls z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd8,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d8 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cls z4.d, p7/m, z31.d +// CHECK-INST: cls z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d8 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cls z4.d, p7/m, z31.d +// CHECK-INST: cls z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d8 04 <unknown> diff --git a/test/MC/AArch64/SVE/clz.s b/test/MC/AArch64/SVE/clz.s index 76e9d1bf83f4..ff69f383e70c 100644 --- a/test/MC/AArch64/SVE/clz.s +++ b/test/MC/AArch64/SVE/clz.s @@ -30,3 +30,31 @@ clz z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd9,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d9 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +clz z4.d, p7/m, z31.d +// CHECK-INST: clz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d9 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +clz z4.d, p7/m, z31.d +// CHECK-INST: clz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d9 04 <unknown> diff --git a/test/MC/AArch64/SVE/cmpeq-diagnostics.s b/test/MC/AArch64/SVE/cmpeq-diagnostics.s index bcda4ac02821..fbf292ec8872 100644 --- a/test/MC/AArch64/SVE/cmpeq-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpeq-diagnostics.s @@ -74,3 +74,31 @@ cmpeq p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpeq p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpeq p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpge-diagnostics.s b/test/MC/AArch64/SVE/cmpge-diagnostics.s index 49520ed5ecd5..44ab473808e7 100644 --- a/test/MC/AArch64/SVE/cmpge-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpge-diagnostics.s @@ -74,3 +74,31 @@ cmpge p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpge p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpge p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpge p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpge p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpgt-diagnostics.s b/test/MC/AArch64/SVE/cmpgt-diagnostics.s index fcc972c41011..1745aab97ea7 100644 --- a/test/MC/AArch64/SVE/cmpgt-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpgt-diagnostics.s @@ -74,3 +74,31 @@ cmpgt p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpgt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpgt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmphi-diagnostics.s b/test/MC/AArch64/SVE/cmphi-diagnostics.s index b0b3010183f3..5d7c0d82f5bf 100644 --- a/test/MC/AArch64/SVE/cmphi-diagnostics.s +++ b/test/MC/AArch64/SVE/cmphi-diagnostics.s @@ -74,3 +74,31 @@ cmphi p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmphi p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphi p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmphi p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphi p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmphs-diagnostics.s b/test/MC/AArch64/SVE/cmphs-diagnostics.s index 955c1af1b8d9..5bfff46ee406 100644 --- a/test/MC/AArch64/SVE/cmphs-diagnostics.s +++ b/test/MC/AArch64/SVE/cmphs-diagnostics.s @@ -74,3 +74,31 @@ cmphs p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmphs p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphs p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmphs p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphs p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmple-diagnostics.s b/test/MC/AArch64/SVE/cmple-diagnostics.s index e40ab1419d5d..d03d2153fd69 100644 --- a/test/MC/AArch64/SVE/cmple-diagnostics.s +++ b/test/MC/AArch64/SVE/cmple-diagnostics.s @@ -74,3 +74,31 @@ cmple p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmple p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmple p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmple p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmple p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmple p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmplo-diagnostics.s b/test/MC/AArch64/SVE/cmplo-diagnostics.s index 825ad13b4dd7..ecbed6081ac2 100644 --- a/test/MC/AArch64/SVE/cmplo-diagnostics.s +++ b/test/MC/AArch64/SVE/cmplo-diagnostics.s @@ -74,3 +74,31 @@ cmplo p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmplo p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplo p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmplo p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplo p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpls-diagnostics.s b/test/MC/AArch64/SVE/cmpls-diagnostics.s index 349a1b3ccf68..c42ce36ae3c9 100644 --- a/test/MC/AArch64/SVE/cmpls-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpls-diagnostics.s @@ -74,3 +74,31 @@ cmpls p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpls p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpls p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpls p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpls p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmplt-diagnostics.s b/test/MC/AArch64/SVE/cmplt-diagnostics.s index 7878ed56d409..0f023e0f866f 100644 --- a/test/MC/AArch64/SVE/cmplt-diagnostics.s +++ b/test/MC/AArch64/SVE/cmplt-diagnostics.s @@ -74,3 +74,31 @@ cmplt p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmplt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmplt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpne-diagnostics.s b/test/MC/AArch64/SVE/cmpne-diagnostics.s index 98bd8b7857b7..74c74c7eaa7c 100644 --- a/test/MC/AArch64/SVE/cmpne-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpne-diagnostics.s @@ -74,3 +74,31 @@ cmpne p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpne p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpne p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpne p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpne p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cnot.s b/test/MC/AArch64/SVE/cnot.s index 06ac6c8660df..83f21816c859 100644 --- a/test/MC/AArch64/SVE/cnot.s +++ b/test/MC/AArch64/SVE/cnot.s @@ -30,3 +30,31 @@ cnot z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdb,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf db 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cnot z4.d, p7/m, z31.d +// CHECK-INST: cnot z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf db 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cnot z4.d, p7/m, z31.d +// CHECK-INST: cnot z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf db 04 <unknown> diff --git a/test/MC/AArch64/SVE/cnt.s b/test/MC/AArch64/SVE/cnt.s index 4a81b1a9a9b9..86373cbe08e3 100644 --- a/test/MC/AArch64/SVE/cnt.s +++ b/test/MC/AArch64/SVE/cnt.s @@ -30,3 +30,31 @@ cnt z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xda,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf da 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cnt z4.d, p7/m, z31.d +// CHECK-INST: cnt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf da 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cnt z4.d, p7/m, z31.d +// CHECK-INST: cnt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf da 04 <unknown> diff --git a/test/MC/AArch64/SVE/compact-diagnostics.s b/test/MC/AArch64/SVE/compact-diagnostics.s index 817e97a83c5a..d252f60e55af 100644 --- a/test/MC/AArch64/SVE/compact-diagnostics.s +++ b/test/MC/AArch64/SVE/compact-diagnostics.s @@ -26,3 +26,19 @@ compact z31.h, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: compact z31.h, p7, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +compact z31.d, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.d, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +compact z31.d, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.d, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cpy.s b/test/MC/AArch64/SVE/cpy.s index 7d11d9288214..968bc5ddfe8d 100644 --- a/test/MC/AArch64/SVE/cpy.s +++ b/test/MC/AArch64/SVE/cpy.s @@ -275,3 +275,79 @@ cpy z21.d, p15/m, #-128, lsl #8 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 15 70 df 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +cpy z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +cpy z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z21.d, p7/z, z28.d +// CHECK-INST: movprfx z21.d, p7/z, z28.d +// CHECK-ENCODING: [0x95,0x3f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 3f d0 04 <unknown> + +cpy z21.d, p7/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p7/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xd7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 d7 05 <unknown> + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 <unknown> + +cpy z21.d, p15/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p15/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xdf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 df 05 <unknown> + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cpy z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cpy z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> diff --git a/test/MC/AArch64/SVE/ctermeq-diagnostics.s b/test/MC/AArch64/SVE/ctermeq-diagnostics.s new file mode 100644 index 000000000000..74afc10cb572 --- /dev/null +++ b/test/MC/AArch64/SVE/ctermeq-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +ctermeq w30, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq w30, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermeq w30, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq w30, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermeq wsp, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq wsp, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermeq x0, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq x0, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ctermeq.s b/test/MC/AArch64/SVE/ctermeq.s new file mode 100644 index 000000000000..3dfac002350a --- /dev/null +++ b/test/MC/AArch64/SVE/ctermeq.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ctermeq w30, wzr +// CHECK-INST: ctermeq w30, wzr +// CHECK-ENCODING: [0xc0,0x23,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c0 23 bf 25 <unknown> + +ctermeq wzr, w30 +// CHECK-INST: ctermeq wzr, w30 +// CHECK-ENCODING: [0xe0,0x23,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 23 be 25 <unknown> + +ctermeq x30, xzr +// CHECK-INST: ctermeq x30, xzr +// CHECK-ENCODING: [0xc0,0x23,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c0 23 ff 25 <unknown> + +ctermeq xzr, x30 +// CHECK-INST: ctermeq xzr, x30 +// CHECK-ENCODING: [0xe0,0x23,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 23 fe 25 <unknown> diff --git a/test/MC/AArch64/SVE/ctermne-diagnostics.s b/test/MC/AArch64/SVE/ctermne-diagnostics.s new file mode 100644 index 000000000000..96346f44449f --- /dev/null +++ b/test/MC/AArch64/SVE/ctermne-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +ctermne w30, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne w30, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermne w30, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne w30, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermne wsp, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne wsp, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermne x0, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne x0, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ctermne.s b/test/MC/AArch64/SVE/ctermne.s new file mode 100644 index 000000000000..54dc5e23a9c5 --- /dev/null +++ b/test/MC/AArch64/SVE/ctermne.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ctermne w30, wzr +// CHECK-INST: ctermne w30, wzr +// CHECK-ENCODING: [0xd0,0x23,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d0 23 bf 25 <unknown> + +ctermne wzr, w30 +// CHECK-INST: ctermne wzr, w30 +// CHECK-ENCODING: [0xf0,0x23,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 23 be 25 <unknown> + +ctermne x30, xzr +// CHECK-INST: ctermne x30, xzr +// CHECK-ENCODING: [0xd0,0x23,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d0 23 ff 25 <unknown> + +ctermne xzr, x30 +// CHECK-INST: ctermne xzr, x30 +// CHECK-ENCODING: [0xf0,0x23,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 23 fe 25 <unknown> diff --git a/test/MC/AArch64/SVE/decp-diagnostics.s b/test/MC/AArch64/SVE/decp-diagnostics.s index 2c8cc4293319..b1e4c9144cca 100644 --- a/test/MC/AArch64/SVE/decp-diagnostics.s +++ b/test/MC/AArch64/SVE/decp-diagnostics.s @@ -36,3 +36,13 @@ decp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: decp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +decp z31.d, p7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: decp z31.d, p7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/decp.s b/test/MC/AArch64/SVE/decp.s index 4866c766aaff..8bbe726a422d 100644 --- a/test/MC/AArch64/SVE/decp.s +++ b/test/MC/AArch64/SVE/decp.s @@ -72,3 +72,19 @@ decp z31.d, p15 // CHECK-ENCODING: [0xff,0x81,0xed,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 81 ed 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +decp z31.d, p15 +// CHECK-INST: decp z31.d, p15 +// CHECK-ENCODING: [0xff,0x81,0xed,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 81 ed 25 <unknown> diff --git a/test/MC/AArch64/SVE/dup-diagnostics.s b/test/MC/AArch64/SVE/dup-diagnostics.s index 6636708c457e..f97ac83aae09 100644 --- a/test/MC/AArch64/SVE/dup-diagnostics.s +++ b/test/MC/AArch64/SVE/dup-diagnostics.s @@ -215,3 +215,43 @@ dup z24.q, z21.q[4] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK-NEXT: dup z24.q, z21.q[4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +dup z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +dup z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21.d, p0/z, z28.d +dup z21.d, #32512 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z21.d, #32512 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +dup z21.d, #32512 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z21.d, #32512 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +dup z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +dup z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/dupm-diagnostics.s b/test/MC/AArch64/SVE/dupm-diagnostics.s index cb2277a1f871..f82c849437b0 100644 --- a/test/MC/AArch64/SVE/dupm-diagnostics.s +++ b/test/MC/AArch64/SVE/dupm-diagnostics.s @@ -37,3 +37,19 @@ dupm z15.d, #0xfffffffffffffffa // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate // CHECK-NEXT: dupm z15.d, #0xfffffffffffffffa // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +dupm z0.d, #0xfffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dupm z0.d, #0xfffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +dupm z0.d, #0xfffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dupm z0.d, #0xfffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/eon-diagnostics.s b/test/MC/AArch64/SVE/eon-diagnostics.s index 5b6f59ce23de..ffdd7222cb20 100644 --- a/test/MC/AArch64/SVE/eon-diagnostics.s +++ b/test/MC/AArch64/SVE/eon-diagnostics.s @@ -50,3 +50,13 @@ eon z7.d, z8.d, #254 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK-NEXT: eon z7.d, z8.d, #254 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +eon z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: eon z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/eon.s b/test/MC/AArch64/SVE/eon.s index 9f6dd2655061..d03755d5a94e 100644 --- a/test/MC/AArch64/SVE/eon.s +++ b/test/MC/AArch64/SVE/eon.s @@ -54,3 +54,19 @@ eon z0.d, z0.d, #0x6 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: a0 ef 43 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +eon z0.d, z0.d, #0x6 +// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 43 05 <unknown> diff --git a/test/MC/AArch64/SVE/eor-diagnostics.s b/test/MC/AArch64/SVE/eor-diagnostics.s index dbed470e7bd4..e8d28737db22 100644 --- a/test/MC/AArch64/SVE/eor-diagnostics.s +++ b/test/MC/AArch64/SVE/eor-diagnostics.s @@ -92,3 +92,25 @@ eor p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: eor p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +eor z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: eor z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +eor z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eor z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +eor z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eor z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/eor.s b/test/MC/AArch64/SVE/eor.s index 8c68ec9c7835..f7b4247ad80b 100644 --- a/test/MC/AArch64/SVE/eor.s +++ b/test/MC/AArch64/SVE/eor.s @@ -108,3 +108,43 @@ eor p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7f 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.b, p7/z, z6.b +// CHECK-INST: movprfx z4.b, p7/z, z6.b +// CHECK-ENCODING: [0xc4,0x3c,0x10,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 10 04 <unknown> + +eor z4.b, p7/m, z4.b, z31.b +// CHECK-INST: eor z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x19,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 19 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +eor z4.b, p7/m, z4.b, z31.b +// CHECK-INST: eor z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x19,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 19 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +eor z0.d, z0.d, #0x6 +// CHECK-INST: eor z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 43 05 <unknown> diff --git a/test/MC/AArch64/SVE/eorv-diagnostics.s b/test/MC/AArch64/SVE/eorv-diagnostics.s index c182615be5d6..6f231a8c6269 100644 --- a/test/MC/AArch64/SVE/eorv-diagnostics.s +++ b/test/MC/AArch64/SVE/eorv-diagnostics.s @@ -31,4 +31,19 @@ eorv v0.2d, p7, z31.d eorv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: eorv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +eorv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eorv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +eorv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eorv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ext-diagnostics.s b/test/MC/AArch64/SVE/ext-diagnostics.s index 8f9bee79b85c..23ae5e2ddd5c 100644 --- a/test/MC/AArch64/SVE/ext-diagnostics.s +++ b/test/MC/AArch64/SVE/ext-diagnostics.s @@ -31,3 +31,13 @@ ext z0.b, z0.b, z1.b, #256 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK-NEXT: ext z0.b, z0.b, z1.b, #256 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +ext z31.b, z31.b, z0.b, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: ext z31.b, z31.b, z0.b, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ext.s b/test/MC/AArch64/SVE/ext.s index 2afc5f09771a..632f61eb107c 100644 --- a/test/MC/AArch64/SVE/ext.s +++ b/test/MC/AArch64/SVE/ext.s @@ -18,3 +18,19 @@ ext z31.b, z31.b, z0.b, #255 // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 1f 1c 3f 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +ext z31.b, z31.b, z0.b, #255 +// CHECK-INST: ext z31.b, z31.b, z0.b, #255 +// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown> diff --git a/test/MC/AArch64/SVE/fabd.s b/test/MC/AArch64/SVE/fabd.s index 98bbc5050a37..7549f554a95f 100644 --- a/test/MC/AArch64/SVE/fabd.s +++ b/test/MC/AArch64/SVE/fabd.s @@ -24,3 +24,31 @@ fabd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c8 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fabd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c8 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fabd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c8 65 <unknown> diff --git a/test/MC/AArch64/SVE/fabs.s b/test/MC/AArch64/SVE/fabs.s index c9d4d8405bef..1bd2c833d1cd 100644 --- a/test/MC/AArch64/SVE/fabs.s +++ b/test/MC/AArch64/SVE/fabs.s @@ -24,3 +24,31 @@ fabs z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdc,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf dc 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fabs z4.d, p7/m, z31.d +// CHECK-INST: fabs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dc 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fabs z4.d, p7/m, z31.d +// CHECK-INST: fabs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dc 04 <unknown> diff --git a/test/MC/AArch64/SVE/facge-diagnostics.s b/test/MC/AArch64/SVE/facge-diagnostics.s index 08710681bf4c..a33627aa68ee 100644 --- a/test/MC/AArch64/SVE/facge-diagnostics.s +++ b/test/MC/AArch64/SVE/facge-diagnostics.s @@ -9,3 +9,19 @@ facge p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: facge p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +facge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +facge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/facgt-diagnostics.s b/test/MC/AArch64/SVE/facgt-diagnostics.s index 12c1ed53527a..c92690bc9de8 100644 --- a/test/MC/AArch64/SVE/facgt-diagnostics.s +++ b/test/MC/AArch64/SVE/facgt-diagnostics.s @@ -9,3 +9,19 @@ facgt p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: facgt p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +facgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +facgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/facle-diagnostics.s b/test/MC/AArch64/SVE/facle-diagnostics.s index 6ecfccffc263..0f3b777308d9 100644 --- a/test/MC/AArch64/SVE/facle-diagnostics.s +++ b/test/MC/AArch64/SVE/facle-diagnostics.s @@ -9,3 +9,19 @@ facle p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: facle p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +facle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +facle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/faclt-diagnostics.s b/test/MC/AArch64/SVE/faclt-diagnostics.s index b0ef736ffcaa..12baa18615d9 100644 --- a/test/MC/AArch64/SVE/faclt-diagnostics.s +++ b/test/MC/AArch64/SVE/faclt-diagnostics.s @@ -9,3 +9,19 @@ faclt p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: faclt p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +faclt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faclt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +faclt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faclt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fadd-diagnostics.s b/test/MC/AArch64/SVE/fadd-diagnostics.s index be8a85fa49b5..b809e2e72b28 100644 --- a/test/MC/AArch64/SVE/fadd-diagnostics.s +++ b/test/MC/AArch64/SVE/fadd-diagnostics.s @@ -68,3 +68,19 @@ fadd z0.h, p8/m, z0.h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: fadd z0.h, p8/m, z0.h, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fadd z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadd z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fadd z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadd z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fadd.s b/test/MC/AArch64/SVE/fadd.s index 36c3171bba89..10935c37fc05 100644 --- a/test/MC/AArch64/SVE/fadd.s +++ b/test/MC/AArch64/SVE/fadd.s @@ -90,3 +90,55 @@ fadd z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x00,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 00 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d8 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d8 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fadd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c0 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fadd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c0 65 <unknown> diff --git a/test/MC/AArch64/SVE/fadda-diagnostics.s b/test/MC/AArch64/SVE/fadda-diagnostics.s index bff63367b159..6386707efa5d 100644 --- a/test/MC/AArch64/SVE/fadda-diagnostics.s +++ b/test/MC/AArch64/SVE/fadda-diagnostics.s @@ -18,4 +18,19 @@ fadda h0, p8, h0, z31.h fadda v0.8h, p7, v0.8h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fadda d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadda d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fadda d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadda d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/faddv-diagnostics.s b/test/MC/AArch64/SVE/faddv-diagnostics.s index 37cb19337d94..f8fa774d8bec 100644 --- a/test/MC/AArch64/SVE/faddv-diagnostics.s +++ b/test/MC/AArch64/SVE/faddv-diagnostics.s @@ -17,4 +17,19 @@ faddv h0, p8, z31.h faddv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: faddv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +faddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +faddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcadd.s b/test/MC/AArch64/SVE/fcadd.s index 5e8c8324c773..9d2398ab25a8 100644 --- a/test/MC/AArch64/SVE/fcadd.s +++ b/test/MC/AArch64/SVE/fcadd.s @@ -42,3 +42,31 @@ fcadd z31.d, p7/m, z31.d, z31.d, #270 // CHECK-ENCODING: [0xff,0x9f,0xc1,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f c1 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f c1 64 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f c1 64 <unknown> diff --git a/test/MC/AArch64/SVE/fcmeq-diagnostics.s b/test/MC/AArch64/SVE/fcmeq-diagnostics.s index d2e8dddda3ed..08dc7dc4010c 100644 --- a/test/MC/AArch64/SVE/fcmeq-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmeq-diagnostics.s @@ -9,3 +9,31 @@ fcmeq p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmge-diagnostics.s b/test/MC/AArch64/SVE/fcmge-diagnostics.s index d6d7b589c861..249d6fc5af12 100644 --- a/test/MC/AArch64/SVE/fcmge-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmge-diagnostics.s @@ -9,3 +9,31 @@ fcmge p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmge p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmgt-diagnostics.s b/test/MC/AArch64/SVE/fcmgt-diagnostics.s index 4ec876922bb3..d9c42217ad2d 100644 --- a/test/MC/AArch64/SVE/fcmgt-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmgt-diagnostics.s @@ -9,3 +9,31 @@ fcmgt p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmla-diagnostics.s b/test/MC/AArch64/SVE/fcmla-diagnostics.s index 560b15f3de90..7ad6db4f1985 100644 --- a/test/MC/AArch64/SVE/fcmla-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmla-diagnostics.s @@ -50,3 +50,13 @@ fcmla z0.d, z1.d, z2.d[0], #0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: fcmla z0.d, z1.d, z2.d[0], #0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p0/z, z28.s +fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmla.s b/test/MC/AArch64/SVE/fcmla.s index 3a0954e7c8ef..2e4dd7f55357 100644 --- a/test/MC/AArch64/SVE/fcmla.s +++ b/test/MC/AArch64/SVE/fcmla.s @@ -102,3 +102,43 @@ fcmla z21.s, z10.s, z5.s[1], #90 // CHECK-ENCODING: [0x55,0x15,0xf5,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 15 f5 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 7f df 64 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 7f df 64 <unknown> + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 <unknown> + +fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-ENCODING: [0x55,0x15,0xf5,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 55 15 f5 64 <unknown> diff --git a/test/MC/AArch64/SVE/fcmle-diagnostics.s b/test/MC/AArch64/SVE/fcmle-diagnostics.s index 4ce8fb679e81..8c3dbe9c634d 100644 --- a/test/MC/AArch64/SVE/fcmle-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmle-diagnostics.s @@ -9,3 +9,31 @@ fcmle p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmle p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmlt-diagnostics.s b/test/MC/AArch64/SVE/fcmlt-diagnostics.s index 1e13a3d2e03a..44a39bb41ac2 100644 --- a/test/MC/AArch64/SVE/fcmlt-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmlt-diagnostics.s @@ -9,3 +9,31 @@ fcmlt p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmlt p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmne-diagnostics.s b/test/MC/AArch64/SVE/fcmne-diagnostics.s index d0e996b4b7bf..8e8173d4c46d 100644 --- a/test/MC/AArch64/SVE/fcmne-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmne-diagnostics.s @@ -9,3 +9,31 @@ fcmne p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmne p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmne p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmuo-diagnostics.s b/test/MC/AArch64/SVE/fcmuo-diagnostics.s index c9a33346b5f0..0905d9b240fe 100644 --- a/test/MC/AArch64/SVE/fcmuo-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmuo-diagnostics.s @@ -9,3 +9,19 @@ fcmuo p0.s, p0/z, z0.s, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcpy.s b/test/MC/AArch64/SVE/fcpy.s index 712f16a6affa..5510e035dd1d 100644 --- a/test/MC/AArch64/SVE/fcpy.s +++ b/test/MC/AArch64/SVE/fcpy.s @@ -1554,3 +1554,31 @@ fcpy z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p0/z, z7.d +// CHECK-INST: movprfx z0.d, p0/z, z7.d +// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 d0 04 <unknown> + +fcpy z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fcpy z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> diff --git a/test/MC/AArch64/SVE/fcvt.s b/test/MC/AArch64/SVE/fcvt.s index e0e9e7679473..3a0d52471186 100644 --- a/test/MC/AArch64/SVE/fcvt.s +++ b/test/MC/AArch64/SVE/fcvt.s @@ -42,3 +42,31 @@ fcvt z0.d, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0xcb,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 cb 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +fcvt z5.d, p0/m, z0.s +// CHECK-INST: fcvt z5.d, p0/m, z0.s +// CHECK-ENCODING: [0x05,0xa0,0xcb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 cb 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +fcvt z5.d, p0/m, z0.s +// CHECK-INST: fcvt z5.d, p0/m, z0.s +// CHECK-ENCODING: [0x05,0xa0,0xcb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 cb 65 <unknown> diff --git a/test/MC/AArch64/SVE/fcvtzs.s b/test/MC/AArch64/SVE/fcvtzs.s index 40e4c44a98d2..ecb7adc46b84 100644 --- a/test/MC/AArch64/SVE/fcvtzs.s +++ b/test/MC/AArch64/SVE/fcvtzs.s @@ -48,3 +48,31 @@ fcvtzs z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xde,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 de 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +fcvtzs z5.d, p0/m, z0.d +// CHECK-INST: fcvtzs z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 de 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +fcvtzs z5.d, p0/m, z0.d +// CHECK-INST: fcvtzs z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 de 65 <unknown> diff --git a/test/MC/AArch64/SVE/fcvtzu.s b/test/MC/AArch64/SVE/fcvtzu.s index 37505d998c5c..cd6993c0f589 100644 --- a/test/MC/AArch64/SVE/fcvtzu.s +++ b/test/MC/AArch64/SVE/fcvtzu.s @@ -48,3 +48,31 @@ fcvtzu z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +fcvtzu z5.d, p0/m, z0.d +// CHECK-INST: fcvtzu z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 df 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +fcvtzu z5.d, p0/m, z0.d +// CHECK-INST: fcvtzu z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 df 65 <unknown> diff --git a/test/MC/AArch64/SVE/fdiv.s b/test/MC/AArch64/SVE/fdiv.s index 112d202d5abb..9f1d4ddf1b77 100644 --- a/test/MC/AArch64/SVE/fdiv.s +++ b/test/MC/AArch64/SVE/fdiv.s @@ -24,3 +24,31 @@ fdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f cd 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cd 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cd 65 <unknown> diff --git a/test/MC/AArch64/SVE/fdivr.s b/test/MC/AArch64/SVE/fdivr.s index 3744dd95c694..37fd871461e3 100644 --- a/test/MC/AArch64/SVE/fdivr.s +++ b/test/MC/AArch64/SVE/fdivr.s @@ -24,3 +24,31 @@ fdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f cc 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cc 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cc 65 <unknown> diff --git a/test/MC/AArch64/SVE/fdup-diagnostics.s b/test/MC/AArch64/SVE/fdup-diagnostics.s index 6128bbe85bba..4432393bfa26 100644 --- a/test/MC/AArch64/SVE/fdup-diagnostics.s +++ b/test/MC/AArch64/SVE/fdup-diagnostics.s @@ -62,3 +62,19 @@ fdup z0.d, #64.00000000 // r = 5, n = 32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK-NEXT: fdup z0.d, #64.00000000 // r = 5, n = 32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fdup z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fdup z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fdup z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fdup z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fexpa-diagnostics.s b/test/MC/AArch64/SVE/fexpa-diagnostics.s index 2269ae0fdfc2..33964f24d4a6 100644 --- a/test/MC/AArch64/SVE/fexpa-diagnostics.s +++ b/test/MC/AArch64/SVE/fexpa-diagnostics.s @@ -12,4 +12,19 @@ fexpa z0.b, z31.b fexpa z0.s, z31.d // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: fexpa z0.s, z31.d -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fexpa z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fexpa z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fexpa z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fexpa z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmad.s b/test/MC/AArch64/SVE/fmad.s index dbcec437c32b..2cfb6a74156c 100644 --- a/test/MC/AArch64/SVE/fmad.s +++ b/test/MC/AArch64/SVE/fmad.s @@ -24,3 +24,31 @@ fmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x9c,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 9c ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x9c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 9c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x9c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 9c ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmax.s b/test/MC/AArch64/SVE/fmax.s index 0e4a6d4c196e..bcdc90403949 100644 --- a/test/MC/AArch64/SVE/fmax.s +++ b/test/MC/AArch64/SVE/fmax.s @@ -66,3 +66,55 @@ fmax z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c6 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p0/z, z7.d +// CHECK-INST: movprfx z0.d, p0/z, z7.d +// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 d0 04 <unknown> + +fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-ENCODING: [0x00,0x80,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 de 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-ENCODING: [0x00,0x80,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 de 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmax z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c6 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmax z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c6 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmaxnm.s b/test/MC/AArch64/SVE/fmaxnm.s index 3016f63154a2..5c44861ea954 100644 --- a/test/MC/AArch64/SVE/fmaxnm.s +++ b/test/MC/AArch64/SVE/fmaxnm.s @@ -72,3 +72,55 @@ fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c4 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dc 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dc 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c4 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c4 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s b/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s index 2eb6191b3893..094831296559 100644 --- a/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s +++ b/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s @@ -17,4 +17,19 @@ fmaxnmv h0, p8, z31.h fmaxnmv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmaxnmv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fmaxnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fmaxnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmaxv-diagnostics.s b/test/MC/AArch64/SVE/fmaxv-diagnostics.s index d679734e2d62..0923dc167f8e 100644 --- a/test/MC/AArch64/SVE/fmaxv-diagnostics.s +++ b/test/MC/AArch64/SVE/fmaxv-diagnostics.s @@ -17,4 +17,19 @@ fmaxv h0, p8, z31.h fmaxv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmaxv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fmaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fmaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmin.s b/test/MC/AArch64/SVE/fmin.s index 2db4d5ca842a..1b0cb4e589c3 100644 --- a/test/MC/AArch64/SVE/fmin.s +++ b/test/MC/AArch64/SVE/fmin.s @@ -72,3 +72,55 @@ fmin z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c df 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c df 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmin z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c7 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmin z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c7 65 <unknown> diff --git a/test/MC/AArch64/SVE/fminnm.s b/test/MC/AArch64/SVE/fminnm.s index 492d5898518c..482b7f561ef2 100644 --- a/test/MC/AArch64/SVE/fminnm.s +++ b/test/MC/AArch64/SVE/fminnm.s @@ -72,3 +72,55 @@ fminnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c5 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dd 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dd 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c5 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c5 65 <unknown> diff --git a/test/MC/AArch64/SVE/fminnmv-diagnostics.s b/test/MC/AArch64/SVE/fminnmv-diagnostics.s index d613d053a5f3..bf9062b5b66d 100644 --- a/test/MC/AArch64/SVE/fminnmv-diagnostics.s +++ b/test/MC/AArch64/SVE/fminnmv-diagnostics.s @@ -17,4 +17,19 @@ fminnmv h0, p8, z31.h fminnmv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fminnmv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fminnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fminnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fminv-diagnostics.s b/test/MC/AArch64/SVE/fminv-diagnostics.s index e1dc7715396c..793d7f7562b2 100644 --- a/test/MC/AArch64/SVE/fminv-diagnostics.s +++ b/test/MC/AArch64/SVE/fminv-diagnostics.s @@ -17,4 +17,19 @@ fminv h0, p8, z31.h fminv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fminv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmla-diagnostics.s b/test/MC/AArch64/SVE/fmla-diagnostics.s index 43b452f1e7be..e9892590c232 100644 --- a/test/MC/AArch64/SVE/fmla-diagnostics.s +++ b/test/MC/AArch64/SVE/fmla-diagnostics.s @@ -70,3 +70,13 @@ fmla z0.d, z1.d, z2.d[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: fmla z0.d, z1.d, z2.d[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmla z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmla z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmla.s b/test/MC/AArch64/SVE/fmla.s index 3b1f54c37598..a28204da0a14 100644 --- a/test/MC/AArch64/SVE/fmla.s +++ b/test/MC/AArch64/SVE/fmla.s @@ -42,3 +42,43 @@ fmla z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x00,0xf7,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 00 f7 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x1c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x1c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmla z0.d, z1.d, z7.d[1] +// CHECK-INST: fmla z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x00,0xf7,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 f7 64 <unknown> diff --git a/test/MC/AArch64/SVE/fmls-diagnostics.s b/test/MC/AArch64/SVE/fmls-diagnostics.s index f7734f8fe9a4..8c2d175642c8 100644 --- a/test/MC/AArch64/SVE/fmls-diagnostics.s +++ b/test/MC/AArch64/SVE/fmls-diagnostics.s @@ -70,3 +70,13 @@ fmls z0.d, z1.d, z2.d[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: fmls z0.d, z1.d, z2.d[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmls z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmls z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmls.s b/test/MC/AArch64/SVE/fmls.s index c337d8c3aec2..390a3128fc44 100644 --- a/test/MC/AArch64/SVE/fmls.s +++ b/test/MC/AArch64/SVE/fmls.s @@ -42,3 +42,43 @@ fmls z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x04,0xf7,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 04 f7 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x3c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 3c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x3c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 3c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmls z0.d, z1.d, z7.d[1] +// CHECK-INST: fmls z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x04,0xf7,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 f7 64 <unknown> diff --git a/test/MC/AArch64/SVE/fmov-diagnostics.s b/test/MC/AArch64/SVE/fmov-diagnostics.s index 3225ff1b1581..fcf53644b50c 100644 --- a/test/MC/AArch64/SVE/fmov-diagnostics.s +++ b/test/MC/AArch64/SVE/fmov-diagnostics.s @@ -140,3 +140,19 @@ fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK-NEXT: fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmov z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmov z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fmov z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmov z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmov.s b/test/MC/AArch64/SVE/fmov.s index 72bac32ba49c..abd1044bc163 100644 --- a/test/MC/AArch64/SVE/fmov.s +++ b/test/MC/AArch64/SVE/fmov.s @@ -1596,3 +1596,31 @@ fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p0/z, z7.d +// CHECK-INST: movprfx z0.d, p0/z, z7.d +// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 d0 04 <unknown> + +fmov z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmov z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> diff --git a/test/MC/AArch64/SVE/fmsb.s b/test/MC/AArch64/SVE/fmsb.s index 4e34073ff107..c1203e2f1f38 100644 --- a/test/MC/AArch64/SVE/fmsb.s +++ b/test/MC/AArch64/SVE/fmsb.s @@ -24,3 +24,31 @@ fmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xbc,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 bc ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xbc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xbc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmul-diagnostics.s b/test/MC/AArch64/SVE/fmul-diagnostics.s index 55bfbd7cef68..be91dc312f36 100644 --- a/test/MC/AArch64/SVE/fmul-diagnostics.s +++ b/test/MC/AArch64/SVE/fmul-diagnostics.s @@ -132,3 +132,31 @@ fmul z0.h, p8/m, z0.h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: fmul z0.h, p8/m, z0.h, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +fmul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fmul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmul.s b/test/MC/AArch64/SVE/fmul.s index fd75166319bf..3cf35f33f8ca 100644 --- a/test/MC/AArch64/SVE/fmul.s +++ b/test/MC/AArch64/SVE/fmul.s @@ -120,3 +120,55 @@ fmul z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x08,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 08 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c da 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c da 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c2 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c2 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmulx.s b/test/MC/AArch64/SVE/fmulx.s index a1c8e6b93258..0c49421fddbc 100644 --- a/test/MC/AArch64/SVE/fmulx.s +++ b/test/MC/AArch64/SVE/fmulx.s @@ -24,3 +24,31 @@ fmulx z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f ca 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f ca 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f ca 65 <unknown> diff --git a/test/MC/AArch64/SVE/fneg.s b/test/MC/AArch64/SVE/fneg.s index 9b9ca9041fb8..47f833e9b81c 100644 --- a/test/MC/AArch64/SVE/fneg.s +++ b/test/MC/AArch64/SVE/fneg.s @@ -24,3 +24,31 @@ fneg z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdd,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf dd 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fneg z4.d, p7/m, z31.d +// CHECK-INST: fneg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dd 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fneg z4.d, p7/m, z31.d +// CHECK-INST: fneg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dd 04 <unknown> diff --git a/test/MC/AArch64/SVE/fnmad.s b/test/MC/AArch64/SVE/fnmad.s index 6bb736c9eb42..3bec7b6be884 100644 --- a/test/MC/AArch64/SVE/fnmad.s +++ b/test/MC/AArch64/SVE/fnmad.s @@ -24,3 +24,31 @@ fnmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xdc,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 dc ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xdc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 dc ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xdc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 dc ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fnmla.s b/test/MC/AArch64/SVE/fnmla.s index 49d443f26103..aa3eb3be9195 100644 --- a/test/MC/AArch64/SVE/fnmla.s +++ b/test/MC/AArch64/SVE/fnmla.s @@ -24,3 +24,31 @@ fnmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 5c ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fnmls.s b/test/MC/AArch64/SVE/fnmls.s index 438fbaeed6d0..90bde2edc4ce 100644 --- a/test/MC/AArch64/SVE/fnmls.s +++ b/test/MC/AArch64/SVE/fnmls.s @@ -24,3 +24,31 @@ fnmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 7c ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fnmsb.s b/test/MC/AArch64/SVE/fnmsb.s index f06de48afbf1..a1767c4091cf 100644 --- a/test/MC/AArch64/SVE/fnmsb.s +++ b/test/MC/AArch64/SVE/fnmsb.s @@ -24,3 +24,31 @@ fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xfc,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 fc ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xfc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xfc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/frecpe-diagnostics.s b/test/MC/AArch64/SVE/frecpe-diagnostics.s index 80467f26f5a3..6457ad0837bc 100644 --- a/test/MC/AArch64/SVE/frecpe-diagnostics.s +++ b/test/MC/AArch64/SVE/frecpe-diagnostics.s @@ -3,4 +3,19 @@ frecpe z0.b, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frecpe z0.b, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frecpe z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecpe z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frecpe z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecpe z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frecps-diagnostics.s b/test/MC/AArch64/SVE/frecps-diagnostics.s index 7de58cff80fa..ec2d6c3954c4 100644 --- a/test/MC/AArch64/SVE/frecps-diagnostics.s +++ b/test/MC/AArch64/SVE/frecps-diagnostics.s @@ -13,3 +13,19 @@ frecps z0.h, z1.s, z2.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frecps z0.h, z1.s, z2.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frecps z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecps z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frecps z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecps z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frecpx.s b/test/MC/AArch64/SVE/frecpx.s index 49226abc33b8..a044703ab714 100644 --- a/test/MC/AArch64/SVE/frecpx.s +++ b/test/MC/AArch64/SVE/frecpx.s @@ -24,3 +24,31 @@ frecpx z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xcc,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf cc 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frecpx z4.d, p7/m, z31.d +// CHECK-INST: frecpx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cc 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frecpx z4.d, p7/m, z31.d +// CHECK-INST: frecpx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cc 65 <unknown> diff --git a/test/MC/AArch64/SVE/frinta.s b/test/MC/AArch64/SVE/frinta.s index ea7a48a29b9b..c89e1618ae7b 100644 --- a/test/MC/AArch64/SVE/frinta.s +++ b/test/MC/AArch64/SVE/frinta.s @@ -24,3 +24,31 @@ frinta z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc4,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c4 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frinta z4.d, p7/m, z31.d +// CHECK-INST: frinta z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c4 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frinta z4.d, p7/m, z31.d +// CHECK-INST: frinta z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c4 65 <unknown> diff --git a/test/MC/AArch64/SVE/frinti.s b/test/MC/AArch64/SVE/frinti.s index 7fde35c4a184..a05cc9fe7b46 100644 --- a/test/MC/AArch64/SVE/frinti.s +++ b/test/MC/AArch64/SVE/frinti.s @@ -24,3 +24,31 @@ frinti z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frinti z4.d, p7/m, z31.d +// CHECK-INST: frinti z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c7 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frinti z4.d, p7/m, z31.d +// CHECK-INST: frinti z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c7 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintm.s b/test/MC/AArch64/SVE/frintm.s index b33e922bbd5f..e085683f9d17 100644 --- a/test/MC/AArch64/SVE/frintm.s +++ b/test/MC/AArch64/SVE/frintm.s @@ -24,3 +24,31 @@ frintm z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc2,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c2 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintm z4.d, p7/m, z31.d +// CHECK-INST: frintm z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c2 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintm z4.d, p7/m, z31.d +// CHECK-INST: frintm z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c2 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintn.s b/test/MC/AArch64/SVE/frintn.s index d19f85520644..1318c8b88318 100644 --- a/test/MC/AArch64/SVE/frintn.s +++ b/test/MC/AArch64/SVE/frintn.s @@ -24,3 +24,31 @@ frintn z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc0,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c0 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintn z4.d, p7/m, z31.d +// CHECK-INST: frintn z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c0 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintn z4.d, p7/m, z31.d +// CHECK-INST: frintn z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c0 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintp.s b/test/MC/AArch64/SVE/frintp.s index 12fce742c798..a36831ecc2dd 100644 --- a/test/MC/AArch64/SVE/frintp.s +++ b/test/MC/AArch64/SVE/frintp.s @@ -24,3 +24,31 @@ frintp z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc1,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c1 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintp z4.d, p7/m, z31.d +// CHECK-INST: frintp z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c1 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintp z4.d, p7/m, z31.d +// CHECK-INST: frintp z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c1 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintx.s b/test/MC/AArch64/SVE/frintx.s index b33f4281d3d5..60244a9cb334 100644 --- a/test/MC/AArch64/SVE/frintx.s +++ b/test/MC/AArch64/SVE/frintx.s @@ -24,3 +24,31 @@ frintx z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc6,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c6 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintx z4.d, p7/m, z31.d +// CHECK-INST: frintx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c6 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintx z4.d, p7/m, z31.d +// CHECK-INST: frintx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c6 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintz.s b/test/MC/AArch64/SVE/frintz.s index 22e2aef98b8f..af794b79a2f2 100644 --- a/test/MC/AArch64/SVE/frintz.s +++ b/test/MC/AArch64/SVE/frintz.s @@ -24,3 +24,31 @@ frintz z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc3,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c3 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintz z4.d, p7/m, z31.d +// CHECK-INST: frintz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c3 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintz z4.d, p7/m, z31.d +// CHECK-INST: frintz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c3 65 <unknown> diff --git a/test/MC/AArch64/SVE/frsqrte-diagnostics.s b/test/MC/AArch64/SVE/frsqrte-diagnostics.s index b7325e164aa1..b38c9370b85b 100644 --- a/test/MC/AArch64/SVE/frsqrte-diagnostics.s +++ b/test/MC/AArch64/SVE/frsqrte-diagnostics.s @@ -3,4 +3,19 @@ frsqrte z0.b, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frsqrte z0.b, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frsqrte z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrte z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frsqrte z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrte z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frsqrts-diagnostics.s b/test/MC/AArch64/SVE/frsqrts-diagnostics.s index 07dde46ad459..2032e74bfc28 100644 --- a/test/MC/AArch64/SVE/frsqrts-diagnostics.s +++ b/test/MC/AArch64/SVE/frsqrts-diagnostics.s @@ -13,3 +13,19 @@ frsqrts z0.h, z1.s, z2.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frsqrts z0.h, z1.s, z2.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frsqrts z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrts z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frsqrts z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrts z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fscale.s b/test/MC/AArch64/SVE/fscale.s index 0ce3d7ecb9a8..ab928b4c77f1 100644 --- a/test/MC/AArch64/SVE/fscale.s +++ b/test/MC/AArch64/SVE/fscale.s @@ -24,3 +24,31 @@ fscale z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c9 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fscale z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c9 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fscale z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c9 65 <unknown> diff --git a/test/MC/AArch64/SVE/fsqrt.s b/test/MC/AArch64/SVE/fsqrt.s index 949faba227b6..b72d2438b33f 100644 --- a/test/MC/AArch64/SVE/fsqrt.s +++ b/test/MC/AArch64/SVE/fsqrt.s @@ -24,3 +24,31 @@ fsqrt z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xcd,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf cd 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fsqrt z4.d, p7/m, z31.d +// CHECK-INST: fsqrt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cd 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fsqrt z4.d, p7/m, z31.d +// CHECK-INST: fsqrt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cd 65 <unknown> diff --git a/test/MC/AArch64/SVE/fsub-diagnostics.s b/test/MC/AArch64/SVE/fsub-diagnostics.s index 27d1b3f7b918..41b36bdbea4d 100644 --- a/test/MC/AArch64/SVE/fsub-diagnostics.s +++ b/test/MC/AArch64/SVE/fsub-diagnostics.s @@ -68,3 +68,19 @@ fsub z0.h, p8/m, z0.h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: fsub z0.h, p8/m, z0.h, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fsub z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fsub z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fsub z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fsub z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fsub.s b/test/MC/AArch64/SVE/fsub.s index 8e96cbb65ad0..49d7448e8574 100644 --- a/test/MC/AArch64/SVE/fsub.s +++ b/test/MC/AArch64/SVE/fsub.s @@ -90,3 +90,55 @@ fsub z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x04,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 04 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d9 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d9 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fsub z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c1 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fsub z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c1 65 <unknown> diff --git a/test/MC/AArch64/SVE/fsubr.s b/test/MC/AArch64/SVE/fsubr.s index 990a0b1ac520..349871702498 100644 --- a/test/MC/AArch64/SVE/fsubr.s +++ b/test/MC/AArch64/SVE/fsubr.s @@ -72,3 +72,55 @@ fsubr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c3 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c db 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c db 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c3 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c3 65 <unknown> diff --git a/test/MC/AArch64/SVE/ftmad-diagnostics.s b/test/MC/AArch64/SVE/ftmad-diagnostics.s index 5b63106fb48b..ec7741810b3c 100644 --- a/test/MC/AArch64/SVE/ftmad-diagnostics.s +++ b/test/MC/AArch64/SVE/ftmad-diagnostics.s @@ -36,3 +36,13 @@ ftmad z0.h, z0.h, z1.h, #8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. // CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ftmad z0.d, z0.d, z31.d, #7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: ftmad z0.d, z0.d, z31.d, #7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ftmad.s b/test/MC/AArch64/SVE/ftmad.s index c18009ec0cb6..3a59a1fb4fd7 100644 --- a/test/MC/AArch64/SVE/ftmad.s +++ b/test/MC/AArch64/SVE/ftmad.s @@ -24,3 +24,19 @@ ftmad z0.d, z0.d, z31.d, #7 // CHECK-ENCODING: [0xe0,0x83,0xd7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 83 d7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +ftmad z0.d, z0.d, z31.d, #7 +// CHECK-INST: ftmad z0.d, z0.d, z31.d, #7 +// CHECK-ENCODING: [0xe0,0x83,0xd7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 d7 65 <unknown> diff --git a/test/MC/AArch64/SVE/ftsmul-diagnostics.s b/test/MC/AArch64/SVE/ftsmul-diagnostics.s index 5ad0a14d798c..08b2966893fe 100644 --- a/test/MC/AArch64/SVE/ftsmul-diagnostics.s +++ b/test/MC/AArch64/SVE/ftsmul-diagnostics.s @@ -13,3 +13,19 @@ ftsmul z0.h, z1.s, z2.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ftsmul z0.h, z1.s, z2.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ftsmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftsmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ftsmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftsmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ftssel-diagnostics.s b/test/MC/AArch64/SVE/ftssel-diagnostics.s index 92991246163f..c0cfac061311 100644 --- a/test/MC/AArch64/SVE/ftssel-diagnostics.s +++ b/test/MC/AArch64/SVE/ftssel-diagnostics.s @@ -3,4 +3,19 @@ ftssel z0.b, z1.b, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ftssel z0.b, z1.b, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ftssel z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftssel z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ftssel z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftssel z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incd-diagnostics.s b/test/MC/AArch64/SVE/incd-diagnostics.s index ddd232062bf5..2c32eea91ef0 100644 --- a/test/MC/AArch64/SVE/incd-diagnostics.s +++ b/test/MC/AArch64/SVE/incd-diagnostics.s @@ -61,3 +61,25 @@ incd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +incd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +incd z0.d, all, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incd z0.d, all, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +incd z0.d, all +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incd z0.d, all +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incd.s b/test/MC/AArch64/SVE/incd.s index 6d146a4612b3..9774c450ed12 100644 --- a/test/MC/AArch64/SVE/incd.s +++ b/test/MC/AArch64/SVE/incd.s @@ -164,3 +164,43 @@ incd x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 e3 f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incd z0.d +// CHECK-INST: incd z0.d +// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 f0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incd z0.d, all, mul #16 +// CHECK-INST: incd z0.d, all, mul #16 +// CHECK-ENCODING: [0xe0,0xc3,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 ff 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incd z0.d, all +// CHECK-INST: incd z0.d +// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 f0 04 <unknown> diff --git a/test/MC/AArch64/SVE/inch-diagnostics.s b/test/MC/AArch64/SVE/inch-diagnostics.s index 31b71cfd49df..b25019bd9bd4 100644 --- a/test/MC/AArch64/SVE/inch-diagnostics.s +++ b/test/MC/AArch64/SVE/inch-diagnostics.s @@ -61,3 +61,25 @@ inch x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: inch x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +inch z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: inch z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +inch z0.h, all, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: inch z0.h, all, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +inch z0.h, all +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: inch z0.h, all +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/inch.s b/test/MC/AArch64/SVE/inch.s index 02519067271d..fd952cd7d3db 100644 --- a/test/MC/AArch64/SVE/inch.s +++ b/test/MC/AArch64/SVE/inch.s @@ -164,3 +164,43 @@ inch x0, #28 // CHECK-ENCODING: [0x80,0xe3,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 e3 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +inch z0.h +// CHECK-INST: inch z0.h +// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 70 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +inch z0.h, all, mul #16 +// CHECK-INST: inch z0.h, all, mul #16 +// CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 7f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +inch z0.h, all +// CHECK-INST: inch z0.h +// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 70 04 <unknown> diff --git a/test/MC/AArch64/SVE/incp-diagnostics.s b/test/MC/AArch64/SVE/incp-diagnostics.s index 71cc91f6d02d..1cc766fcd8b2 100644 --- a/test/MC/AArch64/SVE/incp-diagnostics.s +++ b/test/MC/AArch64/SVE/incp-diagnostics.s @@ -36,3 +36,13 @@ incp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: incp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +incp z31.d, p7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incp z31.d, p7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incp.s b/test/MC/AArch64/SVE/incp.s index c897e846fd05..6bc2c5160925 100644 --- a/test/MC/AArch64/SVE/incp.s +++ b/test/MC/AArch64/SVE/incp.s @@ -72,3 +72,19 @@ incp z31.d, p15 // CHECK-ENCODING: [0xff,0x81,0xec,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 81 ec 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +incp z31.d, p15 +// CHECK-INST: incp z31.d, p15 +// CHECK-ENCODING: [0xff,0x81,0xec,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 81 ec 25 <unknown> diff --git a/test/MC/AArch64/SVE/incw-diagnostics.s b/test/MC/AArch64/SVE/incw-diagnostics.s index e1a85edc931c..88335e9c5d72 100644 --- a/test/MC/AArch64/SVE/incw-diagnostics.s +++ b/test/MC/AArch64/SVE/incw-diagnostics.s @@ -61,3 +61,25 @@ incw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +incw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +incw z0.s, all, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incw z0.s, all, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +incw z0.s, all +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incw z0.s, all +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incw.s b/test/MC/AArch64/SVE/incw.s index a9e34dad08c3..fb6a05ee6f57 100644 --- a/test/MC/AArch64/SVE/incw.s +++ b/test/MC/AArch64/SVE/incw.s @@ -165,3 +165,43 @@ incw x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 e3 b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incw z0.s +// CHECK-INST: incw z0.s +// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 b0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incw z0.s, all, mul #16 +// CHECK-INST: incw z0.s, all, mul #16 +// CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 bf 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incw z0.s, all +// CHECK-INST: incw z0.s +// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 b0 04 <unknown> diff --git a/test/MC/AArch64/SVE/index-diagnostics.s b/test/MC/AArch64/SVE/index-diagnostics.s index be42c9107233..3b2a4aa656fd 100644 --- a/test/MC/AArch64/SVE/index-diagnostics.s +++ b/test/MC/AArch64/SVE/index-diagnostics.s @@ -56,3 +56,43 @@ index z17.d, w9, w7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: index z17.d, w9, w7 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p0/z, z28.d +index z21.d, x10, x21 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z21.d, x10, x21 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +index z21.d, x10, x21 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z21.d, x10, x21 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +index z23.d, x13, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, x13, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +index z23.d, x13, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, x13, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +index z23.d, #13, x8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, #13, x8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +index z23.d, #13, x8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, #13, x8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/insr-diagnostics.s b/test/MC/AArch64/SVE/insr-diagnostics.s index e0ec3e6414c8..a0afb22f8fdf 100644 --- a/test/MC/AArch64/SVE/insr-diagnostics.s +++ b/test/MC/AArch64/SVE/insr-diagnostics.s @@ -43,3 +43,19 @@ insr z31.d, b0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: insr z31.d, b0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +insr z31.d, xzr +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: insr z31.d, xzr +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z4.d, p0/z, z6.d +insr z4.d, d31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: insr z4.d, d31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/insr.s b/test/MC/AArch64/SVE/insr.s index 7e13a1b93fe5..262611300019 100644 --- a/test/MC/AArch64/SVE/insr.s +++ b/test/MC/AArch64/SVE/insr.s @@ -78,3 +78,31 @@ insr z31.d, d31 // CHECK-ENCODING: [0xff,0x3b,0xf4,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 3b f4 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +insr z31.d, xzr +// CHECK-INST: insr z31.d, xzr +// CHECK-ENCODING: [0xff,0x3b,0xe4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 3b e4 05 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +insr z4.d, d31 +// CHECK-INST: insr z4.d, d31 +// CHECK-ENCODING: [0xe4,0x3b,0xf4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 3b f4 05 <unknown> diff --git a/test/MC/AArch64/SVE/lasta-diagnostics.s b/test/MC/AArch64/SVE/lasta-diagnostics.s index dd8155521f5e..b153a67f35f6 100644 --- a/test/MC/AArch64/SVE/lasta-diagnostics.s +++ b/test/MC/AArch64/SVE/lasta-diagnostics.s @@ -52,3 +52,31 @@ lasta d0, p7, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: lasta d0, p7, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +lasta x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lasta x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +lasta d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lasta d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lastb-diagnostics.s b/test/MC/AArch64/SVE/lastb-diagnostics.s index ed92c76cadf6..b86654ffc12d 100644 --- a/test/MC/AArch64/SVE/lastb-diagnostics.s +++ b/test/MC/AArch64/SVE/lastb-diagnostics.s @@ -52,3 +52,31 @@ lastb d0, p7, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: lastb d0, p7, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +lastb x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lastb x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +lastb d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lastb d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1b-diagnostics.s b/test/MC/AArch64/SVE/ld1b-diagnostics.s index 4d4da4021e33..70fecbf5805d 100644 --- a/test/MC/AArch64/SVE/ld1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1b-diagnostics.s @@ -177,3 +177,19 @@ ld1b z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1d-diagnostics.s b/test/MC/AArch64/SVE/ld1d-diagnostics.s index cedb48b41719..2ba540699567 100644 --- a/test/MC/AArch64/SVE/ld1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1d-diagnostics.s @@ -132,3 +132,19 @@ ld1d z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1h-diagnostics.s b/test/MC/AArch64/SVE/ld1h-diagnostics.s index 7c8694131f86..8643a051fe9b 100644 --- a/test/MC/AArch64/SVE/ld1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1h-diagnostics.s @@ -192,3 +192,19 @@ ld1h z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rb-diagnostics.s b/test/MC/AArch64/SVE/ld1rb-diagnostics.s index 18532c78c87a..c862eb5cdb16 100644 --- a/test/MC/AArch64/SVE/ld1rb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rb-diagnostics.s @@ -21,3 +21,19 @@ ld1rb z0.b, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rb z0.b, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rd-diagnostics.s b/test/MC/AArch64/SVE/ld1rd-diagnostics.s index 66eaa8b43a00..e85ffa16ef52 100644 --- a/test/MC/AArch64/SVE/ld1rd-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rd-diagnostics.s @@ -55,3 +55,19 @@ ld1rd z0.d, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rd z0.d, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rh-diagnostics.s b/test/MC/AArch64/SVE/ld1rh-diagnostics.s index bdd4b06c4f62..2665e859d81e 100644 --- a/test/MC/AArch64/SVE/ld1rh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rh-diagnostics.s @@ -45,3 +45,19 @@ ld1rh z0.h, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rh z0.h, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqb-diagnostics.s b/test/MC/AArch64/SVE/ld1rqb-diagnostics.s index 0a8a766d6137..94a8d5c3f5c8 100644 --- a/test/MC/AArch64/SVE/ld1rqb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqb-diagnostics.s @@ -79,3 +79,19 @@ ld1rqb z0.b, p0/z, [x0, w1, uxtw] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqd-diagnostics.s b/test/MC/AArch64/SVE/ld1rqd-diagnostics.s index 1ea8188d6074..8c4ac3ecad6d 100644 --- a/test/MC/AArch64/SVE/ld1rqd-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqd-diagnostics.s @@ -79,3 +79,19 @@ ld1rqd z0.d, p0/z, [x0, w1, uxtw #1] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1rqd z0.d, p0/z, [x0, w1, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z23.d, p3/z, z30.d +ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqh-diagnostics.s b/test/MC/AArch64/SVE/ld1rqh-diagnostics.s index aecc63e76a10..960dda35db6e 100644 --- a/test/MC/AArch64/SVE/ld1rqh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqh-diagnostics.s @@ -79,3 +79,19 @@ ld1rqh z0.h, p0/z, [x0, w1, uxtw #1] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1rqh z0.h, p0/z, [x0, w1, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z23.h, p3/z, z30.h +ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqw-diagnostics.s b/test/MC/AArch64/SVE/ld1rqw-diagnostics.s index 477af4242e9a..b4d45e5ceb6d 100644 --- a/test/MC/AArch64/SVE/ld1rqw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqw-diagnostics.s @@ -79,3 +79,19 @@ ld1rqw z0.s, p0/z, [x0, w1, uxtw #1] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z23.s, p3/z, z30.s +ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rsb-diagnostics.s b/test/MC/AArch64/SVE/ld1rsb-diagnostics.s index 7950eca94adf..28c6ecd9013d 100644 --- a/test/MC/AArch64/SVE/ld1rsb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rsb-diagnostics.s @@ -30,3 +30,19 @@ ld1rsb z0.h, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rsb z0.h, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rsh-diagnostics.s b/test/MC/AArch64/SVE/ld1rsh-diagnostics.s index b33c7934ccb8..ae13b87b61ee 100644 --- a/test/MC/AArch64/SVE/ld1rsh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rsh-diagnostics.s @@ -40,3 +40,19 @@ ld1rsh z0.s, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rsh z0.s, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rsw-diagnostics.s b/test/MC/AArch64/SVE/ld1rsw-diagnostics.s index 4d7cf63980dc..02da02d5cf5b 100644 --- a/test/MC/AArch64/SVE/ld1rsw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rsw-diagnostics.s @@ -45,3 +45,19 @@ ld1rsw z0.d, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rsw z0.d, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rw-diagnostics.s b/test/MC/AArch64/SVE/ld1rw-diagnostics.s index e5e55c9da562..c4bc362d7d0b 100644 --- a/test/MC/AArch64/SVE/ld1rw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rw-diagnostics.s @@ -50,3 +50,19 @@ ld1rw z0.s, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rw z0.s, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1sb-diagnostics.s b/test/MC/AArch64/SVE/ld1sb-diagnostics.s index e936f576fdef..0bbccfc0c956 100644 --- a/test/MC/AArch64/SVE/ld1sb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1sb-diagnostics.s @@ -175,3 +175,19 @@ ld1sb z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1sh-diagnostics.s b/test/MC/AArch64/SVE/ld1sh-diagnostics.s index 91fc364d7dc3..d423480a2844 100644 --- a/test/MC/AArch64/SVE/ld1sh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1sh-diagnostics.s @@ -191,3 +191,19 @@ ld1sh z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1sw-diagnostics.s b/test/MC/AArch64/SVE/ld1sw-diagnostics.s index 2ecf3b7fce32..1061e87301dc 100644 --- a/test/MC/AArch64/SVE/ld1sw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1sw-diagnostics.s @@ -161,3 +161,19 @@ ld1sw z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1w-diagnostics.s b/test/MC/AArch64/SVE/ld1w-diagnostics.s index d1031eac60bf..1aafc27f8585 100644 --- a/test/MC/AArch64/SVE/ld1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1w-diagnostics.s @@ -177,3 +177,19 @@ ld1w z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2b-diagnostics.s b/test/MC/AArch64/SVE/ld2b-diagnostics.s index 136bf026c6ae..3eae31f363d4 100644 --- a/test/MC/AArch64/SVE/ld2b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2b-diagnostics.s @@ -89,3 +89,19 @@ ld2b { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2b { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2d-diagnostics.s b/test/MC/AArch64/SVE/ld2d-diagnostics.s index 7c58ef11530c..7b64621635d8 100644 --- a/test/MC/AArch64/SVE/ld2d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2d-diagnostics.s @@ -94,3 +94,19 @@ ld2d { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2d { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2h-diagnostics.s b/test/MC/AArch64/SVE/ld2h-diagnostics.s index e3d29dc2c34d..4568fe396ee1 100644 --- a/test/MC/AArch64/SVE/ld2h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2h-diagnostics.s @@ -94,3 +94,19 @@ ld2h { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2h { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2w-diagnostics.s b/test/MC/AArch64/SVE/ld2w-diagnostics.s index cf09aa26d1f7..66acedab1e9f 100644 --- a/test/MC/AArch64/SVE/ld2w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2w-diagnostics.s @@ -94,3 +94,19 @@ ld2w { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2w { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3b-diagnostics.s b/test/MC/AArch64/SVE/ld3b-diagnostics.s index c93ec32ae867..388545258bc6 100644 --- a/test/MC/AArch64/SVE/ld3b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3b-diagnostics.s @@ -89,3 +89,19 @@ ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3d-diagnostics.s b/test/MC/AArch64/SVE/ld3d-diagnostics.s index 33b063733e1b..f672fb832004 100644 --- a/test/MC/AArch64/SVE/ld3d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3d-diagnostics.s @@ -94,3 +94,19 @@ ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3h-diagnostics.s b/test/MC/AArch64/SVE/ld3h-diagnostics.s index cf0423a128ab..c5ae5dfcda53 100644 --- a/test/MC/AArch64/SVE/ld3h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3h-diagnostics.s @@ -94,3 +94,19 @@ ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3w-diagnostics.s b/test/MC/AArch64/SVE/ld3w-diagnostics.s index 758fc04667df..d3082c14b8fe 100644 --- a/test/MC/AArch64/SVE/ld3w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3w-diagnostics.s @@ -94,3 +94,19 @@ ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4b-diagnostics.s b/test/MC/AArch64/SVE/ld4b-diagnostics.s index 3120c49fb1ba..65c5bcd26fc6 100644 --- a/test/MC/AArch64/SVE/ld4b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4b-diagnostics.s @@ -89,3 +89,19 @@ ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4d-diagnostics.s b/test/MC/AArch64/SVE/ld4d-diagnostics.s index 8b5715d2249c..ea70ea037012 100644 --- a/test/MC/AArch64/SVE/ld4d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4d-diagnostics.s @@ -94,3 +94,19 @@ ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4h-diagnostics.s b/test/MC/AArch64/SVE/ld4h-diagnostics.s index 45f5bd5108cd..dc5485484f7b 100644 --- a/test/MC/AArch64/SVE/ld4h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4h-diagnostics.s @@ -94,3 +94,19 @@ ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4w-diagnostics.s b/test/MC/AArch64/SVE/ld4w-diagnostics.s index 86547c22b1a5..d4633dd4d55d 100644 --- a/test/MC/AArch64/SVE/ld4w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4w-diagnostics.s @@ -94,3 +94,19 @@ ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1b-diagnostics.s b/test/MC/AArch64/SVE/ldff1b-diagnostics.s index 2ce58d894fb5..8de73ef3e6f8 100644 --- a/test/MC/AArch64/SVE/ldff1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1b-diagnostics.s @@ -112,3 +112,19 @@ ldff1b z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1d-diagnostics.s b/test/MC/AArch64/SVE/ldff1d-diagnostics.s index e5aec40163f2..29978c7303bc 100644 --- a/test/MC/AArch64/SVE/ldff1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1d-diagnostics.s @@ -111,3 +111,19 @@ ldff1d z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1h-diagnostics.s b/test/MC/AArch64/SVE/ldff1h-diagnostics.s index e568031c4791..8674d095351b 100644 --- a/test/MC/AArch64/SVE/ldff1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1h-diagnostics.s @@ -141,3 +141,19 @@ ldff1h z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1sb-diagnostics.s b/test/MC/AArch64/SVE/ldff1sb-diagnostics.s index b9bd9e470c34..23cca8c14545 100644 --- a/test/MC/AArch64/SVE/ldff1sb-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1sb-diagnostics.s @@ -115,3 +115,19 @@ ldff1sb z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1sh-diagnostics.s b/test/MC/AArch64/SVE/ldff1sh-diagnostics.s index e58d9151b85d..4a8d329f973c 100644 --- a/test/MC/AArch64/SVE/ldff1sh-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1sh-diagnostics.s @@ -135,3 +135,19 @@ ldff1sh z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1sw-diagnostics.s b/test/MC/AArch64/SVE/ldff1sw-diagnostics.s index 4571ee664618..ab096f36b8c1 100644 --- a/test/MC/AArch64/SVE/ldff1sw-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1sw-diagnostics.s @@ -116,3 +116,19 @@ ldff1sw z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1w-diagnostics.s b/test/MC/AArch64/SVE/ldff1w-diagnostics.s index 36a7eec8af56..e2cec7c77101 100644 --- a/test/MC/AArch64/SVE/ldff1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1w-diagnostics.s @@ -141,3 +141,19 @@ ldff1w z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1b-diagnostics.s b/test/MC/AArch64/SVE/ldnf1b-diagnostics.s index d680595801dc..b24c15308f4c 100644 --- a/test/MC/AArch64/SVE/ldnf1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1b-diagnostics.s @@ -85,3 +85,19 @@ ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1d-diagnostics.s b/test/MC/AArch64/SVE/ldnf1d-diagnostics.s index c1a47ba02119..8c29bddea0c7 100644 --- a/test/MC/AArch64/SVE/ldnf1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1d-diagnostics.s @@ -40,3 +40,19 @@ ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1h-diagnostics.s b/test/MC/AArch64/SVE/ldnf1h-diagnostics.s index ef4d80a60a7d..6d61423f9997 100644 --- a/test/MC/AArch64/SVE/ldnf1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1h-diagnostics.s @@ -70,3 +70,19 @@ ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s b/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s index a4d42559d01a..23e816425c5d 100644 --- a/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s @@ -84,3 +84,19 @@ ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s b/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s index 7e62d7959576..3071cc6e4694 100644 --- a/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s @@ -69,3 +69,19 @@ ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s b/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s index 0312815614a6..5c133f7a0095 100644 --- a/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s @@ -54,3 +54,19 @@ ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1w-diagnostics.s b/test/MC/AArch64/SVE/ldnf1w-diagnostics.s index 688816e56da8..2fd7123b4925 100644 --- a/test/MC/AArch64/SVE/ldnf1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1w-diagnostics.s @@ -55,3 +55,19 @@ ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1b-diagnostics.s b/test/MC/AArch64/SVE/ldnt1b-diagnostics.s index 8fa065b13b52..b02f633f5ca1 100644 --- a/test/MC/AArch64/SVE/ldnt1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1b-diagnostics.s @@ -59,3 +59,19 @@ ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1d-diagnostics.s b/test/MC/AArch64/SVE/ldnt1d-diagnostics.s index aff76a998623..2aba4dc2e946 100644 --- a/test/MC/AArch64/SVE/ldnt1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1d-diagnostics.s @@ -59,3 +59,19 @@ ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1h-diagnostics.s b/test/MC/AArch64/SVE/ldnt1h-diagnostics.s index 2af29bab9fe1..fce1fb5ae5b5 100644 --- a/test/MC/AArch64/SVE/ldnt1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1h-diagnostics.s @@ -59,3 +59,19 @@ ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1w-diagnostics.s b/test/MC/AArch64/SVE/ldnt1w-diagnostics.s index 67a9644078e6..23ba16a0315c 100644 --- a/test/MC/AArch64/SVE/ldnt1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1w-diagnostics.s @@ -59,3 +59,19 @@ ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lsl-diagnostics.s b/test/MC/AArch64/SVE/lsl-diagnostics.s index 067acf9ace6e..517384896c1c 100644 --- a/test/MC/AArch64/SVE/lsl-diagnostics.s +++ b/test/MC/AArch64/SVE/lsl-diagnostics.s @@ -120,3 +120,31 @@ lsl z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +lsl z31.d, z31.d, #63 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z31.d, z31.d, #63 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lsl z31.d, z31.d, #63 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z31.d, z31.d, #63 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +lsl z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +lsl z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lsl.s b/test/MC/AArch64/SVE/lsl.s index 0e8820e19865..38b895b745a6 100644 --- a/test/MC/AArch64/SVE/lsl.s +++ b/test/MC/AArch64/SVE/lsl.s @@ -162,3 +162,55 @@ lsl z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x8c,0xa2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 8c a2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +lsl z31.d, p0/m, z31.d, #63 +// CHECK-INST: lsl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 83 c3 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +lsl z31.d, p0/m, z31.d, #63 +// CHECK-INST: lsl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 83 c3 04 <unknown> + +movprfx z0.s, p0/z, z7.s +// CHECK-INST: movprfx z0.s, p0/z, z7.s +// CHECK-ENCODING: [0xe0,0x20,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 90 04 <unknown> + +lsl z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x9b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 9b 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +lsl z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x9b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 9b 04 <unknown> diff --git a/test/MC/AArch64/SVE/lslr.s b/test/MC/AArch64/SVE/lslr.s index ad8941f201fe..16e19dec9562 100644 --- a/test/MC/AArch64/SVE/lslr.s +++ b/test/MC/AArch64/SVE/lslr.s @@ -30,3 +30,31 @@ lslr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd7,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d7 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +lslr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d7 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +lslr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d7 04 <unknown> diff --git a/test/MC/AArch64/SVE/lsr-diagnostics.s b/test/MC/AArch64/SVE/lsr-diagnostics.s index 77ad88d6676f..0de5bcd522c9 100644 --- a/test/MC/AArch64/SVE/lsr-diagnostics.s +++ b/test/MC/AArch64/SVE/lsr-diagnostics.s @@ -121,3 +121,31 @@ lsr z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +lsr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lsr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +lsr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +lsr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lsr.s b/test/MC/AArch64/SVE/lsr.s index 9ef662302a94..481326124930 100644 --- a/test/MC/AArch64/SVE/lsr.s +++ b/test/MC/AArch64/SVE/lsr.s @@ -162,3 +162,55 @@ lsr z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x84,0xa2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 84 a2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +lsr z31.d, p0/m, z31.d, #64 +// CHECK-INST: lsr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x81,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 81 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +lsr z31.d, p0/m, z31.d, #64 +// CHECK-INST: lsr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x81,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 81 04 <unknown> + +movprfx z0.s, p0/z, z7.s +// CHECK-INST: movprfx z0.s, p0/z, z7.s +// CHECK-ENCODING: [0xe0,0x20,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 90 04 <unknown> + +lsr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x99,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 99 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +lsr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x99,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 99 04 <unknown> diff --git a/test/MC/AArch64/SVE/lsrr.s b/test/MC/AArch64/SVE/lsrr.s index a6bca70103a5..ec87a711dbfa 100644 --- a/test/MC/AArch64/SVE/lsrr.s +++ b/test/MC/AArch64/SVE/lsrr.s @@ -30,3 +30,31 @@ lsrr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd5,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d5 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d5 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d5 04 <unknown> diff --git a/test/MC/AArch64/SVE/mad.s b/test/MC/AArch64/SVE/mad.s index 3a5d81e32611..b9712d6ef3bb 100644 --- a/test/MC/AArch64/SVE/mad.s +++ b/test/MC/AArch64/SVE/mad.s @@ -30,3 +30,31 @@ mad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 df c1 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 df c1 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 df c1 04 <unknown> diff --git a/test/MC/AArch64/SVE/mla.s b/test/MC/AArch64/SVE/mla.s index 4911e6afd925..d76ee0996a8e 100644 --- a/test/MC/AArch64/SVE/mla.s +++ b/test/MC/AArch64/SVE/mla.s @@ -30,3 +30,31 @@ mla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 5c df 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c df 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c df 04 <unknown> diff --git a/test/MC/AArch64/SVE/mls.s b/test/MC/AArch64/SVE/mls.s index 8c088fdd98b0..32d3d0e2dd8b 100644 --- a/test/MC/AArch64/SVE/mls.s +++ b/test/MC/AArch64/SVE/mls.s @@ -30,3 +30,31 @@ mls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 7c df 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c df 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c df 04 <unknown> diff --git a/test/MC/AArch64/SVE/mov-diagnostics.s b/test/MC/AArch64/SVE/mov-diagnostics.s index 8f0eef0fa4d0..23b8b55be96e 100644 --- a/test/MC/AArch64/SVE/mov-diagnostics.s +++ b/test/MC/AArch64/SVE/mov-diagnostics.s @@ -412,3 +412,79 @@ mov z24.q, z21.q[4] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK-NEXT: mov z24.q, z21.q[4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +mov z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +mov z0.d, #0xe0000000000003ff +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, #0xe0000000000003ff +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +mov z0.d, #0xe0000000000003ff +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, #0xe0000000000003ff +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z4.d, p7/z, z6.d +mov z4.d, p7/m, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z4.d, p7/m, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.d, p15/m, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, p15/m, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +mov z0.d, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +mov z0.d, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +mov z31.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +mov z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/mov.s b/test/MC/AArch64/SVE/mov.s index c0a50e39c706..5704e50c941a 100644 --- a/test/MC/AArch64/SVE/mov.s +++ b/test/MC/AArch64/SVE/mov.s @@ -660,3 +660,79 @@ mov p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7d 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +mov z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +mov z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z21.d, p7/z, z28.d +// CHECK-INST: movprfx z21.d, p7/z, z28.d +// CHECK-ENCODING: [0x95,0x3f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 3f d0 04 <unknown> + +mov z21.d, p7/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p7/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xd7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 d7 05 <unknown> + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 <unknown> + +mov z21.d, p15/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p15/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xdf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 df 05 <unknown> + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +mov z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +mov z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> diff --git a/test/MC/AArch64/SVE/movprfx-diagnostics.s b/test/MC/AArch64/SVE/movprfx-diagnostics.s new file mode 100644 index 000000000000..56b1f5cfc725 --- /dev/null +++ b/test/MC/AArch64/SVE/movprfx-diagnostics.s @@ -0,0 +1,193 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + +// ------------------------------------------------------------------------- // +// Different destination register (unary) + +movprfx z0, z1 +abs z2.d, p0/m, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: abs z2.d, p0/m, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different destination register (binary) + +movprfx z0, z1 +add z2.d, p0/m, z2.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: add z2.d, p0/m, z2.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different destination register (wide element) + +movprfx z0, z1 +asr z2.s, p0/m, z2.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: asr z2.s, p0/m, z2.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different destination register (ternary) + +movprfx z0, z1 +mla z3.d, p0/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: mla z3.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Destination used in other operand (unary) + +movprfx z0, z1 +abs z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: abs z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z1.d +cpy z0.d, p0/m, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: cpy z0.d, p0/m, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z1.d +mov z0.d, p0/m, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: mov z0.d, p0/m, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Destination used in other operand (binary) + +movprfx z0, z1 +add z0.d, p0/m, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: add z0.d, p0/m, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Destination used in other operand (wide element) + +movprfx z0, z1 +asr z0.s, p0/m, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: asr z0.s, p0/m, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Destination used in other operand (ternary) + +movprfx z0, z1 +mla z0.d, p0/m, z0.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: mla z0.d, p0/m, z0.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (unary) + +movprfx z0.d, p0/m, z1.d +abs z0.d, p1/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: abs z0.d, p1/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (binary) + +movprfx z0.d, p0/m, z1.d +add z0.d, p1/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: add z0.d, p1/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (wide element) + +movprfx z0.d, p0/m, z1.d +asr z0.s, p1/m, z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: asr z0.s, p1/m, z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (ternary) + +movprfx z0.d, p0/m, z1.d +mla z0.d, p1/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: mla z0.d, p1/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (unary) + +movprfx z0.s, p0/m, z1.s +abs z0.d, p0/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: abs z0.d, p0/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (binary) + +movprfx z0.s, p0/m, z1.s +add z0.d, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (wide element) + +movprfx z0.d, p0/m, z1.d +asr z0.s, p0/m, z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (ternary) + +movprfx z0.s, p0/m, z1.s +mla z0.d, p0/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Predicated movprfx with non-predicated instruction. + +movprfx z0.d, p0/m, z1.d +add z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: add z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Ensure we don't try to apply a prefix to subsequent instructions (upon failure) + +movprfx z0, z1 +add z0.d, z1.d, z2.d +add z0.d, z1.d, z2.d +// CHECK: [[@LINE-2]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: add z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: +// CHECK: add z0.d, z1.d, z2.d diff --git a/test/MC/AArch64/SVE/movprfx.s b/test/MC/AArch64/SVE/movprfx.s new file mode 100644 index 000000000000..8065967ebc3a --- /dev/null +++ b/test/MC/AArch64/SVE/movprfx.s @@ -0,0 +1,97 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +// This test file is mostly empty because most 'movprfx' tests are embedded +// with other instructions that are destructive and can be prefixed +// by the movprfx instruction. A list of destructive instructions +// is given below by their mnemonic, which have tests in corresponding +// <mnemonic>.s test files: +// +// abs decp fdivr fnmla fsubr mov sdivr sqincw umulh +// add eon fmad fnmls ftmad msb sdot sqsub uqadd +// and eor fmax fnmsb incd mul smax sub uqdecd +// asr ext fmaxnm frecpx inch neg smin subr uqdech +// asrd fabd fmin frinta incp not smulh sxtb uqdecp +// asrr fabs fminnm frinti incw orn splice sxth uqdecw +// bic fadd fmla frintm insr orr sqadd sxtw uqincd +// clasta fcadd fmls frintn lsl rbit sqdecd uabd uqinch +// clastb fcmla fmov frintp lslr revb sqdech ucvtf uqincp +// cls fcpy fmsb frintx lsr revh sqdecp udiv uqincw +// clz fcvt fmul frintz lsrr revw sqdecw udivr uqsub +// cnot fcvtzs fmulx fscale mad sabd sqincd udot uxtb +// cnt fcvtzu fneg fsqrt mla scvtf sqinch umax uxth +// cpy fdiv fnmad fsub mls sdiv sqincp umin uxtw + + +// ------------------------------------------------------------------------- // +// Test compatibility with MOVPRFX instruction with BRK and HLT. +// +// Section 7.1.2 of the SVE Architecture Reference Manual Supplement: +// "it is permitted to use MOVPRFX to prefix an A64 BRK or HLT instruction" + +movprfx z0, z1 +// CHECK-INST: movprfx z0, z1 +// CHECK-ENCODING: [0x20,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc 20 04 <unknown> + +hlt #1 +// CHECK-INST: hlt #0x1 +// CHECK-ENCODING: [0x20,0x00,0x40,0xd4] + +movprfx z0.d, p0/z, z1.d +// CHECK-INST: movprfx z0.d, p0/z, z1.d +// CHECK-ENCODING: [0x20,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 20 d0 04 <unknown> + +hlt #1 +// CHECK-INST: hlt #0x1 +// CHECK-ENCODING: [0x20,0x00,0x40,0xd4] + +movprfx z0, z1 +// CHECK-INST: movprfx z0, z1 +// CHECK-ENCODING: [0x20,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc 20 04 <unknown> + +brk #1 +// CHECK-INST: brk #0x1 +// CHECK-ENCODING: [0x20,0x00,0x20,0xd4] + +movprfx z0.d, p0/z, z1.d +// CHECK-INST: movprfx z0.d, p0/z, z1.d +// CHECK-ENCODING: [0x20,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 20 d0 04 <unknown> + +brk #1 +// CHECK-INST: brk #0x1 +// CHECK-ENCODING: [0x20,0x00,0x20,0xd4] + +// ------------------------------------------------------------------------- // +// Ensure we don't try to apply a prefix to subsequent instructions (upon success) + +movprfx z0, z1 +// CHECK-INST: movprfx z0, z1 +// CHECK-ENCODING: [0x20,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc 20 04 <unknown> + +add z0.d, p0/m, z0.d, z1.d +// CHECK-INST: add z0.d, p0/m, z0.d, z1.d +// CHECK-ENCODING: [0x20,0x00,0xc0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 c0 04 <unknown> + +add z0.d, p0/m, z0.d, z1.d +// CHECK-INST: add z0.d, p0/m, z0.d, z1.d +// CHECK-ENCODING: [0x20,0x00,0xc0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 c0 04 <unknown> diff --git a/test/MC/AArch64/SVE/msb.s b/test/MC/AArch64/SVE/msb.s index 048f32160e12..94715616db51 100644 --- a/test/MC/AArch64/SVE/msb.s +++ b/test/MC/AArch64/SVE/msb.s @@ -30,3 +30,31 @@ msb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 ff c1 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +msb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: msb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 ff c1 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +msb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: msb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 ff c1 04 <unknown> diff --git a/test/MC/AArch64/SVE/mul-diagnostics.s b/test/MC/AArch64/SVE/mul-diagnostics.s index 745c35d613f8..de08aff0fd5a 100644 --- a/test/MC/AArch64/SVE/mul-diagnostics.s +++ b/test/MC/AArch64/SVE/mul-diagnostics.s @@ -36,3 +36,13 @@ mul z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: mul z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +mul z31.d, z31.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: mul z31.d, z31.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/mul.s b/test/MC/AArch64/SVE/mul.s index f83b88ee7125..d1a1f867847f 100644 --- a/test/MC/AArch64/SVE/mul.s +++ b/test/MC/AArch64/SVE/mul.s @@ -78,3 +78,43 @@ mul z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xf0,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff cf f0 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: mul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: mul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d0 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +mul z31.d, z31.d, #127 +// CHECK-INST: mul z31.d, z31.d, #127 +// CHECK-ENCODING: [0xff,0xcf,0xf0,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff cf f0 25 <unknown> diff --git a/test/MC/AArch64/SVE/neg.s b/test/MC/AArch64/SVE/neg.s index 3ad4abf463cc..437f0e959b2d 100644 --- a/test/MC/AArch64/SVE/neg.s +++ b/test/MC/AArch64/SVE/neg.s @@ -54,3 +54,31 @@ neg z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd7,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d7 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +neg z4.d, p7/m, z31.d +// CHECK-INST: neg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d7 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +neg z4.d, p7/m, z31.d +// CHECK-INST: neg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d7 04 <unknown> diff --git a/test/MC/AArch64/SVE/not.s b/test/MC/AArch64/SVE/not.s index 67ebce236c26..35e72bb06ac1 100644 --- a/test/MC/AArch64/SVE/not.s +++ b/test/MC/AArch64/SVE/not.s @@ -42,3 +42,31 @@ not p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7f 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +not z4.d, p7/m, z31.d +// CHECK-INST: not z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xde,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf de 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +not z4.d, p7/m, z31.d +// CHECK-INST: not z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xde,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf de 04 <unknown> diff --git a/test/MC/AArch64/SVE/orn-diagnostics.s b/test/MC/AArch64/SVE/orn-diagnostics.s index d33cf8009068..a9db36ba258c 100644 --- a/test/MC/AArch64/SVE/orn-diagnostics.s +++ b/test/MC/AArch64/SVE/orn-diagnostics.s @@ -77,3 +77,13 @@ orn p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +orn z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: orn z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/orn.s b/test/MC/AArch64/SVE/orn.s index 89b8ea5795e8..1028414070f0 100644 --- a/test/MC/AArch64/SVE/orn.s +++ b/test/MC/AArch64/SVE/orn.s @@ -66,3 +66,19 @@ orn p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7d,0x8f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 7d 8f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +orn z0.d, z0.d, #0x6 +// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 03 05 <unknown> diff --git a/test/MC/AArch64/SVE/orr-diagnostics.s b/test/MC/AArch64/SVE/orr-diagnostics.s index bcea515cc131..7038ea41f470 100644 --- a/test/MC/AArch64/SVE/orr-diagnostics.s +++ b/test/MC/AArch64/SVE/orr-diagnostics.s @@ -92,3 +92,37 @@ orr p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: orr p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +orr z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: orr z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/orr.s b/test/MC/AArch64/SVE/orr.s index 1cf48fdd7a03..7d00cd8c6cf1 100644 --- a/test/MC/AArch64/SVE/orr.s +++ b/test/MC/AArch64/SVE/orr.s @@ -110,3 +110,43 @@ orr p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x8f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7d 8f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +orr z4.d, p7/m, z4.d, z31.d +// CHECK-INST: orr z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f d8 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +orr z4.d, p7/m, z4.d, z31.d +// CHECK-INST: orr z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f d8 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +orr z0.d, z0.d, #0x6 +// CHECK-INST: orr z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 03 05 <unknown> diff --git a/test/MC/AArch64/SVE/orv-diagnostics.s b/test/MC/AArch64/SVE/orv-diagnostics.s index 8a64ad89c005..1892321be28b 100644 --- a/test/MC/AArch64/SVE/orv-diagnostics.s +++ b/test/MC/AArch64/SVE/orv-diagnostics.s @@ -31,4 +31,19 @@ orv v0.2d, p7, z31.d orv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: orv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +orv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +orv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pfalse-diagnostics.s b/test/MC/AArch64/SVE/pfalse-diagnostics.s new file mode 100644 index 000000000000..1a4047d8d80b --- /dev/null +++ b/test/MC/AArch64/SVE/pfalse-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +pfalse p15.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: pfalse p15.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pfalse.s b/test/MC/AArch64/SVE/pfalse.s new file mode 100644 index 000000000000..b1385d8b863f --- /dev/null +++ b/test/MC/AArch64/SVE/pfalse.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pfalse p15.b +// CHECK-INST: pfalse p15.b +// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f e4 18 25 <unknown> diff --git a/test/MC/AArch64/SVE/pfirst-diagnostics.s b/test/MC/AArch64/SVE/pfirst-diagnostics.s new file mode 100644 index 000000000000..6ed891a59f24 --- /dev/null +++ b/test/MC/AArch64/SVE/pfirst-diagnostics.s @@ -0,0 +1,19 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +pfirst p0.h, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: pfirst p0.h, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Tied operands must match + +pfirst p0.b, p15, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: pfirst p0.b, p15, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pfirst.s b/test/MC/AArch64/SVE/pfirst.s new file mode 100644 index 000000000000..8090bf72a0ef --- /dev/null +++ b/test/MC/AArch64/SVE/pfirst.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pfirst p0.b, p15, p0.b +// CHECK-INST: pfirst p0.b, p15, p0.b +// CHECK-ENCODING: [0xe0,0xc1,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c1 58 25 <unknown> + +pfirst p15.b, p15, p15.b +// CHECK-INST: pfirst p15.b, p15, p15.b +// CHECK-ENCODING: [0xef,0xc1,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef c1 58 25 <unknown> diff --git a/test/MC/AArch64/SVE/pnext-diagnostics.s b/test/MC/AArch64/SVE/pnext-diagnostics.s new file mode 100644 index 000000000000..e8ee5669dfea --- /dev/null +++ b/test/MC/AArch64/SVE/pnext-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Tied operands must match + +pnext p0.b, p15, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: pnext p0.b, p15, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pnext.s b/test/MC/AArch64/SVE/pnext.s new file mode 100644 index 000000000000..3d788deb05c4 --- /dev/null +++ b/test/MC/AArch64/SVE/pnext.s @@ -0,0 +1,38 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pnext p15.b, p15, p15.b +// CHECK-INST: pnext p15.b, p15, p15.b +// CHECK-ENCODING: [0xef,0xc5,0x19,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef c5 19 25 <unknown> + +pnext p0.b, p15, p0.b +// CHECK-INST: pnext p0.b, p15, p0.b +// CHECK-ENCODING: [0xe0,0xc5,0x19,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 19 25 <unknown> + +pnext p0.h, p15, p0.h +// CHECK-INST: pnext p0.h, p15, p0.h +// CHECK-ENCODING: [0xe0,0xc5,0x59,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 59 25 <unknown> + +pnext p0.s, p15, p0.s +// CHECK-INST: pnext p0.s, p15, p0.s +// CHECK-ENCODING: [0xe0,0xc5,0x99,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 99 25 <unknown> + +pnext p0.d, p15, p0.d +// CHECK-INST: pnext p0.d, p15, p0.d +// CHECK-ENCODING: [0xe0,0xc5,0xd9,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 d9 25 <unknown> diff --git a/test/MC/AArch64/SVE/prfb-diagnostics.s b/test/MC/AArch64/SVE/prfb-diagnostics.s index 2ffdc6ff6a00..24466ed79480 100644 --- a/test/MC/AArch64/SVE/prfb-diagnostics.s +++ b/test/MC/AArch64/SVE/prfb-diagnostics.s @@ -128,3 +128,19 @@ prfb #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfb #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +prfb pldl1keep, p0, [x0, z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +prfb pldl1keep, p0, [x0, z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/prfd-diagnostics.s b/test/MC/AArch64/SVE/prfd-diagnostics.s index bca2f5b71218..2fb6a296576f 100644 --- a/test/MC/AArch64/SVE/prfd-diagnostics.s +++ b/test/MC/AArch64/SVE/prfd-diagnostics.s @@ -114,3 +114,19 @@ prfd #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfd #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/prfh-diagnostics.s b/test/MC/AArch64/SVE/prfh-diagnostics.s index 0265c9f86a31..a9f8ad84c65c 100644 --- a/test/MC/AArch64/SVE/prfh-diagnostics.s +++ b/test/MC/AArch64/SVE/prfh-diagnostics.s @@ -153,3 +153,19 @@ prfh #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfh #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/prfw-diagnostics.s b/test/MC/AArch64/SVE/prfw-diagnostics.s index 06bc54d2ed0f..510c383f535f 100644 --- a/test/MC/AArch64/SVE/prfw-diagnostics.s +++ b/test/MC/AArch64/SVE/prfw-diagnostics.s @@ -154,3 +154,31 @@ prfw #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfw #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z8.d, p3/z, z15.d +prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z8, z15 +prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21.d, p5/z, z28.d +prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ptest-diagnostics.s b/test/MC/AArch64/SVE/ptest-diagnostics.s new file mode 100644 index 000000000000..f03bf4c60f88 --- /dev/null +++ b/test/MC/AArch64/SVE/ptest-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +ptest p15, p15.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: ptest p15, p15.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ptest.s b/test/MC/AArch64/SVE/ptest.s new file mode 100644 index 000000000000..29622c08c92f --- /dev/null +++ b/test/MC/AArch64/SVE/ptest.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ptest p15, p0.b +// CHECK-INST: ptest p15, p0.b +// CHECK-ENCODING: [0x00,0xfc,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 fc 50 25 <unknown> + +ptest p15, p15.b +// CHECK-INST: ptest p15, p15.b +// CHECK-ENCODING: [0xe0,0xfd,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 fd 50 25 <unknown> diff --git a/test/MC/AArch64/SVE/rbit.s b/test/MC/AArch64/SVE/rbit.s index 9d017d9ce45b..2acba0ebc4e6 100644 --- a/test/MC/AArch64/SVE/rbit.s +++ b/test/MC/AArch64/SVE/rbit.s @@ -30,3 +30,31 @@ rbit z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e7 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +rbit z0.d, p7/m, z31.d +// CHECK-INST: rbit z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e7 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +rbit z0.d, p7/m, z31.d +// CHECK-INST: rbit z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e7 05 <unknown> diff --git a/test/MC/AArch64/SVE/rev-diagnostics.s b/test/MC/AArch64/SVE/rev-diagnostics.s new file mode 100644 index 000000000000..bad4b1655eee --- /dev/null +++ b/test/MC/AArch64/SVE/rev-diagnostics.s @@ -0,0 +1,17 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +rev z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rev z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +rev z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rev z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/revb.s b/test/MC/AArch64/SVE/revb.s index b80f9a5d0492..1393160b80d0 100644 --- a/test/MC/AArch64/SVE/revb.s +++ b/test/MC/AArch64/SVE/revb.s @@ -24,3 +24,31 @@ revb z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e4 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +revb z0.d, p7/m, z31.d +// CHECK-INST: revb z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e4 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +revb z0.d, p7/m, z31.d +// CHECK-INST: revb z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e4 05 <unknown> diff --git a/test/MC/AArch64/SVE/revh.s b/test/MC/AArch64/SVE/revh.s index 8332461a1e69..d37b1bdec530 100644 --- a/test/MC/AArch64/SVE/revh.s +++ b/test/MC/AArch64/SVE/revh.s @@ -18,3 +18,31 @@ revh z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e5 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +revh z0.d, p7/m, z31.d +// CHECK-INST: revh z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e5 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +revh z0.d, p7/m, z31.d +// CHECK-INST: revh z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e5 05 <unknown> diff --git a/test/MC/AArch64/SVE/revw.s b/test/MC/AArch64/SVE/revw.s index 095e2aacd875..c2e419fe2542 100644 --- a/test/MC/AArch64/SVE/revw.s +++ b/test/MC/AArch64/SVE/revw.s @@ -12,3 +12,31 @@ revw z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e6 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +revw z0.d, p7/m, z31.d +// CHECK-INST: revw z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e6 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +revw z0.d, p7/m, z31.d +// CHECK-INST: revw z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e6 05 <unknown> diff --git a/test/MC/AArch64/SVE/sabd.s b/test/MC/AArch64/SVE/sabd.s index 0636d3f76284..4186ff048299 100644 --- a/test/MC/AArch64/SVE/sabd.s +++ b/test/MC/AArch64/SVE/sabd.s @@ -30,3 +30,31 @@ sabd z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcc,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f cc 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cc 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cc 04 <unknown> diff --git a/test/MC/AArch64/SVE/saddv-diagnostics.s b/test/MC/AArch64/SVE/saddv-diagnostics.s index e387e07735ad..d99433222e3e 100644 --- a/test/MC/AArch64/SVE/saddv-diagnostics.s +++ b/test/MC/AArch64/SVE/saddv-diagnostics.s @@ -31,4 +31,19 @@ saddv d0, p7, z31.d saddv d0, p8, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: saddv d0, p8, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.s, p7/z, z6.s +saddv d0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddv d0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +saddv d0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddv d0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/scvtf.s b/test/MC/AArch64/SVE/scvtf.s index 31dec7e144a4..8089e4a0c21f 100644 --- a/test/MC/AArch64/SVE/scvtf.s +++ b/test/MC/AArch64/SVE/scvtf.s @@ -48,3 +48,31 @@ scvtf z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd6,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 d6 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +scvtf z5.d, p0/m, z0.d +// CHECK-INST: scvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d6 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +scvtf z5.d, p0/m, z0.d +// CHECK-INST: scvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d6 65 <unknown> diff --git a/test/MC/AArch64/SVE/sdiv.s b/test/MC/AArch64/SVE/sdiv.s index 565e9f63cfa8..5b617eb763e5 100644 --- a/test/MC/AArch64/SVE/sdiv.s +++ b/test/MC/AArch64/SVE/sdiv.s @@ -18,3 +18,31 @@ sdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d4 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d4 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d4 04 <unknown> diff --git a/test/MC/AArch64/SVE/sdivr.s b/test/MC/AArch64/SVE/sdivr.s index 02c8a3052c05..b85cecedf30d 100644 --- a/test/MC/AArch64/SVE/sdivr.s +++ b/test/MC/AArch64/SVE/sdivr.s @@ -18,3 +18,31 @@ sdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d6 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d6 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d6 04 <unknown> diff --git a/test/MC/AArch64/SVE/sdot-diagnostics.s b/test/MC/AArch64/SVE/sdot-diagnostics.s index cc22f21aa24d..622e27422991 100644 --- a/test/MC/AArch64/SVE/sdot-diagnostics.s +++ b/test/MC/AArch64/SVE/sdot-diagnostics.s @@ -56,3 +56,19 @@ sdot z0.d, z1.h, z15.h[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: sdot z0.d, z1.h, z15.h[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sdot z0.d, z1.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sdot z0.d, z1.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sdot z0.d, z1.h, z15.h[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sdot z0.d, z1.h, z15.h[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sdot.s b/test/MC/AArch64/SVE/sdot.s index dbc6b3eabc05..a7d7e7ecb6da 100644 --- a/test/MC/AArch64/SVE/sdot.s +++ b/test/MC/AArch64/SVE/sdot.s @@ -30,3 +30,31 @@ sdot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x00,0xff,0x44] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 00 ff 44 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdot z0.d, z1.h, z31.h +// CHECK-INST: sdot z0.d, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x00,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 df 44 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdot z0.d, z1.h, z15.h[1] +// CHECK-INST: sdot z0.d, z1.h, z15.h[1] +// CHECK-ENCODING: [0x20,0x00,0xff,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 ff 44 <unknown> diff --git a/test/MC/AArch64/SVE/sel-diagnostics.s b/test/MC/AArch64/SVE/sel-diagnostics.s new file mode 100644 index 000000000000..760f2327f85a --- /dev/null +++ b/test/MC/AArch64/SVE/sel-diagnostics.s @@ -0,0 +1,17 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z28.b, p7/z, z30.b +sel z28.b, p7, z13.b, z8.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sel z28.b, p7, z13.b, z8.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +sel z23.b, p11, z13.b, z8.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sel z23.b, p11, z13.b, z8.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smax-diagnostics.s b/test/MC/AArch64/SVE/smax-diagnostics.s index ac1c286f26ef..77825e013c35 100644 --- a/test/MC/AArch64/SVE/smax-diagnostics.s +++ b/test/MC/AArch64/SVE/smax-diagnostics.s @@ -14,3 +14,13 @@ smax z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: smax z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smax z31.d, z31.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smax z31.d, z31.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smax.s b/test/MC/AArch64/SVE/smax.s index de0e9e2f5247..1fbcc84110e6 100644 --- a/test/MC/AArch64/SVE/smax.s +++ b/test/MC/AArch64/SVE/smax.s @@ -78,3 +78,43 @@ smax z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc8,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f c8 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +smax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c8 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +smax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c8 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +smax z31.d, z31.d, #127 +// CHECK-INST: smax z31.d, z31.d, #127 +// CHECK-ENCODING: [0xff,0xcf,0xe8,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff cf e8 25 <unknown> diff --git a/test/MC/AArch64/SVE/smaxv-diagnostics.s b/test/MC/AArch64/SVE/smaxv-diagnostics.s index 62936022f44d..7486eb67d13c 100644 --- a/test/MC/AArch64/SVE/smaxv-diagnostics.s +++ b/test/MC/AArch64/SVE/smaxv-diagnostics.s @@ -31,4 +31,19 @@ smaxv v0.2d, p7, z31.d smaxv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: smaxv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +smaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +smaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smin-diagnostics.s b/test/MC/AArch64/SVE/smin-diagnostics.s index efe7855c8315..987650901ea9 100644 --- a/test/MC/AArch64/SVE/smin-diagnostics.s +++ b/test/MC/AArch64/SVE/smin-diagnostics.s @@ -14,3 +14,13 @@ smin z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: smin z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smin z31.d, z31.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smin z31.d, z31.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smin.s b/test/MC/AArch64/SVE/smin.s index dd1676bf582e..da26ac04462f 100644 --- a/test/MC/AArch64/SVE/smin.s +++ b/test/MC/AArch64/SVE/smin.s @@ -78,3 +78,43 @@ smin z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xca,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f ca 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +smin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xca,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f ca 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +smin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xca,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f ca 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +smin z31.d, z31.d, #127 +// CHECK-INST: smin z31.d, z31.d, #127 +// CHECK-ENCODING: [0xff,0xcf,0xea,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff cf ea 25 <unknown> diff --git a/test/MC/AArch64/SVE/sminv-diagnostics.s b/test/MC/AArch64/SVE/sminv-diagnostics.s index 85f55772f89e..5f8a4e011e07 100644 --- a/test/MC/AArch64/SVE/sminv-diagnostics.s +++ b/test/MC/AArch64/SVE/sminv-diagnostics.s @@ -31,4 +31,19 @@ sminv v0.2d, p7, z31.d sminv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: sminv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +sminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smulh.s b/test/MC/AArch64/SVE/smulh.s index 354dfd8c8417..7ef8d80dc786 100644 --- a/test/MC/AArch64/SVE/smulh.s +++ b/test/MC/AArch64/SVE/smulh.s @@ -30,3 +30,31 @@ smulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +smulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d2 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +smulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d2 04 <unknown> diff --git a/test/MC/AArch64/SVE/splice-diagnostics.s b/test/MC/AArch64/SVE/splice-diagnostics.s index dbac7403c4cb..3cd659caad93 100644 --- a/test/MC/AArch64/SVE/splice-diagnostics.s +++ b/test/MC/AArch64/SVE/splice-diagnostics.s @@ -25,3 +25,13 @@ splice z0.b, p8, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: splice z0.b, p8, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z4.d, p7/z, z6.d +splice z4.d, p7, z4.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: splice z4.d, p7, z4.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/splice.s b/test/MC/AArch64/SVE/splice.s index a213b76d5091..719a761f3022 100644 --- a/test/MC/AArch64/SVE/splice.s +++ b/test/MC/AArch64/SVE/splice.s @@ -30,3 +30,19 @@ splice z31.d, p7, z31.d, z31.d // CHECK-ENCODING: [0xff,0x9f,0xec,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f ec 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +splice z4.d, p7, z4.d, z31.d +// CHECK-INST: splice z4.d, p7, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x9f,0xec,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f ec 05 <unknown> diff --git a/test/MC/AArch64/SVE/sqadd-diagnostics.s b/test/MC/AArch64/SVE/sqadd-diagnostics.s index 92672b648a6f..ae07bb69f9be 100644 --- a/test/MC/AArch64/SVE/sqadd-diagnostics.s +++ b/test/MC/AArch64/SVE/sqadd-diagnostics.s @@ -86,3 +86,25 @@ sqadd z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: sqadd z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqadd z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqadd z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqadd.s b/test/MC/AArch64/SVE/sqadd.s index 49abd41a6ade..8f722ea1da48 100644 --- a/test/MC/AArch64/SVE/sqadd.s +++ b/test/MC/AArch64/SVE/sqadd.s @@ -115,3 +115,19 @@ sqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e4 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +sqadd z31.d, z31.d, #65280 +// CHECK-INST: sqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e4 25 <unknown> diff --git a/test/MC/AArch64/SVE/sqdecd-diagnostics.s b/test/MC/AArch64/SVE/sqdecd-diagnostics.s index de2270c07005..658af848c363 100644 --- a/test/MC/AArch64/SVE/sqdecd-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdecd-diagnostics.s @@ -79,3 +79,25 @@ sqdecd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdecd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdecd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdecd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdecd.s b/test/MC/AArch64/SVE/sqdecd.s index c240cc9eab88..107d630cb3e4 100644 --- a/test/MC/AArch64/SVE/sqdecd.s +++ b/test/MC/AArch64/SVE/sqdecd.s @@ -294,3 +294,43 @@ sqdecd x0, #28 // CHECK-ENCODING: [0x80,0xfb,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 fb f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecd z0.d +// CHECK-INST: sqdecd z0.d +// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cb e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecd z0.d, pow2, mul #16 +// CHECK-INST: sqdecd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc8,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecd z0.d, pow2 +// CHECK-INST: sqdecd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xc8,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqdech-diagnostics.s b/test/MC/AArch64/SVE/sqdech-diagnostics.s index dd68b9d08f09..af9268cb6ee2 100644 --- a/test/MC/AArch64/SVE/sqdech-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdech-diagnostics.s @@ -79,3 +79,25 @@ sqdech x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdech x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +sqdech z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdech z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqdech z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdech z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqdech z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdech z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdech.s b/test/MC/AArch64/SVE/sqdech.s index b0e8c8d39386..574316825b18 100644 --- a/test/MC/AArch64/SVE/sqdech.s +++ b/test/MC/AArch64/SVE/sqdech.s @@ -294,3 +294,43 @@ sqdech x0, #28 // CHECK-ENCODING: [0x80,0xfb,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 fb 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdech z0.h +// CHECK-INST: sqdech z0.h +// CHECK-ENCODING: [0xe0,0xcb,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cb 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdech z0.h, pow2, mul #16 +// CHECK-INST: sqdech z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc8,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdech z0.h, pow2 +// CHECK-INST: sqdech z0.h, pow2 +// CHECK-ENCODING: [0x00,0xc8,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqdecp-diagnostics.s b/test/MC/AArch64/SVE/sqdecp-diagnostics.s index f3fca0f17c9f..80579b824210 100644 --- a/test/MC/AArch64/SVE/sqdecp-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdecp-diagnostics.s @@ -51,3 +51,13 @@ sqdecp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: sqdecp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdecp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdecp.s b/test/MC/AArch64/SVE/sqdecp.s index 6b6abac8621f..2a56b182f6bb 100644 --- a/test/MC/AArch64/SVE/sqdecp.s +++ b/test/MC/AArch64/SVE/sqdecp.s @@ -72,3 +72,19 @@ sqdecp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xea,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 ea 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecp z0.d, p0 +// CHECK-INST: sqdecp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xea,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 ea 25 <unknown> diff --git a/test/MC/AArch64/SVE/sqdecw-diagnostics.s b/test/MC/AArch64/SVE/sqdecw-diagnostics.s index f3b11c2732c4..97adc35cf16a 100644 --- a/test/MC/AArch64/SVE/sqdecw-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdecw-diagnostics.s @@ -79,3 +79,25 @@ sqdecw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +sqdecw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqdecw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqdecw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdecw.s b/test/MC/AArch64/SVE/sqdecw.s index ac456f3f8cc0..e48d5999d409 100644 --- a/test/MC/AArch64/SVE/sqdecw.s +++ b/test/MC/AArch64/SVE/sqdecw.s @@ -294,3 +294,43 @@ sqdecw x0, #28 // CHECK-ENCODING: [0x80,0xfb,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 fb b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecw z0.s +// CHECK-INST: sqdecw z0.s +// CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cb a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecw z0.s, pow2, mul #16 +// CHECK-INST: sqdecw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc8,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecw z0.s, pow2 +// CHECK-INST: sqdecw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xc8,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqincd-diagnostics.s b/test/MC/AArch64/SVE/sqincd-diagnostics.s index d2bad3bc6b0c..2e462e6f6dc1 100644 --- a/test/MC/AArch64/SVE/sqincd-diagnostics.s +++ b/test/MC/AArch64/SVE/sqincd-diagnostics.s @@ -79,3 +79,25 @@ sqincd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqincd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqincd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqincd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqincd.s b/test/MC/AArch64/SVE/sqincd.s index f6919ffdc9dd..440e4b708ffc 100644 --- a/test/MC/AArch64/SVE/sqincd.s +++ b/test/MC/AArch64/SVE/sqincd.s @@ -294,3 +294,43 @@ sqincd x0, #28 // CHECK-ENCODING: [0x80,0xf3,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f3 f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincd z0.d +// CHECK-INST: sqincd z0.d +// CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincd z0.d, pow2, mul #16 +// CHECK-INST: sqincd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc0,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincd z0.d, pow2 +// CHECK-INST: sqincd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xc0,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqinch-diagnostics.s b/test/MC/AArch64/SVE/sqinch-diagnostics.s index 3394a814a95a..1f9cb8f8b6b2 100644 --- a/test/MC/AArch64/SVE/sqinch-diagnostics.s +++ b/test/MC/AArch64/SVE/sqinch-diagnostics.s @@ -79,3 +79,25 @@ sqinch x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqinch x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +sqinch z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqinch z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqinch z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqinch z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqinch z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqinch z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqinch.s b/test/MC/AArch64/SVE/sqinch.s index 41bdcb9f15be..6ed6dc4758e0 100644 --- a/test/MC/AArch64/SVE/sqinch.s +++ b/test/MC/AArch64/SVE/sqinch.s @@ -294,3 +294,43 @@ sqinch x0, #28 // CHECK-ENCODING: [0x80,0xf3,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f3 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqinch z0.h +// CHECK-INST: sqinch z0.h +// CHECK-ENCODING: [0xe0,0xc3,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqinch z0.h, pow2, mul #16 +// CHECK-INST: sqinch z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc0,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqinch z0.h, pow2 +// CHECK-INST: sqinch z0.h, pow2 +// CHECK-ENCODING: [0x00,0xc0,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqincp-diagnostics.s b/test/MC/AArch64/SVE/sqincp-diagnostics.s index 8b98e62e220d..9bd8587edb04 100644 --- a/test/MC/AArch64/SVE/sqincp-diagnostics.s +++ b/test/MC/AArch64/SVE/sqincp-diagnostics.s @@ -46,3 +46,13 @@ uqdecp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: uqdecp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqincp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqincp.s b/test/MC/AArch64/SVE/sqincp.s index 6f812947df29..f7d427b0ca6e 100644 --- a/test/MC/AArch64/SVE/sqincp.s +++ b/test/MC/AArch64/SVE/sqincp.s @@ -72,3 +72,19 @@ sqincp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 e8 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincp z0.d, p0 +// CHECK-INST: sqincp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xe8,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 e8 25 <unknown> diff --git a/test/MC/AArch64/SVE/sqincw-diagnostics.s b/test/MC/AArch64/SVE/sqincw-diagnostics.s index 53b726fdacde..b0a380e16016 100644 --- a/test/MC/AArch64/SVE/sqincw-diagnostics.s +++ b/test/MC/AArch64/SVE/sqincw-diagnostics.s @@ -79,3 +79,25 @@ sqincw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +sqincw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqincw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqincw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqincw.s b/test/MC/AArch64/SVE/sqincw.s index 1528c30a3788..7ff2bc6540a7 100644 --- a/test/MC/AArch64/SVE/sqincw.s +++ b/test/MC/AArch64/SVE/sqincw.s @@ -294,3 +294,43 @@ sqincw x0, #28 // CHECK-ENCODING: [0x80,0xf3,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f3 b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincw z0.s +// CHECK-INST: sqincw z0.s +// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincw z0.s, pow2, mul #16 +// CHECK-INST: sqincw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc0,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincw z0.s, pow2 +// CHECK-INST: sqincw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xc0,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqsub-diagnostics.s b/test/MC/AArch64/SVE/sqsub-diagnostics.s index 8155c366c0ab..15633050ebfd 100644 --- a/test/MC/AArch64/SVE/sqsub-diagnostics.s +++ b/test/MC/AArch64/SVE/sqsub-diagnostics.s @@ -86,3 +86,25 @@ sqsub z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: sqsub z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqsub z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqsub z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqsub.s b/test/MC/AArch64/SVE/sqsub.s index ad41b5ae41b6..c91d5fe3d124 100644 --- a/test/MC/AArch64/SVE/sqsub.s +++ b/test/MC/AArch64/SVE/sqsub.s @@ -115,3 +115,19 @@ sqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e6 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +sqsub z31.d, z31.d, #65280 +// CHECK-INST: sqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e6 25 <unknown> diff --git a/test/MC/AArch64/SVE/st1b-diagnostics.s b/test/MC/AArch64/SVE/st1b-diagnostics.s index 99bbc55b072c..25f153c78ce9 100644 --- a/test/MC/AArch64/SVE/st1b-diagnostics.s +++ b/test/MC/AArch64/SVE/st1b-diagnostics.s @@ -175,3 +175,19 @@ st1b z0.d, p0, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: st1b z0.d, p0, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1b { z31.d }, p7, [z31.d, #31] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1b { z31.d }, p7, [z31.d, #31] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st1d-diagnostics.s b/test/MC/AArch64/SVE/st1d-diagnostics.s index f510633983f8..82f52ce56784 100644 --- a/test/MC/AArch64/SVE/st1d-diagnostics.s +++ b/test/MC/AArch64/SVE/st1d-diagnostics.s @@ -131,3 +131,19 @@ st1d z0.d, p0, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK-NEXT: st1d z0.d, p0, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1d { z31.d }, p7, [z31.d, #248] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1d { z31.d }, p7, [z31.d, #248] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st1h-diagnostics.s b/test/MC/AArch64/SVE/st1h-diagnostics.s index b8b8ecdebd8b..e58cd52c7858 100644 --- a/test/MC/AArch64/SVE/st1h-diagnostics.s +++ b/test/MC/AArch64/SVE/st1h-diagnostics.s @@ -189,3 +189,19 @@ st1h z0.d, p0, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: st1h z0.d, p0, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1h { z31.d }, p7, [z31.d, #62] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1h { z31.d }, p7, [z31.d, #62] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st1w-diagnostics.s b/test/MC/AArch64/SVE/st1w-diagnostics.s index 2222b0677566..a5c0f0517ecf 100644 --- a/test/MC/AArch64/SVE/st1w-diagnostics.s +++ b/test/MC/AArch64/SVE/st1w-diagnostics.s @@ -178,3 +178,19 @@ st1w z0.d, p0, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: st1w z0.d, p0, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1w { z31.d }, p7, [z31.d, #124] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1w { z31.d }, p7, [z31.d, #124] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1w { z31.d }, p7, [z31.d, #124] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1w { z31.d }, p7, [z31.d, #124] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2b-diagnostics.s b/test/MC/AArch64/SVE/st2b-diagnostics.s index 07fdd64fe15b..ac30bb47192e 100644 --- a/test/MC/AArch64/SVE/st2b-diagnostics.s +++ b/test/MC/AArch64/SVE/st2b-diagnostics.s @@ -89,3 +89,19 @@ st2b { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2b { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2d-diagnostics.s b/test/MC/AArch64/SVE/st2d-diagnostics.s index e5e09424484f..301849f2ee04 100644 --- a/test/MC/AArch64/SVE/st2d-diagnostics.s +++ b/test/MC/AArch64/SVE/st2d-diagnostics.s @@ -94,3 +94,19 @@ st2d { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2d { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2h-diagnostics.s b/test/MC/AArch64/SVE/st2h-diagnostics.s index 0854ada487e7..b22ae30c09ce 100644 --- a/test/MC/AArch64/SVE/st2h-diagnostics.s +++ b/test/MC/AArch64/SVE/st2h-diagnostics.s @@ -94,3 +94,19 @@ st2h { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2h { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2w-diagnostics.s b/test/MC/AArch64/SVE/st2w-diagnostics.s index 61ca5ec964fc..1e40d0a054cb 100644 --- a/test/MC/AArch64/SVE/st2w-diagnostics.s +++ b/test/MC/AArch64/SVE/st2w-diagnostics.s @@ -94,3 +94,19 @@ st2w { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2w { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3b-diagnostics.s b/test/MC/AArch64/SVE/st3b-diagnostics.s index 65201355482d..43016c0c314a 100644 --- a/test/MC/AArch64/SVE/st3b-diagnostics.s +++ b/test/MC/AArch64/SVE/st3b-diagnostics.s @@ -89,3 +89,19 @@ st3b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3d-diagnostics.s b/test/MC/AArch64/SVE/st3d-diagnostics.s index c9e8591e446c..ad089b2ceffd 100644 --- a/test/MC/AArch64/SVE/st3d-diagnostics.s +++ b/test/MC/AArch64/SVE/st3d-diagnostics.s @@ -94,3 +94,19 @@ st3d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3h-diagnostics.s b/test/MC/AArch64/SVE/st3h-diagnostics.s index f6874294cfcf..aba5215defeb 100644 --- a/test/MC/AArch64/SVE/st3h-diagnostics.s +++ b/test/MC/AArch64/SVE/st3h-diagnostics.s @@ -94,3 +94,19 @@ st3h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3w-diagnostics.s b/test/MC/AArch64/SVE/st3w-diagnostics.s index 9c2bb001049f..2e89901b6e1e 100644 --- a/test/MC/AArch64/SVE/st3w-diagnostics.s +++ b/test/MC/AArch64/SVE/st3w-diagnostics.s @@ -94,3 +94,19 @@ st3w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4b-diagnostics.s b/test/MC/AArch64/SVE/st4b-diagnostics.s index c316c81f03cc..dcd31b78a286 100644 --- a/test/MC/AArch64/SVE/st4b-diagnostics.s +++ b/test/MC/AArch64/SVE/st4b-diagnostics.s @@ -89,3 +89,19 @@ st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4d-diagnostics.s b/test/MC/AArch64/SVE/st4d-diagnostics.s index 87f4225a87c4..e63c0c553b54 100644 --- a/test/MC/AArch64/SVE/st4d-diagnostics.s +++ b/test/MC/AArch64/SVE/st4d-diagnostics.s @@ -95,3 +95,19 @@ st4d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4h-diagnostics.s b/test/MC/AArch64/SVE/st4h-diagnostics.s index e3cecfef0212..8d80eb2248c8 100644 --- a/test/MC/AArch64/SVE/st4h-diagnostics.s +++ b/test/MC/AArch64/SVE/st4h-diagnostics.s @@ -94,3 +94,19 @@ st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4w-diagnostics.s b/test/MC/AArch64/SVE/st4w-diagnostics.s index 46bb2d7d7856..8c3816538b79 100644 --- a/test/MC/AArch64/SVE/st4w-diagnostics.s +++ b/test/MC/AArch64/SVE/st4w-diagnostics.s @@ -94,3 +94,19 @@ st4w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1b-diagnostics.s b/test/MC/AArch64/SVE/stnt1b-diagnostics.s index 8f5a0b222dab..4b7806e5b0e8 100644 --- a/test/MC/AArch64/SVE/stnt1b-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1b-diagnostics.s @@ -64,3 +64,19 @@ stnt1b { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1b { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +stnt1b { z0.b }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.b }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1b { z0.b }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.b }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1d-diagnostics.s b/test/MC/AArch64/SVE/stnt1d-diagnostics.s index 9761ad98cc27..a5cbfe1a9343 100644 --- a/test/MC/AArch64/SVE/stnt1d-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1d-diagnostics.s @@ -64,3 +64,19 @@ stnt1d { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1d { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1h-diagnostics.s b/test/MC/AArch64/SVE/stnt1h-diagnostics.s index cf009b74e493..22fe5cb7dee3 100644 --- a/test/MC/AArch64/SVE/stnt1h-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1h-diagnostics.s @@ -64,3 +64,19 @@ stnt1h { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1h { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1w-diagnostics.s b/test/MC/AArch64/SVE/stnt1w-diagnostics.s index eb38fcac1b4b..339ea25c4488 100644 --- a/test/MC/AArch64/SVE/stnt1w-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1w-diagnostics.s @@ -64,3 +64,19 @@ stnt1w { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1w { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sub-diagnostics.s b/test/MC/AArch64/SVE/sub-diagnostics.s index 4ace1ce7dabb..2bd933735bbd 100644 --- a/test/MC/AArch64/SVE/sub-diagnostics.s +++ b/test/MC/AArch64/SVE/sub-diagnostics.s @@ -144,3 +144,25 @@ sub z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: sub z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sub z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sub z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.s, p0/z, z6.s +sub z31.s, z31.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sub z31.s, z31.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sub z31.s, z31.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sub z31.s, z31.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sub.s b/test/MC/AArch64/SVE/sub.s index dcbef0bf3e5e..8e74cf8cf3f2 100644 --- a/test/MC/AArch64/SVE/sub.s +++ b/test/MC/AArch64/SVE/sub.s @@ -286,3 +286,43 @@ sub z31.d, z31.d, #65280 // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e1 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z23.b, p3/z, z30.b +// CHECK-INST: movprfx z23.b, p3/z, z30.b +// CHECK-ENCODING: [0xd7,0x2f,0x10,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d7 2f 10 04 <unknown> + +sub z23.b, p3/m, z23.b, z13.b +// CHECK-INST: sub z23.b, p3/m, z23.b, z13.b +// CHECK-ENCODING: [0xb7,0x0d,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 0d 01 04 <unknown> + +movprfx z23, z30 +// CHECK-INST: movprfx z23, z30 +// CHECK-ENCODING: [0xd7,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d7 bf 20 04 <unknown> + +sub z23.b, p3/m, z23.b, z13.b +// CHECK-INST: sub z23.b, p3/m, z23.b, z13.b +// CHECK-ENCODING: [0xb7,0x0d,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 0d 01 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +sub z31.d, z31.d, #65280 +// CHECK-INST: sub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe1,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e1 25 <unknown> diff --git a/test/MC/AArch64/SVE/subr-diagnostics.s b/test/MC/AArch64/SVE/subr-diagnostics.s index 847bef6dfa7d..cf259ce17ddf 100644 --- a/test/MC/AArch64/SVE/subr-diagnostics.s +++ b/test/MC/AArch64/SVE/subr-diagnostics.s @@ -138,3 +138,13 @@ subr z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: subr z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +subr z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: subr z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/subr.s b/test/MC/AArch64/SVE/subr.s index 595d275a732b..ec6fa65c9621 100644 --- a/test/MC/AArch64/SVE/subr.s +++ b/test/MC/AArch64/SVE/subr.s @@ -115,3 +115,43 @@ subr z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e3 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +subr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: subr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x00,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 00 c3 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +subr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: subr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x00,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 00 c3 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +subr z31.d, z31.d, #65280 +// CHECK-INST: subr z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe3,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e3 25 <unknown> diff --git a/test/MC/AArch64/SVE/sunpkhi-diagnostics.s b/test/MC/AArch64/SVE/sunpkhi-diagnostics.s index 768ef1236bf4..cbbaee25b9ca 100644 --- a/test/MC/AArch64/SVE/sunpkhi-diagnostics.s +++ b/test/MC/AArch64/SVE/sunpkhi-diagnostics.s @@ -18,3 +18,19 @@ sunpkhi z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: sunpkhi z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sunpklo-diagnostics.s b/test/MC/AArch64/SVE/sunpklo-diagnostics.s index 92de4278e23c..14a5a42e5121 100644 --- a/test/MC/AArch64/SVE/sunpklo-diagnostics.s +++ b/test/MC/AArch64/SVE/sunpklo-diagnostics.s @@ -18,3 +18,19 @@ sunpklo z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: sunpklo z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sxtb.s b/test/MC/AArch64/SVE/sxtb.s index fe8a699e60e1..b9fa8b62c71c 100644 --- a/test/MC/AArch64/SVE/sxtb.s +++ b/test/MC/AArch64/SVE/sxtb.s @@ -42,3 +42,31 @@ sxtb z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sxtb z4.d, p7/m, z31.d +// CHECK-INST: sxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d0 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sxtb z4.d, p7/m, z31.d +// CHECK-INST: sxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sxth.s b/test/MC/AArch64/SVE/sxth.s index 138bfa43c6c9..e422de5dd6af 100644 --- a/test/MC/AArch64/SVE/sxth.s +++ b/test/MC/AArch64/SVE/sxth.s @@ -30,3 +30,31 @@ sxth z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sxth z4.d, p7/m, z31.d +// CHECK-INST: sxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d2 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sxth z4.d, p7/m, z31.d +// CHECK-INST: sxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d2 04 <unknown> diff --git a/test/MC/AArch64/SVE/sxtw.s b/test/MC/AArch64/SVE/sxtw.s index ef7b4e9bafba..96c66cb30472 100644 --- a/test/MC/AArch64/SVE/sxtw.s +++ b/test/MC/AArch64/SVE/sxtw.s @@ -18,3 +18,31 @@ sxtw z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd4,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d4 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sxtw z4.d, p7/m, z31.d +// CHECK-INST: sxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d4 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sxtw z4.d, p7/m, z31.d +// CHECK-INST: sxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d4 04 <unknown> diff --git a/test/MC/AArch64/SVE/tbl-diagnostics.s b/test/MC/AArch64/SVE/tbl-diagnostics.s index 8cb8575bbe81..7314fb49d1b2 100644 --- a/test/MC/AArch64/SVE/tbl-diagnostics.s +++ b/test/MC/AArch64/SVE/tbl-diagnostics.s @@ -9,3 +9,19 @@ tbl { z0.h }, z0.h, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK-NEXT: tbl { z0.h }, z0.h, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +tbl z31.d, { z31.d }, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbl z31.d, { z31.d }, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +tbl z31.d, { z31.d }, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbl z31.d, { z31.d }, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/trn1-diagnostics.s b/test/MC/AArch64/SVE/trn1-diagnostics.s index 9e318c1eacd6..7bd0f19fa5c6 100644 --- a/test/MC/AArch64/SVE/trn1-diagnostics.s +++ b/test/MC/AArch64/SVE/trn1-diagnostics.s @@ -41,3 +41,19 @@ trn1 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: trn1 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +trn1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +trn1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/trn2-diagnostics.s b/test/MC/AArch64/SVE/trn2-diagnostics.s index 48b37bf3a181..4c1e29ed2dae 100644 --- a/test/MC/AArch64/SVE/trn2-diagnostics.s +++ b/test/MC/AArch64/SVE/trn2-diagnostics.s @@ -41,3 +41,19 @@ trn2 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: trn2 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +trn2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +trn2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uabd.s b/test/MC/AArch64/SVE/uabd.s index ae06eb8782f8..0f1a4b382518 100644 --- a/test/MC/AArch64/SVE/uabd.s +++ b/test/MC/AArch64/SVE/uabd.s @@ -30,3 +30,31 @@ uabd z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcd,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f cd 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cd 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cd 04 <unknown> diff --git a/test/MC/AArch64/SVE/uaddv-diagnostics.s b/test/MC/AArch64/SVE/uaddv-diagnostics.s index 11ec959913b5..55ffc6075822 100644 --- a/test/MC/AArch64/SVE/uaddv-diagnostics.s +++ b/test/MC/AArch64/SVE/uaddv-diagnostics.s @@ -26,4 +26,19 @@ uaddv s0, p7, z31.s uaddv d0, p8, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: uaddv d0, p8, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +uaddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uaddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ucvtf.s b/test/MC/AArch64/SVE/ucvtf.s index 6848448a6821..9e5f4f792b14 100644 --- a/test/MC/AArch64/SVE/ucvtf.s +++ b/test/MC/AArch64/SVE/ucvtf.s @@ -48,3 +48,31 @@ ucvtf z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 d7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +ucvtf z5.d, p0/m, z0.d +// CHECK-INST: ucvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d7 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +ucvtf z5.d, p0/m, z0.d +// CHECK-INST: ucvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d7 65 <unknown> diff --git a/test/MC/AArch64/SVE/udiv.s b/test/MC/AArch64/SVE/udiv.s index 7ad8a73cb097..ca528ee6d074 100644 --- a/test/MC/AArch64/SVE/udiv.s +++ b/test/MC/AArch64/SVE/udiv.s @@ -18,3 +18,31 @@ udiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d5 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +udiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d5 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d5 04 <unknown> diff --git a/test/MC/AArch64/SVE/udivr.s b/test/MC/AArch64/SVE/udivr.s index f09b7f49b8c1..45bc391d0ef5 100644 --- a/test/MC/AArch64/SVE/udivr.s +++ b/test/MC/AArch64/SVE/udivr.s @@ -18,3 +18,31 @@ udivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d7 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +udivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d7 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d7 04 <unknown> diff --git a/test/MC/AArch64/SVE/udot-diagnostics.s b/test/MC/AArch64/SVE/udot-diagnostics.s index 08abd77592ec..ecdb036c2706 100644 --- a/test/MC/AArch64/SVE/udot-diagnostics.s +++ b/test/MC/AArch64/SVE/udot-diagnostics.s @@ -56,3 +56,19 @@ udot z0.d, z1.h, z15.h[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: udot z0.d, z1.h, z15.h[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +udot z0.d, z1.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: udot z0.d, z1.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +udot z0.d, z1.h, z15.h[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: udot z0.d, z1.h, z15.h[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/udot.s b/test/MC/AArch64/SVE/udot.s index 0c3a392093c8..c9b441172de2 100644 --- a/test/MC/AArch64/SVE/udot.s +++ b/test/MC/AArch64/SVE/udot.s @@ -30,3 +30,31 @@ udot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x04,0xff,0x44] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 04 ff 44 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udot z0.d, z1.h, z31.h +// CHECK-INST: udot z0.d, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x04,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 df 44 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udot z0.d, z1.h, z15.h[1] +// CHECK-INST: udot z0.d, z1.h, z15.h[1] +// CHECK-ENCODING: [0x20,0x04,0xff,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 ff 44 <unknown> diff --git a/test/MC/AArch64/SVE/umax-diagnostics.s b/test/MC/AArch64/SVE/umax-diagnostics.s index f1e9e3916fba..628b8b2a7e5d 100644 --- a/test/MC/AArch64/SVE/umax-diagnostics.s +++ b/test/MC/AArch64/SVE/umax-diagnostics.s @@ -14,3 +14,13 @@ umax z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: umax z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +umax z31.b, z31.b, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umax z31.b, z31.b, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umax.s b/test/MC/AArch64/SVE/umax.s index ac774ec96b1f..bd89da13241b 100644 --- a/test/MC/AArch64/SVE/umax.s +++ b/test/MC/AArch64/SVE/umax.s @@ -78,3 +78,43 @@ umax z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc9,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f c9 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +umax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c9 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +umax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c9 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +umax z31.b, z31.b, #255 +// CHECK-INST: umax z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x29,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 29 25 <unknown> diff --git a/test/MC/AArch64/SVE/umaxv-diagnostics.s b/test/MC/AArch64/SVE/umaxv-diagnostics.s index cfcabb9a8b2c..36512f7568db 100644 --- a/test/MC/AArch64/SVE/umaxv-diagnostics.s +++ b/test/MC/AArch64/SVE/umaxv-diagnostics.s @@ -31,4 +31,19 @@ umaxv v0.2d, p7, z31.d umaxv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: umaxv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +umaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +umaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umin-diagnostics.s b/test/MC/AArch64/SVE/umin-diagnostics.s index 03c708b14620..ce60edf4557e 100644 --- a/test/MC/AArch64/SVE/umin-diagnostics.s +++ b/test/MC/AArch64/SVE/umin-diagnostics.s @@ -14,3 +14,13 @@ umin z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: umin z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +umin z31.b, z31.b, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umin z31.b, z31.b, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umin.s b/test/MC/AArch64/SVE/umin.s index bd142c4e2c17..9aac3092df21 100644 --- a/test/MC/AArch64/SVE/umin.s +++ b/test/MC/AArch64/SVE/umin.s @@ -78,3 +78,43 @@ umin z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcb,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f cb 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +umin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cb 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +umin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cb 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +umin z31.b, z31.b, #255 +// CHECK-INST: umin z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x2b,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 2b 25 <unknown> diff --git a/test/MC/AArch64/SVE/uminv-diagnostics.s b/test/MC/AArch64/SVE/uminv-diagnostics.s index 9208dc9a11f4..f6898352a93a 100644 --- a/test/MC/AArch64/SVE/uminv-diagnostics.s +++ b/test/MC/AArch64/SVE/uminv-diagnostics.s @@ -31,4 +31,19 @@ uminv v0.2d, p7, z31.d uminv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: uminv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +uminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umulh.s b/test/MC/AArch64/SVE/umulh.s index 523428335edd..a5d6eb58603a 100644 --- a/test/MC/AArch64/SVE/umulh.s +++ b/test/MC/AArch64/SVE/umulh.s @@ -30,3 +30,31 @@ umulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d3 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +umulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d3 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +umulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d3 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqadd-diagnostics.s b/test/MC/AArch64/SVE/uqadd-diagnostics.s index 1a6179a14ca5..7dcdba98ccc4 100644 --- a/test/MC/AArch64/SVE/uqadd-diagnostics.s +++ b/test/MC/AArch64/SVE/uqadd-diagnostics.s @@ -86,3 +86,25 @@ uqadd z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: uqadd z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uqadd z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqadd z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +uqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqadd.s b/test/MC/AArch64/SVE/uqadd.s index fc152297c39c..23e213ac85f9 100644 --- a/test/MC/AArch64/SVE/uqadd.s +++ b/test/MC/AArch64/SVE/uqadd.s @@ -115,3 +115,19 @@ uqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e5 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +uqadd z31.d, z31.d, #65280 +// CHECK-INST: uqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e5 25 <unknown> diff --git a/test/MC/AArch64/SVE/uqdecd-diagnostics.s b/test/MC/AArch64/SVE/uqdecd-diagnostics.s index 8f3ce3e6e4fd..fcf40770cb36 100644 --- a/test/MC/AArch64/SVE/uqdecd-diagnostics.s +++ b/test/MC/AArch64/SVE/uqdecd-diagnostics.s @@ -79,3 +79,25 @@ uqdecd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqdecd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqdecd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqdecd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdecd.s b/test/MC/AArch64/SVE/uqdecd.s index 65183428ed5c..f47d0d412990 100644 --- a/test/MC/AArch64/SVE/uqdecd.s +++ b/test/MC/AArch64/SVE/uqdecd.s @@ -294,3 +294,43 @@ uqdecd x0, #28 // CHECK-ENCODING: [0x80,0xff,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 ff f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecd z0.d +// CHECK-INST: uqdecd z0.d +// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cf e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecd z0.d, pow2, mul #16 +// CHECK-INST: uqdecd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xcc,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecd z0.d, pow2 +// CHECK-INST: uqdecd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xcc,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqdech-diagnostics.s b/test/MC/AArch64/SVE/uqdech-diagnostics.s index 936c486599c4..a4e0a24c9d76 100644 --- a/test/MC/AArch64/SVE/uqdech-diagnostics.s +++ b/test/MC/AArch64/SVE/uqdech-diagnostics.s @@ -79,3 +79,25 @@ uqdech x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdech x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +uqdech z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdech z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqdech z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdech z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqdech z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdech z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdech.s b/test/MC/AArch64/SVE/uqdech.s index 950409133e0d..9a1ff5256040 100644 --- a/test/MC/AArch64/SVE/uqdech.s +++ b/test/MC/AArch64/SVE/uqdech.s @@ -294,3 +294,43 @@ uqdech x0, #28 // CHECK-ENCODING: [0x80,0xff,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 ff 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdech z0.h +// CHECK-INST: uqdech z0.h +// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cf 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdech z0.h, pow2, mul #16 +// CHECK-INST: uqdech z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xcc,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdech z0.h, pow2 +// CHECK-INST: uqdech z0.h, pow2 +// CHECK-ENCODING: [0x00,0xcc,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqdecp-diagnostics.s b/test/MC/AArch64/SVE/uqdecp-diagnostics.s new file mode 100644 index 000000000000..8fd345b46ee5 --- /dev/null +++ b/test/MC/AArch64/SVE/uqdecp-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqdecp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdecp.s b/test/MC/AArch64/SVE/uqdecp.s index 4f9a7af45d55..3c07a7da2462 100644 --- a/test/MC/AArch64/SVE/uqdecp.s +++ b/test/MC/AArch64/SVE/uqdecp.s @@ -72,3 +72,19 @@ uqdecp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 eb 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecp z0.d, p0 +// CHECK-INST: uqdecp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xeb,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 eb 25 <unknown> diff --git a/test/MC/AArch64/SVE/uqdecw-diagnostics.s b/test/MC/AArch64/SVE/uqdecw-diagnostics.s index b46373915c31..a7a955e64108 100644 --- a/test/MC/AArch64/SVE/uqdecw-diagnostics.s +++ b/test/MC/AArch64/SVE/uqdecw-diagnostics.s @@ -79,3 +79,25 @@ uqdecw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +uqdecw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqdecw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqdecw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdecw.s b/test/MC/AArch64/SVE/uqdecw.s index 44e96f31b98a..6ed544d5733f 100644 --- a/test/MC/AArch64/SVE/uqdecw.s +++ b/test/MC/AArch64/SVE/uqdecw.s @@ -294,3 +294,43 @@ uqdecw x0, #28 // CHECK-ENCODING: [0x80,0xff,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 ff b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecw z0.s +// CHECK-INST: uqdecw z0.s +// CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cf a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecw z0.s, pow2, mul #16 +// CHECK-INST: uqdecw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xcc,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecw z0.s, pow2 +// CHECK-INST: uqdecw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xcc,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqincd-diagnostics.s b/test/MC/AArch64/SVE/uqincd-diagnostics.s index cb662cfa8f1f..1c6dfa11965f 100644 --- a/test/MC/AArch64/SVE/uqincd-diagnostics.s +++ b/test/MC/AArch64/SVE/uqincd-diagnostics.s @@ -79,3 +79,25 @@ uqincd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqincd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqincd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqincd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqincd.s b/test/MC/AArch64/SVE/uqincd.s index 48890f965db9..d72672ced424 100644 --- a/test/MC/AArch64/SVE/uqincd.s +++ b/test/MC/AArch64/SVE/uqincd.s @@ -294,3 +294,43 @@ uqincd x0, #28 // CHECK-ENCODING: [0x80,0xf7,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f7 f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincd z0.d +// CHECK-INST: uqincd z0.d +// CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincd z0.d, pow2, mul #16 +// CHECK-INST: uqincd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc4,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincd z0.d, pow2 +// CHECK-INST: uqincd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xc4,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqinch-diagnostics.s b/test/MC/AArch64/SVE/uqinch-diagnostics.s index 200d79630607..fc694c4e93de 100644 --- a/test/MC/AArch64/SVE/uqinch-diagnostics.s +++ b/test/MC/AArch64/SVE/uqinch-diagnostics.s @@ -79,3 +79,25 @@ uqinch x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqinch x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +uqinch z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqinch z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqinch z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqinch z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqinch z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqinch z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqinch.s b/test/MC/AArch64/SVE/uqinch.s index 7a471d41d49a..03c7fb7fe9a8 100644 --- a/test/MC/AArch64/SVE/uqinch.s +++ b/test/MC/AArch64/SVE/uqinch.s @@ -296,3 +296,43 @@ uqinch x0, #28 // CHECK-ENCODING: [0x80,0xf7,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f7 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqinch z0.h +// CHECK-INST: uqinch z0.h +// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqinch z0.h, pow2, mul #16 +// CHECK-INST: uqinch z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc4,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqinch z0.h, pow2 +// CHECK-INST: uqinch z0.h, pow2 +// CHECK-ENCODING: [0x00,0xc4,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqincp-diagnostics.s b/test/MC/AArch64/SVE/uqincp-diagnostics.s index 8a4aa25ac413..d5cf76014df5 100644 --- a/test/MC/AArch64/SVE/uqincp-diagnostics.s +++ b/test/MC/AArch64/SVE/uqincp-diagnostics.s @@ -46,3 +46,13 @@ uqincp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: uqincp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqincp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqincp.s b/test/MC/AArch64/SVE/uqincp.s index e7c87efa4e06..a4fb8199d994 100644 --- a/test/MC/AArch64/SVE/uqincp.s +++ b/test/MC/AArch64/SVE/uqincp.s @@ -72,3 +72,19 @@ uqincp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 e9 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincp z0.d, p0 +// CHECK-INST: uqincp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xe9,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 e9 25 <unknown> diff --git a/test/MC/AArch64/SVE/uqincw-diagnostics.s b/test/MC/AArch64/SVE/uqincw-diagnostics.s index c5a632bc88cf..0ad3624230b7 100644 --- a/test/MC/AArch64/SVE/uqincw-diagnostics.s +++ b/test/MC/AArch64/SVE/uqincw-diagnostics.s @@ -79,3 +79,25 @@ uqincw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +uqincw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqincw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqincw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqincw.s b/test/MC/AArch64/SVE/uqincw.s index 097b26f40afe..1944d69625e5 100644 --- a/test/MC/AArch64/SVE/uqincw.s +++ b/test/MC/AArch64/SVE/uqincw.s @@ -294,3 +294,43 @@ uqincw x0, #28 // CHECK-ENCODING: [0x80,0xf7,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f7 b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincw z0.s +// CHECK-INST: uqincw z0.s +// CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincw z0.s, pow2, mul #16 +// CHECK-INST: uqincw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc4,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincw z0.s, pow2 +// CHECK-INST: uqincw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xc4,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqsub-diagnostics.s b/test/MC/AArch64/SVE/uqsub-diagnostics.s index 566334ceea8d..5f8129aa773e 100644 --- a/test/MC/AArch64/SVE/uqsub-diagnostics.s +++ b/test/MC/AArch64/SVE/uqsub-diagnostics.s @@ -86,3 +86,25 @@ uqsub z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: uqsub z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uqsub z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqsub z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +uqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqsub.s b/test/MC/AArch64/SVE/uqsub.s index 4fb90cae9ee7..5bcc10f8b2ea 100644 --- a/test/MC/AArch64/SVE/uqsub.s +++ b/test/MC/AArch64/SVE/uqsub.s @@ -115,3 +115,19 @@ uqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e7 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +uqsub z31.d, z31.d, #65280 +// CHECK-INST: uqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e7 25 <unknown> diff --git a/test/MC/AArch64/SVE/uunpkhi-diagnostics.s b/test/MC/AArch64/SVE/uunpkhi-diagnostics.s index bdae37a32ae3..00adfb86fe42 100644 --- a/test/MC/AArch64/SVE/uunpkhi-diagnostics.s +++ b/test/MC/AArch64/SVE/uunpkhi-diagnostics.s @@ -18,3 +18,19 @@ uunpkhi z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: uunpkhi z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uunpklo-diagnostics.s b/test/MC/AArch64/SVE/uunpklo-diagnostics.s index 00f8a72fbc24..ae4a810fbea7 100644 --- a/test/MC/AArch64/SVE/uunpklo-diagnostics.s +++ b/test/MC/AArch64/SVE/uunpklo-diagnostics.s @@ -18,3 +18,19 @@ uunpklo z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: uunpklo z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uxtb.s b/test/MC/AArch64/SVE/uxtb.s index 5c1e01620e98..81d7dc01e02a 100644 --- a/test/MC/AArch64/SVE/uxtb.s +++ b/test/MC/AArch64/SVE/uxtb.s @@ -42,3 +42,31 @@ uxtb z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd1,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d1 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uxtb z4.d, p7/m, z31.d +// CHECK-INST: uxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d1 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uxtb z4.d, p7/m, z31.d +// CHECK-INST: uxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d1 04 <unknown> diff --git a/test/MC/AArch64/SVE/uxth.s b/test/MC/AArch64/SVE/uxth.s index 9244fa8c960b..10074b409429 100644 --- a/test/MC/AArch64/SVE/uxth.s +++ b/test/MC/AArch64/SVE/uxth.s @@ -30,3 +30,31 @@ uxth z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd3,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d3 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uxth z4.d, p7/m, z31.d +// CHECK-INST: uxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d3 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uxth z4.d, p7/m, z31.d +// CHECK-INST: uxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d3 04 <unknown> diff --git a/test/MC/AArch64/SVE/uxtw.s b/test/MC/AArch64/SVE/uxtw.s index e2dbdbcb0b3f..c72fedf31de3 100644 --- a/test/MC/AArch64/SVE/uxtw.s +++ b/test/MC/AArch64/SVE/uxtw.s @@ -18,3 +18,31 @@ uxtw z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd5,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d5 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uxtw z4.d, p7/m, z31.d +// CHECK-INST: uxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d5 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uxtw z4.d, p7/m, z31.d +// CHECK-INST: uxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d5 04 <unknown> diff --git a/test/MC/AArch64/SVE/uzp1-diagnostics.s b/test/MC/AArch64/SVE/uzp1-diagnostics.s index 3842d60a2916..98f0997527c1 100644 --- a/test/MC/AArch64/SVE/uzp1-diagnostics.s +++ b/test/MC/AArch64/SVE/uzp1-diagnostics.s @@ -41,3 +41,19 @@ uzp1 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: uzp1 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uzp1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uzp1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uzp2-diagnostics.s b/test/MC/AArch64/SVE/uzp2-diagnostics.s index ecb8b33ccba2..a53cfe4aa87c 100644 --- a/test/MC/AArch64/SVE/uzp2-diagnostics.s +++ b/test/MC/AArch64/SVE/uzp2-diagnostics.s @@ -41,3 +41,19 @@ uzp2 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: uzp2 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uzp2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uzp2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilele-diagnostics.s b/test/MC/AArch64/SVE/whilele-diagnostics.s new file mode 100644 index 000000000000..94e3993645df --- /dev/null +++ b/test/MC/AArch64/SVE/whilele-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilele p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilele p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilele p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilele p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilele p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilele p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilele.s b/test/MC/AArch64/SVE/whilele.s new file mode 100644 index 000000000000..e8c48a6e926f --- /dev/null +++ b/test/MC/AArch64/SVE/whilele.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilele p15.b, xzr, x0 +// CHECK-INST: whilele p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x17,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 17 20 25 <unknown> + +whilele p15.b, x0, xzr +// CHECK-INST: whilele p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 3f 25 <unknown> + +whilele p15.b, wzr, w0 +// CHECK-INST: whilele p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x07,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 07 20 25 <unknown> + +whilele p15.b, w0, wzr +// CHECK-INST: whilele p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 3f 25 <unknown> + +whilele p15.h, x0, xzr +// CHECK-INST: whilele p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 7f 25 <unknown> + +whilele p15.h, w0, wzr +// CHECK-INST: whilele p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 7f 25 <unknown> + +whilele p15.s, x0, xzr +// CHECK-INST: whilele p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 bf 25 <unknown> + +whilele p15.s, w0, wzr +// CHECK-INST: whilele p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 bf 25 <unknown> + +whilele p15.d, w0, wzr +// CHECK-INST: whilele p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 ff 25 <unknown> + +whilele p15.d, x0, xzr +// CHECK-INST: whilele p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/whilelo-diagnostics.s b/test/MC/AArch64/SVE/whilelo-diagnostics.s new file mode 100644 index 000000000000..6237a1182d01 --- /dev/null +++ b/test/MC/AArch64/SVE/whilelo-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilelo p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelo p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelo p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelo p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelo p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelo p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilelo.s b/test/MC/AArch64/SVE/whilelo.s new file mode 100644 index 000000000000..30fa35dcd2cf --- /dev/null +++ b/test/MC/AArch64/SVE/whilelo.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilelo p15.b, xzr, x0 +// CHECK-INST: whilelo p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x1f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 1f 20 25 <unknown> + +whilelo p15.b, x0, xzr +// CHECK-INST: whilelo p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c 3f 25 <unknown> + +whilelo p15.b, wzr, w0 +// CHECK-INST: whilelo p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x0f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 0f 20 25 <unknown> + +whilelo p15.b, w0, wzr +// CHECK-INST: whilelo p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c 3f 25 <unknown> + +whilelo p15.h, x0, xzr +// CHECK-INST: whilelo p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c 7f 25 <unknown> + +whilelo p15.h, w0, wzr +// CHECK-INST: whilelo p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c 7f 25 <unknown> + +whilelo p15.s, x0, xzr +// CHECK-INST: whilelo p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c bf 25 <unknown> + +whilelo p15.s, w0, wzr +// CHECK-INST: whilelo p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c bf 25 <unknown> + +whilelo p15.d, w0, wzr +// CHECK-INST: whilelo p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c ff 25 <unknown> + +whilelo p15.d, x0, xzr +// CHECK-INST: whilelo p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/whilels-diagnostics.s b/test/MC/AArch64/SVE/whilels-diagnostics.s new file mode 100644 index 000000000000..6a422900a071 --- /dev/null +++ b/test/MC/AArch64/SVE/whilels-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilels p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilels p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilels p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilels p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilels p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilels p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilels.s b/test/MC/AArch64/SVE/whilels.s new file mode 100644 index 000000000000..3e127d3e1720 --- /dev/null +++ b/test/MC/AArch64/SVE/whilels.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilels p15.b, xzr, x0 +// CHECK-INST: whilels p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x1f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 20 25 <unknown> + +whilels p15.b, x0, xzr +// CHECK-INST: whilels p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c 3f 25 <unknown> + +whilels p15.b, wzr, w0 +// CHECK-INST: whilels p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x0f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 0f 20 25 <unknown> + +whilels p15.b, w0, wzr +// CHECK-INST: whilels p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c 3f 25 <unknown> + +whilels p15.h, x0, xzr +// CHECK-INST: whilels p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c 7f 25 <unknown> + +whilels p15.h, w0, wzr +// CHECK-INST: whilels p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c 7f 25 <unknown> + +whilels p15.s, x0, xzr +// CHECK-INST: whilels p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c bf 25 <unknown> + +whilels p15.s, w0, wzr +// CHECK-INST: whilels p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c bf 25 <unknown> + +whilels p15.d, w0, wzr +// CHECK-INST: whilels p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c ff 25 <unknown> + +whilels p15.d, x0, xzr +// CHECK-INST: whilels p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/whilelt-diagnostics.s b/test/MC/AArch64/SVE/whilelt-diagnostics.s new file mode 100644 index 000000000000..1c3a8f8f46ec --- /dev/null +++ b/test/MC/AArch64/SVE/whilelt-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilelt p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelt p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelt p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelt p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelt p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelt p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilelt.s b/test/MC/AArch64/SVE/whilelt.s new file mode 100644 index 000000000000..9a0723cdc7c9 --- /dev/null +++ b/test/MC/AArch64/SVE/whilelt.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilelt p15.b, xzr, x0 +// CHECK-INST: whilelt p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x17,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 17 20 25 <unknown> + +whilelt p15.b, x0, xzr +// CHECK-INST: whilelt p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 3f 25 <unknown> + +whilelt p15.b, wzr, w0 +// CHECK-INST: whilelt p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x07,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 07 20 25 <unknown> + +whilelt p15.b, w0, wzr +// CHECK-INST: whilelt p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 3f 25 <unknown> + +whilelt p15.h, x0, xzr +// CHECK-INST: whilelt p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 7f 25 <unknown> + +whilelt p15.h, w0, wzr +// CHECK-INST: whilelt p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 7f 25 <unknown> + +whilelt p15.s, x0, xzr +// CHECK-INST: whilelt p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 bf 25 <unknown> + +whilelt p15.s, w0, wzr +// CHECK-INST: whilelt p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 bf 25 <unknown> + +whilelt p15.d, w0, wzr +// CHECK-INST: whilelt p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 ff 25 <unknown> + +whilelt p15.d, x0, xzr +// CHECK-INST: whilelt p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/zip1-diagnostics.s b/test/MC/AArch64/SVE/zip1-diagnostics.s index 17670be5de22..a0652e3880fd 100644 --- a/test/MC/AArch64/SVE/zip1-diagnostics.s +++ b/test/MC/AArch64/SVE/zip1-diagnostics.s @@ -41,3 +41,19 @@ zip1 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip1 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +zip1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +zip1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/zip2-diagnostics.s b/test/MC/AArch64/SVE/zip2-diagnostics.s index 3a78b9432fd7..7691bafb538d 100644 --- a/test/MC/AArch64/SVE/zip2-diagnostics.s +++ b/test/MC/AArch64/SVE/zip2-diagnostics.s @@ -41,3 +41,19 @@ zip2 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip2 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +zip2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +zip2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |