diff options
Diffstat (limited to 'test/MC/ARM')
40 files changed, 1045 insertions, 180 deletions
diff --git a/test/MC/ARM/Windows/invalid-relocation.s b/test/MC/ARM/Windows/invalid-relocation.s index 4f4c59839a6a..c3e74e97634b 100644 --- a/test/MC/ARM/Windows/invalid-relocation.s +++ b/test/MC/ARM/Windows/invalid-relocation.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple thumbv7-windows -filetype obj -o /dev/null 2>&1 %s \ +# RUN: not llvm-mc -triple thumbv7-windows -incremental-linker-compatible -filetype obj -o /dev/null 2>&1 %s \ # RUN: | FileCheck %s .def invalid_relocation diff --git a/test/MC/ARM/arm-elf-relocation-diagnostics.s b/test/MC/ARM/arm-elf-relocation-diagnostics.s index 5fe903f71619..6875d03b303e 100644 --- a/test/MC/ARM/arm-elf-relocation-diagnostics.s +++ b/test/MC/ARM/arm-elf-relocation-diagnostics.s @@ -8,20 +8,19 @@ @ CHECK: .byte target(sbrel) @ CHECK: ^ -@ TODO: enable these negative test cases -@ .hword target(sbrel) -@ @ CHECK-SBREL-HWORD: error: relocated expression must be 32-bit -@ @ CHECK-SBREL-HWORD: .hword target(sbrel) -@ @ CHECK-SBREL-HWORD: ^ -@ -@ .short target(sbrel) -@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit -@ @ CHECK-SBREL-SHORT: .short target(sbrel) -@ @ CHECK-SBREL-SHORT: ^ -@ -@ .quad target(sbrel) -@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit -@ @ CHECK-SBREL-SHORT: .quad target(sbrel) -@ @ CHECK-SBREL-SHORT: ^ + .hword target(sbrel) +@ CHECK: error: relocated expression must be 32-bit +@ CHECK: .hword target(sbrel) +@ CHECK: ^ + + .short target(sbrel) +@ CHECK: error: relocated expression must be 32-bit +@ CHECK: .short target(sbrel) +@ CHECK: ^ + + .quad target(sbrel) +@ CHECK: error: relocated expression must be 32-bit +@ CHECK: .quad target(sbrel) +@ CHECK: ^ diff --git a/test/MC/ARM/arm-thumb-trustzone.s b/test/MC/ARM/arm-thumb-trustzone.s index 7755a3c8e69b..4fec4b7e982c 100644 --- a/test/MC/ARM/arm-thumb-trustzone.s +++ b/test/MC/ARM/arm-thumb-trustzone.s @@ -1,5 +1,6 @@ @ RUN: not llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ @ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ +@ RUN: not llvm-mc -triple=thumbv6kz -mcpu=arm1176jzf-s -show-encoding < %s | FileCheck %s -check-prefix=NOTZ .syntax unified .globl _func diff --git a/test/MC/ARM/arm-trustzone.s b/test/MC/ARM/arm-trustzone.s index 72bac48e84e4..5ab27b58dfe1 100644 --- a/test/MC/ARM/arm-trustzone.s +++ b/test/MC/ARM/arm-trustzone.s @@ -1,5 +1,6 @@ @ RUN: not llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ @ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ +@ RUN: llvm-mc -triple=armv6kz -mcpu=arm1176jz-s -show-encoding < %s | FileCheck %s -check-prefix=TZ .syntax unified .globl _func @@ -14,7 +15,7 @@ _func: @------------------------------------------------------------------------------ @ SMC @------------------------------------------------------------------------------ - smc #0xf + smi #0xf @ SMI is old (ARMv6KZ) name for SMC smceq #0 @ NOTZ-NOT: smc #15 diff --git a/test/MC/ARM/arm11-hint-instr.s b/test/MC/ARM/arm11-hint-instr.s index 6f5a374e417c..2c0fef4adf73 100644 --- a/test/MC/ARM/arm11-hint-instr.s +++ b/test/MC/ARM/arm11-hint-instr.s @@ -5,21 +5,24 @@ @ RUN: | FileCheck --check-prefix=CHECK-ARM %s @ RUN: llvm-mc -triple=armv6t2 -show-encoding < %s \ @ RUN: | FileCheck --check-prefix=CHECK-ARM %s -@ RUN: llvm-mc -triple=thumb -mcpu=arm1156t2-s -show-encoding < %s \ -@ RUN: | FileCheck --check-prefix=CHECK-THUMB %s -@ RUN: llvm-mc -triple=armv6m -show-encoding < %s \ -@ RUN: | FileCheck --check-prefix=CHECK-V6M %s +@ RUN: not llvm-mc -triple=thumb -mcpu=arm1156t2-s -show-encoding < %s > %t3 2> %t4 +@ RUN: FileCheck --check-prefix=CHECK-THUMB %s < %t3 +@ RUN: FileCheck --check-prefix=CHECK-ERROR-THUMB %s < %t4 +@ RUN: not llvm-mc -triple=armv6m -show-encoding < %s > %t5 2> %t6 +@ RUN: FileCheck --check-prefix=CHECK-V6M %s < %t5 +@ RUN: FileCheck --check-prefix=CHECK-ERROR-V6M %s < %t6 .syntax unified @------------------------------------------------------------------------------ -@ YIELD/WFE/WFI/SEV - are not supported pre v6K +@ YIELD/WFE/WFI/SEV/CLREX - are not supported pre v6K @------------------------------------------------------------------------------ nop yield wfe wfi sev + clrex @------------------------------------------------------------------------------ @@ -37,6 +40,9 @@ @ CHECK-ERROR-V6: error: instruction requires: armv6k @ CHECK-ERROR-V6: sev @ CHECK-ERROR-V6: ^ +@ CHECK-ERROR-V6: error: instruction requires: armv6k +@ CHECK-ERROR-V6: clrex +@ CHECK-ERROR-V6: ^ @------------------------------------------------------------------------------ @ v6K using ARM encoding @@ -49,6 +55,7 @@ @ CHECK-ARM: wfe @ encoding: [0x02,0xf0,0x20,0xe3] @ CHECK-ARM: wfi @ encoding: [0x03,0xf0,0x20,0xe3] @ CHECK-ARM: sev @ encoding: [0x04,0xf0,0x20,0xe3] +@ CHECK-ARM: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5] @------------------------------------------------------------------------------ @ v6T2 using THUMB encoding (thumb triple) @@ -58,6 +65,9 @@ @ CHECK-THUMB: wfe @ encoding: [0x20,0xbf] @ CHECK-THUMB: wfi @ encoding: [0x30,0xbf] @ CHECK-THUMB: sev @ encoding: [0x40,0xbf] +@ CHECK-ERROR-THUMB: error: instruction requires: armv7 +@ CHECK-ERROR-THUMB: clrex +@ CHECK-ERROR-THUMB: ^ @------------------------------------------------------------------------------ @ v6M using THUMB encoding @@ -67,3 +77,6 @@ @ CHECK-V6M: wfe @ encoding: [0x20,0xbf] @ CHECK-V6M: wfi @ encoding: [0x30,0xbf] @ CHECK-V6M: sev @ encoding: [0x40,0xbf] +@ CHECK-ERROR-V6M: error: instruction requires: armv7 +@ CHECK-ERROR-V6M: clrex +@ CHECK-ERROR-V6M: ^ diff --git a/test/MC/ARM/basic-arm-instructions-v8.1a.s b/test/MC/ARM/basic-arm-instructions-v8.1a.s index 005f27bb3983..9b764c18448a 100644 --- a/test/MC/ARM/basic-arm-instructions-v8.1a.s +++ b/test/MC/ARM/basic-arm-instructions-v8.1a.s @@ -37,7 +37,7 @@ //CHECK-V8: vqrdmlsh.f32 q3, q4, q5 //CHECK-V8: ^ //CHECK-V8: error: invalid operand for instruction -//CHECK-V8 vqrdmlsh.f64 d3, d5, d5 +//CHECK-V8: vqrdmlsh.f64 d3, d5, d5 //CHECK-V8: ^ vqrdmlah.s16 d0, d1, d2 diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index a1f13b76dda3..99a3cfa7b29e 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -349,6 +349,8 @@ Lforward: and r6, r7, r8, ror r2 and r10, r1, r6, rrx and r2, r3, #0x7fffffff + and sp, sp, #0x7fffffff + and pc, pc, #0x7fffffff @ destination register is optional and r1, #0xf @@ -397,6 +399,8 @@ Lforward: @ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0] @ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0] @ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3] +@ CHECK: bic sp, sp, #-2147483648 @ encoding: [0x02,0xd1,0xcd,0xe3] +@ CHECK: bic pc, pc, #-2147483648 @ encoding: [0x02,0xf1,0xcf,0xe3] @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] @@ -502,6 +506,10 @@ Lforward: bic r6, r7, r8, asr r2 bic r6, r7, r8, ror r2 bic r10, r1, r6, rrx + bic r2, r3, #0x7fffffff + bic sp, sp, #0x7fffffff + bic pc, pc, #0x7fffffff + @ destination register is optional bic r1, #0xf @@ -548,6 +556,9 @@ Lforward: @ CHECK: bic r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0xc7,0xe1] @ CHECK: bic r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0xc7,0xe1] @ CHECK: bic r10, r1, r6, rrx @ encoding: [0x66,0xa0,0xc1,0xe1] +@ CHECK: and r2, r3, #-2147483648 @ encoding: [0x02,0x21,0x03,0xe2] +@ CHECK: and sp, sp, #-2147483648 @ encoding: [0x02,0xd1,0x0d,0xe2] +@ CHECK: and pc, pc, #-2147483648 @ encoding: [0x02,0xf1,0x0f,0xe2] @ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] diff --git a/test/MC/ARM/basic-thumb2-instructions-v8.s b/test/MC/ARM/basic-thumb2-instructions-v8.s index a7882aead01f..46bc1b91ffa5 100644 --- a/test/MC/ARM/basic-thumb2-instructions-v8.s +++ b/test/MC/ARM/basic-thumb2-instructions-v8.s @@ -3,7 +3,7 @@ @ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8 @ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7 -@ HLT +@ HLT (in ARMv8 only) hlt #0 hlt #63 @ CHECK-V8: hlt #0 @ encoding: [0x80,0xba] @@ -19,12 +19,23 @@ @ CHECK-V8: hlt #24 @ encoding: [0x98,0xba] @ CHECK-V7: error: instruction requires: armv8 -@ Can accept AL condition code +@ Can accept AL condition code (in ARMv8 only) hltal #24 @ CHECK-V8: hlt #24 @ encoding: [0x98,0xba] @ CHECK-V7: error: instruction requires: armv8 -@ DCPS{1,2,3} +@ Can accept SP as rGPR (in ARMv8 only) + sbc.w r6, r3, sp, asr #16 + and.w r6, r3, sp, asr #16 + and sp, r0, #0 +@ CHECK-V8: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46] +@ CHECK-V8: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46] +@ CHECK-V8: and sp, r0, #0 @ encoding: [0x00,0xf0,0x00,0x0d] +@ CHECK-V7: error: instruction variant requires ARMv8 or later +@ CHECK-V7: error: instruction variant requires ARMv8 or later +@ CHECK-V7: error: invalid operand for instruction + +@ DCPS{1,2,3} (in ARMv8 only) dcps1 dcps2 dcps3 @@ -36,7 +47,7 @@ @ CHECK-V7: error: instruction requires: armv8 @------------------------------------------------------------------------------ -@ DMB (v8 barriers) +@ DMB (ARMv8-only barriers) @------------------------------------------------------------------------------ dmb ishld dmb oshld @@ -53,7 +64,7 @@ @ CHECK-V7: error: invalid operand for instruction @------------------------------------------------------------------------------ -@ DSB (v8 barriers) +@ DSB (ARMv8-only barriers) @------------------------------------------------------------------------------ dsb ishld dsb oshld @@ -70,7 +81,7 @@ @ CHECK-V7: error: invalid operand for instruction @------------------------------------------------------------------------------ -@ SEVL +@ SEVL (in ARMv8 only) @------------------------------------------------------------------------------ sevl sevl.w diff --git a/test/MC/ARM/big-endian-thumb2-fixup.s b/test/MC/ARM/big-endian-thumb2-fixup.s index 4fd5276fce6e..0aaa26a209fe 100644 --- a/test/MC/ARM/big-endian-thumb2-fixup.s +++ b/test/MC/ARM/big-endian-thumb2-fixup.s @@ -35,14 +35,14 @@ cond_label: @ARM::fixup_t2_ldst_precel_12 .section s_ldst_precel_12,"ax",%progbits - ldr r0, ldst_precel_12_label + ldr.w r0, ldst_precel_12_label nop nop ldst_precel_12_label: @ARM::fixup_t2_adr_pcrel_12 .section s_adr_pcrel_12,"ax",%progbits - adr r0, adr_pcrel_12_label + adr.w r0, adr_pcrel_12_label nop nop adr_pcrel_12_label: diff --git a/test/MC/ARM/coff-debugging-secrel.ll b/test/MC/ARM/coff-debugging-secrel.ll index 1b8b7310171e..a950ba2b6896 100644 --- a/test/MC/ARM/coff-debugging-secrel.ll +++ b/test/MC/ARM/coff-debugging-secrel.ll @@ -1,14 +1,15 @@ ; RUN: llc -mtriple thumbv7--windows-itanium -filetype obj -o - %s \ ; RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-ITANIUM -; RUN: llc -mtriple thumbv7--windows-msvc -filetype obj -o - %s \ +; RUN: sed -e 's/"Dwarf Version"/"CodeView"/' %s \ +; RUN: | llc -mtriple thumbv7--windows-msvc -filetype obj -o - \ ; RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-MSVC ; ModuleID = '/Users/compnerd/work/llvm/test/MC/ARM/reduced.c' target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7--windows-itanium" -define arm_aapcs_vfpcc void @function() { +define arm_aapcs_vfpcc void @function() !dbg !1 { entry: ret void, !dbg !0 } @@ -17,13 +18,13 @@ entry: !llvm.module.flags = !{!9, !10} !0 = !DILocation(line: 1, scope: !1) -!1 = !DISubprogram(name: "function", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !2, scope: !3, type: !4, function: void ()* @function, variables: !6) +!1 = distinct !DISubprogram(name: "function", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !2, scope: !3, type: !4, variables: !6) !2 = !DIFile(filename: "/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", directory: "/Users/compnerd/work/llvm") !3 = !DIFile(filename: "/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", directory: "/Users/compnerd/work/llvm") !4 = !DISubroutineType(types: !5) !5 = !{null} !6 = !{} -!7 = !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0", isOptimized: false, emissionKind: 1, file: !2, enums: !6, retainedTypes: !6, subprograms: !8, globals: !6, imports: !6) +!7 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0", isOptimized: false, emissionKind: 1, file: !2, enums: !6, retainedTypes: !6, subprograms: !8, globals: !6, imports: !6) !8 = !{!1} !9 = !{i32 2, !"Dwarf Version", i32 4} !10 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/MC/ARM/data-in-code.ll b/test/MC/ARM/data-in-code.ll index c4910ff20e61..10657a3fed39 100644 --- a/test/MC/ARM/data-in-code.ll +++ b/test/MC/ARM/data-in-code.ll @@ -53,13 +53,6 @@ exit: ;; ARM: Symbol { ;; ARM: Name: $d -;; ARM-NEXT: Value: 0 -;; ARM-NEXT: Size: 0 -;; ARM-NEXT: Binding: Local -;; ARM-NEXT: Type: None - -;; ARM: Symbol { -;; ARM: Name: $d ;; ARM-NEXT: Value: 0x{{[0-9A-F]+}} ;; ARM-NEXT: Size: 0 ;; ARM-NEXT: Binding: Local @@ -77,10 +70,17 @@ exit: ;; ARM-NEXT: Section: .ARM.exidx ;; ARM-NEXT: } +;; ARM: Symbol { +;; ARM: Name: $d +;; ARM-NEXT: Value: 0 +;; ARM-NEXT: Size: 0 +;; ARM-NEXT: Binding: Local +;; ARM-NEXT: Type: None + ;; ARM-NOT: ${{[atd]}} ;; TMB: Symbol { -;; TMB: Name: $d.2 +;; TMB: Name: $d.1 ;; TMB-NEXT: Value: 0x{{[0-9A-F]+}} ;; TMB-NEXT: Size: 0 ;; TMB-NEXT: Binding: Local diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 6f66dc3b4d0a..a1dd95f7d7fc 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -1,7 +1,7 @@ @ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s +@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s @ RUN: not llvm-mc -triple=armv8 < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s +@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s @ Check for various assembly diagnostic messages on invalid input. @@ -98,22 +98,22 @@ @ Out of range immediates for v8 HLT instruction. hlt #65536 hlt #-1 -@CHECK-ERRORS-V8: error: invalid operand for instruction -@CHECK-ERRORS-V8: hlt #65536 -@CHECK-ERRORS-V8: ^ -@CHECK-ERRORS-V8: error: invalid operand for instruction -@CHECK-ERRORS-V8: hlt #-1 -@CHECK-ERRORS-V8: ^ +@CHECK-ERRORS: error: invalid operand for instruction +@CHECK-ERRORS: hlt #65536 +@CHECK-ERRORS: ^ +@CHECK-ERRORS: error: invalid operand for instruction +@CHECK-ERRORS: hlt #-1 +@CHECK-ERRORS: ^ @ Illegal condition code for v8 HLT instruction. hlteq #2 hltlt #23 -@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified -@CHECK-ERRORS-V8: hlteq #2 -@CHECK-ERRORS-V8: ^ -@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified -@CHECK-ERRORS-V8: hltlt #23 -@CHECK-ERRORS-V8: ^ +@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified +@CHECK-ERRORS: hlteq #2 +@CHECK-ERRORS: ^ +@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified +@CHECK-ERRORS: hltlt #23 +@CHECK-ERRORS: ^ @ Out of range 4 and 3 bit immediates on CDP[2] @@ -149,7 +149,8 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: immediate operand must be in the range [0,15] -@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V8: error: invalid operand for instruction @ p10 and p11 are reserved for NEON mcr p10, #2, r5, c1, c1, #4 @@ -183,7 +184,8 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: immediate operand must be in the range [0,15] -@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V8: error: invalid operand for instruction @ Shifter operand validation for PKH instructions. pkhbt r2, r2, r3, lsl #-1 @@ -394,12 +396,14 @@ ldc2 p2, c8, [r1], { 256 } ldc2 p2, c8, [r1], { -1 } -@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255] -@ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 } -@ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255] -@ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 } -@ CHECK-ERRORS: ^ +@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255] +@ CHECK-ERRORS-V7: ldc2 p2, c8, [r1], { 256 } +@ CHECK-ERRORS-V7: ^ +@ CHECK-ERRORS-V8: error: register expected +@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255] +@ CHECK-ERRORS-V7: ldc2 p2, c8, [r1], { -1 } +@ CHECK-ERRORS-V7: ^ +@ CHECK-ERRORS-V8: error: register expected @ Bad CPS instruction format. cps f,#1 @@ -470,14 +474,14 @@ vrintn.f32 s8, s9 vrintp.f64.f64 d10, d11 vrintm.f64 d12, d13 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 -@ CHECK-ERRORS: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 +@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8 stm sp!, {r0, pc}^ ldm sp!, {r0}^ diff --git a/test/MC/ARM/directive-arch-armv6j.s b/test/MC/ARM/directive-arch-armv6j.s deleted file mode 100644 index e27beef1ebaf..000000000000 --- a/test/MC/ARM/directive-arch-armv6j.s +++ /dev/null @@ -1,34 +0,0 @@ -@ Test the .arch directive for armv6j - -@ This test case will check the default .ARM.attributes value for the -@ armv6j architecture. - -@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-ASM -@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \ -@ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR - - .syntax unified - .arch armv6j - -@ CHECK-ASM: .arch armv6j - -@ CHECK-ATTR: FileAttributes { -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: 6J -@ CHECK-ATTR: } -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: CPU_arch -@ CHECK-ATTR: Description: ARM v6 -@ CHECK-ATTR: } -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: ARM_ISA_use -@ CHECK-ATTR: Description: Permitted -@ CHECK-ATTR: } -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: THUMB_ISA_use -@ CHECK-ATTR: Description: Thumb-1 -@ CHECK-ATTR: } -@ CHECK-ATTR: } - diff --git a/test/MC/ARM/directive-arch-armv6z.s b/test/MC/ARM/directive-arch-armv6z.s index 78a9ab1d5de7..efb8f8bfe9d3 100644 --- a/test/MC/ARM/directive-arch-armv6z.s +++ b/test/MC/ARM/directive-arch-armv6z.s @@ -11,12 +11,12 @@ .syntax unified .arch armv6z -@ CHECK-ASM: .arch armv6z +@ CHECK-ASM: .arch armv6kz @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: 6Z +@ CHECK-ATTR: Value: 6KZ @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_arch diff --git a/test/MC/ARM/directive-arch-armv6zk.s b/test/MC/ARM/directive-arch-armv8.2-a.s index 48d9cc1a2bf1..c9f4469fb0ae 100644 --- a/test/MC/ARM/directive-arch-armv6zk.s +++ b/test/MC/ARM/directive-arch-armv8.2-a.s @@ -1,7 +1,7 @@ -@ Test the .arch directive for armv6zk +@ Test the .arch directive for armv8.2-a @ This test case will check the default .ARM.attributes value for the -@ armv6zk architecture. +@ armv8-a architecture. @ RUN: llvm-mc -triple arm-eabi -filetype asm %s \ @ RUN: | FileCheck %s -check-prefix CHECK-ASM @@ -9,18 +9,22 @@ @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR .syntax unified - .arch armv6zk + .arch armv8.2-a -@ CHECK-ASM: .arch armv6zk +@ CHECK-ASM: .arch armv8.2-a @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: 6ZK +@ CHECK-ATTR: Value: 8.2-A @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_arch -@ CHECK-ATTR: Description: ARM v6KZ +@ CHECK-ATTR: Description: ARM v8 +@ CHECK-ATTR: } +@ CHECK-ATTR: Attribute { +@ CHECK-ATTR: TagName: CPU_arch_profile +@ CHECK-ATTR: Description: Application @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: ARM_ISA_use @@ -28,11 +32,15 @@ @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: THUMB_ISA_use -@ CHECK-ATTR: Description: Thumb-1 +@ CHECK-ATTR: Description: Thumb-2 +@ CHECK-ATTR: } +@ CHECK-ATTR: Attribute { +@ CHECK-ATTR: TagName: MPextension_use +@ CHECK-ATTR: Description: Permitted @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: Virtualization_use -@ CHECK-ATTR: Description: TrustZone +@ CHECK-ATTR: Description: TrustZone + Virtualization Extensions @ CHECK-ATTR: } @ CHECK-ATTR: } diff --git a/test/MC/ARM/directive-arch-semantic-action.s b/test/MC/ARM/directive-arch-semantic-action.s index b9c65d8e49c8..2d64026e041d 100644 --- a/test/MC/ARM/directive-arch-semantic-action.s +++ b/test/MC/ARM/directive-arch-semantic-action.s @@ -1,6 +1,6 @@ @ RUN: not llvm-mc -triple arm-gnueabi-linux -filetype asm %s 2>&1 | FileCheck %s - .arch armv6 + .arch armv6 dsb @ CHECK: error: instruction requires: data-barriers @@ -9,4 +9,4 @@ @ CHECK-NOT: error: instruction requires: data-barriers .arch invalid_architecture_name -@ CHECK: error: Unknown arch name +@ CHECK: error: Unknown arch name diff --git a/test/MC/ARM/directive-arch_extension-sec.s b/test/MC/ARM/directive-arch_extension-sec.s index 55ead8506ab1..645da0f75d31 100644 --- a/test/MC/ARM/directive-arch_extension-sec.s +++ b/test/MC/ARM/directive-arch_extension-sec.s @@ -1,11 +1,13 @@ @ RUN: not llvm-mc -triple armv6-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-ARMv6 -check-prefix CHECK-V6 +@ RUN: | FileCheck %s -check-prefix CHECK-V6 +@ RUN: not llvm-mc -triple armv6k-eabi -filetype asm -o /dev/null 2>&1 %s \ +@ RUN: | FileCheck %s -check-prefix CHECK-V7 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-ARMv7 -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 @ RUN: not llvm-mc -triple thumbv6-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-THUMBv6 -check-prefix CHECK-V6 +@ RUN: | FileCheck %s -check-prefix CHECK-V6 @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-THUMBv7 -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 .syntax unified @@ -13,6 +15,7 @@ @ CHECK-V6: error: architectural extension 'sec' is not allowed for the current base architecture @ CHECK-V6-NEXT: .arch_extension sec @ CHECK-V6-NEXT: ^ +@ CHECK-V7-NOT: error: architectural extension 'sec' is not allowed for the current base architecture .type sec,%function sec: @@ -23,9 +26,11 @@ sec: @ CHECK-V6: error: architectural extension 'sec' is not allowed for the current base architecture @ CHECK-V6-NEXT: .arch_extension nosec @ CHECK-V6-NEXT: ^ +@ CHECK-V7-NOT: error: architectural extension 'sec' is not allowed for the current base architecture .type nosec,%function nosec: smc #0 @ CHECK-V7: error: instruction requires: TrustZone +@ CHECK-V7-NOT: error: instruction requires: TrustZone diff --git a/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s b/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s index 5bf8fbd57fa5..d23c9a93de33 100644 --- a/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s +++ b/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s @@ -25,7 +25,7 @@ b: // DWARF: .debug_info contents: // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] -// CHECK-NOT-DWARF: DW_TAG_ +// DWARF-NOT: DW_TAG_ // DWARF: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) // DWARF: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000004) diff --git a/test/MC/ARM/dwarf-asm-multiple-sections.s b/test/MC/ARM/dwarf-asm-multiple-sections.s index 0eb8bab81620..49550559e956 100644 --- a/test/MC/ARM/dwarf-asm-multiple-sections.s +++ b/test/MC/ARM/dwarf-asm-multiple-sections.s @@ -1,6 +1,8 @@ // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp -// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF -check-prefix DWARF4 %s // RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 3 -fdebug-compilation-dir=/tmp +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF -check-prefix DWARF3 %s // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 1 2>&1 | FileCheck -check-prefix DWARF1 %s // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 5 2>&1 | FileCheck -check-prefix DWARF5 %s @@ -15,8 +17,10 @@ b: // DWARF: .debug_abbrev contents: // DWARF: Abbrev table for offset: 0x00000000 // DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes -// DWARF: DW_AT_stmt_list DW_FORM_data4 -// DWARF: DW_AT_ranges DW_FORM_data4 +// DWARF3: DW_AT_stmt_list DW_FORM_data4 +// DWARF4: DW_AT_stmt_list DW_FORM_sec_offset +// DWARF3: DW_AT_ranges DW_FORM_data4 +// DWARF4: DW_AT_ranges DW_FORM_sec_offset // DWARF: DW_AT_name DW_FORM_string // DWARF: DW_AT_comp_dir DW_FORM_string // DWARF: DW_AT_producer DW_FORM_string @@ -24,8 +28,9 @@ b: // DWARF: .debug_info contents: // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] -// CHECK-NOT-DWARF: DW_TAG_ -// DWARF: DW_AT_ranges [DW_FORM_data4] (0x00000000 +// DWARF-NOT: DW_TAG_ +// DWARF3: DW_AT_ranges [DW_FORM_data4] (0x00000000 +// DWARF4: DW_AT_ranges [DW_FORM_sec_offset] (0x00000000 // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * // DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a") @@ -41,10 +46,10 @@ b: // DWARF: .debug_line contents: -// DWARF: 0x0000000000000000 9 0 1 0 0 is_stmt -// DWARF-NEXT: 0x0000000000000004 9 0 1 0 0 is_stmt end_sequence -// DWARF-NEXT: 0x0000000000000000 13 0 1 0 0 is_stmt -// DWARF-NEXT: 0x0000000000000004 13 0 1 0 0 is_stmt end_sequence +// DWARF: 0x0000000000000000 11 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 11 0 1 0 0 is_stmt end_sequence +// DWARF-NEXT: 0x0000000000000000 15 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 15 0 1 0 0 is_stmt end_sequence // DWARF: .debug_ranges contents: diff --git a/test/MC/ARM/dwarf-asm-nonstandard-section.s b/test/MC/ARM/dwarf-asm-nonstandard-section.s index 497a39ad1162..39065a4d05f1 100644 --- a/test/MC/ARM/dwarf-asm-nonstandard-section.s +++ b/test/MC/ARM/dwarf-asm-nonstandard-section.s @@ -9,7 +9,7 @@ b: // DWARF: .debug_abbrev contents: // DWARF: Abbrev table for offset: 0x00000000 // DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes -// DWARF: DW_AT_stmt_list DW_FORM_data4 +// DWARF: DW_AT_stmt_list DW_FORM_sec_offset // DWARF: DW_AT_low_pc DW_FORM_addr // DWARF: DW_AT_high_pc DW_FORM_addr // DWARF: DW_AT_name DW_FORM_string diff --git a/test/MC/ARM/dwarf-asm-single-section.s b/test/MC/ARM/dwarf-asm-single-section.s index c57e6498a38a..808236f65b3f 100644 --- a/test/MC/ARM/dwarf-asm-single-section.s +++ b/test/MC/ARM/dwarf-asm-single-section.s @@ -10,7 +10,7 @@ a: // DWARF: .debug_abbrev contents: // DWARF: Abbrev table for offset: 0x00000000 // DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes -// DWARF: DW_AT_stmt_list DW_FORM_data4 +// DWARF: DW_AT_stmt_list DW_FORM_sec_offset // DWARF: DW_AT_low_pc DW_FORM_addr // DWARF: DW_AT_high_pc DW_FORM_addr // DWARF: DW_AT_name DW_FORM_string @@ -20,7 +20,7 @@ a: // DWARF: .debug_info contents: // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] -// CHECK-NOT-DWARF: DW_TAG_ +// DWARF-NOT: DW_TAG_ // DWARF: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) // DWARF: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000004) diff --git a/test/MC/ARM/eh-compact-pr0.s b/test/MC/ARM/eh-compact-pr0.s index 9c0581a722e8..66fd4a4efeda 100644 --- a/test/MC/ARM/eh-compact-pr0.s +++ b/test/MC/ARM/eh-compact-pr0.s @@ -68,8 +68,8 @@ func2: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.TEST1 @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 @ RELOC: ] @ RELOC: } @@ -105,7 +105,7 @@ func2: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.TEST2 @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0 @ RELOC: ] @ RELOC: } diff --git a/test/MC/ARM/eh-compact-pr1.s b/test/MC/ARM/eh-compact-pr1.s index 17d32f834e3e..9f40593cf437 100644 --- a/test/MC/ARM/eh-compact-pr1.s +++ b/test/MC/ARM/eh-compact-pr1.s @@ -68,7 +68,7 @@ func1: @ will keep __aeabi_unwind_cpp_pr1. @------------------------------------------------------------------------------- @ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 @ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 +@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0 @ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 @ CHECK: ] diff --git a/test/MC/ARM/eh-directive-handlerdata.s b/test/MC/ARM/eh-directive-handlerdata.s index 980a5f056760..c4352e5dee58 100644 --- a/test/MC/ARM/eh-directive-handlerdata.s +++ b/test/MC/ARM/eh-directive-handlerdata.s @@ -48,8 +48,8 @@ func1: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.TEST1 @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .TEST1 0x0 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0 @ RELOC: ] @ RELOC: } @@ -108,8 +108,8 @@ func2: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.TEST2 @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .TEST2 0x0 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.TEST2 0x0 @ RELOC: ] @ RELOC: } diff --git a/test/MC/ARM/eh-directive-personalityindex.s b/test/MC/ARM/eh-directive-personalityindex.s index 6db942503c6d..5d537bb04d37 100644 --- a/test/MC/ARM/eh-directive-personalityindex.s +++ b/test/MC/ARM/eh-directive-personalityindex.s @@ -28,8 +28,8 @@ pr0: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.pr0 @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .pr0 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .pr0 0x0 @ RELOC: ] @ RELOC: } @@ -57,8 +57,8 @@ pr0_nontrivial: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.pr0.nontrivial @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .pr0.nontrivial 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .pr0.nontrivial 0x0 @ RELOC: ] @ RELOC: } @@ -90,8 +90,8 @@ pr1: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.pr1 @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .pr1 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .pr1 0x0 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr1 0x0 @ RELOC: ] @ RELOC: } @@ -127,8 +127,8 @@ pr1_nontrivial: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.pr1.nontrivial @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .pr1.nontrivial 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr1 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .pr1.nontrivial 0x0 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr1.nontrivial 0x0 @ RELOC: ] @ RELOC: } @@ -161,8 +161,8 @@ pr2: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.pr2 @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .pr2 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .pr2 0x0 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr2 0x0 @ RELOC: ] @ RELOC: } @@ -196,8 +196,8 @@ pr2_nontrivial: @ RELOC: Section { @ RELOC: Name: .rel.ARM.exidx.pr2.nontrivial @ RELOC: Relocations [ -@ RELOC: 0x0 R_ARM_PREL31 .pr2.nontrivial 0x0 @ RELOC: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr2 0x0 +@ RELOC: 0x0 R_ARM_PREL31 .pr2.nontrivial 0x0 @ RELOC: 0x4 R_ARM_PREL31 .ARM.extab.pr2.nontrivial 0x0 @ RELOC: ] @ RELOC: } diff --git a/test/MC/ARM/eh-directive-section-comdat.s b/test/MC/ARM/eh-directive-section-comdat.s index 9c7160ea5e74..8b7f32eaece9 100644 --- a/test/MC/ARM/eh-directive-section-comdat.s +++ b/test/MC/ARM/eh-directive-section-comdat.s @@ -53,8 +53,8 @@ func1: @ These are the section indexes of .TEST1, .ARM.extab.TEST1, .ARM.exidx.TEST1, @ .rel.ARM.extab.TEST1, and .rel.ARM.exidx.TEST1. @------------------------------------------------------------------------------- -@ CHECK-NEXT: 0000: 01000000 06000000 07000000 08000000 -@ CHECK-NEXT: 0010: 09000000 0A000000 +@ CHECK-NEXT: 0000: 01000000 04000000 05000000 06000000 +@ CHECK-NEXT: 0010: 07000000 08000000 @ CHECK-NEXT: ) @ CHECK: } @@ -63,7 +63,7 @@ func1: @ Check the .TEST1 section @------------------------------------------------------------------------------- @ CHECK: Section { -@ CHECK: Index: 6 +@ CHECK: Index: 4 @ CHECK-NEXT: Name: .TEST1 @ CHECK: Type: SHT_PROGBITS (0x1) @------------------------------------------------------------------------------- @@ -81,7 +81,7 @@ func1: @ Check the .ARM.extab.TEST1 section @------------------------------------------------------------------------------- @ CHECK: Section { -@ CHECK: Index: 7 +@ CHECK: Index: 5 @ CHECK-NEXT: Name: .ARM.extab.TEST1 @ CHECK: Type: SHT_PROGBITS (0x1) @------------------------------------------------------------------------------- @@ -94,7 +94,7 @@ func1: @ CHECK: } @ CHECK: Section { -@ CHECK: Index: 8 +@ CHECK: Index: 6 @ CHECK-NEXT: Name: .rel.ARM.extab.TEST1 @ CHECK: } @@ -102,7 +102,7 @@ func1: @ Check the .ARM.exidx.TEST1 section @------------------------------------------------------------------------------- @ CHECK: Section { -@ CHECK: Index: 9 +@ CHECK: Index: 7 @ CHECK-NEXT: Name: .ARM.exidx.TEST1 @ CHECK: Type: SHT_ARM_EXIDX (0x70000001) @------------------------------------------------------------------------------- @@ -113,12 +113,12 @@ func1: @ CHECK: SHF_GROUP (0x200) @ CHECK: SHF_LINK_ORDER (0x80) @ CHECK: ] -@ CHECK: Link: 6 +@ CHECK: Link: 4 @ CHECK: } @ CHECK: Section { -@ CHECK: Index: 10 +@ CHECK: Index: 8 @ CHECK-NEXT: Name: .rel.ARM.exidx.TEST1 @ CHECK: } diff --git a/test/MC/ARM/eh-directive-section-multiple-func.s b/test/MC/ARM/eh-directive-section-multiple-func.s index e5307cf9190c..53c498ab87be 100644 --- a/test/MC/ARM/eh-directive-section-multiple-func.s +++ b/test/MC/ARM/eh-directive-section-multiple-func.s @@ -54,7 +54,7 @@ func2: @ Check the .TEST1 section. There should be two "bx lr" instructions. @------------------------------------------------------------------------------- @ CHECK: Section { -@ CHECK: Index: 5 +@ CHECK: Index: 3 @ CHECK-NEXT: Name: .TEST1 @ CHECK: SectionData ( @ CHECK: 0000: 1EFF2FE1 1EFF2FE1 |../.../.| @@ -87,7 +87,7 @@ func2: @------------------------------------------------------------------------------- @ CHECK: Section { @ CHECK: Name: .ARM.exidx.TEST1 -@ CHECK: Link: 5 +@ CHECK: Link: 3 @------------------------------------------------------------------------------- @ The first word should be the offset to .TEST1. @ The second word should be the offset to .ARM.extab.TEST1 diff --git a/test/MC/ARM/eh-directive-section.s b/test/MC/ARM/eh-directive-section.s index e36d9a99aaf5..bd41fbe5eeea 100644 --- a/test/MC/ARM/eh-directive-section.s +++ b/test/MC/ARM/eh-directive-section.s @@ -50,7 +50,7 @@ func2: @------------------------------------------------------------------------------- @ CHECK: Sections [ @ CHECK: Section { -@ CHECK: Index: 5 +@ CHECK: Index: 3 @ CHECK-NEXT: Name: .TEST1 @ CHECK: SectionData ( @ CHECK: 0000: 1EFF2FE1 |../.| @@ -84,7 +84,7 @@ func2: @------------------------------------------------------------------------------- @ This section should linked with .TEST1 section. @------------------------------------------------------------------------------- -@ CHECK: Link: 5 +@ CHECK: Link: 3 @------------------------------------------------------------------------------- @ The first word should be relocated to the code address in .TEST1 section. @@ -109,7 +109,7 @@ func2: @ Check the TEST2 section (without the dot in the beginning) @------------------------------------------------------------------------------- @ CHECK: Section { -@ CHECK: Index: 10 +@ CHECK: Index: 8 @ CHECK-NEXT: Name: TEST2 @ CHECK: SectionData ( @ CHECK: 0000: 1EFF2FE1 |../.| @@ -143,7 +143,7 @@ func2: @------------------------------------------------------------------------------- @ This section should linked with TEST2 section. @------------------------------------------------------------------------------- -@ CHECK: Link: 10 +@ CHECK: Link: 8 @------------------------------------------------------------------------------- @ The first word should be relocated to the code address in TEST2 section. diff --git a/test/MC/ARM/eh-directive-text-section.s b/test/MC/ARM/eh-directive-text-section.s index 32696d5a1dad..10ccdd54e501 100644 --- a/test/MC/ARM/eh-directive-text-section.s +++ b/test/MC/ARM/eh-directive-text-section.s @@ -77,6 +77,6 @@ func1: @ add an relocation to __aeabi_unwind_cpp_pr0. @------------------------------------------------------------------------------- @ CHECK: Relocations [ -@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 @ CHECK: 0x0 R_ARM_NONE __aeabi_unwind_cpp_pr0 0x0 +@ CHECK: 0x0 R_ARM_PREL31 .text 0x0 @ CHECK: ] diff --git a/test/MC/ARM/eh-link.s b/test/MC/ARM/eh-link.s index e14fb0638b91..19fe14db5f30 100644 --- a/test/MC/ARM/eh-link.s +++ b/test/MC/ARM/eh-link.s @@ -8,7 +8,7 @@ @ name first we could use a FileCheck variable. @ CHECK: Section { -@ CHECK: Index: 6 +@ CHECK: Index: 4 @ CHECK-NEXT: Name: .text @ CHECK-NEXT: Type: SHT_PROGBITS @ CHECK-NEXT: Flags [ @@ -25,7 +25,7 @@ @ CHECK-NEXT: EntrySize: 0 @ CHECK-NEXT: } @ CHECK-NEXT: Section { -@ CHECK-NEXT: Index: 7 +@ CHECK-NEXT: Index: 5 @ CHECK-NEXT: Name: .ARM.exidx @ CHECK-NEXT: Type: SHT_ARM_EXIDX @ CHECK-NEXT: Flags [ @@ -36,14 +36,14 @@ @ CHECK-NEXT: Address: 0x0 @ CHECK-NEXT: Offset: @ CHECK-NEXT: Size: 8 -@ CHECK-NEXT: Link: 6 +@ CHECK-NEXT: Link: 4 @ CHECK-NEXT: Info: 0 @ CHECK-NEXT: AddressAlignment: 4 @ CHECK-NEXT: EntrySize: 0 @ CHECK-NEXT: } @ CHECK: Section { -@ CHECK: Index: 10 +@ CHECK: Index: 8 @ CHECK-NEXT: Name: .text @ CHECK-NEXT: Type: SHT_PROGBITS @ CHECK-NEXT: Flags [ @@ -60,7 +60,7 @@ @ CHECK-NEXT: EntrySize: 0 @ CHECK-NEXT: } @ CHECK-NEXT: Section { -@ CHECK-NEXT: Index: 11 +@ CHECK-NEXT: Index: 9 @ CHECK-NEXT: Name: .ARM.exidx @ CHECK-NEXT: Type: SHT_ARM_EXIDX @ CHECK-NEXT: Flags [ @@ -71,7 +71,7 @@ @ CHECK-NEXT: Address: 0x0 @ CHECK-NEXT: Offset: @ CHECK-NEXT: Size: 8 -@ CHECK-NEXT: Link: 10 +@ CHECK-NEXT: Link: 8 @ CHECK-NEXT: Info: 0 @ CHECK-NEXT: AddressAlignment: 4 @ CHECK-NEXT: EntrySize: 0 diff --git a/test/MC/ARM/error-location-ldr-pseudo.s b/test/MC/ARM/error-location-ldr-pseudo.s new file mode 100644 index 000000000000..b5cdcad72597 --- /dev/null +++ b/test/MC/ARM/error-location-ldr-pseudo.s @@ -0,0 +1,5 @@ +@ RUN: not llvm-mc -triple armv7a--none-eabi -filetype obj < %s -o /dev/null 2>&1 | FileCheck %s + + .text +@ CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: expected relocatable expression + ldr r0, =(-undef) diff --git a/test/MC/ARM/error-location.s b/test/MC/ARM/error-location.s new file mode 100644 index 000000000000..112acf318ed3 --- /dev/null +++ b/test/MC/ARM/error-location.s @@ -0,0 +1,49 @@ +@ RUN: not llvm-mc -triple armv7a--none-eabi -filetype obj < %s -o /dev/null 2>&1 | FileCheck %s + +@ Note: These errors are not always emitted in the order in which the relevant +@ source appears, this file is carefully ordered so that that is the case. + + .text +@ CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: symbol 'undef' can not be undefined in a subtraction expression + .word (0-undef) + +@ CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: expected relocatable expression + .word -undef + +@ CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: No relocation available to represent this relative expression + adr r0, #a-undef + +@ CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: Cannot represent a difference across sections + .word x_a - y_a + +@ CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: Cannot represent a subtraction with a weak symbol + .word a - w + +@ CHECK: <unknown>:0: error: expression could not be evaluated + .set v1, -undef + + .comm common, 4 +@ CHECK: <unknown>:0: error: Common symbol 'common' cannot be used in assignment expr + .set v3, common + +@ CHECK: <unknown>:0: error: Undefined temporary symbol + .word 5f + +@ CHECK: <unknown>:0: error: symbol 'undef' could not be evaluated in a subtraction expression + .set v2, a-undef + + + +w: + .word 0 + .weak w + + + .section sec_x +x_a: + .word 0 + + + .section sec_y +y_a: + .word 0 diff --git a/test/MC/ARM/fullfp16-neon-neg.s b/test/MC/ARM/fullfp16-neon-neg.s new file mode 100644 index 000000000000..1928163db74b --- /dev/null +++ b/test/MC/ARM/fullfp16-neon-neg.s @@ -0,0 +1,289 @@ +@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileCheck %s + + vadd.f16 d0, d1, d2 + vadd.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vsub.f16 d0, d1, d2 + vsub.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmul.f16 d0, d1, d2 + vmul.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmul.f16 d1, d2, d3[2] + vmul.f16 q4, q5, d6[3] +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmla.f16 d0, d1, d2 + vmla.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmla.f16 d5, d6, d7[2] + vmla.f16 q5, q6, d7[3] +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmls.f16 d0, d1, d2 + vmls.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmls.f16 d5, d6, d7[2] + vmls.f16 q5, q6, d7[3] +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vfma.f16 d0, d1, d2 + vfma.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vfms.f16 d0, d1, d2 + vfms.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vceq.f16 d2, d3, d4 + vceq.f16 q2, q3, q4 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vceq.f16 d2, d3, #0 + vceq.f16 q2, q3, #0 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcge.f16 d2, d3, d4 + vcge.f16 q2, q3, q4 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcge.f16 d2, d3, #0 + vcge.f16 q2, q3, #0 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcgt.f16 d2, d3, d4 + vcgt.f16 q2, q3, q4 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcgt.f16 d2, d3, #0 + vcgt.f16 q2, q3, #0 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcle.f16 d2, d3, d4 + vcle.f16 q2, q3, q4 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcle.f16 d2, d3, #0 + vcle.f16 q2, q3, #0 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vclt.f16 d2, d3, d4 + vclt.f16 q2, q3, q4 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vclt.f16 d2, d3, #0 + vclt.f16 q2, q3, #0 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vacge.f16 d0, d1, d2 + vacge.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vacgt.f16 d0, d1, d2 + vacgt.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vacle.f16 d0, d1, d2 + vacle.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vaclt.f16 d0, d1, d2 + vaclt.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vabd.f16 d0, d1, d2 + vabd.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vabs.f16 d0, d1 + vabs.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmax.f16 d0, d1, d2 + vmax.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmin.f16 d0, d1, d2 + vmin.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vmaxnm.f16 d0, d1, d2 + vmaxnm.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vminnm.f16 d0, d1, d2 + vminnm.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vpadd.f16 d0, d1, d2 +@ CHECK: error: instruction requires: + + vpmax.f16 d0, d1, d2 +@ CHECK: error: instruction requires: + + vpmin.f16 d0, d1, d2 +@ CHECK: error: instruction requires: + + vrecpe.f16 d0, d1 + vrecpe.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrecps.f16 d0, d1, d2 + vrecps.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrsqrte.f16 d0, d1 + vrsqrte.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrsqrts.f16 d0, d1, d2 + vrsqrts.f16 q0, q1, q2 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vneg.f16 d0, d1 + vneg.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcvt.s16.f16 d0, d1 + vcvt.u16.f16 d0, d1 + vcvt.f16.s16 d0, d1 + vcvt.f16.u16 d0, d1 + vcvt.s16.f16 q0, q1 + vcvt.u16.f16 q0, q1 + vcvt.f16.s16 q0, q1 + vcvt.f16.u16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcvta.s16.f16 d0, d1 + vcvta.s16.f16 q0, q1 + vcvta.u16.f16 d0, d1 + vcvta.u16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcvtm.s16.f16 d0, d1 + vcvtm.s16.f16 q0, q1 + vcvtm.u16.f16 d0, d1 + vcvtm.u16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcvtn.s16.f16 d0, d1 + vcvtn.s16.f16 q0, q1 + vcvtn.u16.f16 d0, d1 + vcvtn.u16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vcvtp.s16.f16 d0, d1 + vcvtp.s16.f16 q0, q1 + vcvtp.u16.f16 d0, d1 + vcvtp.u16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + + vcvt.s16.f16 d0, d1, #1 + vcvt.u16.f16 d0, d1, #2 + vcvt.f16.s16 d0, d1, #3 + vcvt.f16.u16 d0, d1, #4 + vcvt.s16.f16 q0, q1, #5 + vcvt.u16.f16 q0, q1, #6 + vcvt.f16.s16 q0, q1, #7 + vcvt.f16.u16 q0, q1, #8 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrinta.f16.f16 d0, d1 + vrinta.f16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrintm.f16.f16 d0, d1 + vrintm.f16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrintn.f16.f16 d0, d1 + vrintn.f16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrintp.f16.f16 d0, d1 + vrintp.f16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrintx.f16.f16 d0, d1 + vrintx.f16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: + + vrintz.f16.f16 d0, d1 + vrintz.f16.f16 q0, q1 +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: diff --git a/test/MC/ARM/fullfp16-neon.s b/test/MC/ARM/fullfp16-neon.s new file mode 100644 index 000000000000..32a33720c13b --- /dev/null +++ b/test/MC/ARM/fullfp16-neon.s @@ -0,0 +1,404 @@ +@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+neon -show-encoding < %s | FileCheck %s --check-prefix=ARM +@ RUN: llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,+neon -show-encoding < %s | FileCheck %s --check-prefix=THUMB + + vadd.f16 d0, d1, d2 + vadd.f16 q0, q1, q2 +@ ARM: vadd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x11,0xf2] +@ ARM: vadd.f16 q0, q1, q2 @ encoding: [0x44,0x0d,0x12,0xf2] +@ THUMB: vadd.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x02,0x0d] +@ THUMB: vadd.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0d] + + vsub.f16 d0, d1, d2 + vsub.f16 q0, q1, q2 +@ ARM: vsub.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x31,0xf2] +@ ARM: vsub.f16 q0, q1, q2 @ encoding: [0x44,0x0d,0x32,0xf2] +@ THUMB: vsub.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x02,0x0d] +@ THUMB: vsub.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x44,0x0d] + + vmul.f16 d0, d1, d2 + vmul.f16 q0, q1, q2 +@ ARM: vmul.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x11,0xf3] +@ ARM: vmul.f16 q0, q1, q2 @ encoding: [0x54,0x0d,0x12,0xf3] +@ THUMB: vmul.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0d] +@ THUMB: vmul.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d] + + vmul.f16 d1, d2, d3[2] + vmul.f16 q4, q5, d6[3] +@ ARM: vmul.f16 d1, d2, d3[2] @ encoding: [0x63,0x19,0x92,0xf2] +@ ARM: vmul.f16 q4, q5, d6[3] @ encoding: [0x6e,0x89,0x9a,0xf3] +@ THUMB: vmul.f16 d1, d2, d3[2] @ encoding: [0x92,0xef,0x63,0x19] +@ THUMB: vmul.f16 q4, q5, d6[3] @ encoding: [0x9a,0xff,0x6e,0x89] + + vmla.f16 d0, d1, d2 + vmla.f16 q0, q1, q2 +@ ARM: vmla.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x11,0xf2] +@ ARM: vmla.f16 q0, q1, q2 @ encoding: [0x54,0x0d,0x12,0xf2] +@ THUMB: vmla.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x12,0x0d] +@ THUMB: vmla.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x0d] + + vmla.f16 d5, d6, d7[2] + vmla.f16 q5, q6, d7[3] +@ ARM: vmla.f16 d5, d6, d7[2] @ encoding: [0x67,0x51,0x96,0xf2] +@ ARM: vmla.f16 q5, q6, d7[3] @ encoding: [0x6f,0xa1,0x9c,0xf3] +@ THUMB: vmla.f16 d5, d6, d7[2] @ encoding: [0x96,0xef,0x67,0x51] +@ THUMB: vmla.f16 q5, q6, d7[3] @ encoding: [0x9c,0xff,0x6f,0xa1] + + vmls.f16 d0, d1, d2 + vmls.f16 q0, q1, q2 +@ ARM: vmls.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x31,0xf2] +@ ARM: vmls.f16 q0, q1, q2 @ encoding: [0x54,0x0d,0x32,0xf2] +@ THUMB: vmls.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x12,0x0d] +@ THUMB: vmls.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x0d] + + vmls.f16 d5, d6, d7[2] + vmls.f16 q5, q6, d7[3] +@ ARM: vmls.f16 d5, d6, d7[2] @ encoding: [0x67,0x55,0x96,0xf2] +@ ARM: vmls.f16 q5, q6, d7[3] @ encoding: [0x6f,0xa5,0x9c,0xf3] +@ THUMB: vmls.f16 d5, d6, d7[2] @ encoding: [0x96,0xef,0x67,0x55] +@ THUMB: vmls.f16 q5, q6, d7[3] @ encoding: [0x9c,0xff,0x6f,0xa5] + + vfma.f16 d0, d1, d2 + vfma.f16 q0, q1, q2 +@ ARM: vfma.f16 d0, d1, d2 @ encoding: [0x12,0x0c,0x11,0xf2] +@ ARM: vfma.f16 q0, q1, q2 @ encoding: [0x54,0x0c,0x12,0xf2] +@ THUMB: vfma.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x12,0x0c] +@ THUMB: vfma.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x0c] + + vfms.f16 d0, d1, d2 + vfms.f16 q0, q1, q2 +@ ARM: vfms.f16 d0, d1, d2 @ encoding: [0x12,0x0c,0x31,0xf2] +@ ARM: vfms.f16 q0, q1, q2 @ encoding: [0x54,0x0c,0x32,0xf2] +@ THUMB: vfms.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x12,0x0c] +@ THUMB: vfms.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x0c] + + vceq.f16 d2, d3, d4 + vceq.f16 q2, q3, q4 +@ ARM: vceq.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x13,0xf2] +@ ARM: vceq.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x16,0xf2] +@ THUMB: vceq.f16 d2, d3, d4 @ encoding: [0x13,0xef,0x04,0x2e] +@ THUMB: vceq.f16 q2, q3, q4 @ encoding: [0x16,0xef,0x48,0x4e] + + vceq.f16 d2, d3, #0 + vceq.f16 q2, q3, #0 +@ ARM: vceq.f16 d2, d3, #0 @ encoding: [0x03,0x25,0xb5,0xf3] +@ ARM: vceq.f16 q2, q3, #0 @ encoding: [0x46,0x45,0xb5,0xf3] +@ THUMB: vceq.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x03,0x25] +@ THUMB: vceq.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0x46,0x45] + + vcge.f16 d2, d3, d4 + vcge.f16 q2, q3, q4 +@ ARM: vcge.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x13,0xf3] +@ ARM: vcge.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x16,0xf3] +@ THUMB: vcge.f16 d2, d3, d4 @ encoding: [0x13,0xff,0x04,0x2e] +@ THUMB: vcge.f16 q2, q3, q4 @ encoding: [0x16,0xff,0x48,0x4e] + + vcge.f16 d2, d3, #0 + vcge.f16 q2, q3, #0 +@ ARM: vcge.f16 d2, d3, #0 @ encoding: [0x83,0x24,0xb5,0xf3] +@ ARM: vcge.f16 q2, q3, #0 @ encoding: [0xc6,0x44,0xb5,0xf3] +@ THUMB: vcge.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x83,0x24] +@ THUMB: vcge.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0xc6,0x44] + + vcgt.f16 d2, d3, d4 + vcgt.f16 q2, q3, q4 +@ ARM: vcgt.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x33,0xf3] +@ ARM: vcgt.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x36,0xf3] +@ THUMB: vcgt.f16 d2, d3, d4 @ encoding: [0x33,0xff,0x04,0x2e] +@ THUMB: vcgt.f16 q2, q3, q4 @ encoding: [0x36,0xff,0x48,0x4e] + + vcgt.f16 d2, d3, #0 + vcgt.f16 q2, q3, #0 +@ ARM: vcgt.f16 d2, d3, #0 @ encoding: [0x03,0x24,0xb5,0xf3] +@ ARM: vcgt.f16 q2, q3, #0 @ encoding: [0x46,0x44,0xb5,0xf3] +@ THUMB: vcgt.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x03,0x24] +@ THUMB: vcgt.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0x46,0x44] + + vcle.f16 d2, d3, d4 + vcle.f16 q2, q3, q4 +@ ARM: vcge.f16 d2, d4, d3 @ encoding: [0x03,0x2e,0x14,0xf3] +@ ARM: vcge.f16 q2, q4, q3 @ encoding: [0x46,0x4e,0x18,0xf3] +@ THUMB: vcge.f16 d2, d4, d3 @ encoding: [0x14,0xff,0x03,0x2e] +@ THUMB: vcge.f16 q2, q4, q3 @ encoding: [0x18,0xff,0x46,0x4e] + + vcle.f16 d2, d3, #0 + vcle.f16 q2, q3, #0 +@ ARM: vcle.f16 d2, d3, #0 @ encoding: [0x83,0x25,0xb5,0xf3] +@ ARM: vcle.f16 q2, q3, #0 @ encoding: [0xc6,0x45,0xb5,0xf3] +@ THUMB: vcle.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x83,0x25] +@ THUMB: vcle.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0xc6,0x45] + + vclt.f16 d2, d3, d4 + vclt.f16 q2, q3, q4 +@ ARM: vcgt.f16 d2, d4, d3 @ encoding: [0x03,0x2e,0x34,0xf3] +@ ARM: vcgt.f16 q2, q4, q3 @ encoding: [0x46,0x4e,0x38,0xf3] +@ THUMB: vcgt.f16 d2, d4, d3 @ encoding: [0x34,0xff,0x03,0x2e] +@ THUMB: vcgt.f16 q2, q4, q3 @ encoding: [0x38,0xff,0x46,0x4e] + + vclt.f16 d2, d3, #0 + vclt.f16 q2, q3, #0 +@ ARM: vclt.f16 d2, d3, #0 @ encoding: [0x03,0x26,0xb5,0xf3] +@ ARM: vclt.f16 q2, q3, #0 @ encoding: [0x46,0x46,0xb5,0xf3] +@ THUMB: vclt.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x03,0x26] +@ THUMB: vclt.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0x46,0x46] + + vacge.f16 d0, d1, d2 + vacge.f16 q0, q1, q2 +@ ARM: vacge.f16 d0, d1, d2 @ encoding: [0x12,0x0e,0x11,0xf3] +@ ARM: vacge.f16 q0, q1, q2 @ encoding: [0x54,0x0e,0x12,0xf3] +@ THUMB: vacge.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0e] +@ THUMB: vacge.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0e] + + vacgt.f16 d0, d1, d2 + vacgt.f16 q0, q1, q2 +@ ARM: vacgt.f16 d0, d1, d2 @ encoding: [0x12,0x0e,0x31,0xf3] +@ ARM: vacgt.f16 q0, q1, q2 @ encoding: [0x54,0x0e,0x32,0xf3] +@ THUMB: vacgt.f16 d0, d1, d2 @ encoding: [0x31,0xff,0x12,0x0e] +@ THUMB: vacgt.f16 q0, q1, q2 @ encoding: [0x32,0xff,0x54,0x0e] + + vacle.f16 d0, d1, d2 + vacle.f16 q0, q1, q2 +@ ARM: vacge.f16 d0, d2, d1 @ encoding: [0x11,0x0e,0x12,0xf3] +@ ARM: vacge.f16 q0, q2, q1 @ encoding: [0x52,0x0e,0x14,0xf3] +@ THUMB: vacge.f16 d0, d2, d1 @ encoding: [0x12,0xff,0x11,0x0e] +@ THUMB: vacge.f16 q0, q2, q1 @ encoding: [0x14,0xff,0x52,0x0e] + + vaclt.f16 d0, d1, d2 + vaclt.f16 q0, q1, q2 +@ ARM: vacgt.f16 d0, d2, d1 @ encoding: [0x11,0x0e,0x32,0xf3] +@ ARM: vacgt.f16 q0, q2, q1 @ encoding: [0x52,0x0e,0x34,0xf3] +@ THUMB: vacgt.f16 d0, d2, d1 @ encoding: [0x32,0xff,0x11,0x0e] +@ THUMB: vacgt.f16 q0, q2, q1 @ encoding: [0x34,0xff,0x52,0x0e] + + vabd.f16 d0, d1, d2 + vabd.f16 q0, q1, q2 +@ ARM: vabd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x31,0xf3] +@ ARM: vabd.f16 q0, q1, q2 @ encoding: [0x44,0x0d,0x32,0xf3] +@ THUMB: vabd.f16 d0, d1, d2 @ encoding: [0x31,0xff,0x02,0x0d] +@ THUMB: vabd.f16 q0, q1, q2 @ encoding: [0x32,0xff,0x44,0x0d] + + vabs.f16 d0, d1 + vabs.f16 q0, q1 +@ ARM: vabs.f16 d0, d1 @ encoding: [0x01,0x07,0xb5,0xf3] +@ ARM: vabs.f16 q0, q1 @ encoding: [0x42,0x07,0xb5,0xf3] +@ THUMB: vabs.f16 d0, d1 @ encoding: [0xb5,0xff,0x01,0x07] +@ THUMB: vabs.f16 q0, q1 @ encoding: [0xb5,0xff,0x42,0x07] + + vmax.f16 d0, d1, d2 + vmax.f16 q0, q1, q2 +@ ARM: vmax.f16 d0, d1, d2 @ encoding: [0x02,0x0f,0x11,0xf2] +@ ARM: vmax.f16 q0, q1, q2 @ encoding: [0x44,0x0f,0x12,0xf2] +@ THUMB: vmax.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x02,0x0f] +@ THUMB: vmax.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0f] + + vmin.f16 d0, d1, d2 + vmin.f16 q0, q1, q2 +@ ARM: vmin.f16 d0, d1, d2 @ encoding: [0x02,0x0f,0x31,0xf2] +@ ARM: vmin.f16 q0, q1, q2 @ encoding: [0x44,0x0f,0x32,0xf2] +@ THUMB: vmin.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x02,0x0f] +@ THUMB: vmin.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x44,0x0f] + + vmaxnm.f16 d0, d1, d2 + vmaxnm.f16 q0, q1, q2 +@ ARM: vmaxnm.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x11,0xf3] +@ ARM: vmaxnm.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x12,0xf3] +@ THUMB: vmaxnm.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0f] +@ THUMB: vmaxnm.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0f] + + vminnm.f16 d0, d1, d2 + vminnm.f16 q0, q1, q2 +@ ARM: vminnm.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x31,0xf3] +@ ARM: vminnm.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x32,0xf3] +@ THUMB: vminnm.f16 d0, d1, d2 @ encoding: [0x31,0xff,0x12,0x0f] +@ THUMB: vminnm.f16 q0, q1, q2 @ encoding: [0x32,0xff,0x54,0x0f] + + vpadd.f16 d0, d1, d2 +@ ARM: vpadd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x11,0xf3] +@ THUMB: vpadd.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x02,0x0d] + + vpmax.f16 d0, d1, d2 +@ ARM: vpmax.f16 d0, d1, d2 @ encoding: [0x02,0x0f,0x11,0xf3] +@ THUMB: vpmax.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x02,0x0f] + + vpmin.f16 d0, d1, d2 +@ ARM: vpmin.f16 d0, d1, d2 @ encoding: [0x02,0x0f,0x31,0xf3] +@ THUMB: vpmin.f16 d0, d1, d2 @ encoding: [0x31,0xff,0x02,0x0f] + + vrecpe.f16 d0, d1 + vrecpe.f16 q0, q1 +@ ARM: vrecpe.f16 d0, d1 @ encoding: [0x01,0x05,0xb7,0xf3] +@ ARM: vrecpe.f16 q0, q1 @ encoding: [0x42,0x05,0xb7,0xf3] +@ THUMB: vrecpe.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x05] +@ THUMB: vrecpe.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x05] + + vrecps.f16 d0, d1, d2 + vrecps.f16 q0, q1, q2 +@ ARM: vrecps.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x11,0xf2] +@ ARM: vrecps.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x12,0xf2] +@ THUMB: vrecps.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x12,0x0f] +@ THUMB: vrecps.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x0f] + + vrsqrte.f16 d0, d1 + vrsqrte.f16 q0, q1 +@ ARM: vrsqrte.f16 d0, d1 @ encoding: [0x81,0x05,0xb7,0xf3] +@ ARM: vrsqrte.f16 q0, q1 @ encoding: [0xc2,0x05,0xb7,0xf3] +@ THUMB: vrsqrte.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x05] +@ THUMB: vrsqrte.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x05] + + vrsqrts.f16 d0, d1, d2 + vrsqrts.f16 q0, q1, q2 +@ ARM: vrsqrts.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x31,0xf2] +@ ARM: vrsqrts.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x32,0xf2] +@ THUMB: vrsqrts.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x12,0x0f] +@ THUMB: vrsqrts.f16 q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x0f] + + vneg.f16 d0, d1 + vneg.f16 q0, q1 +@ ARM: vneg.f16 d0, d1 @ encoding: [0x81,0x07,0xb5,0xf3] +@ ARM: vneg.f16 q0, q1 @ encoding: [0xc2,0x07,0xb5,0xf3] +@ THUMB: vneg.f16 d0, d1 @ encoding: [0xb5,0xff,0x81,0x07] +@ THUMB: vneg.f16 q0, q1 @ encoding: [0xb5,0xff,0xc2,0x07] + + vcvt.s16.f16 d0, d1 + vcvt.u16.f16 d0, d1 + vcvt.f16.s16 d0, d1 + vcvt.f16.u16 d0, d1 + vcvt.s16.f16 q0, q1 + vcvt.u16.f16 q0, q1 + vcvt.f16.s16 q0, q1 + vcvt.f16.u16 q0, q1 +@ ARM: vcvt.s16.f16 d0, d1 @ encoding: [0x01,0x07,0xb7,0xf3] +@ ARM: vcvt.u16.f16 d0, d1 @ encoding: [0x81,0x07,0xb7,0xf3] +@ ARM: vcvt.f16.s16 d0, d1 @ encoding: [0x01,0x06,0xb7,0xf3] +@ ARM: vcvt.f16.u16 d0, d1 @ encoding: [0x81,0x06,0xb7,0xf3] +@ ARM: vcvt.s16.f16 q0, q1 @ encoding: [0x42,0x07,0xb7,0xf3] +@ ARM: vcvt.u16.f16 q0, q1 @ encoding: [0xc2,0x07,0xb7,0xf3] +@ ARM: vcvt.f16.s16 q0, q1 @ encoding: [0x42,0x06,0xb7,0xf3] +@ ARM: vcvt.f16.u16 q0, q1 @ encoding: [0xc2,0x06,0xb7,0xf3] +@ THUMB: vcvt.s16.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x07] +@ THUMB: vcvt.u16.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x07] +@ THUMB: vcvt.f16.s16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x06] +@ THUMB: vcvt.f16.u16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x06] +@ THUMB: vcvt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x07] +@ THUMB: vcvt.u16.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x07] +@ THUMB: vcvt.f16.s16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x06] +@ THUMB: vcvt.f16.u16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x06] + + vcvta.s16.f16 d0, d1 + vcvta.s16.f16 q0, q1 + vcvta.u16.f16 d0, d1 + vcvta.u16.f16 q0, q1 +@ ARM: vcvta.s16.f16 d0, d1 @ encoding: [0x01,0x00,0xb7,0xf3] +@ ARM: vcvta.s16.f16 q0, q1 @ encoding: [0x42,0x00,0xb7,0xf3] +@ ARM: vcvta.u16.f16 d0, d1 @ encoding: [0x81,0x00,0xb7,0xf3] +@ ARM: vcvta.u16.f16 q0, q1 @ encoding: [0xc2,0x00,0xb7,0xf3] +@ THUMB: vcvta.s16.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x00] +@ THUMB: vcvta.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x00] +@ THUMB: vcvta.u16.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x00] +@ THUMB: vcvta.u16.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x00] + + vcvtm.s16.f16 d0, d1 + vcvtm.s16.f16 q0, q1 + vcvtm.u16.f16 d0, d1 + vcvtm.u16.f16 q0, q1 +@ ARM: vcvtm.s16.f16 d0, d1 @ encoding: [0x01,0x03,0xb7,0xf3] +@ ARM: vcvtm.s16.f16 q0, q1 @ encoding: [0x42,0x03,0xb7,0xf3] +@ ARM: vcvtm.u16.f16 d0, d1 @ encoding: [0x81,0x03,0xb7,0xf3] +@ ARM: vcvtm.u16.f16 q0, q1 @ encoding: [0xc2,0x03,0xb7,0xf3] +@ THUMB: vcvtm.s16.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x03] +@ THUMB: vcvtm.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03] +@ THUMB: vcvtm.u16.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x03] +@ THUMB: vcvtm.u16.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x03] + + vcvtn.s16.f16 d0, d1 + vcvtn.s16.f16 q0, q1 + vcvtn.u16.f16 d0, d1 + vcvtn.u16.f16 q0, q1 +@ ARM: vcvtn.s16.f16 d0, d1 @ encoding: [0x01,0x01,0xb7,0xf3] +@ ARM: vcvtn.s16.f16 q0, q1 @ encoding: [0x42,0x01,0xb7,0xf3] +@ ARM: vcvtn.u16.f16 d0, d1 @ encoding: [0x81,0x01,0xb7,0xf3] +@ ARM: vcvtn.u16.f16 q0, q1 @ encoding: [0xc2,0x01,0xb7,0xf3] +@ THUMB: vcvtn.s16.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x01] +@ THUMB: vcvtn.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01] +@ THUMB: vcvtn.u16.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x01] +@ THUMB: vcvtn.u16.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x01] + + vcvtp.s16.f16 d0, d1 + vcvtp.s16.f16 q0, q1 + vcvtp.u16.f16 d0, d1 + vcvtp.u16.f16 q0, q1 +@ ARM: vcvtp.s16.f16 d0, d1 @ encoding: [0x01,0x02,0xb7,0xf3] +@ ARM: vcvtp.s16.f16 q0, q1 @ encoding: [0x42,0x02,0xb7,0xf3] +@ ARM: vcvtp.u16.f16 d0, d1 @ encoding: [0x81,0x02,0xb7,0xf3] +@ ARM: vcvtp.u16.f16 q0, q1 @ encoding: [0xc2,0x02,0xb7,0xf3] +@ THUMB: vcvtp.s16.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x02] +@ THUMB: vcvtp.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x02] +@ THUMB: vcvtp.u16.f16 d0, d1 @ encoding: [0xb7,0xff,0x81,0x02] +@ THUMB: vcvtp.u16.f16 q0, q1 @ encoding: [0xb7,0xff,0xc2,0x02] + + + vcvt.s16.f16 d0, d1, #1 + vcvt.u16.f16 d0, d1, #2 + vcvt.f16.s16 d0, d1, #3 + vcvt.f16.u16 d0, d1, #4 + vcvt.s16.f16 q0, q1, #5 + vcvt.u16.f16 q0, q1, #6 + vcvt.f16.s16 q0, q1, #7 + vcvt.f16.u16 q0, q1, #8 +@ ARM: vcvt.s16.f16 d0, d1, #1 @ encoding: [0x11,0x0d,0xbf,0xf2] +@ ARM: vcvt.u16.f16 d0, d1, #2 @ encoding: [0x11,0x0d,0xbe,0xf3] +@ ARM: vcvt.f16.s16 d0, d1, #3 @ encoding: [0x11,0x0c,0xbd,0xf2] +@ ARM: vcvt.f16.u16 d0, d1, #4 @ encoding: [0x11,0x0c,0xbc,0xf3] +@ ARM: vcvt.s16.f16 q0, q1, #5 @ encoding: [0x52,0x0d,0xbb,0xf2] +@ ARM: vcvt.u16.f16 q0, q1, #6 @ encoding: [0x52,0x0d,0xba,0xf3] +@ ARM: vcvt.f16.s16 q0, q1, #7 @ encoding: [0x52,0x0c,0xb9,0xf2] +@ ARM: vcvt.f16.u16 q0, q1, #8 @ encoding: [0x52,0x0c,0xb8,0xf3] +@ THUMB: vcvt.s16.f16 d0, d1, #1 @ encoding: [0xbf,0xef,0x11,0x0d] +@ THUMB: vcvt.u16.f16 d0, d1, #2 @ encoding: [0xbe,0xff,0x11,0x0d] +@ THUMB: vcvt.f16.s16 d0, d1, #3 @ encoding: [0xbd,0xef,0x11,0x0c] +@ THUMB: vcvt.f16.u16 d0, d1, #4 @ encoding: [0xbc,0xff,0x11,0x0c] +@ THUMB: vcvt.s16.f16 q0, q1, #5 @ encoding: [0xbb,0xef,0x52,0x0d] +@ THUMB: vcvt.u16.f16 q0, q1, #6 @ encoding: [0xba,0xff,0x52,0x0d] +@ THUMB: vcvt.f16.s16 q0, q1, #7 @ encoding: [0xb9,0xef,0x52,0x0c] +@ THUMB: vcvt.f16.u16 q0, q1, #8 @ encoding: [0xb8,0xff,0x52,0x0c] + + vrinta.f16.f16 d0, d1 + vrinta.f16.f16 q0, q1 +@ ARM: vrinta.f16 d0, d1 @ encoding: [0x01,0x05,0xb6,0xf3] +@ ARM: vrinta.f16 q0, q1 @ encoding: [0x42,0x05,0xb6,0xf3] +@ THUMB: vrinta.f16 d0, d1 @ encoding: [0xb6,0xff,0x01,0x05] +@ THUMB: vrinta.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x05] + + vrintm.f16.f16 d0, d1 + vrintm.f16.f16 q0, q1 +@ ARM: vrintm.f16 d0, d1 @ encoding: [0x81,0x06,0xb6,0xf3] +@ ARM: vrintm.f16 q0, q1 @ encoding: [0xc2,0x06,0xb6,0xf3] +@ THUMB: vrintm.f16 d0, d1 @ encoding: [0xb6,0xff,0x81,0x06] +@ THUMB: vrintm.f16 q0, q1 @ encoding: [0xb6,0xff,0xc2,0x06] + + vrintn.f16.f16 d0, d1 + vrintn.f16.f16 q0, q1 +@ ARM: vrintn.f16 d0, d1 @ encoding: [0x01,0x04,0xb6,0xf3] +@ ARM: vrintn.f16 q0, q1 @ encoding: [0x42,0x04,0xb6,0xf3] +@ THUMB: vrintn.f16 d0, d1 @ encoding: [0xb6,0xff,0x01,0x04] +@ THUMB: vrintn.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x04] + + vrintp.f16.f16 d0, d1 + vrintp.f16.f16 q0, q1 +@ ARM: vrintp.f16 d0, d1 @ encoding: [0x81,0x07,0xb6,0xf3] +@ ARM: vrintp.f16 q0, q1 @ encoding: [0xc2,0x07,0xb6,0xf3] +@ THUMB: vrintp.f16 d0, d1 @ encoding: [0xb6,0xff,0x81,0x07] +@ THUMB: vrintp.f16 q0, q1 @ encoding: [0xb6,0xff,0xc2,0x07] + + vrintx.f16.f16 d0, d1 + vrintx.f16.f16 q0, q1 +@ ARM: vrintx.f16 d0, d1 @ encoding: [0x81,0x04,0xb6,0xf3] +@ ARM: vrintx.f16 q0, q1 @ encoding: [0xc2,0x04,0xb6,0xf3] +@ THUMB: vrintx.f16 d0, d1 @ encoding: [0xb6,0xff,0x81,0x04] +@ THUMB: vrintx.f16 q0, q1 @ encoding: [0xb6,0xff,0xc2,0x04] + + vrintz.f16.f16 d0, d1 + vrintz.f16.f16 q0, q1 +@ ARM: vrintz.f16 d0, d1 @ encoding: [0x81,0x05,0xb6,0xf3] +@ ARM: vrintz.f16 q0, q1 @ encoding: [0xc2,0x05,0xb6,0xf3] +@ THUMB: vrintz.f16 d0, d1 @ encoding: [0xb6,0xff,0x81,0x05] +@ THUMB: vrintz.f16 q0, q1 @ encoding: [0xb6,0xff,0xc2,0x05] diff --git a/test/MC/ARM/neon-vcvt-fp16.s b/test/MC/ARM/neon-vcvt-fp16.s new file mode 100644 index 000000000000..a23be061c0fa --- /dev/null +++ b/test/MC/ARM/neon-vcvt-fp16.s @@ -0,0 +1,18 @@ +@ RUN: llvm-mc -mcpu=cortex-r7 -triple arm -show-encoding < %s 2>&1| \ +@ RUN: FileCheck %s --check-prefix=CHECK-FP16 +@ RUN: not llvm-mc -mcpu=cortex-r5 -triple arm -show-encoding < %s 2>&1 | \ +@ RUN: FileCheck %s --check-prefix=CHECK-NOFP16 + +@ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtt.f32.f16 s7, s1 +@ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtt.f16.f32 s1, s7 + +@ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtb.f32.f16 s7, s1 +@ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee] +@ CHECK-NOFP16: instruction requires: half-float conversions + vcvtb.f16.f32 s1, s7 diff --git a/test/MC/ARM/thumb-branches.s b/test/MC/ARM/thumb-branches.s new file mode 100644 index 000000000000..b4cdfa12a556 --- /dev/null +++ b/test/MC/ARM/thumb-branches.s @@ -0,0 +1,25 @@ +@ RUN: llvm-mc < %s -triple thumbv5-linux-gnueabi -filetype=obj -o - \ +@ RUN: | llvm-readobj -r | FileCheck %s + + + bl end + .space 0x3fffff +end: + + bl end2 + .space 0x3fffff + .global end2 +end2: + + bl end3 + .space 0x400000 + .global end3 +end3: + + bl end4 + .space 0x400000 +end4: + +@ CHECK: 0x400003 R_ARM_THM_CALL end2 0x0 +@ CHECK: 0x800006 R_ARM_THM_CALL end3 0x0 +@ CHECK: 0xC0000A R_ARM_THM_CALL end4 0x0 diff --git a/test/MC/ARM/thumb-shift-encoding.s b/test/MC/ARM/thumb-shift-encoding.s index 54284132b653..ad35aff45055 100644 --- a/test/MC/ARM/thumb-shift-encoding.s +++ b/test/MC/ARM/thumb-shift-encoding.s @@ -6,40 +6,40 @@ sbc.w r12, lr, r0 sbc.w r1, r8, r9, lsr #32 - sbc.w r2, r7, pc, lsr #16 + sbc.w r2, r7, r10, lsr #16 sbc.w r3, r6, r10, lsl #0 sbc.w r4, r5, lr, lsl #16 sbc.w r5, r4, r11, asr #32 - sbc.w r6, r3, sp, asr #16 + sbc.w r6, r3, r12, asr #16 sbc.w r7, r2, r12, rrx sbc.w r8, r1, r0, ror #16 @ CHECK: sbc.w r12, lr, r0 @ encoding: [0x6e,0xeb,0x00,0x0c] @ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01] -@ CHECK: sbc.w r2, r7, pc, lsr #16 @ encoding: [0x67,0xeb,0x1f,0x42] +@ CHECK: sbc.w r2, r7, r10, lsr #16 @ encoding: [0x67,0xeb,0x1a,0x42] @ CHECK: sbc.w r3, r6, r10 @ encoding: [0x66,0xeb,0x0a,0x03] @ CHECK: sbc.w r4, r5, lr, lsl #16 @ encoding: [0x65,0xeb,0x0e,0x44] @ CHECK: sbc.w r5, r4, r11, asr #32 @ encoding: [0x64,0xeb,0x2b,0x05] -@ CHECK: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46] +@ CHECK: sbc.w r6, r3, r12, asr #16 @ encoding: [0x63,0xeb,0x2c,0x46] @ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07] @ CHECK: sbc.w r8, r1, r0, ror #16 @ encoding: [0x61,0xeb,0x30,0x48] and.w r12, lr, r0 and.w r1, r8, r9, lsr #32 - and.w r2, r7, pc, lsr #16 + and.w r2, r7, r10, lsr #16 and.w r3, r6, r10, lsl #0 and.w r4, r5, lr, lsl #16 and.w r5, r4, r11, asr #32 - and.w r6, r3, sp, asr #16 + and.w r6, r3, r12, asr #16 and.w r7, r2, r12, rrx and.w r8, r1, r0, ror #16 @ CHECK: and.w r12, lr, r0 @ encoding: [0x0e,0xea,0x00,0x0c] @ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01] -@ CHECK: and.w r2, r7, pc, lsr #16 @ encoding: [0x07,0xea,0x1f,0x42] +@ CHECK: and.w r2, r7, r10, lsr #16 @ encoding: [0x07,0xea,0x1a,0x42] @ CHECK: and.w r3, r6, r10 @ encoding: [0x06,0xea,0x0a,0x03] @ CHECK: and.w r4, r5, lr, lsl #16 @ encoding: [0x05,0xea,0x0e,0x44] @ CHECK: and.w r5, r4, r11, asr #32 @ encoding: [0x04,0xea,0x2b,0x05] -@ CHECK: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46] +@ CHECK: and.w r6, r3, r12, asr #16 @ encoding: [0x03,0xea,0x2c,0x46] @ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07] @ CHECK: and.w r8, r1, r0, ror #16 @ encoding: [0x01,0xea,0x30,0x48] diff --git a/test/MC/ARM/thumb1-relax.s b/test/MC/ARM/thumb1-relax.s new file mode 100644 index 000000000000..ba261aa26356 --- /dev/null +++ b/test/MC/ARM/thumb1-relax.s @@ -0,0 +1,35 @@ +@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple thumbv6m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s + +Lhere: +@ CHECK: out of range pc-relative fixup value + ldr r0, Lhere + +@ CHECK: out of range pc-relative fixup value + b Lfar2 + +@ CHECK: out of range pc-relative fixup value + bne Lfar1 + +@ CHECK: out of range pc-relative fixup value + ldr r0, Lfar2 + +@ CHECK: misaligned pc-relative fixup value + adr r0, Lmisaligned + +@ CHECK: misaligned pc-relative fixup value + ldr r0, Lmisaligned + + .balign 4 + .short 0 +Lmisaligned: + .word 42 + + .space 256 +Lfar1: + .word 42 + + .space 2050 +Lfar2: + .word 42 + diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s index 8fd161c2cc53..96978899faa2 100644 --- a/test/MC/ARM/thumb2-diagnostics.s +++ b/test/MC/ARM/thumb2-diagnostics.s @@ -1,5 +1,8 @@ @ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s +@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s + +@ RUN: not llvm-mc -triple=thumbv8-apple-darwin < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s @ Ill-formed IT block instructions. itet eq @@ -41,7 +44,8 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: immediate operand must be in the range [0,15] -@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V8: error: invalid operand for instruction isb #-1 isb #16 @@ -87,7 +91,14 @@ foo2: @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction -ssat r0, #1, r0, asr #32 -usat r0, #1, r0, asr #32 + ssat r0, #1, r0, asr #32 + usat r0, #1, r0, asr #32 @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode + + @ PC is not valid as shifted-rGPR + sbc.w r2, r7, pc, lsr #16 + and.w r2, r7, pc, lsr #16 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction + diff --git a/test/MC/ARM/v7k-dsp.s b/test/MC/ARM/v7k-dsp.s new file mode 100644 index 000000000000..cf5101746389 --- /dev/null +++ b/test/MC/ARM/v7k-dsp.s @@ -0,0 +1,4 @@ +@ RUN: llvm-mc -triple thumbv7k-apple-watchos2.0 %s | FileCheck %s + +@ CHECK: usad8 r2, r1, r4 + usad8 r2, r1, r4 |