diff options
Diffstat (limited to 'test/Transforms/InstSimplify/AndOrXor.ll')
| -rw-r--r-- | test/Transforms/InstSimplify/AndOrXor.ll | 76 |
1 files changed, 62 insertions, 14 deletions
diff --git a/test/Transforms/InstSimplify/AndOrXor.ll b/test/Transforms/InstSimplify/AndOrXor.ll index 251b4dea63b5..ed68f1121278 100644 --- a/test/Transforms/InstSimplify/AndOrXor.ll +++ b/test/Transforms/InstSimplify/AndOrXor.ll @@ -999,28 +999,26 @@ define i64 @shl_or_and2(i32 %a, i1 %b) { ret i64 %tmp5 } -define i32 @shl_or_and3(i32 %a, i32 %b) { ; concatinate two 32-bit integers and extract lower 32-bit +define i64 @shl_or_and3(i32 %a, i32 %b) { ; CHECK-LABEL: @shl_or_and3( ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967295 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -; CHECK-NEXT: ret i32 [[TMP6]] +; CHECK-NEXT: ret i64 [[TMP5]] ; %tmp1 = zext i32 %a to i64 %tmp2 = zext i32 %b to i64 %tmp3 = shl nuw i64 %tmp1, 32 %tmp4 = or i64 %tmp2, %tmp3 %tmp5 = and i64 %tmp4, 4294967295 - %tmp6 = trunc i64 %tmp5 to i32 - ret i32 %tmp6 + ret i64 %tmp5 } -define i32 @shl_or_and4(i16 %a, i16 %b) { ; concatinate two 16-bit integers and extract higher 16-bit +define i32 @shl_or_and4(i16 %a, i16 %b) { ; CHECK-LABEL: @shl_or_and4( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1037,27 +1035,25 @@ define i32 @shl_or_and4(i16 %a, i16 %b) { ret i32 %tmp5 } -define i64 @shl_or_and5(i64 %a, i1 %b) { +define i128 @shl_or_and5(i64 %a, i1 %b) { ; CHECK-LABEL: @shl_or_and5( ; CHECK-NEXT: [[TMP1:%.*]] = zext i64 [[A:%.*]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i128 [[TMP1]], 64 ; CHECK-NEXT: [[TMP4:%.*]] = or i128 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = and i128 [[TMP4]], 1 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i64 -; CHECK-NEXT: ret i64 [[TMP6]] +; CHECK-NEXT: ret i128 [[TMP5]] ; %tmp1 = zext i64 %a to i128 %tmp2 = zext i1 %b to i128 %tmp3 = shl nuw i128 %tmp1, 64 %tmp4 = or i128 %tmp2, %tmp3 %tmp5 = and i128 %tmp4, 1 - %tmp6 = trunc i128 %tmp5 to i64 - ret i64 %tmp6 + ret i128 %tmp5 } +; A variation of above test cases; it fails due to the mask value define i32 @shl_or_and6(i16 %a, i16 %b) { -; A variation of above test case, but fails due to the mask value ; CHECK-LABEL: @shl_or_and6( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1074,8 +1070,8 @@ define i32 @shl_or_and6(i16 %a, i16 %b) { ret i32 %tmp5 } +; A variation of above test cases; it fails due to the mask value define i32 @shl_or_and7(i16 %a, i16 %b) { -; A variation of above test case, but fails due to the mask value ; CHECK-LABEL: @shl_or_and7( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1092,8 +1088,8 @@ define i32 @shl_or_and7(i16 %a, i16 %b) { ret i32 %tmp5 } +; A variation of above test cases; it fails due to the mask value define i32 @shl_or_and8(i16 %a, i16 %b) { -; A variation of above test case, but fails due to the mask value ; CHECK-LABEL: @shl_or_and8( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1109,3 +1105,55 @@ define i32 @shl_or_and8(i16 %a, i16 %b) { %tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF ret i32 %tmp5 } + +define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) { +; CHECK-LABEL: @shl_or_and1v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 1, i64 1> +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i32> %a to <2 x i64> + %tmp2 = zext <2 x i1> %b to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32> + %tmp4 = or <2 x i64> %tmp3, %tmp2 + %tmp5 = and <2 x i64> %tmp4, <i64 1, i64 1> + ret <2 x i64> %tmp5 +} + +define <2 x i64> @shl_or_and2v(<2 x i32> %a, <2 x i1> %b) { +; CHECK-LABEL: @shl_or_and2v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967296, i64 4294967296> +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i1> %b to <2 x i64> + %tmp2 = zext <2 x i32> %a to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32> + %tmp4 = or <2 x i64> %tmp2, %tmp3 + %tmp5 = and <2 x i64> %tmp4, <i64 4294967296, i64 4294967296> + ret <2 x i64> %tmp5 +} + +define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) { +; A variation of above test case, but fails due to the mask value +; CHECK-LABEL: @shl_or_and3v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i32> [[TMP1]], <i32 16, i32 16> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP4]], <i32 -65535, i32 -65535> +; CHECK-NEXT: ret <2 x i32> [[TMP5]] +; + %tmp1 = zext <2 x i16> %a to <2 x i32> + %tmp2 = zext <2 x i16> %b to <2 x i32> + %tmp3 = shl nuw <2 x i32> %tmp1, <i32 16, i32 16> + %tmp4 = or <2 x i32> %tmp2, %tmp3 + %tmp5 = and <2 x i32> %tmp4, <i32 4294901761, i32 4294901761> ; mask with 0xFFFF0001 + ret <2 x i32> %tmp5 +} |