diff options
Diffstat (limited to 'test')
26 files changed, 980 insertions, 155 deletions
diff --git a/test/Analysis/BasicAA/tail-byval.ll b/test/Analysis/BasicAA/tail-byval.ll new file mode 100644 index 000000000000..0aa8dfdaedff --- /dev/null +++ b/test/Analysis/BasicAA/tail-byval.ll @@ -0,0 +1,15 @@ +; RUN: opt -basicaa -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s + +declare void @takebyval(i32* byval %p) + +define i32 @tailbyval() { +entry: + %p = alloca i32 + store i32 42, i32* %p + tail call void @takebyval(i32* byval %p) + %rv = load i32, i32* %p + ret i32 %rv +} +; FIXME: This should be Just Ref. +; CHECK-LABEL: Function: tailbyval: 1 pointers, 1 call sites +; CHECK-NEXT: Both ModRef: Ptr: i32* %p <-> tail call void @takebyval(i32* byval %p) diff --git a/test/BugPoint/compile-custom.ll b/test/BugPoint/compile-custom.ll index 004470943746..cb82a01383e1 100755 --- a/test/BugPoint/compile-custom.ll +++ b/test/BugPoint/compile-custom.ll @@ -1,4 +1,4 @@ -; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext --compile-custom --compile-command="%python %/s.py arg1 arg2" --opt-command opt --output-prefix %t %s | FileCheck %s +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext --compile-custom --compile-command="%/s.py arg1 arg2" --opt-command opt --output-prefix %t %s | FileCheck %s ; REQUIRES: loadable_module ; Test that arguments are correctly passed in --compile-command. The output diff --git a/test/BugPoint/unsymbolized.ll b/test/BugPoint/unsymbolized.ll index ae47682195bb..da26b9dc4808 100644 --- a/test/BugPoint/unsymbolized.ll +++ b/test/BugPoint/unsymbolized.ll @@ -2,7 +2,7 @@ ; RUN: echo "import sys" > %t.py ; RUN: echo "print('args = ' + str(sys.argv))" >> %t.py ; RUN: echo "exit(1)" >> %t.py -; RUN: not bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -opt-command="%python" -opt-args %t.py | FileCheck %s +; RUN: not bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -opt-command=%python -opt-args %t.py | FileCheck %s ; RUN: not --crash opt -load %llvmshlibdir/BugpointPasses%shlibext %s -bugpoint-crashcalls -disable-symbolication 2>&1 | FileCheck --check-prefix=CRASH %s ; RUN: not bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -opt-command=%t.non.existent.opt.binary -opt-args %t.py 2>&1 | FileCheck %s --check-prefix=BAD-OPT diff --git a/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll b/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll new file mode 100644 index 000000000000..6f7fb53f76ce --- /dev/null +++ b/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll @@ -0,0 +1,30 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck %s + +; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR +; with DemandedElts already as wide as the source vector. + +define <3 x i32> @quux() #0 { +; CHECK-LABEL: quux: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 1 +; CHECK-NEXT: v_mov_b32_e32 v2, 1 +; CHECK-NEXT: s_setpc_b64 s[30:31] +bb: + %tmp = shufflevector <4 x i8> <i8 1, i8 2, i8 3, i8 4>, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> + %tmp1 = extractelement <3 x i8> %tmp, i64 0 + %tmp2 = zext i8 %tmp1 to i32 + %tmp3 = insertelement <3 x i32> undef, i32 %tmp2, i32 0 + %tmp4 = extractelement <3 x i8> %tmp, i64 1 + %tmp5 = zext i8 %tmp4 to i32 + %tmp6 = insertelement <3 x i32> %tmp3, i32 %tmp5, i32 1 + %tmp7 = extractelement <3 x i8> %tmp, i64 2 + %tmp8 = zext i8 %tmp7 to i32 + %tmp9 = insertelement <3 x i32> %tmp6, i32 %tmp8, i32 2 + %tmp10 = lshr <3 x i32> %tmp9, <i32 1, i32 1, i32 1> + ret <3 x i32> %tmp10 +} + +attributes #0 = { noinline optnone } diff --git a/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll b/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll deleted file mode 100644 index 45bdb124e032..000000000000 --- a/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll +++ /dev/null @@ -1,122 +0,0 @@ -; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s - -; Check support for returning a float in GPR with soft float ABI -define arm_aapcscc float @zerobits_float_soft() #0 { -; CHECK-LABEL: zerobits_float_soft -; CHECK: mov r0, #0 - %1 = tail call float asm "mov ${0}, #0", "=&r"() - ret float %1 -} - -; Check support for returning a double in GPR with soft float ABI -define arm_aapcscc double @zerobits_double_soft() #0 { -; CHECK-LABEL: zerobits_double_soft -; CHECK: mov r0, #0 -; CHECK-NEXT: mov r1, #0 - %1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"() - ret double %1 -} - -; Check support for returning a float in GPR with matching float input with -; soft float ABI -define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 { -; CHECK-LABEL: flt_gpr_matching_in_op_soft -; CHECK: mov r0, r0 - %1 = call float asm "mov $0, $1", "=&r,0"(float %f) - ret float %1 -} - -; Check support for returning a double in GPR with matching double input with -; soft float ABI -define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 { -; CHECK-LABEL: dbl_gpr_matching_in_op_soft -; CHECK: mov r1, r0 - %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d) - ret double %1 -} - -; Check support for returning a float in specific GPR with matching float input -; with soft float ABI -define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 { -; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft -; CHECK: mov r3, r3 - %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f) - ret float %1 -} - -; Check support for returning a double in specific GPR with matching double -; input with soft float ABI -define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 { -; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft -; CHECK: mov r3, r2 - %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d) - ret double %1 -} - -attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="true" } - - -; Check support for returning a float in GPR with hard float ABI -define float @zerobits_float_hard() #1 { -; CHECK-LABEL: zerobits_float_hard -; CHECK: mov r0, #0 -; CHECK: vmov s0, r0 - %1 = tail call float asm "mov ${0}, #0", "=&r"() - ret float %1 -} - -; Check support for returning a double in GPR with hard float ABI -define double @zerobits_double_hard() #1 { -; CHECK-LABEL: zerobits_double_hard -; CHECK: mov r0, #0 -; CHECK-NEXT: mov r1, #0 -; CHECK: vmov d0, r0, r1 - %1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"() - ret double %1 -} - -; Check support for returning a float in GPR with matching float input with -; hard float ABI -define float @flt_gpr_matching_in_op_hard(float %f) #1 { -; CHECK-LABEL: flt_gpr_matching_in_op_hard -; CHECK: vmov r0, s0 -; CHECK: mov r0, r0 -; CHECK: vmov s0, r0 - %1 = call float asm "mov $0, $1", "=&r,0"(float %f) - ret float %1 -} - -; Check support for returning a double in GPR with matching double input with -; hard float ABI -define double @dbl_gpr_matching_in_op_hard(double %d) #1 { -; CHECK-LABEL: dbl_gpr_matching_in_op_hard -; CHECK: vmov r0, r1, d0 -; CHECK: mov r1, r0 -; CHECK: vmov d0, r0, r1 - %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d) - ret double %1 -} - -; Check support for returning a float in specific GPR with matching float -; input with hard float ABI -define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 { -; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard -; CHECK: vmov r3, s0 -; CHECK: mov r3, r3 -; CHECK: vmov s0, r3 - %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f) - ret float %1 -} - -; Check support for returning a double in specific GPR with matching double -; input with hard float ABI -define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 { -; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard -; CHECK: vmov r2, r3, d0 -; CHECK: mov r3, r2 -; CHECK: vmov d0, r2, r3 - %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d) - ret double %1 -} - -attributes #1 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll b/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll new file mode 100644 index 000000000000..7b98f0f0de31 --- /dev/null +++ b/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll @@ -0,0 +1,307 @@ +; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s + +%struct.twofloat = type { float, float } +%struct.twodouble = type { double, double } + +; Check support for returning a float in GPR with soft float ABI +define arm_aapcscc float @zerobits_float_soft() #0 { +; CHECK-LABEL: zerobits_float_soft +; CHECK: mov r0, #0 + %1 = tail call float asm "mov ${0}, #0", "=&r"() + ret float %1 +} + +; Check support for returning a double in GPR with soft float ABI +define arm_aapcscc double @zerobits_double_soft() #0 { +; CHECK-LABEL: zerobits_double_soft +; CHECK: mov r0, #0 +; CHECK-NEXT: mov r1, #0 + %1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"() + ret double %1 +} + +; Check support for returning a float in GPR with matching float input with +; soft float ABI +define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 { +; CHECK-LABEL: flt_gpr_matching_in_op_soft +; CHECK: mov r0, r0 + %1 = call float asm "mov $0, $1", "=&r,0"(float %f) + ret float %1 +} + +; Check support for returning a double in GPR with matching double input with +; soft float ABI +define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 { +; CHECK-LABEL: dbl_gpr_matching_in_op_soft +; CHECK: mov r1, r0 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d) + ret double %1 +} + +; Check support for returning a float in specific GPR with matching float input +; with soft float ABI +define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 { +; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft +; CHECK: mov r3, r3 + %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f) + ret float %1 +} + +; Check support for returning a double in specific GPR with matching double +; input with soft float ABI +define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 { +; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft +; CHECK: mov r3, r2 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d) + ret double %1 +} + +; Check support for returning several float in GPR +define arm_aapcscc float @zerobits_float_convoluted_soft() #0 { +; CHECK-LABEL: zerobits_float_convoluted_soft +; CHECK: mov r0, #0 +; CHECK-NEXT: mov r1, #0 + %1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"() + %asmresult = extractvalue { float, float } %1, 0 + %asmresult1 = extractvalue { float, float } %1, 1 + %add = fadd float %asmresult, %asmresult1 + ret float %add +} + +; Check support for returning several double in GPR +define double @zerobits_double_convoluted_soft() #0 { +; CHECK-LABEL: zerobits_double_convoluted_soft +; CHECK: mov r0, #0 +; CHECK-NEXT: mov r1, #0 +; CHECK-NEXT: mov r2, #0 +; CHECK-NEXT: mov r3, #0 + %1 = call { double, double } asm "mov ${0:Q}, #0; mov ${0:R}, #0; mov ${1:Q}, #0; mov ${1:R}, #0", "=r,=r"() + %asmresult = extractvalue { double, double } %1, 0 + %asmresult1 = extractvalue { double, double } %1, 1 + %add = fadd double %asmresult, %asmresult1 + ret double %add +} + +; Check support for returning several floats in GPRs with matching float inputs +; with soft float ABI +define arm_aapcscc float @flt_gprs_matching_in_op_soft(float %f1, float %f2) #0 { +; CHECK-LABEL: flt_gprs_matching_in_op_soft +; CHECK: mov r0, r0 +; CHECK-NEXT: mov r1, r1 + %1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&r,=&r,0,1"(float %f1, float %f2) + %asmresult1 = extractvalue { float, float } %1, 0 + %asmresult2 = extractvalue { float, float } %1, 1 + %add = fadd float %asmresult1, %asmresult2 + ret float %add +} + +; Check support for returning several double in GPRs with matching double input +; with soft float ABI +define arm_aapcscc double @dbl_gprs_matching_in_op_soft(double %d1, double %d2) #0 { +; CHECK-LABEL: dbl_gprs_matching_in_op_soft +; CHECK: mov r1, r0 +; CHECK-NEXT: mov r3, r2 + %1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&r,=&r,0,1"(double %d1, double %d2) + %asmresult1 = extractvalue { double, double } %1, 0 + %asmresult2 = extractvalue { double, double } %1, 1 + %add = fadd double %asmresult1, %asmresult2 + ret double %add +} + +; Check support for returning several float in specific GPRs with matching +; float input with soft float ABI +define arm_aapcscc float @flt_gprs_matching_spec_reg_in_op_soft(float %f1, float %f2) #0 { +; CHECK-LABEL: flt_gprs_matching_spec_reg_in_op_soft +; CHECK: mov r3, r3 +; CHECK-NEXT: mov r4, r4 + %1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&{r3},=&{r4},0,1"(float %f1, float %f2) + %asmresult1 = extractvalue { float, float } %1, 0 + %asmresult2 = extractvalue { float, float } %1, 1 + %add = fadd float %asmresult1, %asmresult2 + ret float %add +} + +; Check support for returning several double in specific GPRs with matching +; double input with soft float ABI +define arm_aapcscc double @dbl_gprs_matching_spec_reg_in_op_soft(double %d1, double %d2) #0 { +; CHECK-LABEL: dbl_gprs_matching_spec_reg_in_op_soft +; CHECK: mov r3, r2 +; CHECK-NEXT: mov r5, r4 + %1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&{r2},=&{r4},0,1"(double %d1, double %d2) + %asmresult1 = extractvalue { double, double } %1, 0 + %asmresult2 = extractvalue { double, double } %1, 1 + %add = fadd double %asmresult1, %asmresult2 + ret double %add +} + +attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="true" } + + +; Check support for returning a float in GPR with hard float ABI +define float @zerobits_float_hard() #1 { +; CHECK-LABEL: zerobits_float_hard +; CHECK: mov r0, #0 +; CHECK: vmov s0, r0 + %1 = tail call float asm "mov ${0}, #0", "=&r"() + ret float %1 +} + +; Check support for returning a double in GPR with hard float ABI +define double @zerobits_double_hard() #1 { +; CHECK-LABEL: zerobits_double_hard +; CHECK: mov r0, #0 +; CHECK-NEXT: mov r1, #0 +; CHECK: vmov d0, r0, r1 + %1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"() + ret double %1 +} + +; Check support for returning a float in GPR with matching float input with +; hard float ABI +define float @flt_gpr_matching_in_op_hard(float %f) #1 { +; CHECK-LABEL: flt_gpr_matching_in_op_hard +; CHECK: vmov r0, s0 +; CHECK: mov r0, r0 +; CHECK: vmov s0, r0 + %1 = call float asm "mov $0, $1", "=&r,0"(float %f) + ret float %1 +} + +; Check support for returning a double in GPR with matching double input with +; hard float ABI +define double @dbl_gpr_matching_in_op_hard(double %d) #1 { +; CHECK-LABEL: dbl_gpr_matching_in_op_hard +; CHECK: vmov r0, r1, d0 +; CHECK: mov r1, r0 +; CHECK: vmov d0, r0, r1 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d) + ret double %1 +} + +; Check support for returning a float in specific GPR with matching float +; input with hard float ABI +define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 { +; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard +; CHECK: vmov r3, s0 +; CHECK: mov r3, r3 +; CHECK: vmov s0, r3 + %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f) + ret float %1 +} + +; Check support for returning a double in specific GPR with matching double +; input with hard float ABI +define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 { +; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard +; CHECK: vmov r2, r3, d0 +; CHECK: mov r3, r2 +; CHECK: vmov d0, r2, r3 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d) + ret double %1 +} + +; Check support for returning several float in GPR +define %struct.twofloat @zerobits_float_convoluted_hard() #1 { +; CHECK-LABEL: zerobits_float_convoluted_hard +; CHECK: mov r0, #0 +; CHECK-NEXT: mov r1, #0 +; CHECK: vmov s0, r0 +; CHECK-NEXT: vmov s1, r1 + %1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"() + %asmresult1 = extractvalue { float, float } %1, 0 + %asmresult2 = extractvalue { float, float } %1, 1 + %partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0 + %res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1 + ret %struct.twofloat %res +} + +; Check support for returning several double in GPR +define %struct.twodouble @zerobits_double_convoluted_hard() #1 { +; CHECK-LABEL: zerobits_double_convoluted_hard +; CHECK: mov r0, #0 +; CHECK-NEXT: mov r1, #0 +; CHECK-NEXT: mov r2, #0 +; CHECK-NEXT: mov r3, #0 +; CHECK: vmov d0, r0, r1 +; CHECK-NEXT: vmov d1, r2, r3 + %1 = call { double, double } asm "mov ${0:Q}, #0; mov ${0:R}, #0; mov ${1:Q}, #0; mov ${1:R}, #0", "=r,=r"() + %asmresult1 = extractvalue { double, double } %1, 0 + %asmresult2 = extractvalue { double, double } %1, 1 + %partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0 + %res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1 + ret %struct.twodouble %res +} + +; Check support for returning several floats in GPRs with matching float inputs +; with hard float ABI +define %struct.twofloat @flt_gprs_matching_in_op_hard(float %f1, float %f2) #1 { +; CHECK-LABEL: flt_gprs_matching_in_op_hard +; CHECK: vmov r0, s0 +; CHECK-NEXT: vmov r1, s1 +; CHECK: mov r0, r0 +; CHECK-NEXT: mov r1, r1 +; CHECK: vmov s0, r0 +; CHECK-NEXT: vmov s1, r1 + %1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&r,=&r,0,1"(float %f1, float %f2) + %asmresult1 = extractvalue { float, float } %1, 0 + %asmresult2 = extractvalue { float, float } %1, 1 + %partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0 + %res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1 + ret %struct.twofloat %res +} + +; Check support for returning several double in GPRs with matching double input +; with hard float ABI +define %struct.twodouble @dbl_gprs_matching_in_op_hard(double %d1, double %d2) #1 { +; CHECK-LABEL: dbl_gprs_matching_in_op_hard +; CHECK: vmov r0, r1, d0 +; CHECK-NEXT: vmov r2, r3, d1 +; CHECK: mov r1, r0 +; CHECK-NEXT: mov r3, r2 +; CHECK: vmov d0, r0, r1 +; CHECK-NEXT: vmov d1, r2, r3 + %1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&r,=&r,0,1"(double %d1, double %d2) + %asmresult1 = extractvalue { double, double } %1, 0 + %asmresult2 = extractvalue { double, double } %1, 1 + %partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0 + %res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1 + ret %struct.twodouble %res +} + +; Check support for returning several float in specific GPRs with matching +; float input with hard float ABI +define %struct.twofloat @flt_gprs_matching_spec_reg_in_op_hard(float %f1, float %f2) #1 { +; CHECK-LABEL: flt_gprs_matching_spec_reg_in_op_hard +; CHECK: vmov r3, s0 +; CHECK-NEXT: vmov r4, s1 +; CHECK: mov r3, r3 +; CHECK-NEXT: mov r4, r4 +; CHECK: vmov s0, r3 +; CHECK-NEXT: vmov s1, r4 + %1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&{r3},=&{r4},0,1"(float %f1, float %f2) + %asmresult1 = extractvalue { float, float } %1, 0 + %asmresult2 = extractvalue { float, float } %1, 1 + %partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0 + %res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1 + ret %struct.twofloat %res +} + +; Check support for returning several double in specific GPRs with matching +; double input with hard float ABI +define %struct.twodouble @dbl_gprs_matching_spec_reg_in_op_hard(double %d1, double %d2) #1 { +; CHECK-LABEL: dbl_gprs_matching_spec_reg_in_op_hard +; CHECK: vmov r2, r3, d0 +; CHECK-NEXT: vmov r4, r5, d1 +; CHECK: mov r3, r2 +; CHECK-NEXT: mov r5, r4 +; CHECK: vmov d0, r2, r3 +; CHECK-NEXT: vmov d1, r4, r5 + %1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&{r2},=&{r4},0,1"(double %d1, double %d2) + %asmresult1 = extractvalue { double, double } %1, 0 + %asmresult2 = extractvalue { double, double } %1, 1 + %partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0 + %res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1 + ret %struct.twodouble %res +} + +attributes #1 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/pr38087.ll b/test/CodeGen/PowerPC/pr38087.ll new file mode 100644 index 000000000000..af8704f7d708 --- /dev/null +++ b/test/CodeGen/PowerPC/pr38087.ll @@ -0,0 +1,56 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s | \ +; RUN: FileCheck %s +; Function Attrs: nounwind readnone speculatable +declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 + +; Function Attrs: nounwind readnone speculatable +declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #0 + +define void @draw_llvm_vs_variant0() { +; CHECK-LABEL: draw_llvm_vs_variant0: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ldx r3, 0, r3 +; CHECK-NEXT: mtvsrd f0, r3 +; CHECK-NEXT: xxswapd v2, vs0 +; CHECK-NEXT: vmrglh v2, v2, v2 +; CHECK-NEXT: vextsh2w v2, v2 +; CHECK-NEXT: xvcvsxwsp vs0, v2 +; CHECK-NEXT: xxspltw vs0, vs0, 2 +; CHECK-NEXT: xvmaddasp vs0, vs0, vs0 +; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: blr +entry: + %.size = load i32, i32* undef + %0 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %.size, i32 7) + %1 = extractvalue { i32, i1 } %0, 0 + %2 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %1, i32 0) + %3 = extractvalue { i32, i1 } %2, 0 + %4 = select i1 false, i32 0, i32 %3 + %5 = xor i1 false, true + %6 = sext i1 %5 to i32 + %7 = load <4 x i16>, <4 x i16>* undef, align 2 + %8 = extractelement <4 x i16> %7, i32 0 + %9 = sext i16 %8 to i32 + %10 = insertelement <4 x i32> undef, i32 %9, i32 0 + %11 = extractelement <4 x i16> %7, i32 1 + %12 = sext i16 %11 to i32 + %13 = insertelement <4 x i32> %10, i32 %12, i32 1 + %14 = extractelement <4 x i16> %7, i32 2 + %15 = sext i16 %14 to i32 + %16 = insertelement <4 x i32> %13, i32 %15, i32 2 + %17 = extractelement <4 x i16> %7, i32 3 + %18 = sext i16 %17 to i32 + %19 = insertelement <4 x i32> %16, i32 %18, i32 3 + %20 = sitofp <4 x i32> %19 to <4 x float> + %21 = insertelement <4 x i32> undef, i32 %6, i32 0 + %22 = shufflevector <4 x i32> %21, <4 x i32> undef, <4 x i32> zeroinitializer + %23 = bitcast <4 x float> %20 to <4 x i32> + %24 = and <4 x i32> %23, %22 + %25 = bitcast <4 x i32> %24 to <4 x float> + %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + %27 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> undef, <4 x float> %26) + store <4 x float> %27, <4 x float>* undef + ret void +} diff --git a/test/CodeGen/X86/flags-copy-lowering.mir b/test/CodeGen/X86/flags-copy-lowering.mir index d5991754d40b..98d6f21dc486 100644 --- a/test/CodeGen/X86/flags-copy-lowering.mir +++ b/test/CodeGen/X86/flags-copy-lowering.mir @@ -545,7 +545,7 @@ body: | MOV8mr $rsp, 1, $noreg, -16, $noreg, killed %4 ; CHECK-NOT: $eflags = ; CHECK: %[[ZERO:[^:]*]]:gr32 = MOV32r0 implicit-def $eflags - ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr8 = EXTRACT_SUBREG %[[ZERO]], %subreg.sub_8bit + ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr8 = COPY %[[ZERO]].sub_8bit ; CHECK-NEXT: %[[REPLACEMENT:[^:]*]]:gr8 = SUB8rr %[[ZERO_SUBREG]], %[[CF_REG]] ; CHECK-NEXT: MOV8mr $rsp, 1, $noreg, -16, $noreg, killed %[[REPLACEMENT]] @@ -554,9 +554,9 @@ body: | MOV16mr $rsp, 1, $noreg, -16, $noreg, killed %5 ; CHECK-NOT: $eflags = ; CHECK: %[[CF_EXT:[^:]*]]:gr32 = MOVZX32rr8 %[[CF_REG]] - ; CHECK-NEXT: %[[CF_TRUNC:[^:]*]]:gr16 = EXTRACT_SUBREG %[[CF_EXT]], %subreg.sub_16bit + ; CHECK-NEXT: %[[CF_TRUNC:[^:]*]]:gr16 = COPY %[[CF_EXT]].sub_16bit ; CHECK-NEXT: %[[ZERO:[^:]*]]:gr32 = MOV32r0 implicit-def $eflags - ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr16 = EXTRACT_SUBREG %[[ZERO]], %subreg.sub_16bit + ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr16 = COPY %[[ZERO]].sub_16bit ; CHECK-NEXT: %[[REPLACEMENT:[^:]*]]:gr16 = SUB16rr %[[ZERO_SUBREG]], %[[CF_TRUNC]] ; CHECK-NEXT: MOV16mr $rsp, 1, $noreg, -16, $noreg, killed %[[REPLACEMENT]] diff --git a/test/CodeGen/X86/pr38533.ll b/test/CodeGen/X86/pr38533.ll new file mode 100644 index 000000000000..96d003ba1a84 --- /dev/null +++ b/test/CodeGen/X86/pr38533.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX512 + +; This test makes sure that a vector that needs to be promoted that is bitcasted to fp16 is legalized correctly without causing a width mismatch. +define void @constant_fold_vector_to_half() { +; CHECK-LABEL: constant_fold_vector_to_half: +; CHECK: # %bb.0: +; CHECK-NEXT: movw $16384, (%rax) # imm = 0x4000 +; CHECK-NEXT: retq + store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef + ret void +} + +; Similarly this makes sure that the opposite bitcast of the above is also legalized without crashing. +define void @pr38533_2(half %x) { +; SSE-LABEL: pr38533_2: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rax +; SSE-NEXT: .cfi_def_cfa_offset 16 +; SSE-NEXT: callq __gnu_f2h_ieee +; SSE-NEXT: movw %ax, {{[0-9]+}}(%rsp) +; SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; SSE-NEXT: movw %ax, (%rax) +; SSE-NEXT: popq %rax +; SSE-NEXT: .cfi_def_cfa_offset 8 +; SSE-NEXT: retq +; +; AVX512-LABEL: pr38533_2: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: movw %ax, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax +; AVX512-NEXT: movw %ax, (%rax) +; AVX512-NEXT: retq + %a = bitcast half %x to <4 x i4> + store volatile <4 x i4> %a, <4 x i4>* undef + ret void +} + +; This case is a bitcast from fp16 to a 16-bit wide legal vector type. In this case the result type is legal when the bitcast gets type legalized. +define void @pr38533_3(half %x) { +; SSE-LABEL: pr38533_3: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rax +; SSE-NEXT: .cfi_def_cfa_offset 16 +; SSE-NEXT: callq __gnu_f2h_ieee +; SSE-NEXT: movw %ax, (%rsp) +; SSE-NEXT: movzwl (%rsp), %eax +; SSE-NEXT: movw %ax, (%rax) +; SSE-NEXT: popq %rax +; SSE-NEXT: .cfi_def_cfa_offset 8 +; SSE-NEXT: retq +; +; AVX512-LABEL: pr38533_3: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: movw %ax, (%rax) +; AVX512-NEXT: retq + %a = bitcast half %x to <16 x i1> + store volatile <16 x i1> %a, <16 x i1>* undef + ret void +} diff --git a/test/CodeGen/X86/pr38539.ll b/test/CodeGen/X86/pr38539.ll new file mode 100644 index 000000000000..7a871a9f1177 --- /dev/null +++ b/test/CodeGen/X86/pr38539.ll @@ -0,0 +1,314 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -verify-machineinstrs | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=i686-unknown -verify-machineinstrs | FileCheck %s --check-prefix=X86 + +; This test is targeted at 64-bit mode. It used to crash due to the creation of an EXTRACT_SUBREG after the peephole pass had ran. +define void @f() { +; X64-LABEL: f: +; X64: # %bb.0: # %BB +; X64-NEXT: pushq %rbp +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: pushq %r14 +; X64-NEXT: .cfi_def_cfa_offset 24 +; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 32 +; X64-NEXT: subq $16, %rsp +; X64-NEXT: .cfi_def_cfa_offset 48 +; X64-NEXT: .cfi_offset %rbx, -32 +; X64-NEXT: .cfi_offset %r14, -24 +; X64-NEXT: .cfi_offset %rbp, -16 +; X64-NEXT: movzbl {{[0-9]+}}(%rsp), %ebx +; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: shlq $62, %rcx +; X64-NEXT: sarq $62, %rcx +; X64-NEXT: movq (%rsp), %r14 +; X64-NEXT: movb (%rax), %bpl +; X64-NEXT: xorl %edi, %edi +; X64-NEXT: xorl %esi, %esi +; X64-NEXT: movq %r14, %rdx +; X64-NEXT: callq __modti3 +; X64-NEXT: andl $3, %edx +; X64-NEXT: cmpq %rax, %r14 +; X64-NEXT: sbbq %rdx, %rbx +; X64-NEXT: setb %sil +; X64-NEXT: setae %bl +; X64-NEXT: testb %al, %al +; X64-NEXT: setne %dl +; X64-NEXT: setne (%rax) +; X64-NEXT: movzbl %bpl, %eax +; X64-NEXT: xorl %ecx, %ecx +; X64-NEXT: subb %sil, %cl +; X64-NEXT: # kill: def $eax killed $eax def $ax +; X64-NEXT: divb %al +; X64-NEXT: negb %bl +; X64-NEXT: cmpb %al, %al +; X64-NEXT: setle %al +; X64-NEXT: negb %al +; X64-NEXT: cbtw +; X64-NEXT: idivb %bl +; X64-NEXT: movsbl %ah, %eax +; X64-NEXT: movzbl %al, %eax +; X64-NEXT: andl $1, %eax +; X64-NEXT: shlq $4, %rax +; X64-NEXT: negq %rax +; X64-NEXT: negb %dl +; X64-NEXT: leaq -16(%rsp,%rax), %rax +; X64-NEXT: movq %rax, (%rax) +; X64-NEXT: movl %ecx, %eax +; X64-NEXT: cbtw +; X64-NEXT: idivb %dl +; X64-NEXT: movsbl %ah, %eax +; X64-NEXT: andb $1, %al +; X64-NEXT: movb %al, (%rax) +; X64-NEXT: addq $16, %rsp +; X64-NEXT: .cfi_def_cfa_offset 32 +; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 24 +; X64-NEXT: popq %r14 +; X64-NEXT: .cfi_def_cfa_offset 16 +; X64-NEXT: popq %rbp +; X64-NEXT: .cfi_def_cfa_offset 8 +; X64-NEXT: retq +; +; X86-LABEL: f: +; X86: # %bb.0: # %BB +; X86-NEXT: pushl %ebp +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %ebp, -8 +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: .cfi_def_cfa_register %ebp +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $48, %esp +; X86-NEXT: .cfi_offset %esi, -20 +; X86-NEXT: .cfi_offset %edi, -16 +; X86-NEXT: .cfi_offset %ebx, -12 +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: shll $30, %eax +; X86-NEXT: movl %eax, %ecx +; X86-NEXT: sarl $30, %ecx +; X86-NEXT: sarl $31, %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: movb (%eax), %dl +; X86-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill +; X86-NEXT: leal {{[0-9]+}}(%esp), %edx +; X86-NEXT: pushl %eax +; X86-NEXT: pushl %ecx +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl $0 +; X86-NEXT: pushl $0 +; X86-NEXT: pushl $0 +; X86-NEXT: pushl $0 +; X86-NEXT: pushl %edx +; X86-NEXT: calll __modti3 +; X86-NEXT: addl $32, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: andl $3, %eax +; X86-NEXT: xorl %ecx, %ecx +; X86-NEXT: cmpl {{[0-9]+}}(%esp), %edi +; X86-NEXT: sbbl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: sbbl %eax, %esi +; X86-NEXT: sbbl $0, %ecx +; X86-NEXT: setae %dl +; X86-NEXT: sbbb %cl, %cl +; X86-NEXT: testb %al, %al +; X86-NEXT: setne %ch +; X86-NEXT: setne (%eax) +; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload +; X86-NEXT: movzbl %dh, %eax +; X86-NEXT: # kill: def $eax killed $eax def $ax +; X86-NEXT: divb %dh +; X86-NEXT: negb %ch +; X86-NEXT: negb %dl +; X86-NEXT: cmpb %al, %al +; X86-NEXT: setle %al +; X86-NEXT: negb %al +; X86-NEXT: cbtw +; X86-NEXT: idivb %dl +; X86-NEXT: movsbl %ah, %eax +; X86-NEXT: movzbl %al, %eax +; X86-NEXT: andl $1, %eax +; X86-NEXT: negl %eax +; X86-NEXT: leal (%eax,%eax,2), %eax +; X86-NEXT: leal -4(%esp,%eax,4), %eax +; X86-NEXT: movl %eax, (%eax) +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: cbtw +; X86-NEXT: idivb %ch +; X86-NEXT: movsbl %ah, %eax +; X86-NEXT: andb $1, %al +; X86-NEXT: movb %al, (%eax) +; X86-NEXT: leal -12(%ebp), %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: popl %ebp +; X86-NEXT: .cfi_def_cfa %esp, 4 +; X86-NEXT: retl +BB: + %A30 = alloca i66 + %L17 = load i66, i66* %A30 + %B20 = and i66 %L17, -1 + %G2 = getelementptr i66, i66* %A30, i1 true + %L10 = load i8, i8* undef + %B6 = udiv i8 %L10, %L10 + %C15 = icmp eq i8 undef, 0 + %B8 = srem i66 0, %B20 + %C2 = icmp ule i66 %B8, %B20 + %B5 = or i8 0, %B6 + %C19 = icmp uge i1 false, %C2 + %C1 = icmp sle i8 undef, %B5 + %B37 = srem i1 %C1, %C2 + %C7 = icmp uge i1 false, %C15 + store i1 %C7, i1* undef + %G6 = getelementptr i66, i66* %G2, i1 %B37 + store i66* %G6, i66** undef + %B30 = srem i1 %C19, %C7 + store i1 %B30, i1* undef + ret void +} + +; Similar to above, but bitwidth adjusted to target 32-bit mode. This also shows that we didn't constrain the register class when extracting a subreg. +define void @g() { +; X64-LABEL: g: +; X64: # %bb.0: # %BB +; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax +; X64-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi +; X64-NEXT: shlq $32, %rsi +; X64-NEXT: orq %rax, %rsi +; X64-NEXT: movq %rsi, %rdi +; X64-NEXT: shlq $30, %rdi +; X64-NEXT: sarq $30, %rdi +; X64-NEXT: movb (%rax), %al +; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $eax killed $eax def $ax +; X64-NEXT: divb %al +; X64-NEXT: movl %eax, %r8d +; X64-NEXT: xorl %eax, %eax +; X64-NEXT: xorl %edx, %edx +; X64-NEXT: idivq %rdi +; X64-NEXT: movabsq $17179869183, %rax # imm = 0x3FFFFFFFF +; X64-NEXT: andq %rdx, %rax +; X64-NEXT: testb %al, %al +; X64-NEXT: setne %dil +; X64-NEXT: setne (%rax) +; X64-NEXT: cmpq %rsi, %rax +; X64-NEXT: seta %dl +; X64-NEXT: setbe %cl +; X64-NEXT: negb %cl +; X64-NEXT: cmpb %r8b, %al +; X64-NEXT: setle %al +; X64-NEXT: negb %al +; X64-NEXT: cbtw +; X64-NEXT: idivb %cl +; X64-NEXT: movsbl %ah, %eax +; X64-NEXT: movzbl %al, %eax +; X64-NEXT: andl $1, %eax +; X64-NEXT: shlq $3, %rax +; X64-NEXT: negq %rax +; X64-NEXT: negb %dil +; X64-NEXT: negb %dl +; X64-NEXT: leaq -16(%rsp,%rax), %rax +; X64-NEXT: movq %rax, (%rax) +; X64-NEXT: movl %edx, %eax +; X64-NEXT: cbtw +; X64-NEXT: idivb %dil +; X64-NEXT: movsbl %ah, %eax +; X64-NEXT: andb $1, %al +; X64-NEXT: movb %al, (%rax) +; X64-NEXT: retq +; +; X86-LABEL: g: +; X86: # %bb.0: # %BB +; X86-NEXT: pushl %ebp +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %ebp, -8 +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: .cfi_def_cfa_register %ebp +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: .cfi_offset %esi, -20 +; X86-NEXT: .cfi_offset %edi, -16 +; X86-NEXT: .cfi_offset %ebx, -12 +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: shll $30, %eax +; X86-NEXT: sarl $30, %eax +; X86-NEXT: movl (%esp), %edi +; X86-NEXT: movb (%eax), %bl +; X86-NEXT: pushl %eax +; X86-NEXT: pushl %edi +; X86-NEXT: pushl $0 +; X86-NEXT: pushl $0 +; X86-NEXT: calll __moddi3 +; X86-NEXT: addl $16, %esp +; X86-NEXT: andl $3, %edx +; X86-NEXT: cmpl %eax, %edi +; X86-NEXT: sbbl %edx, %esi +; X86-NEXT: setb %dl +; X86-NEXT: setae %dh +; X86-NEXT: testb %al, %al +; X86-NEXT: setne %bh +; X86-NEXT: setne (%eax) +; X86-NEXT: movzbl %bl, %eax +; X86-NEXT: xorl %ecx, %ecx +; X86-NEXT: subb %dl, %cl +; X86-NEXT: # kill: def $eax killed $eax def $ax +; X86-NEXT: divb %bl +; X86-NEXT: negb %dh +; X86-NEXT: cmpb %al, %al +; X86-NEXT: setle %al +; X86-NEXT: negb %al +; X86-NEXT: cbtw +; X86-NEXT: idivb %dh +; X86-NEXT: movsbl %ah, %eax +; X86-NEXT: movzbl %al, %eax +; X86-NEXT: andl $1, %eax +; X86-NEXT: shll $3, %eax +; X86-NEXT: negl %eax +; X86-NEXT: negb %bh +; X86-NEXT: leal -8(%esp,%eax), %eax +; X86-NEXT: movl %eax, (%eax) +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: cbtw +; X86-NEXT: idivb %bh +; X86-NEXT: movsbl %ah, %eax +; X86-NEXT: andb $1, %al +; X86-NEXT: movb %al, (%eax) +; X86-NEXT: leal -12(%ebp), %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: popl %ebp +; X86-NEXT: .cfi_def_cfa %esp, 4 +; X86-NEXT: retl +BB: + %A30 = alloca i34 + %L17 = load i34, i34* %A30 + %B20 = and i34 %L17, -1 + %G2 = getelementptr i34, i34* %A30, i1 true + %L10 = load i8, i8* undef + %B6 = udiv i8 %L10, %L10 + %C15 = icmp eq i8 undef, 0 + %B8 = srem i34 0, %B20 + %C2 = icmp ule i34 %B8, %B20 + %B5 = or i8 0, %B6 + %C19 = icmp uge i1 false, %C2 + %C1 = icmp sle i8 undef, %B5 + %B37 = srem i1 %C1, %C2 + %C7 = icmp uge i1 false, %C15 + store i1 %C7, i1* undef + %G6 = getelementptr i34, i34* %G2, i1 %B37 + store i34* %G6, i34** undef + %B30 = srem i1 %C19, %C7 + store i1 %B30, i1* undef + ret void +} diff --git a/test/Other/opt-bisect-legacy-pass-manager.ll b/test/Other/opt-bisect-legacy-pass-manager.ll index 560675e893c5..bf89e80d4960 100644 --- a/test/Other/opt-bisect-legacy-pass-manager.ll +++ b/test/Other/opt-bisect-legacy-pass-manager.ll @@ -38,7 +38,7 @@ ; utils/bisect) to locate the optimization that inlines the call to ; f2() in f3(). -; RUN: '%python' %S/opt-bisect-helper.py --start=0 --end=256 --optcmd=opt \ +; RUN: %python %S/opt-bisect-helper.py --start=0 --end=256 --optcmd=opt \ ; RUN: --filecheckcmd=FileCheck --test=%s \ ; RUN: --prefix=CHECK-BISECT-INLINE-HELPER \ ; RUN: | FileCheck %s --check-prefix=CHECK-BISECT-INLINE-RESULT diff --git a/test/TableGen/JSON.td b/test/TableGen/JSON.td index a53215579f2a..968c2577fa99 100644 --- a/test/TableGen/JSON.td +++ b/test/TableGen/JSON.td @@ -1,4 +1,4 @@ -// RUN: llvm-tblgen -dump-json %s | '%python' %S/JSON-check.py %s +// RUN: llvm-tblgen -dump-json %s | %python %S/JSON-check.py %s // CHECK: data['!tablegen_json_version'] == 1 diff --git a/test/ThinLTO/X86/cache.ll b/test/ThinLTO/X86/cache.ll index bcd4f09e3ae6..cce584ec8b5d 100644 --- a/test/ThinLTO/X86/cache.ll +++ b/test/ThinLTO/X86/cache.ll @@ -106,11 +106,11 @@ ; RUN: rm -Rf %t.cache && mkdir %t.cache ; Create cache files with different sizes. ; Only 8B, 16B and 76B files should stay after pruning. -; RUN: "%python" -c "with open(r'%t.cache/llvmcache-foo-1024', 'w') as file: file.truncate(1024)" -; RUN: "%python" -c "with open(r'%t.cache/llvmcache-foo-16', 'w') as file: file.truncate(16)" -; RUN: "%python" -c "with open(r'%t.cache/llvmcache-foo-8', 'w') as file: file.truncate(8)" -; RUN: "%python" -c "with open(r'%t.cache/llvmcache-foo-76', 'w') as file: file.truncate(76)" -; RUN: "%python" -c "with open(r'%t.cache/llvmcache-foo-77', 'w') as file: file.truncate(77)" +; RUN: %python -c "with open(r'%t.cache/llvmcache-foo-1024', 'w') as file: file.truncate(1024)" +; RUN: %python -c "with open(r'%t.cache/llvmcache-foo-16', 'w') as file: file.truncate(16)" +; RUN: %python -c "with open(r'%t.cache/llvmcache-foo-8', 'w') as file: file.truncate(8)" +; RUN: %python -c "with open(r'%t.cache/llvmcache-foo-76', 'w') as file: file.truncate(76)" +; RUN: %python -c "with open(r'%t.cache/llvmcache-foo-77', 'w') as file: file.truncate(77)" ; RUN: llvm-lto -thinlto-action=run -exported-symbol=globalfunc %t2.bc %t.bc -thinlto-cache-dir %t.cache --thinlto-cache-max-size-bytes 100 ; RUN: ls %t.cache/llvmcache-foo-16 ; RUN: ls %t.cache/llvmcache-foo-8 @@ -123,11 +123,11 @@ ; RUN: rm -Rf %t.cache && mkdir %t.cache ; Create cache files with different sizes. ; Only 8B and 16B files should stay after pruning. -; RUN: "%python" -c "print(' ' * 1023)" > %t.cache/llvmcache-foo-1024 -; RUN: "%python" -c "print(' ' * 15)" > %t.cache/llvmcache-foo-16 -; RUN: "%python" -c "print(' ' * 7)" > %t.cache/llvmcache-foo-8 -; RUN: "%python" -c "print(' ' * 75)" > %t.cache/llvmcache-foo-76 -; RUN: "%python" -c "print(' ' * 76)" > %t.cache/llvmcache-foo-77 +; RUN: %python -c "print(' ' * 1023)" > %t.cache/llvmcache-foo-1024 +; RUN: %python -c "print(' ' * 15)" > %t.cache/llvmcache-foo-16 +; RUN: %python -c "print(' ' * 7)" > %t.cache/llvmcache-foo-8 +; RUN: %python -c "print(' ' * 75)" > %t.cache/llvmcache-foo-76 +; RUN: %python -c "print(' ' * 76)" > %t.cache/llvmcache-foo-77 ; RUN: llvm-lto -thinlto-action=run -exported-symbol=globalfunc %t2.bc %t.bc -thinlto-cache-dir %t.cache --thinlto-cache-max-size-files 2 ; RUN: ls %t.cache/llvmcache-foo-16 ; RUN: ls %t.cache/llvmcache-foo-8 diff --git a/test/Transforms/DeadStoreElimination/tail-byval.ll b/test/Transforms/DeadStoreElimination/tail-byval.ll new file mode 100644 index 000000000000..ed2fbd434a75 --- /dev/null +++ b/test/Transforms/DeadStoreElimination/tail-byval.ll @@ -0,0 +1,23 @@ +; RUN: opt -dse -S < %s | FileCheck %s + +; Don't eliminate stores to allocas before tail calls to functions that use +; byval. It's correct to mark calls like these as 'tail'. To implement this tail +; call, the backend should copy the bytes from the alloca into the argument area +; before clearing the stack. + +target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" +target triple = "i386-unknown-linux-gnu" + +declare void @g(i32* byval %p) + +define void @f(i32* byval %x) { +entry: + %p = alloca i32 + %v = load i32, i32* %x + store i32 %v, i32* %p + tail call void @g(i32* byval %p) + ret void +} +; CHECK-LABEL: define void @f(i32* byval %x) +; CHECK: store i32 %v, i32* %p +; CHECK: tail call void @g(i32* byval %p) diff --git a/test/Transforms/EarlyCSE/memoryssa.ll b/test/Transforms/EarlyCSE/memoryssa.ll index 1c10efe22937..41e8d488ab4d 100644 --- a/test/Transforms/EarlyCSE/memoryssa.ll +++ b/test/Transforms/EarlyCSE/memoryssa.ll @@ -106,3 +106,45 @@ end: store i32 %v2, i32* @G3 ret void } + +;; Check that we respect lifetime.start/lifetime.end intrinsics when deleting +;; stores that, without the lifetime calls, would be writebacks. +; CHECK-LABEL: @test_writeback_lifetimes( +; CHECK-NOMEMSSA-LABEL: @test_writeback_lifetimes( +define void @test_writeback_lifetimes(i32* %p) { +entry: + %q = getelementptr i32, i32* %p, i64 1 + %pv = load i32, i32* %p + %qv = load i32, i32* %q + call void @llvm.lifetime.end.p0i8(i64 8, i32* %p) + call void @llvm.lifetime.start.p0i8(i64 8, i32* %p) + ; CHECK: store i32 %pv + ; CHECK-NOMEMSSA-LABEL: store i32 %pv + store i32 %pv, i32* %p + ; CHECK: store i32 %qv, i32* %q + ; CHECK-NOMEMSSA-LABEL: store i32 %qv, i32* %q + store i32 %qv, i32* %q + ret void +} + +;; Check that we respect lifetime.start/lifetime.end intrinsics when deleting +;; stores that, without the lifetime calls, would be writebacks. +; CHECK-LABEL: @test_writeback_lifetimes_multi_arg( +; CHECK-NOMEMSSA-LABEL: @test_writeback_lifetimes_multi_arg( +define void @test_writeback_lifetimes_multi_arg(i32* %p, i32* %q) { +entry: + %pv = load i32, i32* %p + %qv = load i32, i32* %q + call void @llvm.lifetime.end.p0i8(i64 8, i32* %p) + call void @llvm.lifetime.start.p0i8(i64 8, i32* %p) + ; CHECK: store i32 %pv + ; CHECK-NOMEMSSA-LABEL: store i32 %pv + store i32 %pv, i32* %p + ; CHECK: store i32 %qv, i32* %q + ; CHECK-NOMEMSSA-LABEL: store i32 %qv, i32* %q + store i32 %qv, i32* %q + ret void +} + +declare void @llvm.lifetime.end.p0i8(i64, i32*) +declare void @llvm.lifetime.start.p0i8(i64, i32*) diff --git a/test/Transforms/SLPVectorizer/AArch64/PR38339.ll b/test/Transforms/SLPVectorizer/AArch64/PR38339.ll index 1ab4a13260ed..1a981a32804b 100644 --- a/test/Transforms/SLPVectorizer/AArch64/PR38339.ll +++ b/test/Transforms/SLPVectorizer/AArch64/PR38339.ll @@ -27,3 +27,98 @@ define void @f1(<2 x i16> %x, i16* %a) { store i16 %t2, i16* %ptr3 ret void } + +define void @f2(<2 x i16> %x, i16* %a) { +; CHECK-LABEL: @f2( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[CONT:%.*]] +; CHECK: cont: +; CHECK-NEXT: [[XX:%.*]] = phi <2 x i16> [ [[X:%.*]], [[ENTRY:%.*]] ], [ undef, [[CONT]] ] +; CHECK-NEXT: [[AA:%.*]] = phi i16* [ [[A:%.*]], [[ENTRY]] ], [ undef, [[CONT]] ] +; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i16> [[XX]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0> +; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0 +; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1 +; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2 +; CHECK-NEXT: [[PTR3:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3 +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i16> [[SHUFFLE]], i32 0 +; CHECK-NEXT: store i16 [[TMP0]], i16* [[A]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i16* [[PTR0]] to <4 x i16>* +; CHECK-NEXT: store <4 x i16> [[SHUFFLE]], <4 x i16>* [[TMP1]], align 2 +; CHECK-NEXT: [[A_VAL:%.*]] = load i16, i16* [[A]], align 2 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[A_VAL]], 0 +; CHECK-NEXT: br i1 [[CMP]], label [[CONT]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %cont + +cont: ; preds = %entry, %cont + %xx = phi <2 x i16> [ %x, %entry ], [ undef, %cont ] + %aa = phi i16* [ %a, %entry ], [ undef, %cont ] + %t2 = extractelement <2 x i16> %xx, i32 0 + %t3 = extractelement <2 x i16> %xx, i32 1 + %ptr0 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0 + %ptr1 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1 + %ptr2 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2 + %ptr3 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3 + store i16 %t2, i16* %a + store i16 %t2, i16* %ptr0 + store i16 %t3, i16* %ptr1 + store i16 %t3, i16* %ptr2 + store i16 %t2, i16* %ptr3 + %a_val = load i16, i16* %a, align 2 + %cmp = icmp eq i16 %a_val, 0 + br i1 %cmp, label %cont, label %exit + +exit: ; preds = %cont + ret void +} + +define void @f3(<2 x i16> %x, i16* %a) { +; CHECK-LABEL: @f3( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[CONT:%.*]] +; CHECK: cont: +; CHECK-NEXT: [[XX:%.*]] = phi <2 x i16> [ [[X:%.*]], [[ENTRY:%.*]] ], [ undef, [[CONT]] ] +; CHECK-NEXT: [[AA:%.*]] = phi i16* [ [[A:%.*]], [[ENTRY]] ], [ undef, [[CONT]] ] +; CHECK-NEXT: [[REORDER_SHUFFLE:%.*]] = shufflevector <2 x i16> [[XX]], <2 x i16> undef, <2 x i32> <i32 1, i32 0> +; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i16> [[REORDER_SHUFFLE]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0> +; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0 +; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1 +; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2 +; CHECK-NEXT: [[PTR3:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3 +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i16> [[SHUFFLE]], i32 0 +; CHECK-NEXT: store i16 [[TMP0]], i16* [[A]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i16* [[PTR0]] to <4 x i16>* +; CHECK-NEXT: store <4 x i16> [[SHUFFLE]], <4 x i16>* [[TMP1]], align 2 +; CHECK-NEXT: [[A_VAL:%.*]] = load i16, i16* [[A]], align 2 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[A_VAL]], 0 +; CHECK-NEXT: br i1 [[CMP]], label [[CONT]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %cont + +cont: ; preds = %entry, %cont + %xx = phi <2 x i16> [ %x, %entry ], [ undef, %cont ] + %aa = phi i16* [ %a, %entry ], [ undef, %cont ] + %t2 = extractelement <2 x i16> %xx, i32 0 + %t3 = extractelement <2 x i16> %xx, i32 1 + %ptr0 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0 + %ptr1 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1 + %ptr2 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2 + %ptr3 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3 + store i16 %t3, i16* %a + store i16 %t3, i16* %ptr0 + store i16 %t2, i16* %ptr1 + store i16 %t2, i16* %ptr2 + store i16 %t3, i16* %ptr3 + %a_val = load i16, i16* %a, align 2 + %cmp = icmp eq i16 %a_val, 0 + br i1 %cmp, label %cont, label %exit + +exit: ; preds = %cont + ret void +} diff --git a/test/tools/gold/X86/common.ll b/test/tools/gold/X86/common.ll index 1debe7875474..d8b4e031f9db 100644 --- a/test/tools/gold/X86/common.ll +++ b/test/tools/gold/X86/common.ll @@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu" @a = common global i16 0, align 8 -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext \ +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext \ ; RUN: --plugin-opt=emit-llvm \ ; RUN: -shared %t1.o %t2.o -o %t3.o ; RUN: llvm-dis %t3.o -o - | FileCheck %s --check-prefix=A @@ -16,7 +16,7 @@ target triple = "x86_64-unknown-linux-gnu" ; Shared library case, we merge @a as common and keep it for the symbol table. ; A: @a = common global [4 x i8] zeroinitializer, align 8 -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext \ +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext \ ; RUN: --plugin-opt=emit-llvm \ ; RUN: -shared %t1.o %t2b.o -o %t3.o ; RUN: llvm-dis %t3.o -o - | FileCheck %s --check-prefix=B @@ -24,7 +24,7 @@ target triple = "x86_64-unknown-linux-gnu" ; (i16 align 8) + (i8 align 16) = i16 align 16 ; B: @a = common global i16 0, align 16 -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext \ +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext \ ; RUN: --plugin-opt=emit-llvm \ ; RUN: -shared %t1.o %t2c.o -o %t3.o ; RUN: llvm-dis %t3.o -o - | FileCheck %s --check-prefix=C @@ -32,7 +32,7 @@ target triple = "x86_64-unknown-linux-gnu" ; (i16 align 8) + (i8 align 1) = i16 align 8. ; C: @a = common global i16 0, align 8 -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext \ +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext \ ; RUN: --plugin-opt=emit-llvm \ ; RUN: %t1.o %t2.o -o %t3.o ; RUN: llvm-dis %t3.o -o - | FileCheck --check-prefix=EXEC %s @@ -41,7 +41,7 @@ target triple = "x86_64-unknown-linux-gnu" ; EXEC: @a = internal global [4 x i8] zeroinitializer, align 8 ; RUN: llc %p/Inputs/common.ll -o %t2native.o -filetype=obj -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext \ +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext \ ; RUN: --plugin-opt=emit-llvm \ ; RUN: %t1.o %t2native.o -o %t3.o ; RUN: llvm-dis %t3.o -o - | FileCheck --check-prefix=MIXED %s diff --git a/test/tools/gold/X86/v1.16/wrap-1.ll b/test/tools/gold/X86/v1.16/wrap-1.ll index 5ea83b007dfe..806442e49976 100644 --- a/test/tools/gold/X86/v1.16/wrap-1.ll +++ b/test/tools/gold/X86/v1.16/wrap-1.ll @@ -1,12 +1,12 @@ ; LTO ; RUN: llvm-as %s -o %t.o -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext %t.o -o %t.out -wrap=bar -plugin-opt=save-temps +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext %t.o -o %t.out -wrap=bar -plugin-opt=save-temps ; RUN: llvm-readobj -t %t.out | FileCheck %s ; RUN: cat %t.out.resolution.txt | FileCheck -check-prefix=RESOLS %s ; ThinLTO ; RUN: opt -module-summary %s -o %t.o -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext %t.o -o %t.out -wrap=bar -plugin-opt=save-temps +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext %t.o -o %t.out -wrap=bar -plugin-opt=save-temps ; RUN: llvm-readobj -t %t.out | FileCheck %s ; RUN: cat %t.out.resolution.txt | FileCheck -check-prefix=RESOLS %s diff --git a/test/tools/gold/X86/v1.16/wrap-2.ll b/test/tools/gold/X86/v1.16/wrap-2.ll index 7c1d95d5be32..f36456c17ad0 100644 --- a/test/tools/gold/X86/v1.16/wrap-2.ll +++ b/test/tools/gold/X86/v1.16/wrap-2.ll @@ -7,14 +7,14 @@ ; LTO defsym handling, gold will need a fix (not the gold plugin). ; RUN-TODO: llvm-as %s -o %t.o ; RUN-TODO: llvm-as %S/Inputs/wrap-bar.ll -o %t1.o -; RUN-TODO: %gold -plugin %llvmshlibdir/LLVMgold%shlibext %t.o %t1.o -shared -o %t.so -wrap=bar +; RUN-TODO: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext %t.o %t1.o -shared -o %t.so -wrap=bar ; RUN-TODO: llvm-objdump -d %t.so | FileCheck %s ; RUN-TODO: llvm-readobj -t %t.so | FileCheck -check-prefix=BIND %s ; ThinLTO ; RUN: opt -module-summary %s -o %t.o ; RUN: opt -module-summary %S/Inputs/wrap-bar.ll -o %t1.o -; RUN: %gold -plugin %llvmshlibdir/LLVMgold%shlibext %t.o %t1.o -shared -o %t.so -wrap=bar +; RUN: %gold -m elf_x86_64 -plugin %llvmshlibdir/LLVMgold%shlibext %t.o %t1.o -shared -o %t.so -wrap=bar ; RUN: llvm-objdump -d %t.so | FileCheck %s -check-prefix=THIN ; RUN: llvm-readobj -t %t.so | FileCheck -check-prefix=BIND %s diff --git a/test/tools/llvm-cov/showLineExecutionCounts.cpp b/test/tools/llvm-cov/showLineExecutionCounts.cpp index c7e373eb8756..7fc36a7a911e 100644 --- a/test/tools/llvm-cov/showLineExecutionCounts.cpp +++ b/test/tools/llvm-cov/showLineExecutionCounts.cpp @@ -37,7 +37,7 @@ int main() { // TEXT: [[@LINE]]| 161|int main( // // RUN: llvm-cov export %S/Inputs/lineExecutionCounts.covmapping -instr-profile %t.profdata -name=main 2>/dev/null > %t.export.json // RUN: FileCheck -input-file %t.export.json %S/Inputs/lineExecutionCounts.json -// RUN: cat %t.export.json | "%python" -c "import json, sys; json.loads(sys.stdin.read())" +// RUN: cat %t.export.json | %python -c "import json, sys; json.loads(sys.stdin.read())" // // RUN: llvm-cov export %S/Inputs/lineExecutionCounts.covmapping -instr-profile %t.profdata 2>/dev/null -summary-only > %t.export-summary.json // RUN: not grep '"name":"main"' %t.export-summary.json diff --git a/test/tools/llvm-objcopy/auto-remove-shndx.test b/test/tools/llvm-objcopy/auto-remove-shndx.test index 349d35a6dc90..5452f34d96de 100644 --- a/test/tools/llvm-objcopy/auto-remove-shndx.test +++ b/test/tools/llvm-objcopy/auto-remove-shndx.test @@ -1,4 +1,4 @@ -# RUN: '%python' %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t +# RUN: %python %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t # RUN: llvm-objcopy -R .text -R s0 -R s1 -R s2 -R s3 -R s4 -R s5 -R s6 %t %t2 # RUN: llvm-readobj -sections %t2 | FileCheck --check-prefix=SECS %s diff --git a/test/tools/llvm-objcopy/many-sections.test b/test/tools/llvm-objcopy/many-sections.test index b514fbe6bf40..7aaa3a7fe7f2 100644 --- a/test/tools/llvm-objcopy/many-sections.test +++ b/test/tools/llvm-objcopy/many-sections.test @@ -1,4 +1,4 @@ -RUN: '%python' %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t +RUN: %python %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t RUN: llvm-objcopy %t %t2 RUN: llvm-readobj -file-headers %t2 | FileCheck --check-prefix=EHDR %s RUN: llvm-readobj -sections %t2 | FileCheck --check-prefix=SECS %s diff --git a/test/tools/llvm-objcopy/remove-shndx.test b/test/tools/llvm-objcopy/remove-shndx.test index 77f4622cd5a0..b8ea94cbc1da 100644 --- a/test/tools/llvm-objcopy/remove-shndx.test +++ b/test/tools/llvm-objcopy/remove-shndx.test @@ -1,6 +1,6 @@ # This test checks to see that a .symtab_shndx section is added to any binary # that needs it, even if the original was removed. -RUN: '%python' %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t +RUN: %python %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t RUN: llvm-objcopy -R .symtab_shndx %t %t2 RUN: llvm-readobj -sections %t2 | FileCheck %s diff --git a/test/tools/llvm-objcopy/strict-no-add.test b/test/tools/llvm-objcopy/strict-no-add.test index 00d5dc112200..15f5251db343 100644 --- a/test/tools/llvm-objcopy/strict-no-add.test +++ b/test/tools/llvm-objcopy/strict-no-add.test @@ -1,7 +1,7 @@ # This test makes sure that sections added at the end that don't have symbols # defined in them don't trigger the creation of a large index table. -RUN: '%python' %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t.0 +RUN: %python %p/Inputs/ungzip.py %p/Inputs/many-sections.o.gz > %t.0 RUN: cat %p/Inputs/alloc-symtab.o > %t RUN: llvm-objcopy -R .text -R s0 -R s1 -R s2 -R s3 -R s4 -R s5 -R s6 %t.0 %t2 RUN: llvm-objcopy -add-section=.s0=%t -add-section=.s1=%t -add-section=.s2=%t %t2 %t2 diff --git a/test/tools/llvm-symbolizer/pdb/pdb.test b/test/tools/llvm-symbolizer/pdb/pdb.test index 29be9f132399..a97b35eab9c4 100644 --- a/test/tools/llvm-symbolizer/pdb/pdb.test +++ b/test/tools/llvm-symbolizer/pdb/pdb.test @@ -9,7 +9,7 @@ Subtract ImageBase from all the offsets and run the test again with --relative-address. RUN: grep '^ADDR:' %s | sed -s 's/ADDR: //' \ -RUN: | "%python" -c 'import sys;print("\n".join([hex(int(x, 16) - 0x400000) for x in sys.stdin]))' \ +RUN: | %python -c 'import sys;print("\n".join([hex(int(x, 16) - 0x400000) for x in sys.stdin]))' \ RUN: | llvm-symbolizer -obj="%p/Inputs/test.exe" -demangle=false --relative-address \ RUN: | FileCheck %s --check-prefix=CHECK-NO-DEMANGLE diff --git a/test/tools/llvm-symbolizer/ppc64.test b/test/tools/llvm-symbolizer/ppc64.test index 34ebad88b585..fc8e4ffc7e2e 100644 --- a/test/tools/llvm-symbolizer/ppc64.test +++ b/test/tools/llvm-symbolizer/ppc64.test @@ -4,7 +4,7 @@ int foo() { return 0; } int bar() { return foo(); } int _start() { return bar(); } -RUN: "%python" -c "print('0x1000014c\n0x1000018c\n0x100001cc')" | llvm-symbolizer -obj=%p/Inputs/ppc64 | FileCheck %s +RUN: %python -c "print('0x1000014c\n0x1000018c\n0x100001cc')" | llvm-symbolizer -obj=%p/Inputs/ppc64 | FileCheck %s CHECK: foo CHECK: bar |