aboutsummaryrefslogtreecommitdiff
path: root/test
diff options
context:
space:
mode:
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/PowerPC/combine_loads_from_build_pair.ll2
-rw-r--r--test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll15
-rw-r--r--test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll11
-rw-r--r--test/CodeGen/X86/bitcast-int-to-vector-bool.ll11
-rw-r--r--test/CodeGen/X86/setcc-wide-types.ll252
-rw-r--r--test/CodeGen/X86/win32-eh-available-externally.ll28
6 files changed, 295 insertions, 24 deletions
diff --git a/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll b/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll
index 0f8f18a17879..45cc740d1eae 100644
--- a/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll
+++ b/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll
@@ -12,6 +12,8 @@ define i64 @func1(i64 %p1, i64 %p2, i64 %p3, i64 %p4, { i64, i8* } %struct) {
; CHECK-DAG: [[LOBITS:t[0-9]+]]: i32,ch = load<LD4[FixedStack-2]>
; CHECK-DAG: [[HIBITS:t[0-9]+]]: i32,ch = load<LD4[FixedStack-1]>
; CHECK: Combining: t{{[0-9]+}}: i64 = build_pair [[LOBITS]], [[HIBITS]]
+; CHECK-NEXT: Creating new node
+; CHECK-SAME: load<LD8[FixedStack-1]
; CHECK-NEXT: into
; CHECK-SAME: load<LD8[FixedStack-1]
; CHECK-LABEL: Optimized lowered selection DAG:
diff --git a/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll b/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
index dcddb8e82642..6ef2be99dee5 100644
--- a/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
+++ b/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
@@ -48,9 +48,8 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
; AVX512-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
-; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
-; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512-NEXT: retq
%1 = bitcast i2 %a0 to <2 x i1>
%2 = sext <2 x i1> %1 to <2 x i64>
@@ -91,10 +90,8 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) {
; AVX512-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
-; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX512-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
-; AVX512-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
-; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
%2 = sext <4 x i1> %1 to <4 x i32>
@@ -246,8 +243,8 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
; AVX512-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
-; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
+; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
+; AVX512-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; AVX512-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
%2 = sext <4 x i1> %1 to <4 x i64>
diff --git a/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll b/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
index f88b540323cb..9e77cd11449e 100644
--- a/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
+++ b/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
@@ -63,9 +63,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) {
; AVX512VLBW-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512VLBW-NEXT: kmovd %eax, %k1
-; AVX512VLBW-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
-; AVX512VLBW-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
-; AVX512VLBW-NEXT: vzeroupper
+; AVX512VLBW-NEXT: vmovdqa64 {{.*}}(%rip), %xmm0 {%k1} {z}
; AVX512VLBW-NEXT: retq
%1 = bitcast i2 %a0 to <2 x i1>
%2 = zext <2 x i1> %1 to <2 x i64>
@@ -120,9 +118,7 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) {
; AVX512VLBW-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512VLBW-NEXT: kmovd %eax, %k1
-; AVX512VLBW-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z}
-; AVX512VLBW-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
-; AVX512VLBW-NEXT: vzeroupper
+; AVX512VLBW-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z}
; AVX512VLBW-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
%2 = zext <4 x i1> %1 to <4 x i32>
@@ -317,8 +313,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) {
; AVX512VLBW-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512VLBW-NEXT: kmovd %eax, %k1
-; AVX512VLBW-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z}
-; AVX512VLBW-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
+; AVX512VLBW-NEXT: vpbroadcastq {{.*}}(%rip), %ymm0 {%k1} {z}
; AVX512VLBW-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
%2 = zext <4 x i1> %1 to <4 x i64>
diff --git a/test/CodeGen/X86/bitcast-int-to-vector-bool.ll b/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
index 6d9f832d861f..45a48fae146d 100644
--- a/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
+++ b/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
@@ -46,9 +46,8 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroext %a0) {
; AVX512-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
-; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
-; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512-NEXT: retq
%1 = bitcast i2 %a0 to <2 x i1>
ret <2 x i1> %1
@@ -90,10 +89,8 @@ define <4 x i1> @bitcast_i4_4i1(i4 zeroext %a0) {
; AVX512-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; AVX512-NEXT: kmovd %eax, %k1
-; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
-; AVX512-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
-; AVX512-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
-; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512-NEXT: retq
%1 = bitcast i4 %a0 to <4 x i1>
ret <4 x i1> %1
diff --git a/test/CodeGen/X86/setcc-wide-types.ll b/test/CodeGen/X86/setcc-wide-types.ll
index f935db72dcb9..410378ffbad2 100644
--- a/test/CodeGen/X86/setcc-wide-types.ll
+++ b/test/CodeGen/X86/setcc-wide-types.ll
@@ -138,3 +138,255 @@ define i32 @eq_i256(<4 x i64> %x, <4 x i64> %y) {
ret i32 %zext
}
+; This test models the expansion of 'memcmp(a, b, 32) != 0'
+; if we allowed 2 pairs of 16-byte loads per block.
+
+define i32 @ne_i128_pair(i128* %a, i128* %b) {
+; SSE2-LABEL: ne_i128_pair:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movq (%rdi), %rax
+; SSE2-NEXT: movq 8(%rdi), %rcx
+; SSE2-NEXT: xorq (%rsi), %rax
+; SSE2-NEXT: xorq 8(%rsi), %rcx
+; SSE2-NEXT: movq 24(%rdi), %rdx
+; SSE2-NEXT: movq 16(%rdi), %rdi
+; SSE2-NEXT: xorq 16(%rsi), %rdi
+; SSE2-NEXT: orq %rax, %rdi
+; SSE2-NEXT: xorq 24(%rsi), %rdx
+; SSE2-NEXT: orq %rcx, %rdx
+; SSE2-NEXT: xorl %eax, %eax
+; SSE2-NEXT: orq %rdi, %rdx
+; SSE2-NEXT: setne %al
+; SSE2-NEXT: retq
+;
+; AVX2-LABEL: ne_i128_pair:
+; AVX2: # %bb.0:
+; AVX2-NEXT: movq (%rdi), %rax
+; AVX2-NEXT: movq 8(%rdi), %rcx
+; AVX2-NEXT: xorq (%rsi), %rax
+; AVX2-NEXT: xorq 8(%rsi), %rcx
+; AVX2-NEXT: movq 24(%rdi), %rdx
+; AVX2-NEXT: movq 16(%rdi), %rdi
+; AVX2-NEXT: xorq 16(%rsi), %rdi
+; AVX2-NEXT: orq %rax, %rdi
+; AVX2-NEXT: xorq 24(%rsi), %rdx
+; AVX2-NEXT: orq %rcx, %rdx
+; AVX2-NEXT: xorl %eax, %eax
+; AVX2-NEXT: orq %rdi, %rdx
+; AVX2-NEXT: setne %al
+; AVX2-NEXT: retq
+ %a0 = load i128, i128* %a
+ %b0 = load i128, i128* %b
+ %xor1 = xor i128 %a0, %b0
+ %ap1 = getelementptr i128, i128* %a, i128 1
+ %bp1 = getelementptr i128, i128* %b, i128 1
+ %a1 = load i128, i128* %ap1
+ %b1 = load i128, i128* %bp1
+ %xor2 = xor i128 %a1, %b1
+ %or = or i128 %xor1, %xor2
+ %cmp = icmp ne i128 %or, 0
+ %z = zext i1 %cmp to i32
+ ret i32 %z
+}
+
+; This test models the expansion of 'memcmp(a, b, 32) == 0'
+; if we allowed 2 pairs of 16-byte loads per block.
+
+define i32 @eq_i128_pair(i128* %a, i128* %b) {
+; SSE2-LABEL: eq_i128_pair:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movq (%rdi), %rax
+; SSE2-NEXT: movq 8(%rdi), %rcx
+; SSE2-NEXT: xorq (%rsi), %rax
+; SSE2-NEXT: xorq 8(%rsi), %rcx
+; SSE2-NEXT: movq 24(%rdi), %rdx
+; SSE2-NEXT: movq 16(%rdi), %rdi
+; SSE2-NEXT: xorq 16(%rsi), %rdi
+; SSE2-NEXT: orq %rax, %rdi
+; SSE2-NEXT: xorq 24(%rsi), %rdx
+; SSE2-NEXT: orq %rcx, %rdx
+; SSE2-NEXT: xorl %eax, %eax
+; SSE2-NEXT: orq %rdi, %rdx
+; SSE2-NEXT: sete %al
+; SSE2-NEXT: retq
+;
+; AVX2-LABEL: eq_i128_pair:
+; AVX2: # %bb.0:
+; AVX2-NEXT: movq (%rdi), %rax
+; AVX2-NEXT: movq 8(%rdi), %rcx
+; AVX2-NEXT: xorq (%rsi), %rax
+; AVX2-NEXT: xorq 8(%rsi), %rcx
+; AVX2-NEXT: movq 24(%rdi), %rdx
+; AVX2-NEXT: movq 16(%rdi), %rdi
+; AVX2-NEXT: xorq 16(%rsi), %rdi
+; AVX2-NEXT: orq %rax, %rdi
+; AVX2-NEXT: xorq 24(%rsi), %rdx
+; AVX2-NEXT: orq %rcx, %rdx
+; AVX2-NEXT: xorl %eax, %eax
+; AVX2-NEXT: orq %rdi, %rdx
+; AVX2-NEXT: sete %al
+; AVX2-NEXT: retq
+ %a0 = load i128, i128* %a
+ %b0 = load i128, i128* %b
+ %xor1 = xor i128 %a0, %b0
+ %ap1 = getelementptr i128, i128* %a, i128 1
+ %bp1 = getelementptr i128, i128* %b, i128 1
+ %a1 = load i128, i128* %ap1
+ %b1 = load i128, i128* %bp1
+ %xor2 = xor i128 %a1, %b1
+ %or = or i128 %xor1, %xor2
+ %cmp = icmp eq i128 %or, 0
+ %z = zext i1 %cmp to i32
+ ret i32 %z
+}
+
+; This test models the expansion of 'memcmp(a, b, 64) != 0'
+; if we allowed 2 pairs of 32-byte loads per block.
+
+define i32 @ne_i256_pair(i256* %a, i256* %b) {
+; SSE2-LABEL: ne_i256_pair:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movq 16(%rdi), %r9
+; SSE2-NEXT: movq 24(%rdi), %r11
+; SSE2-NEXT: movq (%rdi), %r8
+; SSE2-NEXT: movq 8(%rdi), %r10
+; SSE2-NEXT: xorq 8(%rsi), %r10
+; SSE2-NEXT: xorq 24(%rsi), %r11
+; SSE2-NEXT: xorq (%rsi), %r8
+; SSE2-NEXT: xorq 16(%rsi), %r9
+; SSE2-NEXT: movq 48(%rdi), %rdx
+; SSE2-NEXT: movq 32(%rdi), %rax
+; SSE2-NEXT: movq 56(%rdi), %rcx
+; SSE2-NEXT: movq 40(%rdi), %rdi
+; SSE2-NEXT: xorq 40(%rsi), %rdi
+; SSE2-NEXT: xorq 56(%rsi), %rcx
+; SSE2-NEXT: orq %r11, %rcx
+; SSE2-NEXT: orq %rdi, %rcx
+; SSE2-NEXT: orq %r10, %rcx
+; SSE2-NEXT: xorq 32(%rsi), %rax
+; SSE2-NEXT: xorq 48(%rsi), %rdx
+; SSE2-NEXT: orq %r9, %rdx
+; SSE2-NEXT: orq %rax, %rdx
+; SSE2-NEXT: orq %r8, %rdx
+; SSE2-NEXT: xorl %eax, %eax
+; SSE2-NEXT: orq %rcx, %rdx
+; SSE2-NEXT: setne %al
+; SSE2-NEXT: retq
+;
+; AVX2-LABEL: ne_i256_pair:
+; AVX2: # %bb.0:
+; AVX2-NEXT: movq 16(%rdi), %r9
+; AVX2-NEXT: movq 24(%rdi), %r11
+; AVX2-NEXT: movq (%rdi), %r8
+; AVX2-NEXT: movq 8(%rdi), %r10
+; AVX2-NEXT: xorq 8(%rsi), %r10
+; AVX2-NEXT: xorq 24(%rsi), %r11
+; AVX2-NEXT: xorq (%rsi), %r8
+; AVX2-NEXT: xorq 16(%rsi), %r9
+; AVX2-NEXT: movq 48(%rdi), %rdx
+; AVX2-NEXT: movq 32(%rdi), %rax
+; AVX2-NEXT: movq 56(%rdi), %rcx
+; AVX2-NEXT: movq 40(%rdi), %rdi
+; AVX2-NEXT: xorq 40(%rsi), %rdi
+; AVX2-NEXT: xorq 56(%rsi), %rcx
+; AVX2-NEXT: orq %r11, %rcx
+; AVX2-NEXT: orq %rdi, %rcx
+; AVX2-NEXT: orq %r10, %rcx
+; AVX2-NEXT: xorq 32(%rsi), %rax
+; AVX2-NEXT: xorq 48(%rsi), %rdx
+; AVX2-NEXT: orq %r9, %rdx
+; AVX2-NEXT: orq %rax, %rdx
+; AVX2-NEXT: orq %r8, %rdx
+; AVX2-NEXT: xorl %eax, %eax
+; AVX2-NEXT: orq %rcx, %rdx
+; AVX2-NEXT: setne %al
+; AVX2-NEXT: retq
+ %a0 = load i256, i256* %a
+ %b0 = load i256, i256* %b
+ %xor1 = xor i256 %a0, %b0
+ %ap1 = getelementptr i256, i256* %a, i256 1
+ %bp1 = getelementptr i256, i256* %b, i256 1
+ %a1 = load i256, i256* %ap1
+ %b1 = load i256, i256* %bp1
+ %xor2 = xor i256 %a1, %b1
+ %or = or i256 %xor1, %xor2
+ %cmp = icmp ne i256 %or, 0
+ %z = zext i1 %cmp to i32
+ ret i32 %z
+}
+
+; This test models the expansion of 'memcmp(a, b, 64) == 0'
+; if we allowed 2 pairs of 32-byte loads per block.
+
+define i32 @eq_i256_pair(i256* %a, i256* %b) {
+; SSE2-LABEL: eq_i256_pair:
+; SSE2: # %bb.0:
+; SSE2-NEXT: movq 16(%rdi), %r9
+; SSE2-NEXT: movq 24(%rdi), %r11
+; SSE2-NEXT: movq (%rdi), %r8
+; SSE2-NEXT: movq 8(%rdi), %r10
+; SSE2-NEXT: xorq 8(%rsi), %r10
+; SSE2-NEXT: xorq 24(%rsi), %r11
+; SSE2-NEXT: xorq (%rsi), %r8
+; SSE2-NEXT: xorq 16(%rsi), %r9
+; SSE2-NEXT: movq 48(%rdi), %rdx
+; SSE2-NEXT: movq 32(%rdi), %rax
+; SSE2-NEXT: movq 56(%rdi), %rcx
+; SSE2-NEXT: movq 40(%rdi), %rdi
+; SSE2-NEXT: xorq 40(%rsi), %rdi
+; SSE2-NEXT: xorq 56(%rsi), %rcx
+; SSE2-NEXT: orq %r11, %rcx
+; SSE2-NEXT: orq %rdi, %rcx
+; SSE2-NEXT: orq %r10, %rcx
+; SSE2-NEXT: xorq 32(%rsi), %rax
+; SSE2-NEXT: xorq 48(%rsi), %rdx
+; SSE2-NEXT: orq %r9, %rdx
+; SSE2-NEXT: orq %rax, %rdx
+; SSE2-NEXT: orq %r8, %rdx
+; SSE2-NEXT: xorl %eax, %eax
+; SSE2-NEXT: orq %rcx, %rdx
+; SSE2-NEXT: sete %al
+; SSE2-NEXT: retq
+;
+; AVX2-LABEL: eq_i256_pair:
+; AVX2: # %bb.0:
+; AVX2-NEXT: movq 16(%rdi), %r9
+; AVX2-NEXT: movq 24(%rdi), %r11
+; AVX2-NEXT: movq (%rdi), %r8
+; AVX2-NEXT: movq 8(%rdi), %r10
+; AVX2-NEXT: xorq 8(%rsi), %r10
+; AVX2-NEXT: xorq 24(%rsi), %r11
+; AVX2-NEXT: xorq (%rsi), %r8
+; AVX2-NEXT: xorq 16(%rsi), %r9
+; AVX2-NEXT: movq 48(%rdi), %rdx
+; AVX2-NEXT: movq 32(%rdi), %rax
+; AVX2-NEXT: movq 56(%rdi), %rcx
+; AVX2-NEXT: movq 40(%rdi), %rdi
+; AVX2-NEXT: xorq 40(%rsi), %rdi
+; AVX2-NEXT: xorq 56(%rsi), %rcx
+; AVX2-NEXT: orq %r11, %rcx
+; AVX2-NEXT: orq %rdi, %rcx
+; AVX2-NEXT: orq %r10, %rcx
+; AVX2-NEXT: xorq 32(%rsi), %rax
+; AVX2-NEXT: xorq 48(%rsi), %rdx
+; AVX2-NEXT: orq %r9, %rdx
+; AVX2-NEXT: orq %rax, %rdx
+; AVX2-NEXT: orq %r8, %rdx
+; AVX2-NEXT: xorl %eax, %eax
+; AVX2-NEXT: orq %rcx, %rdx
+; AVX2-NEXT: sete %al
+; AVX2-NEXT: retq
+ %a0 = load i256, i256* %a
+ %b0 = load i256, i256* %b
+ %xor1 = xor i256 %a0, %b0
+ %ap1 = getelementptr i256, i256* %a, i256 1
+ %bp1 = getelementptr i256, i256* %b, i256 1
+ %a1 = load i256, i256* %ap1
+ %b1 = load i256, i256* %bp1
+ %xor2 = xor i256 %a1, %b1
+ %or = or i256 %xor1, %xor2
+ %cmp = icmp eq i256 %or, 0
+ %z = zext i1 %cmp to i32
+ ret i32 %z
+}
+
diff --git a/test/CodeGen/X86/win32-eh-available-externally.ll b/test/CodeGen/X86/win32-eh-available-externally.ll
new file mode 100644
index 000000000000..49da191de978
--- /dev/null
+++ b/test/CodeGen/X86/win32-eh-available-externally.ll
@@ -0,0 +1,28 @@
+; RUN: opt -S -x86-winehstate < %s | FileCheck %s --check-prefix=IR
+; RUN: llc < %s | FileCheck %s --check-prefix=ASM
+
+; IR-NOT: define.*__ehhandler
+; IR: define available_externally void @foo(void ()*)
+; IR-NOT: define.*__ehhandler
+
+; No code should be emitted.
+; ASM-NOT: __ehtable
+; ASM-NOT: __ehhandler
+
+target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
+target triple = "i686-pc-windows-msvc"
+
+declare i32 @__CxxFrameHandler3(...) unnamed_addr
+
+define available_externally void @foo(void ()*) personality i32 (...)* @__CxxFrameHandler3 {
+start:
+ invoke void %0()
+ to label %good unwind label %bad
+
+good: ; preds = %start
+ ret void
+
+bad: ; preds = %start
+ %cleanuppad = cleanuppad within none []
+ cleanupret from %cleanuppad unwind to caller
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-21 18:11:48 +0000