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-rw-r--r--utils/TableGen/CodeGenTarget.h15
1 files changed, 5 insertions, 10 deletions
diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h
index cf4a0bbe5bd9..85a8c1b18878 100644
--- a/utils/TableGen/CodeGenTarget.h
+++ b/utils/TableGen/CodeGenTarget.h
@@ -52,8 +52,8 @@ enum SDNP {
/// record corresponds to.
MVT::SimpleValueType getValueType(Record *Rec);
-std::string getName(MVT::SimpleValueType T);
-std::string getEnumName(MVT::SimpleValueType T);
+StringRef getName(MVT::SimpleValueType T);
+StringRef getEnumName(MVT::SimpleValueType T);
/// getQualifiedName - Return the name of the specified record, with a
/// namespace qualifier if the record contains one.
@@ -139,9 +139,7 @@ public:
/// supported by the target (i.e. there are registers that directly hold it).
bool isLegalValueType(MVT::SimpleValueType VT) const {
ArrayRef<MVT::SimpleValueType> LegalVTs = getLegalValueTypes();
- for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
- if (LegalVTs[i] == VT) return true;
- return false;
+ return std::find(LegalVTs.begin(), LegalVTs.end(), VT) != LegalVTs.end();
}
CodeGenSchedModels &getSchedModels() const;
@@ -163,18 +161,15 @@ public:
/// getInstructionsByEnumValue - Return all of the instructions defined by the
/// target, ordered by their enum value.
- const std::vector<const CodeGenInstruction*> &
+ ArrayRef<const CodeGenInstruction *>
getInstructionsByEnumValue() const {
if (InstrsByEnum.empty()) ComputeInstrsByEnum();
return InstrsByEnum;
}
- typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
+ typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
- iterator_range<inst_iterator> instructions() const {
- return make_range(inst_begin(), inst_end());
- }
/// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?