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* Merge llvm-project release/17.x llvmorg-17.0.1-25-g098e653a5bedDimitry Andric2023-12-0811-118/+134
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-17.0.1-25-g098e653a5bed. PR: 273753 MFC after: 1 month
* Merge llvm-project release/17.x llvmorg-17.0.0-rc4-10-g0176e8729ea4Dimitry Andric2023-12-08100-1343/+1075
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-17.0.0-rc4-10-g0176e8729ea4. PR: 273753 MFC after: 1 month
* Merge llvm-project main llvmorg-17-init-19304-gd0b54bb50e51Dimitry Andric2023-12-081972-97277/+183046
| | | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvm-project main llvmorg-17-init-19304-gd0b54bb50e51, the last commit before the upstream release/17.x branch was created. PR: 273753 MFC after: 1 month
* Merge commit 8757ce490130 from llvm-project (by Simon Pilgrim):Dimitry Andric2023-07-163-100/+24
| | | | | | | | | | | | | | | | | | | | | [PowerPC] Replace PPCISD::VABSD cases with generic ISD::ABDU(X,Y) node A move towards using the generic ISD::ABDU nodes on more backends Also support ISD::ABDS for v4i32 types using the existing signbit flip trick PowerPC has a select(icmp_ugt(x,y),sub(x,y),sub(y,x)) -> abdu(x,y) combine that I intend to move to DAGCombiner in a future patch. The ABS(SUB(X,Y)) -> PPCISD::VABSD(X,Y,1) v4i32 combine wasn't legal (https://alive2.llvm.org/ce/z/jc2hLU) - so I've removed it, having already added the legal sub nsw tests equivalent. Differential Revision: https://reviews.llvm.org/D142313 This fixes a "Wasn't expecting to be able to lower this!" fatal error when compiling graphics/opencv for PowerPC. Requested by: pkubaj PR: 271047 MFC after: 1 month
* Merge llvm-project release/16.x llvmorg-16.0.5-0-g185b81e034baDimitry Andric2023-06-224-10/+69
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-16.0.5-0-g185b81e034ba (aka 16.0.5 release). PR: 271047 MFC after: 1 month
* Merge llvm-project release/16.x llvmorg-16.0.4-0-gae42196bc493Dimitry Andric2023-06-223-9/+20
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-16.0.4-0-gae42196bc493 (aka 16.0.4 release). PR: 271047 MFC after: 1 month
* Merge llvm-project release/16.x llvmorg-16.0.3-0-gda3cd333bea5Dimitry Andric2023-06-223-18/+36
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-16.0.3-0-gda3cd333bea5 (aka 16.0.3 release). PR: 271047 MFC after: 1 month
* Merge llvm-project release/16.x llvmorg-16.0.2-0-g18ddebe1a1a9Dimitry Andric2023-06-223-14/+20
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-16.0.2-0-g18ddebe1a1a9 (aka 16.0.2 release). PR: 271047 MFC after: 1 month
* Merge llvm-project release/16.x llvmorg-16.0.1-0-gcd89023f7979Dimitry Andric2023-06-2273-302/+2931
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-16.0.1-0-gcd89023f7979 (aka 16.0.1 release). PR: 271047 MFC after: 1 month
* Merge llvm-project main llvmorg-16-init-18548-gb0daacf58f41Dimitry Andric2023-06-222260-101056/+208241
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-16-init-18548-gb0daacf58f41. PR: 271047 MFC after: 1 month
* Apply llvm fix for hanging gcc builds on 32-bit armDimitry Andric2023-06-191-5/+11
| | | | | | | | | | | | | | | | Merge commit 962c306a11d0 from llvm-project (by Florian Hahn): [LV] Don't consider pointer as uniform if it is also stored. Update isVectorizedMemAccessUse to also check if the pointer is stored. This prevents LV to incorrectly consider a pointer as uniform if it is used as both pointer and stored by the same StoreInst. Fixes #61396. PR: 271992 Reported by: John F. Carr <jfc@mit.edu> MFC after: 3 days
* llvm/lld: damage control threadingMateusz Guzik2023-04-031-2/+13
| | | | | | | See the comment inside. Reviewed by: dim Differential Revision: https://reviews.freebsd.org/D39389
* llvm: make sure to use ELFv2 ABI on powerpc64Piotr Kubaj2023-02-161-1/+4
| | | | | | | | | | Currently LLVM is more or less set up to use ELFv2, but it still defaults to ELFv1 in some places. This causes lld to generate broken binaries when used with LTO. PR: 269455 Approved by: dim MFC after: 3 days
* Merge llvm-project release/15.x llvmorg-15.0.7-0-g8dfdcc7b7bf6Dimitry Andric2023-02-083-7/+12
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15.0.7-0-g8dfdcc7b7bf6. PR: 265425 MFC after: 2 weeks
* Merge llvm-project release/15.x llvmorg-15.0.6-0-g088f33605d8aDimitry Andric2023-02-0816-62/+138
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15.0.6-0-g088f33605d8a. PR: 265425 MFC after: 2 weeks
* Merge llvm-project release/15.x llvmorg-15.0.2-10-gf3c5289e7846Dimitry Andric2023-02-0812-22/+59
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15.0.2-10-gf3c5289e7846. PR: 265425 MFC after: 2 weeks
* Merge llvm-project release/15.x llvmorg-15.0.0-9-g1c73596d3454Dimitry Andric2023-02-0818-116/+429
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15.0.0-9-g1c73596d3454. PR: 265425 MFC after: 2 weeks
* Merge llvm-project release/15.x llvmorg-15.0.0-rc2-40-gfbd2950d8d0dDimitry Andric2023-02-0823-96/+363
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15.0.0-rc2-40-gfbd2950d8d0d. PR: 265425 MFC after: 2 weeks
* Merge llvm-project main llvmorg-15-init-17826-g1f8ae9d7e7e4Dimitry Andric2023-02-08136-1472/+2811
| | | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15-init-17826-g1f8ae9d7e7e4, the last commit before the upstream release/16.x branch was created. PR: 265425 MFC after: 2 weeks
* Merge llvm-project main llvmorg-15-init-17485-ga3e38b4a206bDimitry Andric2023-02-08419-5293/+11599
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15-init-17485-ga3e38b4a206b. PR: 265425 MFC after: 2 weeks
* Merge llvm-project main llvmorg-15-init-16436-g18a6ab5b8d1fDimitry Andric2023-02-08455-4494/+12488
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15-init-16436-g18a6ab5b8d1f. PR: 265425 MFC after: 2 weeks
* Merge llvm-project main llvmorg-15-init-15358-g53dc0f10787Dimitry Andric2023-02-082294-70890/+217747
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15-init-15358-g53dc0f10787. PR: 265425 MFC after: 2 weeks
* Apply llvm fix for assertion/crash building math/vtkDimitry Andric2022-09-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Merge commit 307ace7f20d5 from llvm git (by David Sherwood): [LoopVectorize] Ensure the VPReductionRecipe is placed after all it's inputs When vectorising ordered reductions we call a function LoopVectorizationPlanner::adjustRecipesForReductions to replace the existing VPWidenRecipe for the fadd instruction with a new VPReductionRecipe. We attempt to insert the new recipe in the same place, but this is wrong because createBlockInMask may have generated new recipes that VPReductionRecipe now depends upon. I have changed the insertion code to append the recipe to the VPBasicBlock instead. Added a new RUN with tail-folding enabled to the existing test: Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll Differential Revision: https://reviews.llvm.org/D129550 Reported by: yuri PR: 264834 MFC after: 3 days
* Apply tentative llvm fix for avoiding fma on PowerPC SPEDimitry Andric2022-07-091-0/+2
| | | | | | | | | | | | | | | Merge llvm review D77558, by Justin Hibbits: PowerPC: Don't hoist float multiply + add to fused operation on SPE SPE doesn't have a fmadd instruction, so don't bother hoisting a multiply and add sequence to this, as it'd become just a library call. Hoisting happens too late for the CTR usability test to veto using the CTR in a loop, and results in an assert "Invalid PPC CTR loop!". Reported by: alfredo Obtained from: https://reviews.llvm.org/D77558 MFC after: 3 days
* Apply llvm fix for assertion/crash building archivers/c-blosc2Dimitry Andric2022-07-011-1/+5
| | | | | | | | | | | | | | | | Merge commit 88ce403c6aab from llvm git (by Florian Hahn): [LV] Add new block to place recurrence splice, if needed. In some cases, a recurrence splice instructions needs to be inserted between to regions, for example if the regions get re-arranged during sinking. Fixes #56146. PR: 264979 Reported by: Robert Clausecker <fuz@fuz.su> MFC after: 3 days
* Merge llvm-project release/14.x llvmorg-14.0.5-0-gc12386ae247cDimitry Andric2022-06-127-28/+69
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14.0.5-0-gc12386ae247c, aka 14.0.5 release. PR: 261742 MFC after: 3 days
* Merge llvm-project release/14.x llvmorg-14.0.4-0-g29f1039a7285Dimitry Andric2022-06-0415-26/+1279
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14.0.4-0-g29f1039a7285, aka 14.0.4 release. PR: 261742 MFC after: 3 days
* Apply llvm fix for possible hangs with CPUTYPE=skylake-avx512Dimitry Andric2022-06-011-1/+5
| | | | | | | | | | | | Merge commit e8305c0b8f49 from llvm git (by Simon Pilgrim) [X86] combineX86ShuffleChain - don't fold to truncate(concat(V1,V2)) if it was already a PACK op Fixes #55050 PR: 264394 Reported by: VVD <vvd@unislabs.com> MFC after: 3 days
* Apply llvm fix for "Invalid PPC CTR loop!" error on powerpcspeDimitry Andric2022-05-181-3/+1
| | | | | | | | | | | | | | | Merge commit d9d15af7873f from llvm git (Qiu Chaofan): [PowerPC] Treat llvm.fmuladd intrinsic as using CTR This fixes bug 55463, similar to D78668. This is a temporary fix since we will switch to post-isel CTR loop determination in the future. Reviewed By: dim, shchenz Differential Revision: https://reviews.llvm.org/D125746 MFC after: 2 weeks
* Merge llvm-project release/14.x llvmorg-14.0.3-0-g1f9140064dfbDimitry Andric2022-05-1445-263/+498
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14.0.3-0-g1f9140064dfb. PR: 261742 MFC after: 2 weeks
* Merge llvm-project release/14.x llvmorg-14.0.0-rc4-2-gadd3ab7f4c8aDimitry Andric2022-05-1416-130/+287
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14.0.0-rc4-2-gadd3ab7f4c8a. PR: 261742 MFC after: 2 weeks
* Merge llvm-project release/14.x llvmorg-14.0.0-rc2-12-g09546e1b5103Dimitry Andric2022-05-1420-284/+471
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14.0.0-rc2-12-g09546e1b5103. PR: 261742 MFC after: 2 weeks
* Merge llvm-project release/14.x llvmorg-14.0.0-rc1-74-g4dc3cb8e3255Dimitry Andric2022-05-1430-740/+1388
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14.0.0-rc1-74-g4dc3cb8e3255. PR: 261742 MFC after: 2 weeks
* Apply fix for asm constraint error in www/php80-opcacheDimitry Andric2022-05-141-2/+3
| | | | | | | | | | | | | | | | | | | | | | | Merge commit 027c16bef4b7 from llvm git (by Nick Desaulniers): [X86ISelLowering] permit BlockAddressSDNode "i" constraints for PIC When building 32b x86 code as PIC, the existing handling of "i" constraints is conservative since generally we have to go through the GOT to find references to functions. But generally, BlockAddresses from C code refer to the Function in the current TU. Permit BlockAddresses to be used with the "i" constraint for those cases. I regressed this in commit 4edb9983cb8c ("[SelectionDAG] treat X constrained labels as i for asm") Fixes: https://github.com/llvm/llvm-project/issues/53868 Reviewed By: efriedma, MaskRay Differential Revision: https://reviews.llvm.org/D119905
* Merge llvm-project release/14.x llvmorg-14-init-18315-g190be5457c90Dimitry Andric2022-05-144-3/+9
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14-init-18315-g190be5457c90. PR: 261742 MFC after: 2 weeks
* Merge llvm-project main llvmorg-14-init-18294-gdb01b123d012Dimitry Andric2022-05-14270-2567/+5102
| | | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14-init-18294-gdb01b123d012, the last commit before the upstream release/14.x branch was created. PR: 261742 MFC after: 2 weeks
* Merge llvm-project main llvmorg-14-init-17616-g024a1fab5c35Dimitry Andric2022-05-14964-13302/+31115
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14-init-17616-g024a1fab5c35. PR: 261742 MFC after: 2 weeks
* Merge llvm-project main llvmorg-14-init-13186-g0c553cc1af2eDimitry Andric2022-05-14621-10850/+23349
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14-init-13186-g0c553cc1af2e. PR: 261742 MFC after: 2 weeks
* Merge llvm-project main llvmorg-14-init-11187-g222442ec2d71Dimitry Andric2022-05-14360-4120/+8762
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14-init-11187-g222442ec2d71. PR: 261742 MFC after: 2 weeks
* Merge llvm-project main llvmorg-14-init-10223-g401b76fdf2b3Dimitry Andric2022-05-1413-86/+61
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14-init-10223-g401b76fdf2b3. PR: 261742 MFC after: 2 weeks
* Merge llvm-project main llvmorg-14-init-10186-gff7f2cfa959bDimitry Andric2022-05-141590-48562/+104458
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-14-init-10186-gff7f2cfa959b. PR: 261742 MFC after: 2 weeks
* clang: Skip attempts to access /proc/self/fdMateusz Guzik2022-03-271-1/+13
| | | | | | | | | In contrast to Linux it does not provide entries which can be readlinked -- these are just regular files, not giving the expected outcome. That's on top of procfs not being mounted by default to begin with. Reviewed by: dim Differential Revision: https://reviews.freebsd.org/D34684
* Fix llvm build after 1b3bef43e3cb, due to API changeDimitry Andric2022-03-191-1/+1
| | | | | | | | | | | | | | | | After merging llvm commit b9ca73e1a8fd for PR 262608, it would fail to compile with: /usr/src/contrib/llvm-project/llvm/lib/IR/Operator.cpp:197:22: error: no member named 'isZero' in 'llvm::APInt' if (!IndexedSize.isZero()) { ~~~~~~~~~~~ ^ Upstream refactored their APInt class, and isZero() was one of the newer methods which did not yet exist in llvm 13.0.0. Fix this by using the older but equivalent isNullValue() method instead. Fixes: 1b3bef43e3cb MFC after: 3 days
* Apply llvm fix for assertion compiling certain versions of WineDimitry Andric2022-03-191-4/+6
| | | | | | | | | | | | | | | | | | | | | | Merge commit b9ca73e1a8fd from llvm git (by Stephen Tozer): [DebugInfo] Correctly handle arrays with 0-width elements in GEP salvaging Fixes an issue where GEP salvaging did not properly account for GEP instructions which stepped over array elements of width 0 (effectively a no-op). This unnecessarily produced long expressions by appending `... + (x * 0)` and potentially extended the number of SSA values used in the dbg.value. This also erroneously triggered an assert in the salvage function that the element width would be strictly positive. These issues are resolved by simply ignoring these useless operands. Reviewed By: aprantl Differential Revision: https://reviews.llvm.org/D111809 PR: 262608 Reported by: Damjan Jovanovic <damjan.jov@gmail.com> MFC after: 3 days
* Apply llvm fix for assertion failure compiling recent libc++Dimitry Andric2022-01-293-22/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge commit c7c84b90879f from llvm git (by Adrian Prantl): [DwarfDebug] Refuse to emit DW_OP_LLVM_arg values wider than 64 bits DwarfExpression::addUnsignedConstant(const APInt &Value) only supports wider-than-64-bit values when it is used to emit a top-level DWARF expression representing the location of a variable. Before this change, it was possible to call addUnsignedConstant on >64 bit values within a subexpression when substituting DW_OP_LLVM_arg values. This can trigger an assertion failure (e.g. PR52584, PR52333) when it happens in a fragment (DW_OP_LLVM_fragment) expression, as addUnsignedConstant on >64 bit values splits the constant into separate DW_OP_pieces, which modifies DwarfExpression::OffsetInBits. This change papers over the assertion errors by bailing on overly wide DW_OP_LLVM_arg values. A more comprehensive fix might be to be to split wide values into pointer-sized fragments. [0] https://github.com/llvm/llvm-project/blob/e71fa03/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp#L799-L805 Patch by Ricky Zhou! Differential Revision: https://reviews.llvm.org/D115343 MFC after: 3 days
* Apply clang fix for crash or assertion failure compiling part of llvmDimitry Andric2021-12-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge commit 77e8f4eeeeed from llvm git (by David Green): [ARM] Define ComplexPatternFuncMutatesDAG Some of the Arm complex pattern functions call canExtractShiftFromMul, which can modify the DAG in-place. For this to be valid and handled successfully we need to define ComplexPatternFuncMutatesDAG. Differential Revision: https://reviews.llvm.org/D107476 When building parts of llvm targeting armv6 on stable/12, the following assertion can appear (or if assertions are disabled, clang is likely to crash): Assertion failed: (NodeToMatch->getOpcode() != ISD::DELETED_NODE && "NodeToMatch was removed partway through selection"), function SelectCodeCommon, file /usr/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp, line 3573. PLEASE submit a bug report to https://bugs.freebsd.org/submit/ and include the crash backtrace, preprocessed source, and associated run script. Stack dump: 0. Program arguments: /usr/obj/usr/src/freebsd12-amd64/tmp/usr/bin/c++ -cc1 -triple armv6kz-unknown-freebsd12.3-gnueabihf -S --mrelax-relocations -disable-free -disable-llvm-verifier -discard-value-names -mrelocation-model static -mconstructor-aliases -target-cpu arm1176jzf-s -target-feature +vfp2 -target-feature +vfp2sp -target-feature -vfp3 -target-feature -vfp3d16 -target-feature -vfp3d16sp -target-feature -vfp3sp -target-feature -fp16 -target-feature -vfp4 -target-feature -vfp4d16 -target-feature -vfp4d16sp -target-feature -vfp4sp -target-feature -fp-armv8 -target-feature -fp-armv8d16 -target-feature -fp-armv8d16sp -target-feature -fp-armv8sp -target-feature -fullfp16 -target-feature +fp64 -target-feature -d32 -target-feature -neon -target-feature -sha2 -target-feature -aes -target-feature -fp16fml -target-feature +strict-align -target-abi aapcs-linux -mfloat-abi hard -fallow-half-arguments-and-returns -ffunction-sections -fdata-sections -O1 -std=c++14 -fdeprecated-macro -fno-rtti -fno-signed-char -faddrsig -fexperimental-new-pass-manager PPCISelLowering-009095.ii 1. <eof> parser at end of file 2. Code generation 3. Running pass 'Function Pass Manager' on module 'PPCISelLowering-009095.cpp'. 4. Running pass 'ARM Instruction Selection' on function '@_ZN4llvm17PPCTargetLoweringC2ERKNS_16PPCTargetMachineERKNS_12PPCSubtargetE' This crash or assertion is fixed by the upstream commit. MFC after: 3 days
* Apply fix for clang incorrectly optimizing part of dns/bind916Dimitry Andric2021-12-151-0/+4
| | | | | | | | | | | | | | | | | | | Merge commit e5a8af7a90c6 from llvm git (by Gulfem Savrun Yeniceri): [Passes] Fix relative lookup table converter pass This patch fixes the relative table converter pass for the lookup table accesses that are resulted in an instruction sequence, where gep is not immediately followed by a load, such as gep being hoisted outside the loop or another instruction is inserted in between them. The fix inserts the call to load.relative.instrinsic in the original place of load instead of gep. Issue is reported by FreeBSD via https://bugs.freebsd.org/259921. Differential Revision: https://reviews.llvm.org/D115571 PR: 259921 Reported by: O. Hartmann <freebsd@walstatt-de.de> MFC after: 3 days
* Apply fix for LLVM PR51957 (Miscompilation in Botan's SHA3)Dimitry Andric2021-11-131-6/+19
| | | | | | | | | | | | | | | | | | | | | Merge commit e27a6db5298f from llvm git (by Jameson Nash): Bad SLPVectorization shufflevector replacement, resulting in write to wrong memory location We see that it might otherwise do: %10 = getelementptr {}**, <2 x {}***> %9, <2 x i32> <i32 10, i32 4> %11 = bitcast <2 x {}***> %10 to <2 x i64*> ... %27 = extractelement <2 x i64*> %11, i32 0 %28 = bitcast i64* %27 to <2 x i64>* store <2 x i64> %22, <2 x i64>* %28, align 4, !tbaa !2 Which is an out-of-bounds store (the extractelement got offset 10 instead of offset 4 as intended). With the fix, we correctly generate extractelement for i32 1 and generate correct code. Differential Revision: https://reviews.llvm.org/D106613
* Fix "Bad machine code" when building world for mips or mips64Dimitry Andric2021-11-131-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge commit f5755c0849a5 from llvm git (by Jessica Clarke): [Mips] Add glue between CopyFromReg, CopyToReg and RDHWR nodes for TLS The MIPS ABI requires the thread pointer be accessed via rdhwr $3, $r29. This is currently represented by (CopyToReg $3, (RDHWR $29)) followed by a (CopyFromReg $3). However, there is no glue between these, meaning scheduling can break those apart. In particular, PR51691 is a report where PseudoSELECT_I was moved to between the CopyToReg and CopyFromReg, and since its expansion uses branches, it split the def and use of the physical register between two basic blocks, resulting in the def being eliminated and the use having no def. It also seems possible that a similar situation could arise splitting up the CopyToReg from the RDHWR, causing the RDHWR to use a destination register other than $3, violating the ABI requirement. Thus, add glue between all three nodes to ensure they aren't split up during instruction selection. No regression test is added since any test would be implictly relying on specific scheduling behaviour, so whilst it might be testing that glue is preventing reordering today, changes to scheduling behaviour could result in the test no longer being able to catch a regression here, as the reordering might no longer happen for other unrelated reasons. Fixes PR51691. Reviewed By: atanasyan, dim Differential Revision: https://reviews.llvm.org/D111967
* Merge llvm-project 13.0.0 releaseDimitry Andric2021-11-136-38/+42
| | | | | | | | This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-13.0.0-0-gd7b669b3a303, aka 13.0.0 release. PR: 258209 MFC after: 2 weeks
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