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On boot we don't need to perform any CPU cache management when the IDC
and DIC fields in the ctr_el0 register are set. Add a command to tell
loader to ignore these fields. This could be useful, for example, if the
hardware is misreporting the values and we are missing a quirk to enable
it.
It is not expected this will be needed, but is only intended as a
workaround to ensure the kernel can still boot.
Sponsored by: The FreeBSD Foundation
(cherry picked from commit c399283c71e310e1573e8d27f9cb9d27a4ea3376)
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In the arm64 loader we need to syncronise the I and D caches. On some
newer CPUs the I and D caches are coherent so we don't need to perform
these operations.
While here remove the arguments to cpu_inval_icache as they are unneeded.
Reported by: cperciva
Tested by: cperciva
Sponsored by: Innovate UK
(cherry picked from commit c1381f07f61a66979f1569995f37f2a0413c0413)
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Notes:
svn path=/head/; revision=333079
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Sponsored by: Netflix
Notes:
svn path=/head/; revision=325834
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