aboutsummaryrefslogtreecommitdiff
path: root/sys/amd64/pci/pci_cfgreg.c
Commit message (Expand)AuthorAgeFilesLines
* pci_cfgreg.c: Use io port config access for early boot time.Konstantin Belousov2019-04-091-50/+7
* Do not flush cache for PCIe config window.Konstantin Belousov2018-10-181-1/+1
* sys/amd64: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-271-0/+2
* pcicfg: Fix direct calls of pci_cfg{read,write} on systems w/o PCI host bridge.Sepherosa Ziehau2017-05-041-6/+7
* Pull in r267961 and r267973 again. Fix for issues reported will follow.Hans Petter Selasky2014-06-281-1/+0
* Revert r267961, r267973:Glen Barber2014-06-271-0/+1
* Extend the meaning of the CTLFLAG_TUN flag to automatically check ifHans Petter Selasky2014-06-271-1/+0
* Fix undefined behavior: (1 << 31) is not defined as 1 is an int and thisEitan Adler2013-11-301-1/+1
* Remove duplicate code. Reduce diff between amd64 and i386.Jung-uk Kim2012-12-011-6/+7
* Use volatile keywords properly.Jung-uk Kim2012-11-301-11/+11
* Tidy up inline assembly. No functional change.Jung-uk Kim2012-11-301-8/+8
* pciereg_cfg*: use assembly to access the mem-mapped cfg spaceAndriy Gapon2012-10-141-6/+19
* number of cleanups in i386 and amd64 pci md codeAndriy Gapon2009-09-241-8/+8
* Add a read-only sysctl hw.pci.mcfg to mirror the tunable by the same name.John Baldwin2009-05-181-0/+5
* Fall back to using configuration type 1 accesses for PCI config requests ifJohn Baldwin2009-03-241-0/+2
* Add a 'hw.pci.mcfg' tunable. It can be set to 0 to disable memory-mappedJohn Baldwin2008-09-111-0/+6
* Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIeJohn Baldwin2008-09-101-14/+48
* Extend the support for PCI-e memory mapped configuration space access:John Baldwin2008-08-221-3/+137
* Adjust the code to probe for the PCI config mechanism to use.John Baldwin2007-11-281-167/+11
* Modify the pci_cfgdisable() routine to bring it more in line withBill Paul2005-10-251-2/+6
* MFi386: whitespace, copyright header, etc updatesPeter Wemm2005-01-211-1/+0
* Begin all license/copyright comments with /*-Warner Losh2005-01-051-1/+1
* MFi386: nuke pci_cfgintrPeter Wemm2004-03-131-22/+1
* MFi386: change an outb to a DELAY()Peter Wemm2004-01-281-1/+1
* Various whitespace and cosmetic sync-up's with i386.Peter Wemm2003-12-061-0/+1
* Use __FBSDID().David E. O'Brien2003-07-251-3/+3
* Commit MD parts of a loosely functional AMD64 port. This is based onPeter Wemm2003-05-011-489/+15
* Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has beenPeter Wemm2003-02-181-129/+28
* MFp4:Warner Losh2002-11-141-1/+1
* MFp4:Warner Losh2002-11-021-10/+34
* Use 0xffffffff instead of -1 for id to compare against.Warner Losh2002-11-021-10/+11
* o go ahead and route the interupt, even if it is supposedly unique.Warner Losh2002-10-071-7/+12
* Don't call function in return() for a void function.Poul-Henning Kamp2002-09-281-3/+5
* Put verbose printf's in the PCI BIOS interrupt routing code underJohn Baldwin2002-09-231-1/+4
* Axe unused include.John Baldwin2002-09-201-1/+0
* Make sure a $PIR table header has a valid length before accepting the tableJohn Baldwin2002-09-091-1/+2
* Add a function pci_probe_route_table() that returns true if our PCI BIOSJohn Baldwin2002-09-061-0/+19
* Dump the $PIR table if booting verbose.John Baldwin2002-09-061-0/+3
* - Add a pci_cfgintr_valid() function to see if a given IRQ is a validJohn Baldwin2002-09-061-1/+33
* Add support for printing out the contents of a PCI BIOS $PIR interruptJohn Baldwin2002-09-061-2/+54
* Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,John Baldwin2002-09-051-2/+2
* style(9)ize the whole fileWarner Losh2002-07-211-474/+492
* Use a common function to map the bogus intlines.Warner Losh2002-06-011-11/+17
* Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just havingBrooks Davis2002-05-291-0/+8
* o Work around bugs in the powerof2 macro: It thinks that 0 is a power ofWarner Losh2002-04-241-12/+18
* Don't call the bios if the interrupt appaers to be already routed. SomeWarner Losh2002-03-161-3/+3
* The Libretto L series has no $PIR table, but does have a _PIR table.Warner Losh2002-01-201-13/+22
* MFS: I was confused. This code wasn't in -current after all.Warner Losh2001-11-261-5/+14
* It turns out that while Toshiba laptops don't want to route interruptsWarner Losh2001-08-281-17/+10
* MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.Warner Losh2001-08-271-30/+60