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* Consolidate identical ELF auxargs type defintions.Brooks Davis2018-10-221-32/+0
* Remove the L1 and L2 xscale page defines and rename the generic macros toAndrew Turner2018-08-161-64/+9
* Remove pmap_kenter_section from the arm pmap. It's unused.Andrew Turner2018-08-151-1/+0
* Remove ARM_HAVE_SUPERSECTIONS. It was only supported on some XScale CPUs.Andrew Turner2018-08-151-8/+0
* Make code and data only used within the arm pmap code as static.Andrew Turner2018-08-151-21/+0
* Remove arm pmap variables that are only ever set and never read.Andrew Turner2018-08-151-8/+0
* Remove ARM_MMU_GENERIC, it's the only ARMV4/v5 MMU we support.Andrew Turner2018-08-151-35/+0
* Remove checks for now unsupported CPU_* values in arm headers.Andrew Turner2018-08-152-28/+4
* Start to remove XScale support from the ARMv4/v5 pmap. Support for XScaleAndrew Turner2018-08-151-10/+0
* Remove cpu_pfr from arm. It's unused.Andrew Turner2018-08-141-1/+0
* Add support for pmap_enter(..., psind=1) to the armv6 pmap. In other words,Alan Cox2018-08-081-0/+1
* Implement atomic_swap_64(9).Marius Strobl2018-08-071-0/+13
* Use the cp15 functions to read cp15 registers rather than using assemblyAndrew Turner2018-07-281-4/+0
* Make the arm cpu setup functions static. Any other place that needs theseAndrew Turner2018-07-281-7/+0
* Remove old CPU_ values from the arm cpufunc code. These have been removed.Andrew Turner2018-07-281-110/+1
* Only support INTRNG in the SMP code on arm. We already require INTRNG onAndrew Turner2018-07-281-18/+0
* Revert r336773: it removed too much.Warner Losh2018-07-278-7/+211
* Remove xscale supportWarner Losh2018-07-278-211/+7
* Remove Atmel AT91RM9200 and AT91SAM9 support.Warner Losh2018-07-271-110/+0
* arm: Implement cpu_est_clockrate for armv[67]Emmanuel Vadot2018-07-191-1/+2
* Remove the dead code from ARM cpufunc_* files.Michal Meloun2018-07-181-13/+0
* Also check if __ARM_ARCH_6KZ__ is defined when detecting when to use ARMv6Andrew Turner2018-07-181-0/+1
* Remove kernel support for armebWarner Losh2018-07-173-9/+5
* Export a breakpoint() function to userland for arm and arm64.John Baldwin2018-07-061-1/+14
* Back pcpu zone with domain correct pagesMatt Macy2018-07-061-2/+2
* Allow us to read the physmap data into our own array and use this to buildAndrew Turner2018-05-241-0/+1
* Remove 'All Rights Reserved.' from all of my Copyrights in sys/arm andWarner Losh2018-05-014-4/+2
* Implement 32-bit atomic_fcmpset() in userland for armv4/v5.John Baldwin2018-04-231-3/+31
* Fix some harmless type mismatches in the ARM atomic_cmpset implementations.John Baldwin2018-04-232-28/+28
* No need to force md code to define a macro that's the same asWarner Losh2018-04-161-3/+0
* Enable ArmadaXP using INTRNG interrupt controllerMarcin Wojtas2018-04-031-7/+0
* amd64: Protect the kernel text, data, and BSS by setting the RW/NX bitsJonathan T. Looney2018-03-061-0/+13
* Do not include float interfaces when using libsa.Warner Losh2018-02-231-0/+2
* Move __va_list and related defines to sys/sys/_types.hWarner Losh2018-02-121-14/+0
* Implement mitigation for Spectre version 2 attacks on ARMv7.Michal Meloun2018-01-272-1/+9
* Define PHYS_TO_DMAP() and DMAP_TO_PHYS() as panics on the architecturesNathan Whitehorn2018-01-191-0/+2
* Remove SFBUF_OPTIONAL_DIRECT_MAP and such hacks, replacing them across theNathan Whitehorn2018-01-191-0/+2
* Make kernel option KERNVIRTADDR optional, remove it from std.<platform>Ian Lepore2017-12-301-0/+13
* Introduce an architecture-agnostic <sys/_stdarg.h> to reducePoul-Henning Kamp2017-12-251-51/+7
* Remove arm-specific implementations of atomic_load/store_xxx() now thatIan Lepore2017-12-201-27/+0
* Add atomic_load(9) and atomic_store(9) operations.Konstantin Belousov2017-12-191-0/+2
* Add the virtualisation special register definitions.Andrew Turner2017-12-141-6/+29
* sys/arm: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-2743-1/+87
* sys: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-2013-0/+26
* spdx: initial adoption of licensing ID tags.Pedro F. Giffuni2017-11-187-0/+14
* All CP15 registers are bit fields or counters, don't use signed typeMichal Meloun2017-11-052-6/+6
* Add a 'place holder' arm struct efi_fb until a real one comesWarner Losh2017-10-261-0/+15
* Fullify implementation of AT_HWCAP and AT_HWCAP2 for ARMv6,7.Michal Meloun2017-10-213-0/+33
* Add AT_HWCAP2 ELF auxiliary vector.Michal Meloun2017-10-211-1/+2
* Save VFP state in getcontext(3) on ARM.Michal Meloun2017-10-162-0/+7
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