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* atomics: Constify loadsOlivier Certner2025-01-171-1/+1
* arm64: Ensure sctlr and pstate are in known statesAndrew Turner2024-09-021-0/+4
* arm64: Support counter access with E2HAndrew Turner2024-09-021-2/+7
* arm64: Fix indentation to be consistentAndrew Turner2024-07-151-7/+7
* arm64: Add the pointer auth registers to armreg.hAndrew Turner2024-07-151-0/+80
* arm64: Use the UL macro in TCR_EL1 definesAndrew Turner2024-07-151-48/+48
* arm64: add PMBSR_MSS_{BSC,FSC} status code fieldZachary Leaf2024-07-151-0/+2
* arm64: make SPE regs use ALT_NAME macroZachary Leaf2024-07-151-60/+72
* arm64: Add MRS_REG_ALT_NAME ID register macrosAndrew Turner2024-07-151-0/+15
* am64: Allow cpu.h to be included from assemblyAndrew Turner2024-07-151-0/+4
* arm64: Add EL1 hardware breakpoint exceptionsAndrew Turner2024-07-152-1/+4
* arm64: Add a macro to find a VM fault addressAndrew Turner2024-07-151-0/+2
* arm64: Add the TCR_EL2.PS maskAndrew Turner2024-07-151-0/+1
* arm64: Add ISS_MSR_REG for ESR_ELx.ISS valuesAndrew Turner2024-07-151-0/+6
* arm64: Add more spsr_el1 register valuesAndrew Turner2024-07-151-0/+7
* Mark the arm64 PSR register fields with ULAndrew Turner2024-07-151-23/+23
* arm64: Add CurrentEL register definitionsAndrew Turner2024-07-151-0/+8
* arm64: Decode the ID_AA64PFR2_EL1 registerAndrew Turner2024-07-151-0/+8
* arm64: Decode the ID_AA64MMFR4_EL1 registerAndrew Turner2024-07-151-0/+8
* arm64: Decode the ID_AA64MMFR3_EL1 registerAndrew Turner2024-07-151-0/+28
* arm64, riscv: removed unused struct pv_addrMitchell Horne2024-06-061-10/+0
* arm64, riscv: remove unused declarationMitchell Horne2024-06-061-1/+0
* arm64: Add more HWCAP2 valuesAndrew Turner2024-02-191-0/+27
* arm64: Expand HWCAP2 to be 64 bitAndrew Turner2024-02-191-18/+18
* arm64: Add a BTI landing pad to .mcountAndrew Turner2024-02-191-0/+2
* arm64: Add PAC instruction macrosAndrew Turner2024-02-191-0/+22
* arm64: Support creating a BTI & PAC noteAndrew Turner2024-02-191-0/+52
* arm64: Add BTI landing pads to assembly functionsAndrew Turner2024-02-191-1/+29
* Add BTI exceptionsAndrew Turner2024-02-191-0/+1
* arm64: Add TCR register masksAndrew Turner2024-02-191-1/+4
* arm64: Fix the TCR_TBI0 macro to use ULAndrew Turner2024-02-191-1/+1
* arm64: Fix the TCR_EPD0 definitionAndrew Turner2024-02-191-1/+1
* pci_cfgreg: Add shims to preserve ABI of pci_cfgreg(read|write)John Baldwin2024-01-181-2/+5
* pci_cfgreg: Add a PCI domain argument to the low-level register APIJohn Baldwin2024-01-181-2/+2
* arm64: lop off another 24MB of KVA for early device mappingsKyle Evans2023-12-151-1/+5
* add pmap_active_cpus()Konstantin Belousov2023-10-261-0/+2
* arm64: Update the ID_AA64PFR1_EL1 fieldsAndrew Turner2023-09-251-9/+37
* arm64: Update the ID_AA64PFR0_EL1 fieldsAndrew Turner2023-09-251-5/+12
* arm64: Don't use hex for ID_AA64MMFR2_EL1_op/CR*Andrew Turner2023-09-251-5/+5
* arm64: Update the ID_AA64MMFR1_EL1 fieldsAndrew Turner2023-09-251-0/+36
* arm64: Update the ID_AA64MMFR0_EL1 fieldsAndrew Turner2023-09-251-10/+25
* arm64: Update the ID_AA64ISAR1_EL1 fieldsAndrew Turner2023-09-251-5/+18
* arm64: Update the ID_AA64ISAR0_EL1 fieldsAndrew Turner2023-09-251-5/+9
* arm64: Update the ID_AA64DFR0_EL1 fieldsAndrew Turner2023-09-251-6/+38
* Add more arm64 special register valuesAndrew Turner2023-09-251-0/+16
* arm64: Fix the definition of ID_AA64DFR1_EL1Andrew Turner2023-09-251-1/+1
* Add more arm64 ID registersAndrew Turner2023-09-251-0/+16
* Add more arm64 special registersAndrew Turner2023-09-251-2/+46
* Split out pmap_map_delete on arm64Andrew Turner2023-09-251-1/+1
* Mark EENTRY as .textAndrew Turner2023-09-251-1/+1
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