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* arm64: Add a function to check a range of CPU revsAndrew Turner2026-01-141-0/+25
* arm64: Replace cpu_tlb_flushID in initarmAndrew Turner2026-01-141-0/+2
* arm64: Read the CPU feature tunables onceAndrew Turner2026-01-141-0/+3
* arm64: Add cpu_feat_disabled for disabled featuresAndrew Turner2026-01-141-1/+4
* arm64: Support managing features from loaderAndrew Turner2026-01-141-1/+26
* arm64: Add a sysctl to see if features are enabledAndrew Turner2026-01-141-3/+10
* arm64: Add a macro to create cpu_featAndrew Turner2026-01-141-0/+10
* arm64: Add a new CPU feature frameworkAndrew Turner2026-01-141-0/+88
* arm64: Add the new C1 CPU IDsAndrew Turner2026-01-141-0/+4
* arm64: Add more CPU MIDR valuesAndrew Turner2026-01-141-1/+19
* runq: Deduce most parameters, remove machine headersOlivier Certner2025-07-281-50/+0
* Don't rely on sys/_types.h including sys/cdefs.hBrooks Davis2025-06-231-0/+2
* arm64: bus: Add 36-bit address mask for use in bus space allocationsKa Ho Ng2025-03-151-0/+1
* atomics: Constify loadsOlivier Certner2025-01-161-1/+1
* atomic(9): Implement atomic_testand(clear|set)_ptrJohn Baldwin2024-12-011-0/+2
* arm64: Stop trashing x28 in savectxAndrew Turner2024-10-211-1/+1
* arm64: Enable SVE in userspaceAndrew Turner2024-10-211-0/+1
* arm64: Don't trap SVE to EL2Andrew Turner2024-10-211-1/+1
* arm64: Support SVE in ptrace and core dumpsAndrew Turner2024-10-211-0/+13
* arm64: Add an SVE sysarchAndrew Turner2024-10-211-0/+3
* arm64: Add the SVE registers to the signal frameAndrew Turner2024-10-211-0/+8
* arm64: Initial SVE supportAndrew Turner2024-10-213-3/+18
* arm64: Create a version of vfp_save_state for cpu_switchAndrew Turner2024-10-211-0/+1
* arm64: Split out a savectx version of vfp_save_stateAndrew Turner2024-10-211-0/+1
* arm64: Adjust the indentation of CPTR_EL2 valuesAndrew Turner2024-10-211-6/+6
* arm64: add additional MDCR_EL2 fieldsZachary Leaf2024-10-211-0/+30
* arm64: Add the tcr_el2 ds fieldAndrew Turner2024-10-211-0/+2
* arm64: Fix the ESR_EL1_op2 valueAndrew Turner2024-10-211-1/+1
* arm64: Add EL1 and EL12 register alt namesAndrew Turner2024-10-211-0/+222
* arm64: add CONTEXTIDR_EL1 regZachary Leaf2024-10-211-0/+9
* armv8rng: Don't require toolchain to support FEAT_RNGJessica Clarke2024-10-211-0/+9
* intrng: Extract arm/arm64 IPI->PIC glue codeJessica Clarke2024-09-061-4/+0
* arm64: Expand the use of Armv8.1-A atomicsAndrew Turner2024-09-021-2/+3
* arm64: Ensure sctlr and pstate are in known statesAndrew Turner2024-09-021-0/+4
* arm64: Support counter access with E2HAndrew Turner2024-09-021-2/+7
* arm64: Support passing more registers to signalsAndrew Turner2024-09-021-1/+15
* arm64: Fix indentation to be consistentAndrew Turner2024-07-151-7/+7
* arm64: Add the pointer auth registers to armreg.hAndrew Turner2024-07-151-0/+80
* arm64: Use the UL macro in TCR_EL1 definesAndrew Turner2024-07-151-48/+48
* arm64: add PMBSR_MSS_{BSC,FSC} status code fieldZachary Leaf2024-07-151-0/+2
* arm64: make SPE regs use ALT_NAME macroZachary Leaf2024-07-151-60/+72
* arm64: Add MRS_REG_ALT_NAME ID register macrosAndrew Turner2024-07-151-0/+15
* am64: Allow cpu.h to be included from assemblyAndrew Turner2024-07-151-0/+4
* arm64: Add EL1 hardware breakpoint exceptionsAndrew Turner2024-07-152-1/+4
* arm64: Add a macro to find a VM fault addressAndrew Turner2024-07-151-0/+2
* arm64: Add the TCR_EL2.PS maskAndrew Turner2024-07-151-0/+1
* arm64: Add ISS_MSR_REG for ESR_ELx.ISS valuesAndrew Turner2024-07-151-0/+6
* arm64: Add more spsr_el1 register valuesAndrew Turner2024-07-151-0/+7
* arm64: Add CurrentEL register definitionsAndrew Turner2024-07-151-0/+8
* arm64, riscv: removed unused struct pv_addrMitchell Horne2024-05-271-10/+0
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