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* ig4_iic: Allow sleeping if called from iichid interrupt handler.Vladimir Kondratyev2025-05-152-5/+1
| | | | | | | | | | | This replaces 50 ms busy loop with mtx_sleep for the same duration thus saving CPU time when iichid is driven with interrupts. Sponsored by: Future Crew, LLC MFC after: 2 month Differential Revision: https://reviews.freebsd.org/D48956 (cherry picked from commit c7225a3ede3cf99c538158962f4d65dee435bbcd)
* ig4(4): Add Intel ACPI HIDDmitry Luhtionov2025-04-301-0/+1
| | | | | | MFC after: 1 month (cherry picked from commit 64dcfa2593d4729f16cb3e2d97088a2e69900df1)
* ig4(4): Add Meteor Lake PCI IDsAustin Shafer2024-11-121-0/+4
| | | | | | | PR: 282389 MFC after: 3 days (cherry picked from commit bab5e3d468305928e9e5cf1ca9efcee4c89f6a76)
* Add smbus and i2c device IDs for Meteor LakeSHENG-YI HONG2024-10-171-0/+8
| | | | | | | | | | Reviewed by: emaste, Daniel Schaefer <dhs@frame.work> MFC after: 3 days Sponsored by: Framework Computer Inc Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D46249 (cherry picked from commit d3b05d0ea10abe059dc63c6fb6ef3f061b758af2)
* ig4: Actively use FIFO thresholdsAlexander Motin2024-01-191-20/+17
| | | | | | | | | | | | | | | Before every wait for FIFO interrupt set how much data/space do we want to see there. Previous code was not using it for receive, as result aggregating interrupts only within processing latency. The new code needs only one interrupt per transfer per FIFO length. On my Dell XPS 13 9310 with iichid(4) touchscreen and touchpad this reduces the interrupt rate per device down to 2 per sample or 16-20 per second when idle and 120-160 per second when actively touched. MFC after: 1 month (cherry picked from commit 13037eaabede7fb7fbc25f4e84b549c73f9acb3c)
* ig4: Fix FIFO depths detectionAlexander Motin2024-01-191-19/+31
| | | | | | | | | | | | | | At least on my Tiger Lake-LP queue depth detection failed before the ig4iic_set_config() call, resulting in no FIFO use. Moving it after solves the problem, getting proper 64 bytes size. On my Dell XPS 13 9310 with iichid(4) touchscreen and touchpad this by few times reduces context switch rate in the driver, and probably also improves the I2C bus utilization. MFC after: 1 month (cherry picked from commit 9c9d7fdd9f0041783955c5f540ac55a900877c0c)
* ig4: Add PCI IDs for Intel Ice Lake I2C controller.Vladimir Kondratyev2023-12-191-0/+12
| | | | | PR: 275115 Tested by: Sam <sam3423.yntmr_AT_slmail_DOT_me>
* sys: Remove $FreeBSD$: one-line .c patternWarner Losh2023-08-163-6/+0
| | | | Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
* sys: Remove $FreeBSD$: two-line .h patternWarner Losh2023-08-162-4/+0
| | | | Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
* ichiic: use bool for one-bit wide bit-fieldsDimitry Andric2023-04-194-12/+12
| | | | | | | | | | | A one-bit wide bit-field can take only the values 0 and -1. Clang 16 introduced a warning that "implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1". Fix by using c99 bool. Reported by: Clang Reviewed by: emaste, wulf MFC after: 3 days Differential Revision: https://reviews.freebsd.org/D39665
* ig4(4): Add device HID to match I2C controller on ASUS X540 laptopsVladimir Kondratyev2022-07-211-0/+1
| | | | | Tested by: Andrés Ramírez <rrandresf_AT_hotmail_DOT_com> MFC after: 1 week
* ichiic: Remove unused devclass arguments to DRIVER_MODULE.John Baldwin2022-05-094-8/+2
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* Remove unused iicbus_devclass.John Baldwin2022-05-061-3/+2
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* ig4(4): Add PNP info for ACPI attachmentVladimir Kondratyev2022-03-021-0/+1
| | | | MFC after: 2 month
* ig4: Add PCI IDs for Intel Alder Lake I2C controller.Alexander Motin2021-11-251-0/+40
| | | | | Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> MFC after: 2 weeks
* ig4: Add PCI IDs for Intel Gemini Lake I2C controller.Vladimir Kondratyev2021-02-233-1/+24
| | | | | Submitted by: Dmitry Luhtionov MFC after: 2 weeks
* ig4(4): Increase timeout to about 1 secondAllan Jude2021-02-181-1/+1
| | | | | | | | | | | | | | | | | | Per the i2c spec, a slave device can stretch SCL idefinitely, so 25ms is a bit arbitrary in general. smbus does specify an optional timeout recovery mechanism to be done at about 25~35ms, but the IPMI SSIF spec says that BMCs don't have any obligation to implement that. The BMC on Altra seems to mostly respond within 25ms, but occasionally will stretch SCL for ~300 msec. Also, the count_us mechanism seems to actually timeout around 25% earlier than it would claim (timeout really happening around 19ms instead of 25ms). Sponsored by: Ampere Computing LLC Submitted by: Klara Inc. Reviewed by: manu, imp Differential Revision: https://reviews.freebsd.org/D28747
* ig4(4): Add PCI IDs for Intel Tiger LakeVladimir Kondratyev2020-12-053-3/+46
| | | | | | | | Submitted by: Neel Chauhan <neel AT neelc DOT org> Differential Revision: https://reviews.freebsd.org/D27483 Notes: svn path=/head/; revision=368366
* ig4(4): Add PCI IDs for Intel Comit Lake I2C controllers.Vladimir Kondratyev2020-10-311-0/+28
| | | | | | | MFC after: 2 weeks Notes: svn path=/head/; revision=367230
* ig4iic_acpi_probe: remove set but unused variableAndriy Gapon2020-04-301-2/+0
| | | | | | | MFC after: 1 week Notes: svn path=/head/; revision=360499
* ig4(4): Add PCI IDs for Intel Bay Trail I2C controllers.Vladimir Kondratyev2020-04-261-0/+14
| | | | | | | | | PR: 245654 Reported by: <xspbe3ho3p5uac@protonmail.com> MFC after: 1 week Notes: svn path=/head/; revision=360355
* ig4: ensure that drivers always attach in correct orderAndriy Gapon2020-04-241-1/+2
| | | | | | | | | | | | | | | | | | | Use DRIVER_MODULE_ORDERED(SI_ORDER_ANY) so that ig4's ACPI attachment happens after iicbus and acpi_iicbus drivers are registered. I have seen a problem where iicbus attached under ig4 instead of acpi_iicbus when ig4.ko was loaded with kldload. I believe that that happened because ig4 driver was a first driver to register, it attached and created an iicbus child. Then iicbus driver was registered and, since it was the only driver that could attach to the iicbus child device, it did exactly that. After that acpi_iicbus driver was registered. It would be able to attach to the iicbus device, but it was already attached, so nothing happened. MFC after: 2 weeks Notes: svn path=/head/; revision=360241
* iicbus(4): Add support for ACPI-based children enumerationVladimir Kondratyev2020-03-091-0/+4
| | | | | | | | | | | | | | | | | | | | When iicbus is attached as child of Designware I2C controller it scans all ACPI nodes for "I2C Serial Bus Connection Resource Descriptor" described in section 19.6.57 of ACPI specs. If such a descriptor is found, I2C child is added to iicbus, it's I2C address, IRQ resource and ACPI handle are added to ivars. Existing ACPI bus-hosted child is deleted afterwards. The driver also installs so called "I2C address space handler" which is disabled by default as nontested. Set hw.iicbus.enable_acpi_space_handler loader tunable to 1 to enable it. Reviewed by: markj MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D22901 Notes: svn path=/head/; revision=358820
* [ig4] Remove unused methods from bus interfaceVladimir Kondratyev2019-12-102-4/+0
| | | | | | | | | | | bus_get/set_resource methods are implemented in child device (iicbus). As their implementation with bus_generic_rl_get/set calls do not recurse up the tree, the versions in ig4 are never called. Suggested by: jhb Notes: svn path=/head/; revision=355596
* [ig4] Try to workaround MIPS namespace pollution issueVladimir Kondratyev2019-11-041-5/+5
| | | | Notes: svn path=/head/; revision=354327
* [ig4] Convert ithread interrupt handler to filter based one.Vladimir Kondratyev2019-11-031-9/+13
| | | | Notes: svn path=/head/; revision=354322
* [ig4] Enable additional registers support on Appolo Lake controllersVladimir Kondratyev2019-11-031-1/+1
| | | | | | | To be inline with intel-lpss Linux driver Notes: svn path=/head/; revision=354321
* [ig4] Add support for CannonLake controllersVladimir Kondratyev2019-11-034-10/+37
| | | | | | | | | | They are clocked at 216MHz rate, much higher than previous models. PR: 240485 Submitted by: Neel Chauhan <neel@neelc.org> Notes: svn path=/head/; revision=354320
* [ig4] Add generic resource methods to bus interfaceVladimir Kondratyev2019-11-032-0/+23
| | | | | | | That allows ig4 children to allocate IRQs Notes: svn path=/head/; revision=354319
* [ig4] Minor improvement of write pipeliningVladimir Kondratyev2019-11-031-0/+8
| | | | | | | With leaving some data queued in the TX FIFO at the end of write cycle. Notes: svn path=/head/; revision=354318
* [ig4] wait for bus stop condition after stop command issuedVladimir Kondratyev2019-11-031-1/+9
| | | | | | | | It gives better error detection and ig4 driver's lock coverage in a pipelined write case Notes: svn path=/head/; revision=354317
* [ig4] On SkyLake controllers issue reset on attach unconditionally.Vladimir Kondratyev2019-11-031-1/+1
| | | | | | | | It is very helpful during debugging of I2C issues. It is done only for SkyLakes due to lack of testing on other hardware. Notes: svn path=/head/; revision=354316
* [ig4] Set STOP condition and flush TX/RX FIFOs on errorVladimir Kondratyev2019-11-032-22/+66
| | | | | | | | | if controller has not it done for us yet. Reset controller when transfer abort is failed. Notes: svn path=/head/; revision=354315
* [ig4] Improve error detectionVladimir Kondratyev2019-11-032-14/+71
| | | | | | | | | | | | | | | Handle error bits of INTR_STAT and TX_ABORT registers. Move interrupt clearing from interrupt handler to polling loop to get common execution path with polled mode. Do not clear interrupts with reading of IG4_REG_CLR_INTR register as interrupts, triggered during the period from reg_read(IG4_REG_INTR_STAT) to reg_read(IG4_REG_CLR_INTR) will be missed. Instead, read each IG4_REG_CLR_* register separately. Notes: svn path=/head/; revision=354314
* [ig4] Convert polling loop from status-based to interrupt-basedVladimir Kondratyev2019-11-031-21/+12
| | | | | | | | | INTR_STAT register exposes more useful informaton then STA register does e.g. it exposes error and I2C bus STOP conditions. Make it a main source of I2C transfer state. Notes: svn path=/head/; revision=354313
* [ig4] Use interrupts for waiting for empty TX FIFOVladimir Kondratyev2019-11-031-0/+9
| | | | Notes: svn path=/head/; revision=354312
* [ig4] Convert last remaining usage of TX_NOTFULL status to TX_EMPTYVladimir Kondratyev2019-11-031-4/+4
| | | | | | | | in ig4iic_read routine. It makes possible interrupt utilization while waiting for empty space in TX FIFO. Notes: svn path=/head/; revision=354311
* [ig4] Rewrite ig4iic_write routine to use TX_EMPTY status flagVladimir Kondratyev2019-11-031-10/+20
| | | | | | | | rather than TX_NOTFULL. It makes possible interrupt utilization while waiting for empty space in TX FIFO. Notes: svn path=/head/; revision=354310
* [ig4] Remove dead code inherited from DragonflyBSDVladimir Kondratyev2019-11-032-26/+0
| | | | Notes: svn path=/head/; revision=354309
* [ig4] Add suspend/resume supportVladimir Kondratyev2019-11-034-17/+106
| | | | | | | | | | That is done with re-execution of controller initialization procedure from resume handler. PR: 238037 Notes: svn path=/head/; revision=354308
* [ig4] Implement burst mode for data readsVladimir Kondratyev2019-11-033-24/+91
| | | | | | | | | | | In this mode DATA_CMD register reads and writes are performed in TX/RX FIFO-sized bursts to increase I2C bus utilization. That reduces read time from 60us to 30us per byte when read data is fit in to RX FIFO buffer in FAST speed mode in my setup. Notes: svn path=/head/; revision=354307
* [ig4] Set clock registers based on controller modelVladimir Kondratyev2019-11-033-27/+250
| | | | | | | | | | | | IC clock rates are varied between different controller models so we have to adjust timing registers in each case individually. Borrow intresting constants and formulas from Intel specs, i2c-designware and lpss_intel drivers and apply them to FreeBSD supported controller models. Implement fetching of timing data via ACPI methods execution if available. Notes: svn path=/head/; revision=354306
* [ig4] dump IG4_REG_COMP_PARAM1 and IG4_REG_COMP_VER registers unconditionallyVladimir Kondratyev2019-11-032-5/+3
| | | | | | | They appeared to be supported (although undocumented) on SkyLakes+ too. Notes: svn path=/head/; revision=354305
* [ig4] Do not wait until interrupts are enabled at attach stageVladimir Kondratyev2019-11-032-29/+3
| | | | | | | | | | | | as the driver is fully functional on a cold boot through utilization of polled mode. As a side effect, ig4 children probe and attach methods can be called earlier in the boot sequence, so now it is up to the child drivers to wait for a kernel initialization completion if it is required. Notes: svn path=/head/; revision=354303
* [ig4] Allow enabling of polled mode from iicbus allocation callbackVladimir Kondratyev2019-11-034-7/+50
| | | | | | | | | | If controller is allocated with IIC_NOWAIT option ig4 enables polled mode for a period of allocation that makes possible to start I2C transfers from the contexts where sleeping is not allowed e.g. from ithreads or callouts. Notes: svn path=/head/; revision=354302
* [ig4] Add support for polled modeVladimir Kondratyev2019-11-031-1/+5
| | | | | | | | | | | | Currently ig4 internally depends on it's own interrupts and uses mtx_sleep() to wait for them. That means it can not be used from any context where sleeping is disallowed e.g. on cold boot, from DDB/KDB, from other device driver's interrupt handlers and so on. This change replaces sleeps with busy loops in cold boot and DDB cases. Notes: svn path=/head/; revision=354301
* [ig4] disable controller before initialization of clock countersVladimir Kondratyev2019-11-031-5/+7
| | | | | | | It is required by controller specifications. Notes: svn path=/head/; revision=354300
* [ig4] Stop I2C controller after checking that it's kind of functional.Vladimir Kondratyev2019-11-031-0/+5
| | | | | | | Obtained from: DragonfliBSD (0b3eedb) Notes: svn path=/head/; revision=354299
* [ig4] We actually need to set the Rx threshold register one smaller.Vladimir Kondratyev2019-11-031-1/+1
| | | | | | | | | | | Setting the IG4_REG_RX_TL register to 1 was actually generating an interrupt after 2 bytes were available in the Rx fifo. We need to set the register to 0 to get an interrupt for 1 byte already. Obtained from: DragonflyBSD (02f0bf2) Notes: svn path=/head/; revision=354298
* [ig4] Ignore stray interruptsVladimir Kondratyev2019-11-031-3/+6
| | | | Notes: svn path=/head/; revision=354297
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