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* Use uintmax_t (typedef'd to rman_res_t type) for rman ranges.Justin Hibbits2016-03-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544 Notes: svn path=/head/; revision=297000
* Let rman_init() initialize the default rman range.Justin Hibbits2016-03-031-2/+0
| | | | | | | | If rm_start and rm_end are both 0 on input to rman_init(), rman_init() pre-initializes them to the default range. No need to set it before. Notes: svn path=/head/; revision=296331
* Fix 2 bugs in the mpc85xx local bus controller driver.Justin Hibbits2016-03-021-2/+26
| | | | | | | | | | | | | 1) Include opt_platform.h to get QORIQ_DPAA. Otherwise the definition of OCP85XX_TGTIF_LBC is incorrect. 2) The child resources are already allocated, just activate them, instead of incorrectly remapping the memory regions (resource lists for lbc consist of the virtual address of the child's resources, not the physical address). Sponsored by: Alex Perez/Inertial Computing Notes: svn path=/head/; revision=296287
* Add another compatibility check for QorIQ GPIO driver.Justin Hibbits2016-03-011-1/+2
| | | | | | | | | | | Some MPC85xx GPIO controllers are compatible with QorIQ. It may make more sense in the future to rename this and mpc85xx_gpio.c, as mpc85xx_gpio.c appears to only be compatible with a few mpc85xx SoCs. All other MPC85xx SoCs use the same controller as QorIQ. Notes: svn path=/head/; revision=296251
* Move another range check to use RMAN_IS_DEFAULT_RANGE().Justin Hibbits2016-02-271-1/+1
| | | | Notes: svn path=/head/; revision=296141
* Allow the size argument for law_enable() to be non-power-of-2.Justin Hibbits2016-02-231-1/+2
| | | | | | | | Although the local access windows are powers of 2 in size, allow arguments that aren't power of 2, and round up. Notes: svn path=/head/; revision=295908
* Revert r295756:Zbigniew Bodek2016-02-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract common code from PowerPC's ofw_pci Import portions of the PowerPC OF PCI implementation into new file "ofw_pci.c", common for other platforms. The files ofw_pci.c and ofw_pci.h from sys/powerpc/ofw no longer exist. All required declarations are moved to sys/dev/ofw/ofw_pci.h. This creates a new ofw_pci_write_ivar() function and modifies ofw_pci_nranges(), ofw_pci_read_ivar(), ofw_pci_route_interrupt() methods. Most functions contain existing ppc implementations in the majority unchanged. Now there is no need to have multiple identical copies of methods for various architectures. Submitted by: Marcin Mazurek <mma@semihalf.com> Obtained from: Semihalf Sponsored by: Annapurna Labs Reviewed by: jhibbits, mmel Differential Revision: https://reviews.freebsd.org/D4879 This needs to return to the drawing board as it breaks both PowerPC and Sparc64 build. Pointed out by: jhibbits Notes: svn path=/head/; revision=295837
* Introduce a RMAN_IS_DEFAULT_RANGE() macro, and use it.Justin Hibbits2016-02-201-1/+1
| | | | | | | | | | | | | | This simplifies checking for default resource range for bus_alloc_resource(), and improves readability. This is part of, and related to, the migration of rman_res_t from u_long to uintmax_t. Discussed with: jhb Suggested by: marcel Notes: svn path=/head/; revision=295832
* Extract common code from PowerPC's ofw_pciZbigniew Bodek2016-02-181-3/+1
| | | | | | | | | | | | | | | | | | | | | | Import portions of the PowerPC OF PCI implementation into new file "ofw_pci.c", common for other platforms. The files ofw_pci.c and ofw_pci.h from sys/powerpc/ofw no longer exist. All required declarations are moved to sys/dev/ofw/ofw_pci.h. This creates a new ofw_pci_write_ivar() function and modifies ofw_pci_nranges(), ofw_pci_read_ivar(), ofw_pci_route_interrupt() methods. Most functions contain existing ppc implementations in the majority unchanged. Now there is no need to have multiple identical copies of methods for various architectures. Submitted by: Marcin Mazurek <mma@semihalf.com> Obtained from: Semihalf Sponsored by: Annapurna Labs Reviewed by: jhibbits, mmel Differential Revision: https://reviews.freebsd.org/D4879 Notes: svn path=/head/; revision=295756
* Make lbc(4) the same driver pass as simplebus.Justin Hibbits2016-02-031-1/+2
| | | | | | | | | | | Device trees mark lbc as compatible with simplebus. Since simplebus is passed first, it attaches first. When lbc's pass (default pass) comes, the bus is already attached to simplebus, so is skipped. Sponsored by: Alex Perez/Inertial Computing Notes: svn path=/head/; revision=295183
* Convert rman to use rman_res_t instead of u_longJustin Hibbits2016-01-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075 Notes: svn path=/head/; revision=294883
* Initialize the rid for input.Justin Hibbits2016-01-031-0/+1
| | | | | | | | Left uninitialized, random rid causes the IRQ setup to fail, and the PCI device to not be attached. Notes: svn path=/head/; revision=293107
* Add error interrupt handler for Freescale PCI errorsJustin Hibbits2016-01-031-1/+112
| | | | | | | | | This eliminates a 'interrupt storm' warning spam with the P5020. Obtained from: Semihalf Notes: svn path=/head/; revision=293106
* Use uint32_t for LBC block size.Justin Hibbits2016-01-011-3/+3
| | | | | | | | | LBC block size can only be up to 4GB. The existing code already clamps it, but mixes unsigned long and uint32_t. This works on 32-bit targets, but not 64-bit, so isn't completely correct. This fixes the type confusion. Notes: svn path=/head/; revision=293041
* Extend idle support for newer Book-E cores.Justin Hibbits2016-01-012-0/+43
| | | | | | | | | | | Newer Book-E cores (e500mc, e5500, e6500) do not support the WE bit in the MSR, and instead delegate CPU idling to the SoC. Perhaps in the future the QORIQ_DPAA option for the mpc85xx platform will become a subclass, which will eliminate most of the #ifdef's. Notes: svn path=/head/; revision=293030
* Add platform support for QorIQ SoCs.Justin Hibbits2015-12-303-12/+297
| | | | | | | | | | | | This includes the following changes: * SMP kickoff for QorIQ (tested on P5020) * Errata fixes for some silicon revisions * Enables L2 (and L3 if available) caches Obtained from: Semihalf Sponsored by: Alex Perez/Inertial Computing Notes: svn path=/head/; revision=292903
* Move the DRIVER_MODULE() statements that declare mmc(4) to be a child ofIan Lepore2015-12-141-0/+1
| | | | | | | | | the various bridge drivers out of dev/mmc.c and into the bridge drivers. Requested by: jhb (almost two years ago; better late than never) Notes: svn path=/head/; revision=292180
* Add Freescale QorIQ GPIO driver.Justin Hibbits2015-11-301-0/+309
| | | | | | | | | Still missing interrupt support, to come later. Sponsored by: Alex Perez/Inertial Computing Notes: svn path=/head/; revision=291462
* Remove a debug panic that crept into r291151Justin Hibbits2015-11-221-1/+0
| | | | Notes: svn path=/head/; revision=291152
* Modernize mpc85xx PCI hostbridge driver.Justin Hibbits2015-11-222-138/+8
| | | | | | | | | | | | | | | | Summary: * Take advantage of NEW_PCIB to remove a lot of setup code. * Fix some bugs related to multiple PCI bridges. There's still room for more cleanup, and still some bugs leftover, but this cleans up a lot. Test Plan: Tested on P5020 board with IDT PCIe switch. Differential Revision: https://reviews.freebsd.org/D4127 Notes: svn path=/head/; revision=291151
* Add support for new LAW registers in QorIQ SoCs.Justin Hibbits2015-11-182-35/+125
| | | | | | | | | | | | | | QorIQ SoCs (e5500 core, P5 family) have 2 BARs for local access windows, while MPC85XX, and P1/P2 families use only a single BAR register. This also adds the QORIQ_DPAA option, mutually exclusive to MPC85XX, to handle this difference. Obtained from: Semihalf Sponsored by: Alex Perez/Inertial Computing Notes: svn path=/head/; revision=291008
* Use 64-bit addresses for configuring inbound and outbound address windows.Justin Hibbits2015-11-031-8/+8
| | | | | | | This allows using the full host and PCI ranges in the controller configuration. Notes: svn path=/head/; revision=290319
* Use the correct space (PCI addresses) for the I/O and memory ranges.Justin Hibbits2015-11-031-6/+6
| | | | | | | PCIR_IOBASE/IOLIMIT/... all use PCI-space addresses, not host addresses. Notes: svn path=/head/; revision=290317
* Use IIC_EBUSBSY and IIC_BUSERR status values consistantly across all drivers.Ian Lepore2015-10-091-1/+1
| | | | | | | | | | | | | | | Make it clearer what each one means in the comments that define them. IIC_BUSBSY was used in many places to mean two different things, either "someone else has reserved the bus so you have to wait until they're done" or "the signal level on the bus was not in the state I expected before/after issuing some command". Now IIC_BUSERR is used consistantly to refer to protocol/signaling errors, and IIC_BUSBSY refers to ownership/reservation of the bus. Notes: svn path=/head/; revision=289093
* Fix freescale sdhc driver, and add it to the files list.Justin Hibbits2015-08-271-5/+3
| | | | | | | Also, add it to the mmc DRIVER_MODULE attachment list. Notes: svn path=/head/; revision=287189
* The Freescale qoriq PCIe controller is compatible with mpc85xx.Justin Hibbits2015-08-261-1/+4
| | | | | | | | | | Add the compatible checks. Obtained from: Semihalf (partial) Sponsored by: Alex Perez/Inertial Computing Notes: svn path=/head/; revision=287154
* Make the mpc85xx platform a kobj base class.Justin Hibbits2015-08-222-7/+7
| | | | | | | | | | | | | | | | | | Summary: Some systems are based around mpc85xx, but need special initialization. By making the mpc85xx platform a base class, these systems can be platform subclasses, and perform board-specific initialization in addition to the mpc85xx initialization. Test Plan: Tested on my RB800. A platform class was created, and will be committed separately. Reviewed By: nwhitehorn Differential Revision: https://reviews.freebsd.org/D3305 Notes: svn path=/head/; revision=287011
* Simplify the PCI bus scanning logic.Justin Hibbits2015-08-211-14/+3
| | | | | | | | | | | Rather than special casing on PCIC_BRIDGE || PCIC_PROCESSOR, allow all HDRTYPE_BRIDGE types. Obtained from: Semihalf Sponsored by: Alex Perez/Intertial Computing Notes: svn path=/head/; revision=286976
* Remove debug printf.Justin Hibbits2015-08-191-1/+0
| | | | Notes: svn path=/head/; revision=286923
* Add a PCI bridge for the Freescale PCIe Root ComplexJustin Hibbits2015-05-112-3/+115
| | | | | | | | | | | | | | | | | | | | | | | Summary: The Freescale PCIe Root Complex shows up as a Processor class device, PowerPC subclass, so the generic PCI code ignores it for a bridge. This adds support for it. As part of this, update the Freescale PCI hostbridge driver, to allow probing beyond the root complex, instead of only allowing "proper" PCI-PCI bridges. Reviewers: #powerpc, marcel, nwhitehorn Reviewed By: nwhitehorn Subscribers: imp Differential Revision: https://reviews.freebsd.org/D2442 Relnotes: yes Notes: svn path=/head/; revision=282783
* Add a GPIO driver for the mpc85xx.Justin Hibbits2015-04-041-0/+307
| | | | | | | | This has only been tested on the RB800, using the RB800's FDT, and pulls the GPOUT and GPIN registers from the FDT. Notes: svn path=/head/; revision=281057
* Move Open Firmware device root on PowerPC, ARM, and MIPS systems toNathan Whitehorn2014-02-052-2/+2
| | | | | | | | | | | a sub-node of nexus (ofwbus) rather than direct attach under nexus. This fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier. SPARC is unchanged. Reviewed by: imp, ian Notes: svn path=/head/; revision=261513
* Rearchitect platform memory map parsing to make it lessNathan Whitehorn2013-12-011-4/+4
| | | | | | | | | | | | | Open Firmware-centric: - Keep the static list of regions in platform.c instead of ofw_machdep.c - Move various merging and sorting operations to platform.c as well - Move apple_hacks code out of ofw_machdep.c and into platform_powermac.c, where it belongs - Move CHRP-specific dynamic-reconfiguration memory parsing into platform_chrp.c instead of pretending it is shared code Notes: svn path=/head/; revision=258807
* Move CCSR discovery into the platform module, while simultaneously makingNathan Whitehorn2013-11-172-2/+56
| | | | | | | | | | it more flexible about how the CCSR range is found. With this change, the stock MPC85XX will boot on a Routerboard 800. Hardware donated by: Benjamin Perrault Notes: svn path=/head/; revision=258244
* Rename the "bare" platform "mpc85xx", which is what it actually is, andNathan Whitehorn2013-11-111-0/+356
| | | | | | | | | | | | add actual platform probing based on PVR. Still needs a little more work: in particular, the CCRS setup should move here. Also turn "bare" into a truly bare platform that doesn't pretend to know how to do anything except get the memory map. This should also be enhanced to process the FDT reserved memory list, but that is for another day. Notes: svn path=/head/; revision=257995
* Be more flexible about which compatible strings to accept. This brings upNathan Whitehorn2013-11-111-0/+1
| | | | | | | the PCI Express bus on the RB800 using the firmware device tree. Notes: svn path=/head/; revision=257994
* Teach nexus(4) about Open Firmware (e.g. FDT) on ARM and MIPS, retiringNathan Whitehorn2013-11-052-2/+2
| | | | | | | | | | | | | | | | | | | | fdtbus in most cases. This brings ARM and MIPS more in line with existing Open Firmware platforms like sparc64 and powerpc, as well as preventing double-enumeration of the OF tree on embedded PowerPC (first through nexus, then through fdtbus). This change is also designed to simplify resource management on FDT platforms by letting there exist a platform-defined root bus resource_activate() call instead of replying on fdtbus to do the right thing through fdt_bs_tag. The OFW_BUS_MAP_INTR() and OFW_BUS_CONFIG_INTR() kobj methods are also available to implement for similar purposes. Discussed on: -arm, -mips Tested by: zbb, brooks, imp, and others MFC after: 6 weeks Notes: svn path=/head/; revision=257702
* Interrelated improvements to early boot mappings:Nathan Whitehorn2013-10-262-0/+3
| | | | | | | | | | | | | | | | | | | - Remove explicit requirement that the SOC registers be found except as an optimization (although the MPC85XX LAW drivers still require they be found externally, which should change). - Remove magic CCSRBAR_VA value. - Allow bus_machdep.c's early-boot code to handle non 1:1 mappings and systems not in real-mode or global 1:1 maps in early boot. - Allow pmap_mapdev() on Book-E to reissue previous addresses if the area is already mapped. Additionally have it check all mappings, not just the CCSR area. This allows the console on e500 systems to actually work on systems where the boot loader was not kind enough to set up a 1:1 mapping before starting the kernel. Notes: svn path=/head/; revision=257178
* Remove all the instances of '#undef DEBUG' from kernel.Luiz Otavio O Souza2013-10-251-2/+0
| | | | | | | | Suggested by: rpaulo Approved by: adrian (mentor) Notes: svn path=/head/; revision=257127
* Convert e500 PCI driver to use common PPC PCI bus glue. No functionalNathan Whitehorn2013-10-251-274/+75
| | | | | | | changes. Notes: svn path=/head/; revision=257117
* Allow PIC drivers to translate firmware sense codes for themselves. ThisNathan Whitehorn2013-10-241-0/+37
| | | | | | | | is designed to replace the tables in dev/fdt/fdt_ARCH.c, but will not happen quite yet. Notes: svn path=/head/; revision=257059
* Since the PS3 port was committed, the AIM nexus device works perfectly fineNathan Whitehorn2013-10-201-201/+0
| | | | | | | | on all PowerPC platforms, whether or not they have Open Firmware. Remove some more duplication and have there be only one nexus driver. Notes: svn path=/head/; revision=256799
* Align the PCI Express #defines with the style used for the PCI-XGavin Atkinson2012-09-181-6/+6
| | | | | | | | | | | | | | | | | | | | #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week Notes: svn path=/head/; revision=240680
* Support lbc interrupts:Marcel Moolenaar2012-07-032-34/+108
| | | | | | | | | | | | | | | | | | | | o Save and clear the LTESR register in the interrupt handler. o In lbc_read_reg(), return the saved LTESR register value if applicable (i.e. when the saved value is not invalid (read: ~0U)). o In lbc_write_reg(), clear the bits in the saved register when when it's written to and when the asved value is not invalid. o Also in lbc_write_reg(), the LTESR register is unlocked (in H/W) when bit 1 of LTEATR is cleared. We use this to invalidate our saved LTESR register value. Subsequent reads and write go to H/W directly. While here: o In lbc_read_reg() & lbc_write_reg(), add some belts and suspenders to catch when register offsets are out of range. o In lbc_attach(), initialize completely and don't leave something left for lbc_banks_enable(). Notes: svn path=/head/; revision=238045
* Properly implement the bus_config_intr, bus_setup_intr and bus_teardown_intrMarcel Moolenaar2012-07-021-2/+58
| | | | | | | | | methods so that MI drvers can depend on us doing the right thing instead of having to go around us and call MD code directly. See the FDT code for example (not for long though). Notes: svn path=/head/; revision=238042
* Import eSDHC driver for Freescale integrated controller.Rafal Jaworowski2012-05-262-0/+1603
| | | | | | | | Obtained from: Freescale, Semihalf Written by: Michal Dubiel Notes: svn path=/head/; revision=236121
* Move OpenPIC FDT bus glue to a shared location, so that other PowerPCRafal Jaworowski2012-05-261-93/+0
| | | | | | | | | platforms can use it, not only MPC85XX. This is just reorg, no functional changes. Notes: svn path=/head/; revision=236119
* A few improvements:Marcel Moolenaar2012-05-242-64/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | 1. Define all registers. These definitions are needed to support the FCM driver for direct-connect NAND. 2. Repurpose lbc_read_reg() and lbc_write_reg() for use by localbus attached device drivers. Use bus_space functions directly in the lbc driver itself. 3. Be smarter about programming LAWs and mapping memory. The ranges defined in the FDT are per bank (= chip select) and since we can have up to 8 banks, we could easily use more than 8 LAWs or TLB enrties when per-bank memory ranges need multiple LAWs or TLBs due to alignment or size constraints. We now combine all memory ranges into the fewest possible set of contiguous regions and program the hardware for that. Thus, a cleverly written FDT with 8 devices may still only need 1 LAW or 1 TLB entry. Note that the memory ranges can be assigned randomly to the banks. We sort as we build to handle that. 4. Support the FCM when programming the OR register. This is mostly for documention purposes as we do not have a way to define the mode for a bank. 5. Remove Semihalf-ism: do not define DEBUG (only to undefine it again). Notes: svn path=/head/; revision=235937
* Remove Semihakf-ism. DEBUG is a kernel configuration option. ItMarcel Moolenaar2012-05-241-3/+0
| | | | | | | should not be defined in source files. Notes: svn path=/head/; revision=235935
* Just return if the size of the window is 0. This can happen when theMarcel Moolenaar2012-05-241-1/+7
| | | | | | | | | | FDT does not define all ranges possible for a particular node (e.g. PCI). While here, only update the trgt_mem and trgt_io pointers if there's no error. This avoids that we knowingly write an invalid target (= -1). Notes: svn path=/head/; revision=235934
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