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* Add support for SPARC64 V (and where it already makes sense for otherMarius Strobl2010-05-021-1/+6
* - Assert that HEAPSZ is a multiple of PAGE_SIZE as at least the firmwareMarius Strobl2010-02-131-6/+14
* For cheetah-class CPUs ensure that the dt512_0 is set to hold 8k pagesMarius Strobl2008-09-081-0/+1
* cosmetic changes and style fixesMarius Strobl2008-08-131-1/+1
* unbreak sparc64 loader buildKip Macy2006-10-091-1/+1
* kernel clean up to make the sun4v kernel buildKip Macy2006-10-091-1/+1
* Add convenience macros for the bits in ASI_ESTATE_ERROR_EN_REG (usedMarius Strobl2006-03-291-0/+16
* Add ASI definitions of UltraSPARC-III (Cu) processors, and add someThomas Moestl2002-07-161-8/+102
* Add asis for the upa config reg, which contains the hardware cpu id, andJake Burkholder2002-01-081-0/+2
* Header file updates needed for the cache code: add/correct some ASIThomas Moestl2001-11-091-2/+15
* The definition for ASI_IMMU_TAG_TARGET_REG was wrong. Sort.Jake Burkholder2001-09-031-12/+13
* Add a definition for the load store unit control register.Jake Burkholder2001-08-201-0/+2
* Add asis for interrupt registers.Jake Burkholder2001-08-101-0/+14
* The author isn't a [UC] Regents. Correct the copyright language.David E. O'Brien2001-08-091-2/+2
* Add floating point context switching code for sparc64.Thomas Moestl2001-08-041-0/+11
* Flesh out the sparc64 port considerably. This contains:Jake Burkholder2001-07-311-0/+93