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* Add AT_HWCAP2 ELF auxiliary vector.Michal Meloun2017-10-211-2/+4
| | | | | | | | | | | | | - allocate value for new AT_HWCAP2 auxiliary vector on all platforms. - expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly same way as for AT_HWCAP. MFC after: 1 month Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D12699 Notes: svn path=/head/; revision=324814
* x86: Decode AMD "Extended Feature Extensions ID EBX" bitsConrad Meyer2017-09-203-0/+20
| | | | | | | | | | | In particular, this determines CPU support for the CLZERO instruction. (No, I am not making this name up.) Sponsored by: Dell EMC Isilon Notes: svn path=/head/; revision=323822
* MCA: Expand AMD Thresholding support to cover all banksConrad Meyer2017-09-172-55/+68
| | | | | | | | | | | | | | | | | | When it was added in r314636, AMD Thresholding was hardcoded to only bank 4 (Northbridge) for some reason. However, even on family 10h the MCAx_MISC register Valid/Present bits determine whether thresholding is supported on that bank. Expand thresholding support to monitor all monitorable banks. This simplifies some of the logic and makes it more consistent with our Intel CMCI support. Reviewed by: markj (earlier version) Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12321 Notes: svn path=/head/; revision=323690
* Add AT_EHDRFLAGS and AT_HWCAP on amd64.John Baldwin2017-09-141-1/+3
| | | | | | | | x86 has two separate (but identical) list of AT_* constants and the earlier commit to add AT_HWCAP only updated the i386 list. Notes: svn path=/head/; revision=323585
* Add AT_HWCAP and AT_EHDRFLAGS on all platforms.John Baldwin2017-09-141-1/+3
| | | | | | | | | | | | | | | | | | A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'. A process ABI can set this field to point to a value holding a mask of architecture-specific CPU feature flags. If an ABI does not wish to supply AT_HWCAP to processes the field can be left as NULL. The support code for AT_EHDRFLAGS was already present on all systems, just the #define was not present. This is a step towards unifying the AT_* constants across platforms. Reviewed by: kib MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D12290 Notes: svn path=/head/; revision=323579
* MCA: Rename AMD MISC bits/masksConrad Meyer2017-09-112-36/+36
| | | | | | | | | | | They apply to all AMD MCAi_MISC0 registers, not just MCA4 (NB). No functional change. Sponsored by: Dell EMC Isilon Notes: svn path=/head/; revision=323463
* x86 MCA: Extract CMCI support predicate into functionConrad Meyer2017-09-111-3/+15
| | | | | | | | | | | | On AMD, the MCG_CAP feature bit is reserved -- not explicitly zero. Do not use it to determine CMCI support. Reviewed by: avg, markj Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12320 Notes: svn path=/head/; revision=323462
* Fix ioapic acpi id matching on PCI attach and rid calculation.Konstantin Belousov2017-09-111-4/+4
| | | | | | | | Sponsored by: The FreeBSD Foundation MFC after: 11 days Notes: svn path=/head/; revision=323450
* Decode new AMD SVM feature bits on family 17hConrad Meyer2017-09-111-1/+19
| | | | | | | Sponsored by: Dell EMC Isilon Notes: svn path=/head/; revision=323449
* Enhance qpi.c to make it usable on all Core-microarchitecture Xeons.Konstantin Belousov2017-09-081-15/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Scan all buses for CSR bus, not stopping on the first failed match. Scan all slots for function 0 on the found bus, for instance on IvyBridge the slot 0 is not decoded at all. Since the scan is quite unsafe, and access to the buses is mostly useful for developers, enable the csr buses scan with the tunable. Current qpi.c makes too many assumptions about the uncore configuration buses location and about slots occupied. Also it restricts itself only to Nehalem CPUs. It is needed on all Core-based Xeons. On the 2600 v2 (IvyBridge) machine I have access to, the CSR buses have numbers 31 (BSP socket) and 63 (second socket), and there is no functions pci0.31.0.0 or pci0.63.0.0. According to the CPU datasheet, all devices on the uncore bus occupy slots >= 8. Practically, the attach to config buses is required for the intel-pcm pcm-memory.x tool to work, for instance. Reviewed by: jhb (previous version) Sponsored by: Mellanox Technologies MFC after: 1 week Differential revision: https://reviews.freebsd.org/D12268 Notes: svn path=/head/; revision=323327
* Use IOAPIC PCI rid as the interrupt TLP source id for DMAR interruptKonstantin Belousov2017-09-081-5/+21
| | | | | | | | | | | | | | | | | remapping. VT-d specification requires use of PCI rid as source id for IOAPICs enumerated by PCI bus. The values from the DMAR ACPI table should be only used when IOAPIC is not on PCI. Reviewed by: jhb Sponsored by: The FreeBSD Foundation Hardware provided by: Intel MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D12205 Notes: svn path=/head/; revision=323326
* Add an ioapic_get_rid() function to obtain PCIe TLP requester-id forKonstantin Belousov2017-09-082-1/+96
| | | | | | | | | | | | | | | | | | | | the interrupt messages from given IOAPIC, if the IOAPIC can be enumerated on PCI bus. If IOAPIC has PCI binding, match the PCI device against MADT enumerated IOAPIC. Match is done first by registers window physical address, then by IOAPIC ID as read from the APIC ID register. PCI bsf address of the matched PCI device is the rid. Reviewed by: jhb Sponsored by: The FreeBSD Foundation Hardware provided by: Intel MFC after: 2 weeks X-Differential revision: https://reviews.freebsd.org/D12205 Notes: svn path=/head/; revision=323325
* Add a constant specifying the min size of the IOAPIC registers window.Konstantin Belousov2017-09-081-0/+2
| | | | | | | | Sponsored by: The FreeBSD Foundation MFC after: 1 week Notes: svn path=/head/; revision=323324
* Consistently use tabs for indent.Konstantin Belousov2017-09-081-7/+7
| | | | | | | | Sponsored by: The FreeBSD Foundation MFC after: 1 week Notes: svn path=/head/; revision=323310
* mca: Fix printf types from r323289 on i386Conrad Meyer2017-09-081-3/+5
| | | | | | | | Reported by: Michael Butler <imb AT protected-networks.net> Sponsored by: Dell EMC Isilon Notes: svn path=/head/; revision=323295
* x86 MCA: Helpfully, print why ECC thresholding is not enabled on AMDConrad Meyer2017-09-071-4/+15
| | | | | | | Sponsored by: Dell EMC Isilon Notes: svn path=/head/; revision=323289
* x86 MCA: Enable AMD thresholding support on 17hConrad Meyer2017-09-072-2/+15
| | | | | | | | | | | | | | | 17h supports MCA thresholding in the same way as 16h and earlier. Supposedly a ScalableMca feature bit in CPUID 8000_0007:EBX must be set, but that was not true for earlier models, so be careful about relying on it. While here, document a missing bit in LS MCA MISC0. Reviewed by: truckman Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12237 Notes: svn path=/head/; revision=323288
* Store AMD RAS Capabilities cpuid value and name flagsConrad Meyer2017-09-073-0/+12
| | | | | | | | | Reviewed by: truckman Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12237 Notes: svn path=/head/; revision=323287
* cpufreq(4) hwpstate: Yield CPU awaiting frequency changeConrad Meyer2017-09-071-6/+8
| | | | | | | | | | | | | It doesn't seem necessary to busy the CPU while waiting to transition into a different p-state. PR: 221621 (related, but does not completely address) Reviewed by: truckman Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12260 Notes: svn path=/head/; revision=323286
* Fix typos. Stop claiming that two children are created.Konstantin Belousov2017-09-061-3/+3
| | | | | | | | Sponsored by: The FreeBSD Foundation MFC after: 1 week Notes: svn path=/head/; revision=323217
* acpi/srat: zero the SRAT cpu arrayRoger Pau Monné2017-09-041-0/+1
| | | | | | | | | | | | | Fix from fallout introduced in r322348 that moved the cpus array to a dynamic allocation without zeroing the area. Reported by: mjg MFC with: r322348 Reviewed by: mjg Differential revision: https://reviews.freebsd.org/D12220 Notes: svn path=/head/; revision=323154
* Stop masking FSGSBASE and SMEP features under monitors.Konstantin Belousov2017-08-241-7/+4
| | | | | | | | | | | | | | | | | | | | Not enabling FSGSBASE in %cr4 does not prevent reporting of the feature by the CPUID instruction (blame Int*l). As result, kernels which were run under monitors pretended that usermode cannot modify TLS base without the syscall, while libc noted right combination of capable CPU and the new kernel version, trying to use the WRFSBASE instruction. Really old hypervisors that cannot handle enablement of these features in %cr4 would require the manual configuration, by setting the loader tunable hw.cpu_stdext_disable=0x81 Reported by: lwhsu, mjoras Sponsored by: The FreeBSD Foundation MFC after: 18 days Notes: svn path=/head/; revision=322833
* Fix off-by-one error when parsing SRAT table.Alexander Motin2017-08-221-1/+1
| | | | | | | | Reviewed by: jhb MFC after: 1 week Notes: svn path=/head/; revision=322802
* subr_smp: Clean up topology analysis, add additional layersConrad Meyer2017-08-221-17/+30
| | | | | | | | | | | | | | | | | | | | Rather than repeatedly nesting loops, separate concerns with a single loop per call stack level. Use a table to drive the recursive routine. Handle missing topology layers more gracefully (infer a single unit). Analyze some additional optional layers which may be present on e.g. AMD Zen systems (groups, aka dies, per package; and cachegroups, aka CCXes, per group). Display that additional information in the boot-time topology information, when it is relevent (non-one). Reviewed by: markj@, mjoras@ (earlier version) Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12019 Notes: svn path=/head/; revision=322776
* hwpstate: Add support for family 17h pstate info from MSRsConrad Meyer2017-08-201-0/+13
| | | | | | | | | | | | | | | | | This information is normally available via acpi_perf, but in case it is not, add support for fetching the information via MSRs on AMD family 17h (Zen) processors. Zen uses a slightly different formula than previous generation AMD CPUs. This was inspired by, but does not fix, PR 221621. Reported by: Sean P. R. <seanpr AT swbell.net> Reviewed by: mjoras@ Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12082 Notes: svn path=/head/; revision=322710
* Discover CPU topology on multi-die AMD Zen systemsConrad Meyer2017-08-171-4/+29
| | | | | | | | | | | | | | | | | The Nodes per Processor topology information determines how many bits of the APIC ID represent the Node (Zeppelin die, on Zen systems) ID. Documented in Ryzen and Epyc Processor Programming Reference (PPR). Correct topology information enables the scheduler to make better decisions on this hardware. Reviewed by: kib@ Tested by: jeff@ (earlier version) Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D11801 Notes: svn path=/head/; revision=322621
* Fix unused varable warning in !SMP caseConrad Meyer2017-08-171-0/+2
| | | | | | | | | | | Fallout from r322588. I'm not sure why !SMP is a knob we have, but, we have it. Reported by: Michael Butler <imb AT protected-networks.net> Sponsored by: Dell EMC Isilon Notes: svn path=/head/; revision=322611
* x86: Add dynamic interrupt rebalancingConrad Meyer2017-08-161-7/+139
| | | | | | | | | | | | | | | | | | | Add an option to dynamically rebalance interrupts across cores (hw.intrbalance); off by default. The goal is to minimize preemption. By placing interrupt sources on distinct CPUs, ithreads get preferentially scheduled on distinct CPUs. Overall preemption is reduced and latency is reduced. In our workflow it reduced "fighting" between two high-frequency interrupt sources. Reduced latency was proven by, e.g., SPEC2008. Submitted by: jeff@ (earlier version) Reviewed by: kib@ Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D10435 Notes: svn path=/head/; revision=322588
* srat: use pmap_unmapbiosRoger Pau Monné2017-08-131-1/+1
| | | | | | | | | | To match the pmap_mapbios. Reported by: jhb MFC with: r322403 Notes: svn path=/head/; revision=322457
* Stop calling atrtc_set() from the xen timer clock_settime() method. ThatIan Lepore2017-08-111-1/+1
| | | | | | | | | | | | | | | | | removes the only reference to atrtc_set() from outside of atrtc.c, so make it static. The xen timer driver registers as a realtime clock with 1us resolution. In the past that resulted in only the xen timer's clock_settime() getting called, so it would call atrtc_set() to set the hardware clock as well. As of r32090, the clock_settime() method of all registered realtime clocks gets called, so the xen driver no longer needs to chain-call the lower-resolution driver. Thanks to royger@ for talking me through the xen stuff, and for testing. Notes: svn path=/head/; revision=322411
* acpi/srat: fix build without DMAPRoger Pau Monné2017-08-111-1/+10
| | | | | | | | | | Use pmap_mapbios to map memory used to store the cpus array. Reported by: lwhsu X-MFC-with: r322348 Notes: svn path=/head/; revision=322403
* mptable: fix i386 build failureRoger Pau Monné2017-08-102-1/+12
| | | | | | | | Reported by: emaste X-MFC-with: r322347 Notes: svn path=/head/; revision=322372
* x86: bump MAX_APIC_ID to 512Roger Pau Monné2017-08-104-13/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new define to take int account the xAPIC ID limit, for systems where x2APIC is not available/reliable. Also change some of the usages of the APIC ID to use an unsigned int (which is the correct storage type to deal with x2APIC IDs as found in x2APIC MADT entries). This allows booting FreeBSD on a box with 256 CPUs and APIC IDs up to 295: FreeBSD/SMP: Multiprocessor System Detected: 256 CPUs FreeBSD/SMP: 1 package(s) x 64 core(s) x 4 hardware threads Package HW ID = 0 Core HW ID = 0 CPU0 (BSP): APIC ID: 0 CPU1 (AP/HT): APIC ID: 1 CPU2 (AP/HT): APIC ID: 2 CPU3 (AP/HT): APIC ID: 3 [...] Core HW ID = 73 CPU252 (AP): APIC ID: 292 CPU253 (AP/HT): APIC ID: 293 CPU254 (AP/HT): APIC ID: 294 CPU255 (AP/HT): APIC ID: 295 Submitted by: kib (previous version) Relnotes: yes MFC after: 1 month Reviewed by: kib Differential revision: https://reviews.freebsd.org/D11913 Notes: svn path=/head/; revision=322349
* x86: make the arrays that depend on MAX_APIC_ID dynamicRoger Pau Monné2017-08-106-21/+75
| | | | | | | | | | | | | | | | | | | So that MAX_APIC_ID can be bumped without wasting memory. Note that the usage of MAX_APIC_ID in the SRAT parsing forces the parser to allocate memory directly from the phys_avail physical memory array, which is not the best approach probably, but I haven't found any other way to allocate memory so early in boot. This memory is not returned to the system afterwards, but at least it's sized according to the maximum APIC ID found in the MADT table. Sponsored by: Citrix Systems R&D MFC after: 1 month Reviewed by: kib Differential revision: https://reviews.freebsd.org/D11912 Notes: svn path=/head/; revision=322348
* apic_enumerator: only set mp_ncpus and mp_maxid at probe cpus phaseRoger Pau Monné2017-08-107-13/+83
| | | | | | | | | | | | | | | | | Populate the lapics arrays and call cpu_add/lapic_create in the setup phase instead. Also store the max APIC ID found in the newly introduced max_apic_id global variable. This is a requirement in order to make the static arrays currently using MAX_LAPIC_ID dynamic. Sponsored by: Citrix Systems R&D MFC after: 1 month Reviewed by: kib Differential revision: https://reviews.freebsd.org/D11911 Notes: svn path=/head/; revision=322347
* Split identify_cpu() into two functions for amd64 as we do for i386. ThisJung-uk Kim2017-08-092-13/+15
| | | | | | | | | | | | reduces diff between amd64 and i386. Also, it fixes a regression introduced in r322076, i.e., identify_hypervisor() failed to identify some hypervisors. This function assumes cpu_feature2 is already initialized. Reported by: dexuan Tested by: dexuan Notes: svn path=/head/; revision=322323
* Detect hypervisors early. We used to set lower hz on hypervisors by defaultJung-uk Kim2017-08-052-2/+2
| | | | | | | | | | but it was broken since r273800 (and r278522, its MFC to stable/10) because identify_cpu() is called too late, i.e., after init_param1(). MFC after: 3 days Notes: svn path=/head/; revision=322076
* Don't trace running threads that have interrupts disabled.Mark Johnston2017-07-311-3/+4
| | | | | | | | | | | In this case we shouldn't assume that the thread has a valid frame pointer. Reviewed by: kib MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D11787 Notes: svn path=/head/; revision=321803
* __pcpu: gcc -Wredundant-declsRyan Libby2017-07-211-2/+0
| | | | | | | | | | | | | | | Pollution from counter.h made __pcpu visible in amd64/pmap.c. Delete the existing extern decl of __pcpu in amd64/pmap.c and avoid referring to that symbol, instead accessing the pcpu region via PCPU_SET macros. Also delete an unused extern decl of __pcpu from mp_x86.c. Reviewed by: kib Approved by: markj (mentor) Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D11666 Notes: svn path=/head/; revision=321335
* Protect access to the AT realtime clock with its own mutex.Ian Lepore2017-07-121-0/+14
| | | | | | | | | | | | | | | | | | The mutex protecting access to the registered realtime clock should not be overloaded to protect access to the atrtc hardware, which might not even be the registered rtc. More importantly, the resettodr mutex needs to be eliminated to remove locking/sleeping restrictions on clock drivers, and that can't happen if MD code for amd64 depends on it. This change moves the protection into what's really being protected: access to the atrtc date and time registers. This change also adds protection when the clock is accessed from xentimer_settime(), which bypasses the resettodr locking. Differential Revision: https://reviews.freebsd.org/D11483 Notes: svn path=/head/; revision=320901
* Clean up MD pollution of bus_dma.h:Jason A. Harmening2017-07-015-143/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | --Remove special-case handling of sparc64 bus_dmamap* functions. Replace with a more generic mechanism that allows MD busdma implementations to generate inline mapping functions by defining WANT_INLINE_DMAMAP in <machine/bus_dma.h>. This is currently useful for sparc64, x86, and arm64, which all implement non-load dmamap operations as simple wrappers around map objects which may be bus- or device-specific. --Remove NULL-checked bus_dmamap macros. Implement the equivalent NULL checks in the inlined x86 implementation. For non-x86 platforms, these checks are a minor pessimization as those platforms do not currently allow NULL maps. NULL maps were originally allowed on arm64, which appears to have been the motivation behind adding arm[64]-specific barriers to bus_dma.h, but that support was removed in r299463. --Simplify the internal interface used by the bus_dmamap_load* variants and move it to bus_dma_internal.h --Fix some drivers that directly include sys/bus_dma.h despite the recommendations of bus_dma(9) Reviewed by: kib (previous revision), marius Differential Revision: https://reviews.freebsd.org/D10729 Notes: svn path=/head/; revision=320528
* Fix batched unload for DMAR busdma in qi mode.Konstantin Belousov2017-06-193-34/+25
| | | | | | | | | | | | | | | | | | | | | | | | | Do not queue dmar_map_entries with zeroed gseq to dmar_qi_invalidate_locked(). Zero gseq stops the processing in the qi task. Do not assign possibly uninitialized on-stack gseq to map entries when requeuing them on unit tlb_flush queue. Random garbage in gsec is interpreted as too high invalidation sequence number and again stop the processing in the task. Make the sequence numbers generation completely contained in dmar_qi_invalidate_locked() and dmar_qi_emit_wait_seq(). Upper code directly passes boolean requesting emiting wait command instead of trying to provide hint to avoid it by passing NULL gseq pointer. Microoptimize the requeueing to tlb_flush queue by doing it for the whole queue. Diagnosed and tested by: Brett Gutstein <bgutstein@rice.edu> Discussed with: alc Sponsored by: The FreeBSD Foundation MFC after: 1 week Notes: svn path=/head/; revision=320125
* Don't try to assign interrupts to a CPU on single-CPU systems.John Baldwin2017-06-141-1/+5
| | | | | | | | | | | | | | | All interrupts are routed to the sole CPU in that case implicitly. This is a regression in EARLY_AP_STARTUP. Previously the 'assign_cpu' variable was only set when a multi-CPU system finished booting, so it's value both meant that interrupts could be assigned and that there was more than one CPU. PR: 219882 Reported by: ota@j.email.ne.jp MFC after: 3 days Notes: svn path=/head/; revision=319942
* More accurately handle early EFER restoration on resume.Konstantin Belousov2017-06-111-1/+2
| | | | | | | | | | | | | Do not try to set LMA bit while CPU is still in legacy mode. Apparently Intel CPUs ignore non-id writes to LMA, while AMD's (over-)react with #GP. Reported and tested by: danfe Sponsored by: The FreeBSD Foundation MFC after: 3 days Notes: svn path=/head/; revision=319825
* Allow sysctl kern.vm_guest to return bhyve when running under bhyve.Marcelo Araujo2017-06-081-0/+2
| | | | | | | | | | | Submitted by: Sean Fagan <sef@ixsystems.com> Reviewed by: grehan MFH: 4 weeks. Sponsored by: iXsystems, Inc. Differential Revision: https://reviews.freebsd.org/D11090 Notes: svn path=/head/; revision=319678
* fix indentationAndriy Gapon2017-05-301-1/+1
| | | | | | | MFC after: 4 days Notes: svn path=/head/; revision=319212
* Remove constants and comments for unimplemented entries in the default LDT.John Baldwin2017-05-241-3/+0
| | | | | | | These entries will never be added to the default LDT in the future. Notes: svn path=/head/; revision=318800
* Remove the BSD/OS 2.1 system call gate LDT entry.John Baldwin2017-05-231-2/+1
| | | | | | | | | | | | An extra copy of the system call gate was added to the default LDT back in 1996 (r18513 / r18514). However, the ability to run BSD/OS 2.1 i386 binaries under FreeBSD's native ABI is most likely no longer needed. Discussed with: kib Notes: svn path=/head/; revision=318761
* Avoid use of contiguous memory allocations in busdma when possible.Hans Petter Selasky2017-05-161-9/+22
| | | | | | | | | | | | | | | | | | | | | | | This patch improves the boundary checks in busdma to allow more cases using the regular page based kernel memory allocator. Especially in the case of having a non-zero boundary in the parent DMA tag. For example AMD64 based platforms set the PCI DMA tag boundary to PCI_DMA_BOUNDARY, 4GB, which before this patch caused contiguous memory allocations to be preferred when allocating more than PAGE_SIZE bytes. Even if the required alignment was less than PAGE_SIZE bytes. This patch also fixes the nsegments check for using kmem_alloc_attr() when the maximum segment size is less than PAGE_SIZE bytes. Updated some comments describing the code in question. Differential Revision: https://reviews.freebsd.org/D10645 Reviewed by: kib, jhb, gallatin, scottl MFC after: 1 week Sponsored by: Mellanox Technologies Notes: svn path=/head/; revision=318353
* Ensure that resume path on amd64 only accesses page tables for normalKonstantin Belousov2017-05-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | operation after processor is configured to allow all required features. In particular, NX must be enabled in EFER, otherwise load of page table element with nx bit set causes reserved bit page fault. Since malloc uses direct mapping for small allocations, in particular for the suspension pcbs, and DMAP is nx after r316767, this commit tripped fault on resume path. Restore complete state of EFER while wakeup code is still executing with custom page table, before calling resumectx, instead of trying to guess which features might be needed before resumectx restored EFER on its own. Bisected and tested by: trasz Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Notes: svn path=/head/; revision=318318
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