From 21fc6a2a10cf6fbd294decbb0001473693ec1618 Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Fri, 16 Apr 2021 21:28:08 +0300 Subject: amd64: invalidate TLB between page table update and access When setting up trampoline mapping for LA57 switcher, it is possible that TLB still has some random mapping at that address. Sponsored by: The FreeBSD Foundation MFC after: 1 week --- sys/amd64/amd64/pmap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c index 66617bffa8df..5a6a1cee8b8c 100644 --- a/sys/amd64/amd64/pmap.c +++ b/sys/amd64/amd64/pmap.c @@ -2168,6 +2168,7 @@ pmap_bootstrap_la57(void *arg __unused) *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) = la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code); la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code); + invlpg((vm_offset_t)la57_tramp); la57_tramp(KPML5phys); /* -- cgit v1.2.3