From efa9b503c69a3437270fe1f1b77c21c2d358a678 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Thu, 20 Dec 2018 01:05:09 +0000 Subject: Fix obtaining RSP address in TPM CRB for non-amd64 platforms On amd64 the RSP address can be read in single 8-byte transaction, which is obviously not possible on 32-bit platforms. Fix that by performing 2 4-byte read on them. Obtained from: Semihalf Sponsored by: Stormshield --- sys/dev/tpm/tpm20.h | 2 ++ sys/dev/tpm/tpm_crb.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/sys/dev/tpm/tpm20.h b/sys/dev/tpm/tpm20.h index 38340c33f76a..fcede6f1b605 100644 --- a/sys/dev/tpm/tpm20.h +++ b/sys/dev/tpm/tpm20.h @@ -153,12 +153,14 @@ RD4(struct tpm_sc *sc, bus_size_t off) return (bus_read_4(sc->mem_res, off)); } +#ifdef __amd64__ static inline uint64_t RD8(struct tpm_sc *sc, bus_size_t off) { return (bus_read_8(sc->mem_res, off)); } +#endif static inline void WR1(struct tpm_sc *sc, bus_size_t off, uint8_t val) { diff --git a/sys/dev/tpm/tpm_crb.c b/sys/dev/tpm/tpm_crb.c index c48109a02389..778b208b83eb 100644 --- a/sys/dev/tpm/tpm_crb.c +++ b/sys/dev/tpm/tpm_crb.c @@ -50,6 +50,7 @@ __FBSDID("$FreeBSD$"); #define TPM_CRB_CTRL_CMD_HADDR 0x60 #define TPM_CRB_CTRL_RSP_SIZE 0x64 #define TPM_CRB_CTRL_RSP_ADDR 0x68 +#define TPM_CRB_CTRL_RSP_HADDR 0x6c #define TPM_CRB_DATA_BUFFER 0x80 #define TPM_LOC_STATE_ESTB BIT(0) @@ -188,7 +189,12 @@ tpmcrb_attach(device_t dev) * addr is stored in two 4 byte neighboring registers, whereas RSP is * stored in a single 8 byte one. */ +#ifdef __amd64__ crb_sc->rsp_off = RD8(sc, TPM_CRB_CTRL_RSP_ADDR); +#else + crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR); + crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32); +#endif crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR); crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32); crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE); -- cgit v1.2.3