From da75c2cc5808a45edc76752ba495dcc5dcd4346c Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Fri, 27 Feb 2015 22:16:54 +0000 Subject: Import from device-tree git://xenbits.xen.org/people/ianc/device-tree-rebasing.git @c8c1b3a77934768c7f7a4a9c10140c8bec529059 --- Bindings/rtc/atmel,at91sam9-rtc.txt | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Bindings/rtc/atmel,at91sam9-rtc.txt (limited to 'Bindings/rtc/atmel,at91sam9-rtc.txt') diff --git a/Bindings/rtc/atmel,at91sam9-rtc.txt b/Bindings/rtc/atmel,at91sam9-rtc.txt new file mode 100644 index 000000000000..6ae79d1843f3 --- /dev/null +++ b/Bindings/rtc/atmel,at91sam9-rtc.txt @@ -0,0 +1,23 @@ +Atmel AT91SAM9260 Real Time Timer + +Required properties: +- compatible: should be: "atmel,at91sam9260-rtt" +- reg: should encode the memory region of the RTT controller +- interrupts: rtt alarm/event interrupt +- clocks: should contain the 32 KHz slow clk that will drive the RTT block. +- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store + the time base when the RTT is used as an RTC. + The first cell should point to the GPBR node and the second one + encode the offset within the GPBR block (or in other words, the + GPBR register used to store the time base). + + +Example: + +rtt@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 4 7>; + clocks = <&clk32k>; + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; -- cgit v1.2.3