From 5d9861c835f76e36b6ac87b7cce92bd674a264c2 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Thu, 21 Nov 2019 20:36:46 +0000 Subject: Merge commit a751f557d from llvm git (by Simon Atanasyan): [mips] Set macros for Octeon+ CPU This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 --- contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'contrib') diff --git a/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp b/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp index a08c2318aec1..b9ab80df6194 100644 --- a/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp @@ -62,7 +62,7 @@ void MipsTargetInfo::fillValidCPUList( unsigned MipsTargetInfo::getISARev() const { return llvm::StringSwitch(getCPU()) .Cases("mips32", "mips64", 1) - .Cases("mips32r2", "mips64r2", "octeon", 2) + .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2) .Cases("mips32r3", "mips64r3", 3) .Cases("mips32r5", "mips64r5", 5) .Cases("mips32r6", "mips64r6", 6) @@ -188,7 +188,10 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); - Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); + if (CPU == "octeon+") + Builder.defineMacro("_MIPS_ARCH_OCTEONP"); + else + Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); if (StringRef(CPU).startswith("octeon")) Builder.defineMacro("__OCTEON__"); -- cgit v1.2.3