From 4f1cbb2fdce0b0f2552635358dab38bb1978a9ad Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Wed, 4 Mar 2015 03:51:54 +0000 Subject: Add DDR flush registers for QCA955x. --- sys/mips/atheros/qca955xreg.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'sys/mips/atheros') diff --git a/sys/mips/atheros/qca955xreg.h b/sys/mips/atheros/qca955xreg.h index 905b296d2c29..555070d69217 100644 --- a/sys/mips/atheros/qca955xreg.h +++ b/sys/mips/atheros/qca955xreg.h @@ -198,4 +198,11 @@ #define QCA955X_PLL_VAL_100 0x00000101 #define QCA955X_PLL_VAL_10 0x00001616 +/* DDR block */ +#define QCA955X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c) +#define QCA955X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0) +#define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) +#define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) +#define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) + #endif /* __QCA955XREG_H__ */ -- cgit v1.2.3