blob: 4c72fa2359750464acbabf6e1bf0c6d07dc34a90 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
|
//===-- SIPostRABundler.cpp -----------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file
/// This pass creates bundles of memory instructions to protect adjacent loads
/// and stores from beeing rescheduled apart from each other post-RA.
///
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPUSubtarget.h"
#include "SIDefines.h"
#include "SIInstrInfo.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/InitializePasses.h"
using namespace llvm;
#define DEBUG_TYPE "si-post-ra-bundler"
namespace {
class SIPostRABundler : public MachineFunctionPass {
public:
static char ID;
public:
SIPostRABundler() : MachineFunctionPass(ID) {
initializeSIPostRABundlerPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
return "SI post-RA bundler";
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
const SIRegisterInfo *TRI;
SmallSet<Register, 16> Defs;
bool isDependentLoad(const MachineInstr &MI) const;
};
} // End anonymous namespace.
INITIALIZE_PASS(SIPostRABundler, DEBUG_TYPE, "SI post-RA bundler", false, false)
char SIPostRABundler::ID = 0;
char &llvm::SIPostRABundlerID = SIPostRABundler::ID;
FunctionPass *llvm::createSIPostRABundlerPass() {
return new SIPostRABundler();
}
bool SIPostRABundler::isDependentLoad(const MachineInstr &MI) const {
if (!MI.mayLoad())
return false;
for (const MachineOperand &Op : MI.explicit_operands()) {
if (!Op.isReg())
continue;
Register Reg = Op.getReg();
for (Register Def : Defs)
if (TRI->regsOverlap(Reg, Def))
return true;
}
return false;
}
bool SIPostRABundler::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
bool Changed = false;
const uint64_t MemFlags = SIInstrFlags::MTBUF | SIInstrFlags::MUBUF |
SIInstrFlags::SMRD | SIInstrFlags::DS |
SIInstrFlags::FLAT | SIInstrFlags::MIMG;
for (MachineBasicBlock &MBB : MF) {
MachineBasicBlock::instr_iterator Next;
MachineBasicBlock::instr_iterator B = MBB.instr_begin();
MachineBasicBlock::instr_iterator E = MBB.instr_end();
for (auto I = B; I != E; I = Next) {
Next = std::next(I);
const uint64_t IMemFlags = I->getDesc().TSFlags & MemFlags;
if (IMemFlags == 0 || I->isBundled() || !I->mayLoadOrStore() ||
B->mayLoad() != I->mayLoad() || B->mayStore() != I->mayStore() ||
((B->getDesc().TSFlags & MemFlags) != IMemFlags) ||
isDependentLoad(*I)) {
if (B != I) {
if (std::next(B) != I) {
finalizeBundle(MBB, B, I);
Changed = true;
}
Next = I;
}
B = Next;
Defs.clear();
continue;
}
if (I->getNumExplicitDefs() == 0)
continue;
Defs.insert(I->defs().begin()->getReg());
}
if (B != E && std::next(B) != E) {
finalizeBundle(MBB, B, E);
Changed = true;
}
Defs.clear();
}
return Changed;
}
|
