1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
|
//===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// The Hexagon processor has no instructions that load or store predicate
// registers directly. So, when these registers must be spilled a general
// purpose register must be found and the value copied to/from it from/to
// the predicate register. This code currently does not use the register
// scavenger mechanism available in the allocator. There are two registers
// reserved to allow spilling/restoring predicate registers. One is used to
// hold the predicate value. The other is used when stack frame offsets are
// too large.
//
//===----------------------------------------------------------------------===//
#include "Hexagon.h"
#include "HexagonMachineFunctionInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LatencyPriorityQueue.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
namespace llvm {
FunctionPass *createHexagonExpandPredSpillCode();
void initializeHexagonExpandPredSpillCodePass(PassRegistry&);
}
namespace {
class HexagonExpandPredSpillCode : public MachineFunctionPass {
public:
static char ID;
HexagonExpandPredSpillCode() : MachineFunctionPass(ID) {
PassRegistry &Registry = *PassRegistry::getPassRegistry();
initializeHexagonExpandPredSpillCodePass(Registry);
}
const char *getPassName() const override {
return "Hexagon Expand Predicate Spill Code";
}
bool runOnMachineFunction(MachineFunction &Fn) override;
};
char HexagonExpandPredSpillCode::ID = 0;
bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
const HexagonSubtarget &QST = Fn.getSubtarget<HexagonSubtarget>();
const HexagonInstrInfo *TII = QST.getInstrInfo();
// Loop over all of the basic blocks.
for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
MBBb != MBBe; ++MBBb) {
MachineBasicBlock* MBB = MBBb;
// Traverse the basic block.
for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
++MII) {
MachineInstr *MI = MII;
int Opc = MI->getOpcode();
if (Opc == Hexagon::S2_storerb_pci_pseudo ||
Opc == Hexagon::S2_storerh_pci_pseudo ||
Opc == Hexagon::S2_storeri_pci_pseudo ||
Opc == Hexagon::S2_storerd_pci_pseudo ||
Opc == Hexagon::S2_storerf_pci_pseudo) {
unsigned Opcode;
if (Opc == Hexagon::S2_storerd_pci_pseudo)
Opcode = Hexagon::S2_storerd_pci;
else if (Opc == Hexagon::S2_storeri_pci_pseudo)
Opcode = Hexagon::S2_storeri_pci;
else if (Opc == Hexagon::S2_storerh_pci_pseudo)
Opcode = Hexagon::S2_storerh_pci;
else if (Opc == Hexagon::S2_storerf_pci_pseudo)
Opcode = Hexagon::S2_storerf_pci;
else if (Opc == Hexagon::S2_storerb_pci_pseudo)
Opcode = Hexagon::S2_storerb_pci;
else
llvm_unreachable("wrong Opc");
MachineOperand &Op0 = MI->getOperand(0);
MachineOperand &Op1 = MI->getOperand(1);
MachineOperand &Op2 = MI->getOperand(2);
MachineOperand &Op3 = MI->getOperand(3); // Modifier value.
MachineOperand &Op4 = MI->getOperand(4);
// Emit a "C6 = Rn, C6 is the control register for M0".
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
Hexagon::C6)->addOperand(Op3);
// Replace the pseude circ_ldd by the real circ_ldd.
MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Opcode));
NewMI->addOperand(Op0);
NewMI->addOperand(Op1);
NewMI->addOperand(Op4);
NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
false, /*isDef*/
false, /*isImpl*/
true /*isKill*/));
NewMI->addOperand(Op2);
MII = MBB->erase(MI);
--MII;
} else if (Opc == Hexagon::L2_loadrd_pci_pseudo ||
Opc == Hexagon::L2_loadri_pci_pseudo ||
Opc == Hexagon::L2_loadrh_pci_pseudo ||
Opc == Hexagon::L2_loadruh_pci_pseudo||
Opc == Hexagon::L2_loadrb_pci_pseudo ||
Opc == Hexagon::L2_loadrub_pci_pseudo) {
unsigned Opcode;
if (Opc == Hexagon::L2_loadrd_pci_pseudo)
Opcode = Hexagon::L2_loadrd_pci;
else if (Opc == Hexagon::L2_loadri_pci_pseudo)
Opcode = Hexagon::L2_loadri_pci;
else if (Opc == Hexagon::L2_loadrh_pci_pseudo)
Opcode = Hexagon::L2_loadrh_pci;
else if (Opc == Hexagon::L2_loadruh_pci_pseudo)
Opcode = Hexagon::L2_loadruh_pci;
else if (Opc == Hexagon::L2_loadrb_pci_pseudo)
Opcode = Hexagon::L2_loadrb_pci;
else if (Opc == Hexagon::L2_loadrub_pci_pseudo)
Opcode = Hexagon::L2_loadrub_pci;
else
llvm_unreachable("wrong Opc");
MachineOperand &Op0 = MI->getOperand(0);
MachineOperand &Op1 = MI->getOperand(1);
MachineOperand &Op2 = MI->getOperand(2);
MachineOperand &Op4 = MI->getOperand(4); // Modifier value.
MachineOperand &Op5 = MI->getOperand(5);
// Emit a "C6 = Rn, C6 is the control register for M0".
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
Hexagon::C6)->addOperand(Op4);
// Replace the pseude circ_ldd by the real circ_ldd.
MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Opcode));
NewMI->addOperand(Op1);
NewMI->addOperand(Op0);
NewMI->addOperand(Op2);
NewMI->addOperand(Op5);
NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
false, /*isDef*/
false, /*isImpl*/
true /*isKill*/));
MII = MBB->erase(MI);
--MII;
} else if (Opc == Hexagon::L2_loadrd_pbr_pseudo ||
Opc == Hexagon::L2_loadri_pbr_pseudo ||
Opc == Hexagon::L2_loadrh_pbr_pseudo ||
Opc == Hexagon::L2_loadruh_pbr_pseudo||
Opc == Hexagon::L2_loadrb_pbr_pseudo ||
Opc == Hexagon::L2_loadrub_pbr_pseudo) {
unsigned Opcode;
if (Opc == Hexagon::L2_loadrd_pbr_pseudo)
Opcode = Hexagon::L2_loadrd_pbr;
else if (Opc == Hexagon::L2_loadri_pbr_pseudo)
Opcode = Hexagon::L2_loadri_pbr;
else if (Opc == Hexagon::L2_loadrh_pbr_pseudo)
Opcode = Hexagon::L2_loadrh_pbr;
else if (Opc == Hexagon::L2_loadruh_pbr_pseudo)
Opcode = Hexagon::L2_loadruh_pbr;
else if (Opc == Hexagon::L2_loadrb_pbr_pseudo)
Opcode = Hexagon::L2_loadrb_pbr;
else if (Opc == Hexagon::L2_loadrub_pbr_pseudo)
Opcode = Hexagon::L2_loadrub_pbr;
else
llvm_unreachable("wrong Opc");
MachineOperand &Op0 = MI->getOperand(0);
MachineOperand &Op1 = MI->getOperand(1);
MachineOperand &Op2 = MI->getOperand(2);
MachineOperand &Op4 = MI->getOperand(4); // Modifier value.
// Emit a "C6 = Rn, C6 is the control register for M0".
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
Hexagon::C6)->addOperand(Op4);
// Replace the pseudo brev_ldd by the real brev_ldd.
MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Opcode));
NewMI->addOperand(Op1);
NewMI->addOperand(Op0);
NewMI->addOperand(Op2);
NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
false, /*isDef*/
false, /*isImpl*/
true /*isKill*/));
MII = MBB->erase(MI);
--MII;
} else if (Opc == Hexagon::S2_storerd_pbr_pseudo ||
Opc == Hexagon::S2_storeri_pbr_pseudo ||
Opc == Hexagon::S2_storerh_pbr_pseudo ||
Opc == Hexagon::S2_storerb_pbr_pseudo ||
Opc == Hexagon::S2_storerf_pbr_pseudo) {
unsigned Opcode;
if (Opc == Hexagon::S2_storerd_pbr_pseudo)
Opcode = Hexagon::S2_storerd_pbr;
else if (Opc == Hexagon::S2_storeri_pbr_pseudo)
Opcode = Hexagon::S2_storeri_pbr;
else if (Opc == Hexagon::S2_storerh_pbr_pseudo)
Opcode = Hexagon::S2_storerh_pbr;
else if (Opc == Hexagon::S2_storerf_pbr_pseudo)
Opcode = Hexagon::S2_storerf_pbr;
else if (Opc == Hexagon::S2_storerb_pbr_pseudo)
Opcode = Hexagon::S2_storerb_pbr;
else
llvm_unreachable("wrong Opc");
MachineOperand &Op0 = MI->getOperand(0);
MachineOperand &Op1 = MI->getOperand(1);
MachineOperand &Op2 = MI->getOperand(2);
MachineOperand &Op3 = MI->getOperand(3); // Modifier value.
// Emit a "C6 = Rn, C6 is the control register for M0".
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
Hexagon::C6)->addOperand(Op3);
// Replace the pseudo brev_ldd by the real brev_ldd.
MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Opcode));
NewMI->addOperand(Op0);
NewMI->addOperand(Op1);
NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
false, /*isDef*/
false, /*isImpl*/
true /*isKill*/));
NewMI->addOperand(Op2);
MII = MBB->erase(MI);
--MII;
} else if (Opc == Hexagon::STriw_pred) {
// STriw_pred [R30], ofst, SrcReg;
unsigned FP = MI->getOperand(0).getReg();
assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(1).isImm() && "Not an offset");
int Offset = MI->getOperand(1).getImm();
int SrcReg = MI->getOperand(2).getReg();
assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
"Not a predicate register");
if (!TII->isValidOffset(Hexagon::S2_storeri_io, Offset)) {
if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::CONST32_Int_Real),
HEXAGON_RESERVED_REG_1).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add),
HEXAGON_RESERVED_REG_1)
.addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
HEXAGON_RESERVED_REG_2).addReg(SrcReg);
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::S2_storeri_io))
.addReg(HEXAGON_RESERVED_REG_1)
.addImm(0).addReg(HEXAGON_RESERVED_REG_2);
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
HEXAGON_RESERVED_REG_2).addReg(SrcReg);
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::S2_storeri_io))
.addReg(HEXAGON_RESERVED_REG_1)
.addImm(0)
.addReg(HEXAGON_RESERVED_REG_2);
}
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
HEXAGON_RESERVED_REG_2).addReg(SrcReg);
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::S2_storeri_io)).
addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
}
MII = MBB->erase(MI);
--MII;
} else if (Opc == Hexagon::LDriw_pred) {
// DstReg = LDriw_pred [R30], ofst.
int DstReg = MI->getOperand(0).getReg();
assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
"Not a predicate register");
unsigned FP = MI->getOperand(1).getReg();
assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm();
if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {
if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::CONST32_Int_Real),
HEXAGON_RESERVED_REG_1).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add),
HEXAGON_RESERVED_REG_1)
.addReg(FP)
.addReg(HEXAGON_RESERVED_REG_1);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
HEXAGON_RESERVED_REG_2)
.addReg(HEXAGON_RESERVED_REG_1)
.addImm(0);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2);
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
HEXAGON_RESERVED_REG_2)
.addReg(HEXAGON_RESERVED_REG_1)
.addImm(0);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2);
}
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2);
}
MII = MBB->erase(MI);
--MII;
}
}
}
return true;
}
} // namespace
//===----------------------------------------------------------------------===//
// Public Constructor Functions
//===----------------------------------------------------------------------===//
static void initializePassOnce(PassRegistry &Registry) {
const char *Name = "Hexagon Expand Predicate Spill Code";
PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred",
&HexagonExpandPredSpillCode::ID,
nullptr, false, false);
Registry.registerPass(*PI, true);
}
void llvm::initializeHexagonExpandPredSpillCodePass(PassRegistry &Registry) {
CALL_ONCE_INITIALIZATION(initializePassOnce)
}
FunctionPass*
llvm::createHexagonExpandPredSpillCode() {
return new HexagonExpandPredSpillCode();
}
|
