1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
|
//===- llvm/CodeGen/VirtRegMap.h - Virtual Register Map ---------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements a virtual register map. This maps virtual registers to
// physical registers and virtual registers to stack slots. It is created and
// updated by a register allocator and then used by a machine code rewriter that
// adds spill code and rewrites virtual into physical register references.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_VIRTREGMAP_H
#define LLVM_CODEGEN_VIRTREGMAP_H
#include "llvm/ADT/IndexedMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TileShapeInfo.h"
#include "llvm/Pass.h"
#include <cassert>
namespace llvm {
class MachineFunction;
class MachineRegisterInfo;
class raw_ostream;
class TargetInstrInfo;
class VirtRegMap : public MachineFunctionPass {
public:
enum {
NO_PHYS_REG = 0,
NO_STACK_SLOT = (1L << 30)-1,
MAX_STACK_SLOT = (1L << 18)-1
};
private:
MachineRegisterInfo *MRI;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
MachineFunction *MF;
/// Virt2PhysMap - This is a virtual to physical register
/// mapping. Each virtual register is required to have an entry in
/// it; even spilled virtual registers (the register mapped to a
/// spilled register is the temporary used to load it from the
/// stack).
IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap;
/// Virt2StackSlotMap - This is virtual register to stack slot
/// mapping. Each spilled virtual register has an entry in it
/// which corresponds to the stack slot this register is spilled
/// at.
IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
/// Virt2SplitMap - This is virtual register to splitted virtual register
/// mapping.
IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
/// Virt2ShapeMap - For X86 AMX register whose register is bound shape
/// information.
DenseMap<unsigned, ShapeT> Virt2ShapeMap;
/// createSpillSlot - Allocate a spill slot for RC from MFI.
unsigned createSpillSlot(const TargetRegisterClass *RC);
public:
static char ID;
VirtRegMap()
: MachineFunctionPass(ID), MRI(nullptr), TII(nullptr), TRI(nullptr),
MF(nullptr), Virt2PhysMap(NO_PHYS_REG),
Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) {}
VirtRegMap(const VirtRegMap &) = delete;
VirtRegMap &operator=(const VirtRegMap &) = delete;
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
MachineFunction &getMachineFunction() const {
assert(MF && "getMachineFunction called before runOnMachineFunction");
return *MF;
}
MachineRegisterInfo &getRegInfo() const { return *MRI; }
const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
void grow();
/// returns true if the specified virtual register is
/// mapped to a physical register
bool hasPhys(Register virtReg) const {
return getPhys(virtReg) != NO_PHYS_REG;
}
/// returns the physical register mapped to the specified
/// virtual register
MCRegister getPhys(Register virtReg) const {
assert(virtReg.isVirtual());
return MCRegister::from(Virt2PhysMap[virtReg.id()]);
}
/// creates a mapping for the specified virtual register to
/// the specified physical register
void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
bool isShapeMapEmpty() const { return Virt2ShapeMap.empty(); }
bool hasShape(Register virtReg) const {
return getShape(virtReg).isValid();
}
ShapeT getShape(Register virtReg) const {
assert(virtReg.isVirtual());
return Virt2ShapeMap.lookup(virtReg);
}
void assignVirt2Shape(Register virtReg, ShapeT shape) {
Virt2ShapeMap[virtReg.id()] = shape;
}
/// clears the specified virtual register's, physical
/// register mapping
void clearVirt(Register virtReg) {
assert(virtReg.isVirtual());
assert(Virt2PhysMap[virtReg.id()] != NO_PHYS_REG &&
"attempt to clear a not assigned virtual register");
Virt2PhysMap[virtReg.id()] = NO_PHYS_REG;
}
/// clears all virtual to physical register mappings
void clearAllVirt() {
Virt2PhysMap.clear();
grow();
}
/// returns true if VirtReg is assigned to its preferred physreg.
bool hasPreferredPhys(Register VirtReg);
/// returns true if VirtReg has a known preferred register.
/// This returns false if VirtReg has a preference that is a virtual
/// register that hasn't been assigned yet.
bool hasKnownPreference(Register VirtReg);
/// records virtReg is a split live interval from SReg.
void setIsSplitFromReg(Register virtReg, Register SReg) {
Virt2SplitMap[virtReg.id()] = SReg;
if (hasShape(SReg)) {
Virt2ShapeMap[virtReg.id()] = getShape(SReg);
}
}
/// returns the live interval virtReg is split from.
Register getPreSplitReg(Register virtReg) const {
return Virt2SplitMap[virtReg.id()];
}
/// getOriginal - Return the original virtual register that VirtReg descends
/// from through splitting.
/// A register that was not created by splitting is its own original.
/// This operation is idempotent.
Register getOriginal(Register VirtReg) const {
Register Orig = getPreSplitReg(VirtReg);
return Orig ? Orig : VirtReg;
}
/// returns true if the specified virtual register is not
/// mapped to a stack slot or rematerialized.
bool isAssignedReg(Register virtReg) const {
if (getStackSlot(virtReg) == NO_STACK_SLOT)
return true;
// Split register can be assigned a physical register as well as a
// stack slot or remat id.
return (Virt2SplitMap[virtReg.id()] &&
Virt2PhysMap[virtReg.id()] != NO_PHYS_REG);
}
/// returns the stack slot mapped to the specified virtual
/// register
int getStackSlot(Register virtReg) const {
assert(virtReg.isVirtual());
return Virt2StackSlotMap[virtReg.id()];
}
/// create a mapping for the specifed virtual register to
/// the next available stack slot
int assignVirt2StackSlot(Register virtReg);
/// create a mapping for the specified virtual register to
/// the specified stack slot
void assignVirt2StackSlot(Register virtReg, int SS);
void print(raw_ostream &OS, const Module* M = nullptr) const override;
void dump() const;
};
inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
VRM.print(OS);
return OS;
}
} // end llvm namespace
#endif // LLVM_CODEGEN_VIRTREGMAP_H
|
