1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
|
//===-- SIPostRABundler.cpp -----------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file
/// This pass creates bundles of memory instructions to protect adjacent loads
/// and stores from beeing rescheduled apart from each other post-RA.
///
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
using namespace llvm;
#define DEBUG_TYPE "si-post-ra-bundler"
namespace {
class SIPostRABundler : public MachineFunctionPass {
public:
static char ID;
public:
SIPostRABundler() : MachineFunctionPass(ID) {
initializeSIPostRABundlerPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
return "SI post-RA bundler";
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
const SIRegisterInfo *TRI;
SmallSet<Register, 16> Defs;
void collectUsedRegUnits(const MachineInstr &MI,
BitVector &UsedRegUnits) const;
bool isBundleCandidate(const MachineInstr &MI) const;
bool isDependentLoad(const MachineInstr &MI) const;
bool canBundle(const MachineInstr &MI, const MachineInstr &NextMI) const;
};
constexpr uint64_t MemFlags = SIInstrFlags::MTBUF | SIInstrFlags::MUBUF |
SIInstrFlags::SMRD | SIInstrFlags::DS |
SIInstrFlags::FLAT | SIInstrFlags::MIMG;
} // End anonymous namespace.
INITIALIZE_PASS(SIPostRABundler, DEBUG_TYPE, "SI post-RA bundler", false, false)
char SIPostRABundler::ID = 0;
char &llvm::SIPostRABundlerID = SIPostRABundler::ID;
FunctionPass *llvm::createSIPostRABundlerPass() {
return new SIPostRABundler();
}
bool SIPostRABundler::isDependentLoad(const MachineInstr &MI) const {
if (!MI.mayLoad())
return false;
for (const MachineOperand &Op : MI.explicit_operands()) {
if (!Op.isReg())
continue;
Register Reg = Op.getReg();
for (Register Def : Defs)
if (TRI->regsOverlap(Reg, Def))
return true;
}
return false;
}
void SIPostRABundler::collectUsedRegUnits(const MachineInstr &MI,
BitVector &UsedRegUnits) const {
for (const MachineOperand &Op : MI.operands()) {
if (!Op.isReg() || !Op.readsReg())
continue;
Register Reg = Op.getReg();
assert(!Op.getSubReg() &&
"subregister indexes should not be present after RA");
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
UsedRegUnits.set(*Units);
}
}
bool SIPostRABundler::isBundleCandidate(const MachineInstr &MI) const {
const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags;
return IMemFlags != 0 && MI.mayLoadOrStore() && !MI.isBundled();
}
bool SIPostRABundler::canBundle(const MachineInstr &MI,
const MachineInstr &NextMI) const {
const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags;
return (IMemFlags != 0 && MI.mayLoadOrStore() && !NextMI.isBundled() &&
NextMI.mayLoad() == MI.mayLoad() && NextMI.mayStore() == MI.mayStore() &&
((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) &&
!isDependentLoad(NextMI));
}
bool SIPostRABundler::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
BitVector BundleUsedRegUnits(TRI->getNumRegUnits());
BitVector KillUsedRegUnits(TRI->getNumRegUnits());
bool Changed = false;
for (MachineBasicBlock &MBB : MF) {
MachineBasicBlock::instr_iterator Next;
MachineBasicBlock::instr_iterator B = MBB.instr_begin();
MachineBasicBlock::instr_iterator E = MBB.instr_end();
for (auto I = B; I != E; I = Next) {
Next = std::next(I);
if (!isBundleCandidate(*I))
continue;
assert(Defs.empty());
if (I->getNumExplicitDefs() != 0)
Defs.insert(I->defs().begin()->getReg());
MachineBasicBlock::instr_iterator BundleStart = I;
MachineBasicBlock::instr_iterator BundleEnd = I;
unsigned ClauseLength = 1;
for (I = Next; I != E; I = Next) {
Next = std::next(I);
assert(BundleEnd != I);
if (canBundle(*BundleEnd, *I)) {
BundleEnd = I;
if (I->getNumExplicitDefs() != 0)
Defs.insert(I->defs().begin()->getReg());
++ClauseLength;
} else if (!I->isMetaInstruction()) {
// Allow meta instructions in between bundle candidates, but do not
// start or end a bundle on one.
//
// TODO: It may be better to move meta instructions like dbg_value
// after the bundle. We're relying on the memory legalizer to unbundle
// these.
break;
}
}
Next = std::next(BundleEnd);
if (ClauseLength > 1) {
Changed = true;
// Before register allocation, kills are inserted after potential soft
// clauses to hint register allocation. Look for kills that look like
// this, and erase them.
if (Next != E && Next->isKill()) {
// TODO: Should maybe back-propagate kill flags to the bundle.
for (const MachineInstr &BundleMI : make_range(BundleStart, Next))
collectUsedRegUnits(BundleMI, BundleUsedRegUnits);
BundleUsedRegUnits.flip();
while (Next != E && Next->isKill()) {
MachineInstr &Kill = *Next;
collectUsedRegUnits(Kill, KillUsedRegUnits);
KillUsedRegUnits &= BundleUsedRegUnits;
// Erase the kill if it's a subset of the used registers.
//
// TODO: Should we just remove all kills? Is there any real reason to
// keep them after RA?
if (KillUsedRegUnits.none()) {
++Next;
Kill.eraseFromParent();
} else
break;
KillUsedRegUnits.reset();
}
BundleUsedRegUnits.reset();
}
finalizeBundle(MBB, BundleStart, Next);
}
Defs.clear();
}
}
return Changed;
}
|
