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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
define <2 x i64> @PR25554(<2 x i64> %v0, <2 x i64> %v1) {
; SSE-LABEL: PR25554:
; SSE: # BB#0:
; SSE-NEXT: movl $1, %eax
; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: PR25554:
; AVX: # BB#0:
; AVX-NEXT: movl $1, %eax
; AVX-NEXT: vmovq %rax, %xmm1
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
; AVX-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%c1 = or <2 x i64> %v0, <i64 1, i64 0>
%c2 = add <2 x i64> %c1, <i64 0, i64 1>
ret <2 x i64> %c2
}
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