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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid destination or source register.
andv d0, p7, z31.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: andv d0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
andv d0, p7, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: andv d0, p7, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
andv d0, p7, z31.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: andv d0, p7, z31.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
andv v0.2d, p7, z31.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: andv v0.2d, p7, z31.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid predicate
andv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: andv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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