devel/llvm-morello: Update to a new snapshot

This snapshot includes the final version of the patch applied in
93a0c2d46a28d0929d75182583ca2fc63bf8898b.

Sponsored by:	DARPA, AFRL

4 files changed, 7 insertions, 140 deletions

diff --git a/devel/llvm-morello/Makefile b/devel/llvm-morello/Makefile
index d4a504ca85d5..4d8ccdbe668a 100644
--- a/devel/llvm-morello/Makefile
+++ b/devel/llvm-morello/Makefile
@@ -17,7 +17,9 @@ GL_COMMIT=	${LLVM_COMMIT}
 # Regularly tested targets as part of Android development
 LLVM_TARGETS=	AArch64;ARM;BPF;X86
 
+.if exists(${.CURDIR}/files)
 EXTRA_PATCHES=	${.CURDIR}/files
+.endif
 
 .include "${.CURDIR}/Makefile.snapshot"
 
diff --git a/devel/llvm-morello/Makefile.snapshot b/devel/llvm-morello/Makefile.snapshot
index b6067228874a..9a9473ff73f8 100644
--- a/devel/llvm-morello/Makefile.snapshot
+++ b/devel/llvm-morello/Makefile.snapshot
@@ -1,5 +1,5 @@
 LLVM_MAJOR=	13
 LLVM_RELEASE=	${LLVM_MAJOR}.0.0
-SNAPDATE=	20220502
+SNAPDATE=	20220523
 
-LLVM_COMMIT=	0d2a3da490a43b0b78161f0040c3cbf60cb6e07d
+LLVM_COMMIT=	a7d0053c29e0275a7d920170fe686ba3b6d61cbf
diff --git a/devel/llvm-morello/distinfo b/devel/llvm-morello/distinfo
index 3c2e07f1662e..a4a5c0f9fe41 100644
--- a/devel/llvm-morello/distinfo
+++ b/devel/llvm-morello/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1651683901
-SHA256 (morello-llvm-project-0d2a3da490a43b0b78161f0040c3cbf60cb6e07d_GL0.tar.gz) = b50884c3b6bde5d36a9a89a916bb17c06f0c1263998ec456c0c4b51c8dd6f7df
-SIZE (morello-llvm-project-0d2a3da490a43b0b78161f0040c3cbf60cb6e07d_GL0.tar.gz) = 152764070
+TIMESTAMP = 1653335263
+SHA256 (morello-llvm-project-a7d0053c29e0275a7d920170fe686ba3b6d61cbf_GL0.tar.gz) = a009da4fba150575ca52f16e3dbe0380d8a3a917f601666a0fa9a43d59c34e59
+SIZE (morello-llvm-project-a7d0053c29e0275a7d920170fe686ba3b6d61cbf_GL0.tar.gz) = 152780065
diff --git a/devel/llvm-morello/files/patch-scratch-reg-fix b/devel/llvm-morello/files/patch-scratch-reg-fix
deleted file mode 100644
index 2a6ef90705a7..000000000000
--- a/devel/llvm-morello/files/patch-scratch-reg-fix
+++ /dev/null
@@ -1,135 +0,0 @@
-commit a7d0053c29e0275a7d920170fe686ba3b6d61cbf
-Author: Silviu Baranga <silviu.baranga@arm.com>
-Date:   Wed May 18 14:31:24 2022 +0100
-
-    [Morello] Don't use a scratch register for re-aligning the stack.
-    
-    Purecap can use alignd which can use csp.
-    
-    This avoids using C9 as a scratch register which can cause issues
-    with the new varargs PCS.
-
-diff --git llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
-index 42944b417f49..205a7576fe06 100644
---- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
-+++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
-@@ -593,32 +593,15 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves(
- // but we would then have to make sure that we were in fact saving at least one
- // callee-save register in the prologue, which is additional complexity that
- // doesn't seem worth the benefit.
--static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB,
--    unsigned OldScratch = AArch64::NoRegister) {
--
--  static const MCPhysReg ScratchCapReg1[2] = {AArch64::C6, AArch64::C9};
--  static const MCPhysReg ScratchCapReg2[2] = {AArch64::C7, AArch64::C10};
--
-+static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) {
-   MachineFunction *MF = MBB->getParent();
--
-   const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
--  bool HasPureCap = Subtarget.hasPureCap();
--  bool Use32CapRegs = !Subtarget.use16CapRegs();
--  // We can use an intra-procedural registers here since aligning the
--  // prologue doesn't require having this live across branches.
--  unsigned DefaultScratch = HasPureCap ? ScratchCapReg1[Use32CapRegs] : AArch64::X9;
--  if (OldScratch == DefaultScratch)
--    DefaultScratch = HasPureCap ? ScratchCapReg2[Use32CapRegs] : AArch64::X10;
--
--  const TargetRegisterClass ScratchRegClass =
--      HasPureCap ? AArch64::CapRegClass : AArch64::GPR64RegClass;
-+  assert(!Subtarget.hasPureCap() &&
-+      "Purecap doesn't need a scratch register");
- 
-   // If MBB is an entry block, use X9 as the scratch register
--  if (&MF->front() == MBB) {
--    assert(DefaultScratch != OldScratch &&
--           "Should not reuse scratch register");
--    return DefaultScratch;
--  }
-+  if (&MF->front() == MBB)
-+    return AArch64::X9;
- 
-   const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
-   LivePhysRegs LiveRegs(TRI);
-@@ -629,15 +612,12 @@ static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB,
-   for (unsigned i = 0; CSRegs[i]; ++i)
-     LiveRegs.addReg(CSRegs[i]);
- 
--  if (OldScratch != AArch64::NoRegister)
--    LiveRegs.addReg(OldScratch);
--
--  // Prefer X9/C6 since it was historically used for the prologue scratch reg.
-+  // Prefer X9 since it was historically used for the prologue scratch reg.
-   const MachineRegisterInfo &MRI = MF->getRegInfo();
--  if (LiveRegs.available(MRI, DefaultScratch))
--    return DefaultScratch;
-+  if (LiveRegs.available(MRI, AArch64::X9))
-+    return AArch64::X9;
- 
--  for (unsigned Reg : ScratchRegClass) {
-+  for (unsigned Reg : AArch64::GPR64RegClass) {
-     if (LiveRegs.available(MRI, Reg))
-       return Reg;
-   }
-@@ -650,9 +630,11 @@ bool AArch64FrameLowering::canUseAsPrologue(
-   MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
-   const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
-   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
-+  bool HasPureCap = Subtarget.hasPureCap();
- 
-   // Don't need a scratch register if we're not going to re-align the stack.
--  if (!RegInfo->hasStackRealignment(*MF))
-+  // Purecap doesn't need a scratch to re-align the stack.
-+  if (HasPureCap || !RegInfo->hasStackRealignment(*MF))
-     return true;
-   // Otherwise, we can use any block as long as it has a scratch register
-   // available.
-@@ -1542,7 +1524,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
-         !IsFunclet && RegInfo->hasStackRealignment(MF);
-     unsigned scratchSPReg = SP;
- 
--    if (NeedsRealignment) {
-+    if (NeedsRealignment && !HasPureCap) {
-       scratchSPReg = findScratchNonCalleeSaveRegister(&MBB);
-       assert(scratchSPReg != AArch64::NoRegister);
-     }
-@@ -1559,7 +1541,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
-     if (NeedsRealignment) {
-       const unsigned NrBitsToZero = Log2(MFI.getMaxAlign());
-       assert(NrBitsToZero > 1);
--      assert(scratchSPReg != SP);
-+      assert((scratchSPReg != SP) != HasPureCap);
- 
-       // SUB X9, SP, NumBytes
-       //   -- X9 is temporary register, so shouldn't contain any live data here,
-diff --git llvm/test/CodeGen/AArch64/morello-sandbox-align-and-pad.ll llvm/test/CodeGen/AArch64/morello-sandbox-align-and-pad.ll
-index b0e8f567e331..cb9fef678cea 100644
---- llvm/test/CodeGen/AArch64/morello-sandbox-align-and-pad.ll
-+++ llvm/test/CodeGen/AArch64/morello-sandbox-align-and-pad.ll
-@@ -11,8 +11,8 @@ target datalayout = "e-m:e-pf200:128:128-i8:8:32-i16:16:32-i64:64-i128:128-n32:6
- define i32 @fun1() addrspace(200) {
- entry:
- ; Allocate extra memory. CSP still needs to be 16 bytes aligned.
--; PCS16:	sub c6, csp, #1024, lsl #12
--; PCS16-NEXT: sub c6, c6, #4032
-+; PCS16:	sub csp, csp, #1024, lsl #12
-+; PCS16-NEXT: sub csp, csp, #4032
- 
- ; PCS16: mov w[[REG:[0-9]+]], #2048
- ; PCS16-NEXT: movk w8, #64, lsl #16
-@@ -34,12 +34,12 @@ declare i32 @g(i32 addrspace(200)*) local_unnamed_addr addrspace(200) #2
- ; CHECK-LABEL: fun2
- define i32 @fun2() addrspace(200) {
- entry:
--; Here we need more alignment than the stack alignment. We know that the scratch register is c6.
--; PCS16: alignd	csp, c6, #14
-+; Here we need more alignment than the stack alignment.
-+; PCS16: alignd	csp, csp, #14
- ; PCS16: mov w[[REG:[0-9]+]], #33554432
- ; PCS16: scbndse c{{.*}}, c{{.*}}, x[[REG]]
- ;
--; PCS32: alignd	csp, c9, #11
-+; PCS32: alignd	csp, csp, #14
- ; PCS32: mov w[[REG:[0-9]+]], #33554432
- ; PCS32: scbndse c{{.*}}, c{{.*}}, x[[REG]]
-