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| author | Andrew Turner <andrew@FreeBSD.org> | 2023-06-09 17:46:58 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2023-09-25 08:41:32 +0000 |
| commit | 0fb5ae0c7c3d8adf4d1e0d8badf7e724db279f8a (patch) | |
| tree | 356b0014f91f63ffbd080e9bd50f7dfd1600174a | |
| parent | da9d00c5bac94f4e3ed19e08f0df4fb63d1acb98 (diff) | |
| download | src-0fb5ae0c7c3d8adf4d1e0d8badf7e724db279f8a.tar.gz src-0fb5ae0c7c3d8adf4d1e0d8badf7e724db279f8a.zip | |
Add more arm64 special register values
These will be used to simplify the kernel special register handling.
Sponsored by: Arm Ltd
(cherry picked from commit 178747a1586d48a8063014d7b8528ec47205e1bf)
| -rw-r--r-- | sys/arm64/include/armreg.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 9b60ea2a6263..d307781f2d01 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -1247,6 +1247,14 @@ #define MDSCR_MDE_SHIFT 15 #define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT) +/* MIDR_EL1 - Main ID Register */ +#define MIDR_EL1 MRS_REG(MIDR_EL1) +#define MIDR_EL1_op0 3 +#define MIDR_EL1_op1 0 +#define MIDR_EL1_CRn 0 +#define MIDR_EL1_CRm 0 +#define MIDR_EL1_op2 0 + /* MPIDR_EL1 - Multiprocessor Affinity Register */ #define MPIDR_EL1 MRS_REG(MPIDR_EL1) #define MPIDR_EL1_op0 3 @@ -1886,6 +1894,14 @@ #define PSR_SETTABLE_32 PSR_FLAGS #define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS) +/* REVIDR_EL1 - Revision ID Register */ +#define REVIDR_EL1 MRS_REG(REVIDR_EL1) +#define REVIDR_EL1_op0 3 +#define REVIDR_EL1_op1 0 +#define REVIDR_EL1_CRn 0 +#define REVIDR_EL1_CRm 0 +#define REVIDR_EL1_op2 6 + /* TCR_EL1 - Translation Control Register */ /* Bits 63:59 are reserved */ #define TCR_TCMA1_SHIFT 58 |