diff options
| author | Guinan Sun <guinanx.sun@intel.com> | 2020-07-06 08:11:56 +0000 |
|---|---|---|
| committer | Kevin Bowling <kbowling@FreeBSD.org> | 2021-09-17 21:18:25 +0000 |
| commit | 1883a6ff3b2ebaf108c45717c8eb94e0a76bb0b9 (patch) | |
| tree | e0e5cbe945bf0cf3cd2038b4f2c8293176478df0 | |
| parent | 6b9d35fac12bf657cd1df8f1521c70704ff62b61 (diff) | |
| download | src-1883a6ff3b2ebaf108c45717c8eb94e0a76bb0b9.tar.gz src-1883a6ff3b2ebaf108c45717c8eb94e0a76bb0b9.zip | |
e1000: update for i210 slow system clock
This code is required for the update for system clock.
Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>
Approved by: imp
Obtained from: DPDK (3f0188c8f29847038bc9f306b2570ace57e3811c)
MFC after: 1 week
| -rw-r--r-- | sys/dev/e1000/e1000_i210.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/sys/dev/e1000/e1000_i210.c b/sys/dev/e1000/e1000_i210.c index 0bdad37e56d3..cd85a8c3172a 100644 --- a/sys/dev/e1000/e1000_i210.c +++ b/sys/dev/e1000/e1000_i210.c @@ -612,6 +612,8 @@ static s32 e1000_pll_workaround_i210(struct e1000_hw *hw) u16 nvm_word, phy_word, pci_word, tmp_nvm; int i; + /* Get PHY semaphore */ + hw->phy.ops.acquire(hw); /* Get and set needed register values */ wuc = E1000_READ_REG(hw, E1000_WUC); mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); @@ -626,8 +628,11 @@ static s32 e1000_pll_workaround_i210(struct e1000_hw *hw) tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL; for (i = 0; i < E1000_MAX_PLL_TRIES; i++) { /* check current state directly from internal PHY */ - e1000_read_phy_reg_gs40g(hw, (E1000_PHY_PLL_FREQ_PAGE | - E1000_PHY_PLL_FREQ_REG), &phy_word); + e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0xFC); + usec_delay(20); + e1000_read_phy_reg_mdic(hw, E1000_PHY_PLL_FREQ_REG, &phy_word); + usec_delay(20); + e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, 0); if ((phy_word & E1000_PHY_PLL_UNCONF) != E1000_PHY_PLL_UNCONF) { ret_val = E1000_SUCCESS; @@ -661,6 +666,8 @@ static s32 e1000_pll_workaround_i210(struct e1000_hw *hw) } /* restore MDICNFG setting */ E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); + /* Release PHY semaphore */ + hw->phy.ops.release(hw); return ret_val; } |