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authorNavdeep Parhar <np@FreeBSD.org>2024-04-26 00:39:55 +0000
committerNavdeep Parhar <np@FreeBSD.org>2024-04-29 19:34:51 +0000
commit1c7f9c8b4673abf3723be09afed4443261e0d186 (patch)
tree4167e1645d0cfbbeca1ee60c6683e459772aaec8
parentb59c5d97edf17525405d95b1f5746c4a79a9c7c4 (diff)
downloadsrc-1c7f9c8b4673abf3723be09afed4443261e0d186.tar.gz
src-1c7f9c8b4673abf3723be09afed4443261e0d186.zip
cxgbe(4): Retire t4_intr_clear.
The firmware clears the interrupts already and it has a better idea of exactly what to clear for which generation of the ASIC. There is no need for the driver to get involved. MFC after: 1 week Sponsored by: Chelsio Communications
-rw-r--r--sys/dev/cxgbe/common/common.h1
-rw-r--r--sys/dev/cxgbe/common/t4_hw.c93
-rw-r--r--sys/dev/cxgbe/t4_main.c2
3 files changed, 0 insertions, 96 deletions
diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
index 79bb6276f4c7..f91d4ebf7334 100644
--- a/sys/dev/cxgbe/common/common.h
+++ b/sys/dev/cxgbe/common/common.h
@@ -618,7 +618,6 @@ struct fw_filter_wr;
void t4_intr_enable(struct adapter *adapter);
void t4_intr_disable(struct adapter *adapter);
-void t4_intr_clear(struct adapter *adapter);
bool t4_slow_intr_handler(struct adapter *adapter, bool verbose);
int t4_hash_mac_addr(const u8 *addr);
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 4ca87727ca59..e3d5cf814e4d 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -5455,99 +5455,6 @@ void t4_intr_disable(struct adapter *adap)
}
/**
- * t4_intr_clear - clear all interrupts
- * @adap: the adapter whose interrupts should be cleared
- *
- * Clears all interrupts. The caller must be a PCI function managing
- * global interrupts.
- */
-void t4_intr_clear(struct adapter *adap)
-{
- static const u32 cause_reg[] = {
- A_CIM_HOST_INT_CAUSE,
- A_CIM_HOST_UPACC_INT_CAUSE,
- MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
- A_CPL_INTR_CAUSE,
- EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1),
- A_LE_DB_INT_CAUSE,
- A_MA_INT_WRAP_STATUS,
- A_MA_PARITY_ERROR_STATUS1,
- A_MA_INT_CAUSE,
- A_MPS_CLS_INT_CAUSE,
- A_MPS_RX_PERR_INT_CAUSE,
- A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
- A_MPS_STAT_PERR_INT_CAUSE_SRAM,
- A_MPS_TRC_INT_CAUSE,
- A_MPS_TX_INT_CAUSE,
- A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
- A_NCSI_INT_CAUSE,
- A_PCIE_INT_CAUSE,
- A_PCIE_NONFAT_ERR,
- A_PL_PL_INT_CAUSE,
- A_PM_RX_INT_CAUSE,
- A_PM_TX_INT_CAUSE,
- A_SGE_INT_CAUSE1,
- A_SGE_INT_CAUSE2,
- A_SGE_INT_CAUSE3,
- A_SGE_INT_CAUSE4,
- A_SMB_INT_CAUSE,
- A_TP_INT_CAUSE,
- A_ULP_RX_INT_CAUSE,
- A_ULP_RX_INT_CAUSE_2,
- A_ULP_TX_INT_CAUSE,
- A_ULP_TX_INT_CAUSE_2,
-
- MYPF_REG(A_PL_PF_INT_CAUSE),
- };
- int i;
- const int nchan = adap->chip_params->nchan;
-
- for (i = 0; i < ARRAY_SIZE(cause_reg); i++)
- t4_write_reg(adap, cause_reg[i], 0xffffffff);
-
- if (is_t4(adap)) {
- t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
- 0xffffffff);
- t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
- 0xffffffff);
- t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff);
- for (i = 0; i < nchan; i++) {
- t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE),
- 0xffffffff);
- }
- }
- if (chip_id(adap) >= CHELSIO_T5) {
- t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
- t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff);
- t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff);
- t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff);
- if (is_t5(adap)) {
- t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1),
- 0xffffffff);
- }
- for (i = 0; i < nchan; i++) {
- t4_write_reg(adap, T5_PORT_REG(i,
- A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff);
- if (chip_id(adap) > CHELSIO_T5) {
- t4_write_reg(adap, T5_PORT_REG(i,
- A_MAC_PORT_PERR_INT_CAUSE_100G),
- 0xffffffff);
- }
- t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE),
- 0xffffffff);
- }
- }
- if (chip_id(adap) >= CHELSIO_T6) {
- t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff);
- }
-
- t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
- t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff);
- t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff);
- (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */
-}
-
-/**
* hash_mac_addr - return the hash value of a MAC address
* @addr: the 48-bit Ethernet MAC address
*
diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c
index 5c2e1fd232c2..7bdce5faf7af 100644
--- a/sys/dev/cxgbe/t4_main.c
+++ b/sys/dev/cxgbe/t4_main.c
@@ -1333,7 +1333,6 @@ t4_attach(device_t dev)
rc = partition_resources(sc);
if (rc != 0)
goto done; /* error message displayed already */
- t4_intr_clear(sc);
}
rc = get_params__post_init(sc);
@@ -2289,7 +2288,6 @@ t4_resume(device_t dev)
rc = partition_resources(sc);
if (rc != 0)
goto done; /* error message displayed already */
- t4_intr_clear(sc);
}
rc = get_params__post_init(sc);