Do not expose to scheduler caches of single CPU.

Before this change my dual-Xeon(R) Gold 6242R always reported 3 levels
or topology (root, package/L3 and core/L2).  But with SMT disabled
core/L2 matches thread, so additional topology level only causes more
traversal work.  With this change SMT case is reported same as before,
while non-SMT is reported with only 2 much more simple levels.

MFC after:	2 weeks

1 files changed, 6 insertions, 0 deletions

diff --git a/sys/x86/x86/mp_x86.c b/sys/x86/x86/mp_x86.c
index c98ac12a7c3f..0698cb51b2d0 100644
--- a/sys/x86/x86/mp_x86.c
+++ b/sys/x86/x86/mp_x86.c
@@ -829,6 +829,12 @@ x86topo_add_sched_group(struct topo_node *root, struct cpu_group *cg_root)
 		node = topo_next_nonchild_node(root, node);
 	}
 
+	/*
+	 * We are not interested in nodes including only one CPU each.
+	 */
+	if (nchildren == root->cpu_count)
+		return;
+
 	cg_root->cg_child = smp_topo_alloc(nchildren);
 	cg_root->cg_children = nchildren;