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| author | Vladimir Kondratyev <wulf@FreeBSD.org> | 2023-11-27 15:25:48 +0000 |
|---|---|---|
| committer | Vladimir Kondratyev <wulf@FreeBSD.org> | 2023-11-27 15:25:48 +0000 |
| commit | 789ffce392946d2f71a51bbac60db16dcdea2928 (patch) | |
| tree | 596fc79b3981cb541b1d9e615207af7372d6f522 | |
| parent | 21fce617d1de231a30833cdd9819ef61277b08d8 (diff) | |
| download | src-789ffce392946d2f71a51bbac60db16dcdea2928.tar.gz src-789ffce392946d2f71a51bbac60db16dcdea2928.zip | |
ig4: Add PCI IDs for Intel Ice Lake I2C controller.
PR: 275115
Tested by: Sam <sam3423.yntmr_AT_slmail_DOT_me>
MFC after: 2 weeks
| -rw-r--r-- | sys/dev/ichiic/ig4_pci.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c index bb4b75c0c6d1..9f12e713cdeb 100644 --- a/sys/dev/ichiic/ig4_pci.c +++ b/sys/dev/ichiic/ig4_pci.c @@ -119,6 +119,12 @@ static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086 #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086 #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086 +#define PCI_CHIP_ICELAKE_LP_I2C_0 0x34e88086 +#define PCI_CHIP_ICELAKE_LP_I2C_1 0x34e98086 +#define PCI_CHIP_ICELAKE_LP_I2C_2 0x34ea8086 +#define PCI_CHIP_ICELAKE_LP_I2C_3 0x34eb8086 +#define PCI_CHIP_ICELAKE_LP_I2C_4 0x34c58086 +#define PCI_CHIP_ICELAKE_LP_I2C_5 0x34c68086 #define PCI_CHIP_TIGERLAKE_H_I2C_0 0x43d88086 #define PCI_CHIP_TIGERLAKE_H_I2C_1 0x43e88086 #define PCI_CHIP_TIGERLAKE_H_I2C_2 0x43e98086 @@ -225,6 +231,12 @@ static struct ig4iic_pci_device ig4iic_pci_devices[] = { { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE}, + { PCI_CHIP_ICELAKE_LP_I2C_0, "Intel Ice Lake-LP I2C Controller-0", IG4_TIGERLAKE}, + { PCI_CHIP_ICELAKE_LP_I2C_1, "Intel Ice Lake-LP I2C Controller-1", IG4_TIGERLAKE}, + { PCI_CHIP_ICELAKE_LP_I2C_2, "Intel Ice Lake-LP I2C Controller-2", IG4_TIGERLAKE}, + { PCI_CHIP_ICELAKE_LP_I2C_3, "Intel Ice Lake-LP I2C Controller-3", IG4_TIGERLAKE}, + { PCI_CHIP_ICELAKE_LP_I2C_4, "Intel Ice Lake-LP I2C Controller-4", IG4_TIGERLAKE}, + { PCI_CHIP_ICELAKE_LP_I2C_5, "Intel Ice Lake-LP I2C Controller-5", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE}, { PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE}, |