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| author | Andrew Turner <andrew@FreeBSD.org> | 2023-09-06 17:32:15 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2023-09-06 17:32:49 +0000 |
| commit | 8f26d01f53316c055cc1116eb56ff438da50d831 (patch) | |
| tree | 921e387841ded106845365dff5f0620393b7aa1a | |
| parent | 9e2cafe4fb901214903484998adf51a6cc5e4ebb (diff) | |
| download | src-8f26d01f53316c055cc1116eb56ff438da50d831.tar.gz src-8f26d01f53316c055cc1116eb56ff438da50d831.zip | |
arm64: Fix the TCR_EPD0 definition
Sponsored by: Arm Ltd
| -rw-r--r-- | sys/arm64/include/armreg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 5892a9b08502..034504727b39 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2167,7 +2167,7 @@ #define TCR_IRGN0_SHIFT 8 #define TCR_IRGN0_WBWA (1UL << TCR_IRGN0_SHIFT) #define TCR_EPD0_SHIFT 7 -#define TCR_EPD0 (1UL << TCR_EPD1_SHIFT) +#define TCR_EPD0 (1UL << TCR_EPD0_SHIFT) /* Bit 6 is reserved */ #define TCR_T0SZ_SHIFT 0 #define TCR_T0SZ_MASK 0x3f |