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| author | Mitchell Horne <mhorne@FreeBSD.org> | 2022-10-11 13:39:50 +0000 |
|---|---|---|
| committer | Mitchell Horne <mhorne@FreeBSD.org> | 2022-10-18 14:08:22 +0000 |
| commit | 97edb6baa91096a2d7d37546ad59596abe5c5b1b (patch) | |
| tree | 890125ccda34dde0adc4a10cdb2035981a0703fe | |
| parent | fff5fec16b2ec42b0cb357fdbb675353e3126f21 (diff) | |
| download | src-97edb6baa91096a2d7d37546ad59596abe5c5b1b.tar.gz src-97edb6baa91096a2d7d37546ad59596abe5c5b1b.zip | |
riscv: handle misaligned address exceptions
If this exception is coming from userspace, send the appropriate SIGBUS
to the process. If it's coming from the kernel this is still fatal, but
we can give a better panic message.
Typical misaligned loads/stores are emulated by the SBI firmware, and
require no intervention from our kernel. The notable exception here is
misaligned access with atomic instructions. These can generate the
exception and panic seen in the PR.
With this, we now handle all defined exception types.
PR: 266109
MFC after: 1 week
Found by: syzkaller
Reported by: P1umer <p1umer1337@gmail.com>
Differential Revision: https://reviews.freebsd.org/D36876
(cherry picked from commit 9b4cbaa9c3da233cf06381c3d22e3472ee586585)
| -rw-r--r-- | sys/riscv/riscv/trap.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/sys/riscv/riscv/trap.c b/sys/riscv/riscv/trap.c index 9a889661b965..4da6c9d21502 100644 --- a/sys/riscv/riscv/trap.c +++ b/sys/riscv/riscv/trap.c @@ -302,6 +302,13 @@ do_trap_supervisor(struct trapframe *frame) dump_regs(frame); panic("Memory access exception at 0x%016lx\n", frame->tf_sepc); break; + case SCAUSE_LOAD_MISALIGNED: + case SCAUSE_STORE_MISALIGNED: + case SCAUSE_INST_MISALIGNED: + dump_regs(frame); + panic("Misaligned address exception at %#016lx: %#016lx\n", + frame->tf_sepc, frame->tf_stval); + break; case SCAUSE_STORE_PAGE_FAULT: case SCAUSE_LOAD_PAGE_FAULT: case SCAUSE_INST_PAGE_FAULT: @@ -370,6 +377,13 @@ do_trap_user(struct trapframe *frame) exception); userret(td, frame); break; + case SCAUSE_LOAD_MISALIGNED: + case SCAUSE_STORE_MISALIGNED: + case SCAUSE_INST_MISALIGNED: + call_trapsignal(td, SIGBUS, BUS_ADRALN, (void *)frame->tf_sepc, + exception); + userret(td, frame); + break; case SCAUSE_STORE_PAGE_FAULT: case SCAUSE_LOAD_PAGE_FAULT: case SCAUSE_INST_PAGE_FAULT: |