scc(4)/uart(4): Remove obsolete support for Siemens SAB 82532

It's no longer used since 58aa35d42975c298ca0adba705c042596303c9f5
and r357455 respectively.

13 files changed, 6 insertions, 1259 deletions

diff --git a/share/man/man4/scc.4 b/share/man/man4/scc.4
index 45f6a5e6d596..e03f43011b07 100644
--- a/share/man/man4/scc.4
+++ b/share/man/man4/scc.4
@@ -25,7 +25,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd December 25, 2020
+.Dd December 26, 2020
 .Dt SCC 4
 .Os
 .\"
@@ -56,8 +56,6 @@ driver supports the following classes of SCCs:
 .It
 QUICC: Freescale/NXP QUad Integrated Communications Controllers.
 .It
-SAB82532: Siemens SAB 82532 based serial communications controllers.
-.It
 Z8530: Zilog 8530 based serial communications controllers.
 .El
 .\"
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index 22fb430a76c7..657f51c2abb1 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -1771,8 +1771,8 @@ options 	BREAK_TO_DEBUGGER	# A BREAK/DBG on the console goes to
 options 	ALT_BREAK_TO_DEBUGGER
 
 # Serial Communications Controller
-# Supports the Freescale/NXP QUad Integrated, Siemens SAB 82532 and Zilog Z8530
-# multi-channel communications controllers.
+# Supports the Freescale/NXP QUad Integrated and Zilog Z8530 multi-channel
+# communications controllers.
 device		scc
 
 # PCI Universal Communications driver
diff --git a/sys/conf/files b/sys/conf/files
index 86dce97eb5e8..dc4cadb36c14 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -3066,7 +3066,6 @@ dev/scc/scc_if.m		optional scc
 dev/scc/scc_bfe_quicc.c		optional scc quicc
 dev/scc/scc_core.c		optional scc
 dev/scc/scc_dev_quicc.c		optional scc quicc
-dev/scc/scc_dev_sab82532.c	optional scc
 dev/scc/scc_dev_z8530.c		optional scc
 dev/sdhci/sdhci.c		optional sdhci
 dev/sdhci/sdhci_fdt.c		optional sdhci fdt
@@ -3240,7 +3239,6 @@ dev/uart/uart_dev_mvebu.c	optional uart uart_mvebu
 dev/uart/uart_dev_ns8250.c	optional uart uart_ns8250 | uart uart_snps
 dev/uart/uart_dev_pl011.c	optional uart pl011
 dev/uart/uart_dev_quicc.c	optional uart quicc
-dev/uart/uart_dev_sab82532.c	optional uart uart_sab82532 | uart scc
 dev/uart/uart_dev_snps.c	optional uart uart_snps fdt
 dev/uart/uart_dev_z8530.c	optional uart uart_z8530 | uart scc
 dev/uart/uart_if.m		optional uart
diff --git a/sys/dev/ic/sab82532.h b/sys/dev/ic/sab82532.h
deleted file mode 100644
index 4cc723b6464c..000000000000
--- a/sys/dev/ic/sab82532.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/*	$OpenBSD: sab82532reg.h,v 1.2 2002/04/08 17:49:42 jason Exp $	*/
-
-/*-
- * SPDX-License-Identifier: BSD-4-Clause
- *
- * Copyright (c) 2001 Jason L. Wright (jason@thought.net)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Jason L. Wright
- * 4. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Effort sponsored in part by the Defense Advanced Research Projects
- * Agency (DARPA) and Air Force Research Laboratory, Air Force
- * Materiel Command, USAF, under agreement number F30602-01-2-0537.
- *
- * $FreeBSD$
- */
-
-#ifndef _DEV_IC_SAB82532_H_
-#define	_DEV_IC_SAB82532_H_
-
-/*
- * Register definitions for SAB82532 based on "Enhanced Serial Communication
- * Controller ESCC2 Version 3.2 User's Manual 07.96" from:
- * http://www.infineon.com
- */
-
-#define	SAB_NCHAN	2	/* number of channels */
-#define	SAB_CHANLEN	0x40	/* length of channel register set */
-
-#define	SAB_CHAN_A	0x00	/* channel A register offset */
-#define	SAB_CHAN_B	0x40	/* channel B register offset */
-
-#define	SAB_RFIFO	0x00	/* r: rx fifo */
-#define	SAB_XFIFO	0x00	/* w: tx fifo */
-#define	SAB_STAR	0x20	/* r: status register */
-#define	SAB_CMDR	0x20	/* w: command register */
-#define	SAB_MODE	0x22	/* rw: mode register */
-#define	SAB_TIMR	0x23	/* rw: timer register */
-#define	SAB_XON		0x24	/* rw: xon character */
-#define	SAB_XOFF	0x25	/* rw: xoff character */
-#define	SAB_TCR		0x26	/* rw: termination character */
-#define	SAB_DAFO	0x27	/* rw: data format */
-#define	SAB_RFC		0x28	/* rw: rfifo control register */
-#define	SAB_RBCL	0x2a	/* r: rx byte count low */
-#define	SAB_TBCL	0x2a	/* w: tx byte count low */
-#define	SAB_RBCH	0x2b	/* r: rx byte count high */
-#define	SAB_XBCH	0x2b	/* w: tx byte count high */
-#define	SAB_CCR0	0x2c	/* rw: channel configuration register 0 */
-#define	SAB_CCR1	0x2d	/* rw: channel configuration register 1 */
-#define	SAB_CCR2	0x2e	/* rw: channel configuration register 2 */
-#define	SAB_CCR3	0x2f	/* rw: channel configuration register 3 */
-#define	SAB_TSAX	0x30	/* w: time-slot assignment register tx */
-#define	SAB_TSAR	0x31	/* w: time-slot assignment register rx */
-#define	SAB_XCCR	0x32	/* w: tx channel capacity register */
-#define	SAB_RCCR	0x33	/* w: receive channel capacity register */
-#define	SAB_VSTR	0x34	/* r: version status */
-#define	SAB_BGR		0x34	/* w: baud rate generator */
-#define	SAB_TIC		0x35	/* w: transmit immediate character */
-#define	SAB_MXN		0x36	/* w: mask xon character */
-#define	SAB_MXF		0x37	/* w: mask xoff character */
-#define	SAB_GIS		0x38	/* r: global interrupt status */
-#define	SAB_IVA		0x38	/* w: interrupt vector address */
-#define	SAB_IPC		0x39	/* rw: interrupt port configuration */
-#define	SAB_ISR0	0x3a	/* r: interrupt status 0 */
-#define	SAB_IMR0	0x3a	/* w: interrupt mask 0 */
-#define	SAB_ISR1	0x3b	/* r: interrupt status 1 */
-#define	SAB_IMR1	0x3b	/* w: interrupt mask 1 */
-#define	SAB_PVR		0x3c	/* rw: port value register */
-#define	SAB_PIS		0x3d	/* r: port interrupt status */
-#define	SAB_PIM		0x3d	/* w: port interrupt mask */
-#define	SAB_PCR		0x3e	/* w: port configuration register */
-#define	SAB_CCR4	0x3f	/* rw: channel configuration register 4 */
-
-/* SAB_STAR: status register */
-#define	SAB_STAR_XDOV	0x80	/* transmit data overflow */
-#define	SAB_STAR_XFW	0x40	/* transmit fifo write enable */
-#define	SAB_STAR_RFNE	0x20	/* rfifo not empty */
-#define	SAB_STAR_FCS	0x10	/* flow control status */
-#define	SAB_STAR_TEC	0x08	/* tx immediate char is executing */
-#define	SAB_STAR_CEC	0x04	/* command is executing */
-#define	SAB_STAR_CTS	0x02	/* cts status: 0:inactive/high,1:active/low */
-
-/* SAB_CMDR: command register */
-#define	SAB_CMDR_RMC	0x80	/* receive message complete */
-#define	SAB_CMDR_RRES	0x40	/* receiver reset */
-#define	SAB_CMDR_RFRD	0x20	/* receive fifo read enable */
-#define	SAB_CMDR_STI	0x10	/* start timer */
-#define	SAB_CMDR_XF	0x08	/* transmit frame */
-#define	SAB_CMDR_XRES	0x01	/* transmit reset */
-
-/* SAB_MODE: mode register */
-#define	SAB_MODE_FRTS	0x40	/* flow control using rts */
-#define	SAB_MODE_FCTS	0x20	/* flow control using cts */
-#define	SAB_MODE_FLON	0x10	/* flow control on */
-#define	SAB_MODE_RAC	0x08	/* receiver active */
-#define	SAB_MODE_RTS	0x04	/* request to send */
-#define	SAB_MODE_TRS	0x02	/* timer resolution */
-#define	SAB_MODE_TLP	0x01	/* test loop */
-
-/* SAB_TIMR: timer register */
-#define	SAB_TIMR_CNT	0xe0	/* count mask */
-#define	SAB_TIMR_VAL	0x1f	/* value mask */
-
-/* SAB_DAFO: data format */
-#define	SAB_DAFO_XBRK	0x40	/* transmit break */
-#define	SAB_DAFO_STOP	0x20	/* stop bit: 0:1 bit, 1:2 bits */
-#define	SAB_DAFO_PAR1	0x10	/* parity 1, see below */
-#define	SAB_DAFO_PAR0	0x08	/* parity 0, see below */
-#define	SAB_DAFO_PARE	0x04	/* parity enable */
-#define	SAB_DAFO_CHL1	0x02	/* character length 1, see below */
-#define	SAB_DAFO_CHL0	0x01	/* character length 0, see below */
-
-#define	SAB_DAFO_CHL_CSIZE	(SAB_DAFO_CHL1|SAB_DAFO_CHL0)
-#define	SAB_DAFO_CHL_CS5	(SAB_DAFO_CHL1|SAB_DAFO_CHL0)
-#define	SAB_DAFO_CHL_CS6	(SAB_DAFO_CHL1)
-#define	SAB_DAFO_CHL_CS7	(SAB_DAFO_CHL0)
-#define	SAB_DAFO_CHL_CS8	(0)
-
-#define	SAB_DAFO_PARMASK	(SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
-#define	SAB_DAFO_PAR_MARK	(SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
-#define	SAB_DAFO_PAR_EVEN	(SAB_DAFO_PAR1|SAB_DAFO_PARE)
-#define	SAB_DAFO_PAR_ODD	(SAB_DAFO_PAR0|SAB_DAFO_PARE)
-#define	SAB_DAFO_PAR_SPACE	(SAB_DAFO_PARE)
-#define	SAB_DAFO_PAR_NONE	(0)
-
-/* SAB_RFC: rfifo control register */
-#define	SAB_RFC_DPS	0x40	/* disable parity storage */
-#define	SAB_RFC_DXS	0x20	/* disable storage of xon/xoff characters */
-#define	SAB_RFC_RFDF	0x10	/* rfifo data format: 0 data,1 data+stat */
-#define	SAB_RFC_RFTH1	0x08	/* rfifo threshold level 1, see below */
-#define	SAB_RFC_RFTH0	0x04	/* rfifo threshold level 0, see below */
-#define	SAB_RFC_TCDE	0x01	/* termination character detection enable */
-
-#define	SAB_RFC_RFTH_MASK	(SAB_RFC_RFTH1|SAB_RFC_RFTH0)
-#define	SAB_RFC_RFTH_32CHAR	(SAB_RFC_RFTH1|SAB_RFC_RFTH0)
-#define	SAB_RFC_RFTH_16CHAR	(SAB_RFC_RFTH1)
-#define	SAB_RFC_RFTH_4CHAR	(SAB_RFC_RFTH0)
-#define	SAB_RFC_RFTH_1CHAR	(0)
-
-/* SAB_RBCH: received byte count high */
-#define	SAB_RBCH_DMA	0x80	/* read back of XBCH DMA bit */
-#define	SAB_RBCH_CAS	0x20	/* read back of XBCH CAS bit */
-#define	SAB_RBCH_CNT	0x0f	/* ms 4 bits of rx byte count (not used) */
-
-/* SAB_XBCH: transmit byte count high */
-#define	SAB_XBCH_DMA	0x80	/* dma mode: 1:dma, 0:interrupt */
-#define	SAB_XBCH_CAS	0x20	/* carrier detect auto-start */
-#define	SAB_XBCH_XC	0x10	/* transmit continuously */
-#define	SAB_XBCH_CNT	0x0f	/* ms 4 bits of tx byte count */
-
-/* SAB_CCR0: channel configuration register 0 */
-#define	SAB_CCR0_PU	0x80	/* 0:power-down, 1:power-up */
-#define	SAB_CCR0_MCE	0x40	/* master clock enable */
-#define	SAB_CCR0_SC2	0x10	/* serial port config 2, see below */
-#define	SAB_CCR0_SC1	0x08	/* serial port config 1, see below */
-#define	SAB_CCR0_SC0	0x04	/* serial port config 0, see below */
-#define	SAB_CCR0_SM1	0x02	/* serial mode 1, see below */
-#define	SAB_CCR0_SM0	0x01	/* serial mode 0, see below */
-
-#define	SAB_CCR0_SC_MASK	(SAB_CCR0_SC2|SAB_CCR0_SC1|SAB_CCR0_SC0)
-#define	SAB_CCR0_SC_NRZ		(0)
-#define	SAB_CCR0_SC_NRZI	(SAB_CCR0_SC1)
-#define	SAB_CCR0_SC_FM0		(SAB_CCR0_SC2)
-#define	SAB_CCR0_SC_FM1		(SAB_CCR0_SC2|SAB_CCR0_SC0)
-#define	SAB_CCR0_SC_MANCHESTER	(SAB_CCR0_SC2|SAB_CCR0_SC1)
-
-#define	SAB_CCR0_SM_MASK	(SAB_CCR0_SM1|SAB_CCR0_SM0)
-#define	SAB_CCR0_SM_DLC		(0)
-#define	SAB_CCR0_SM_DLCLOOP	(SAB_CCR0_SM0)
-#define	SAB_CCR0_SM_BISYNC	(SAB_CCR0_SM1)
-#define	SAB_CCR0_SM_ASYNC	(SAB_CCR0_SM1|SAB_CCR0_SM0)
-
-/* SAB_CCR1: channel configuration register 1 */
-#define	SAB_CCR1_ODS	0x10	/* Output driver select:1:pushpull,0:odrain */
-#define	SAB_CCR1_BCR	0x08	/* bit clock rate: 1:async, 0:isochronous */
-#define	SAB_CCR1_CM2	0x04	/* clock mode 2, see below */
-#define	SAB_CCR1_CM1	0x02	/* clock mode 1, see below */
-#define	SAB_CCR1_CM0	0x01	/* clock mode 0, see below */
-
-#define	SAB_CCR1_CM_MASK	(SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)
-#define	SAB_CCR1_CM_7		(SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)
-
-/* SAB_CCR2: channel configuration register 2, depends on clock mode above */
-/* clock mode 0a, 1, 4, 5 */
-#define	SAB_CCR2_SOC1	0x80	/* special output 1, below */
-#define	SAB_CCR2_SOC0	0x40	/* special output 0, below */
-#define	SAB_CCR2_SOC_MASK	(SAB_CCR2_SOC1|SAB_CCR2_SOC0)
-#define	SAB_CCR2_SOC_RTSHIGH	(SAB_CCR2_SOC1)
-#define	SAB_CCR2_SOC_RTSNORM	(0)
-#define	SAB_CCR2_SOC_RTSRX	(SAB_CCR2_SOC1|SAB_CCR2_SOC0)
-/* clock mode 0b, 2, 3, 6, 7 */
-#define	SAB_CCR2_BR9	0x80	/* baud rate bit 9 */
-#define	SAB_CCR2_BR8	0x40	/* baud rate bit 8 */
-#define	SAB_CCR2_BDF	0x20	/* baud rate division factor: 0:1: 1:BRG */
-#define	SAB_CCR2_SSEL	0x10	/* clock source select */
-/* clock mode 5 */
-#define	SAB_CCR2_XCS0	0x20	/* tx clock shift, bit 0 */
-#define	SAB_CCR2_RCS0	0x10	/* rx clock shift, bit 0 */
-/* clock mode 0b, 2, 3, 4, 5, 6, 7 */
-#define	SAB_CCR2_TOE	0x08	/* tx clock output enable */
-/* clock mode 0a, 0b, 1, 2, 3, 4, 5, 6, 7 */
-#define	SAB_CCR2_RWX	0x04	/* read/write exchange (dma mode only) */
-#define	SAB_CCR2_DIV	0x01	/* data inversion (nrz) */
-
-/* SAB_CCR3: channel configuration register 3 (v2 or greater) */
-#define	SAB_CCR3_PSD	0x01	/* dpll phase shift disable (nrz/nrzi) */
-
-/* SAB_TSAX: time-slot assignment register transmit (clock mode 5 only) */
-#define	SAB_TSAX_TSNX	0xfc	/* time-slot number transmit */
-#define	SAB_TSAX_XCS2	0x02	/* transmit clock shift bit 2 */
-#define	SAB_TSAX_XCS1	0x01	/* transmit clock shift bit 1 */
-
-/* SAB_TSAR: time-slot assignment register receive (clock mode 5 only) */
-#define	SAB_TSAR_TSNR	0xfc	/* time-slot number receive */
-#define	SAB_TSAR_RCS2	0x02	/* receive clock shift bit 2 */
-#define	SAB_TSAR_RCS1	0x01	/* receive clock shift bit 1 */
-
-/* SAB_VSTR: version status register */
-#define	SAB_VSTR_CD	0x80	/* carrier detect status */
-#define	SAB_VSTR_DPLA	0x40	/* dpll asynchronous */
-#define	SAB_VSTR_VMASK	0x0f	/* chip version mask: */
-#define	SAB_VSTR_V_1	0x00	/*   version 1 */
-#define	SAB_VSTR_V_2	0x01	/*   version 2 */
-#define	SAB_VSTR_V_32	0x02	/*   version 3.2 */
-
-/* SAB_GIS: global interrupt status register */
-#define	SAB_GIS_PI	0x80	/* universal port interrupt */
-#define	SAB_GIS_ISA1	0x08	/* interrupt status a1 */
-#define	SAB_GIS_ISA0	0x04	/* interrupt status a0 */
-#define	SAB_GIS_ISB1	0x02	/* interrupt status b1 */
-#define	SAB_GIS_ISB0	0x01	/* interrupt status b0 */
-
-/* SAB_IVA: interrupt vector address */
-#define	SAB_IVA_MASK	0xf8	/* interrupt vector address mask */
-
-/* SAB_IPC: interrupt port configuration */
-#define	SAB_IPC_VIS	0x80	/* masked interrupt bits visible */
-#define	SAB_IPC_SLAMASK	0x18	/* slave address mask */
-#define	SAB_IPC_CASM	0x04	/* cascading mode */
-#define	SAB_IPC_ICMASK	0x03	/* port config mask: */
-#define	SAB_IPC_ICOD	0x00	/*   open drain output */
-#define	SAB_IPC_ICPL	0x01	/*   push/pull active low output */
-#define	SAB_IPC_ICPH	0x03	/*   push/pull active high output */
-
-/* SAB_ISR0: interrupt status 0 */
-#define	SAB_ISR0_TCD	0x80	/* termination character detected */
-#define	SAB_ISR0_TIME	0x40	/* time-out limit exceeded */
-#define	SAB_ISR0_PERR	0x20	/* parity error */
-#define	SAB_ISR0_FERR	0x10	/* framing error */
-#define	SAB_ISR0_PLLA	0x08	/* dpll asynchronous */
-#define	SAB_ISR0_CDSC	0x04	/* carrier detect status change */
-#define	SAB_ISR0_RFO	0x02	/* rfifo overflow */
-#define	SAB_ISR0_RPF	0x01	/* receive pool full */
-
-/* SAB_ISR1: interrupt status 1 */
-#define	SAB_ISR1_BRK	0x80	/* break detected */
-#define	SAB_ISR1_BRKT	0x40	/* break terminated */
-#define	SAB_ISR1_ALLS	0x20	/* all sent */
-#define	SAB_ISR1_XOFF	0x10	/* xoff detected */
-#define	SAB_ISR1_TIN	0x08	/* timer interrupt */
-#define	SAB_ISR1_CSC	0x04	/* clear to send status change */
-#define	SAB_ISR1_XON	0x02	/* xon detected */
-#define	SAB_ISR1_XPR	0x01	/* transmit pool ready */
-
-/* SAB_IMR0: interrupt mask 0 */
-#define	SAB_IMR0_TCD	0x80	/* termination character detected */
-#define	SAB_IMR0_TIME	0x40	/* time-out limit exceeded */
-#define	SAB_IMR0_PERR	0x20	/* parity error */
-#define	SAB_IMR0_FERR	0x10	/* framing error */
-#define	SAB_IMR0_PLLA	0x08	/* dpll asynchronous */
-#define	SAB_IMR0_CDSC	0x04	/* carrier detect status change */
-#define	SAB_IMR0_RFO	0x02	/* rfifo overflow */
-#define	SAB_IMR0_RPF	0x01	/* receive pool full */
-
-/* SAB_ISR1: interrupt mask 1 */
-#define	SAB_IMR1_BRK	0x80	/* break detected */
-#define	SAB_IMR1_BRKT	0x40	/* break terminated */
-#define	SAB_IMR1_ALLS	0x20	/* all sent */
-#define	SAB_IMR1_XDU	0x10	/* xoff detected */
-#define	SAB_IMR1_TIN	0x08	/* timer interrupt */
-#define	SAB_IMR1_CSC	0x04	/* clear to send status change */
-#define	SAB_IMR1_XMR	0x02	/* xon detected */
-#define	SAB_IMR1_XPR	0x01	/* transmit pool ready */
-
-/* SAB_PVR: port value register */
-#define	SAB_PVR_DSR_A	0x01	/* port A DSR */
-#define	SAB_PVR_DTR_A	0x02	/* port A DTR */
-#define	SAB_PVR_DTR_B	0x04	/* port B DTR */
-#define	SAB_PVR_DSR_B	0x08	/* port B DSR */
-#define	SAB_PVR_MAGIC	0x10	/* dunno... */
-
-/* SAB_CCR4: channel configuration register 4 */
-#define	SAB_CCR4_MCK4	0x80	/* master clock divide by 4 */
-#define	SAB_CCR4_EBRG	0x40	/* enhanced baud rate generator mode */
-#define	SAB_CCR4_TST1	0x20	/* test pin */
-#define	SAB_CCR4_ICD	0x10	/* invert polarity of carrier detect */
-
-/* Receive status byte */
-#define	SAB_RSTAT_PE	0x80	/* parity error */
-#define	SAB_RSTAT_FE	0x40	/* framing error */
-#define	SAB_RSTAT_PAR	0x01	/* parity bit */
-
-#endif /* _DEV_IC_SAB82532_H_ */
diff --git a/sys/dev/scc/scc_bfe.h b/sys/dev/scc/scc_bfe.h
index 0b7f91f83f99..1ccd176e5539 100644
--- a/sys/dev/scc/scc_bfe.h
+++ b/sys/dev/scc/scc_bfe.h
@@ -113,7 +113,6 @@ struct scc_class {
 };
 
 extern struct scc_class scc_quicc_class;
-extern struct scc_class scc_sab82532_class;
 extern struct scc_class scc_z8530_escc_class;
 extern struct scc_class scc_z8530_legacy_class;
 
diff --git a/sys/dev/scc/scc_bus.h b/sys/dev/scc/scc_bus.h
index 47a43db01a65..08fcd2626fa5 100644
--- a/sys/dev/scc/scc_bus.h
+++ b/sys/dev/scc/scc_bus.h
@@ -42,7 +42,7 @@
 #define	SCC_IVAR_HWMTX		5
 
 /* Hardware class -- the SCC type. */
-#define	SCC_CLASS_SAB82532	0
+#define	SCC_CLASS_UNUSED	0
 #define	SCC_CLASS_Z8530		1
 #define	SCC_CLASS_QUICC		2
 
diff --git a/sys/dev/scc/scc_dev_sab82532.c b/sys/dev/scc/scc_dev_sab82532.c
deleted file mode 100644
index 9bf02198552f..000000000000
--- a/sys/dev/scc/scc_dev_sab82532.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2004-2006 Marcel Moolenaar
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/conf.h>
-#include <machine/bus.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/rman.h>
-#include <sys/serial.h>
-
-#include <dev/scc/scc_bfe.h>
-#include <dev/scc/scc_bus.h>
-
-#include <dev/ic/sab82532.h>
-
-#include "scc_if.h"
-
-static int sab82532_bfe_attach(struct scc_softc *, int);
-static int sab82532_bfe_iclear(struct scc_softc *, struct scc_chan *);
-static int sab82532_bfe_ipend(struct scc_softc *);
-static int sab82532_bfe_probe(struct scc_softc *);
-
-static kobj_method_t sab82532_methods[] = {
-	KOBJMETHOD(scc_attach,	sab82532_bfe_attach),
-	KOBJMETHOD(scc_iclear,	sab82532_bfe_iclear),
-	KOBJMETHOD(scc_ipend,	sab82532_bfe_ipend),
-	KOBJMETHOD(scc_probe,	sab82532_bfe_probe),
-	KOBJMETHOD_END
-};
-
-struct scc_class scc_sab82532_class = {
-	"sab82532 class",
-	sab82532_methods,
-	sizeof(struct scc_softc),
-	.cl_channels = SAB_NCHAN,
-	.cl_class = SCC_CLASS_SAB82532,
-	.cl_modes = SCC_MODE_ASYNC | SCC_MODE_BISYNC | SCC_MODE_HDLC,
-	.cl_range = SAB_CHANLEN,
-};
-
-static int
-sab82532_bfe_attach(struct scc_softc *sc __unused, int reset __unused)
-{
-
-	return (0);
-}
-
-static int
-sab82532_bfe_iclear(struct scc_softc *sc, struct scc_chan *ch)
-{
-	struct scc_bas *bas;
-	int i, ofs, rbcl;
-
-	bas = &sc->sc_bas;
-	ofs = (ch->ch_nr - 1) * SAB_CHANLEN;
-	mtx_lock_spin(&sc->sc_hwmtx);
-	if (ch->ch_ipend & SER_INT_RXREADY) {
-		if (scc_getreg(bas, ofs + SAB_STAR) & SAB_STAR_RFNE) {
-			rbcl = scc_getreg(bas, ofs + SAB_RBCL) & 31;
-			if (rbcl == 0)
-				rbcl = 32;
-			for (i = 0; i < rbcl; i += 2) {
-				(void)scc_getreg(bas, ofs + SAB_RFIFO);
-				(void)scc_getreg(bas, ofs + SAB_RFIFO + 1);
-			}
-		}
-		while (scc_getreg(bas, ofs + SAB_STAR) & SAB_STAR_CEC)
-			;
-		scc_setreg(bas, ofs + SAB_CMDR, SAB_CMDR_RMC);
-		scc_barrier(bas);
-	}
-	mtx_unlock_spin(&sc->sc_hwmtx);
-	return (0);
-}
-
-static int
-sab82532_bfe_ipend(struct scc_softc *sc)
-{
-	struct scc_bas *bas;
-	struct scc_chan *ch;
-	int ipend;
-	int c, ofs;
-	uint8_t isr0, isr1;
-
-	bas = &sc->sc_bas;
-	ipend = 0;
-	for (c = 0; c < SAB_NCHAN; c++) {
-		ch = &sc->sc_chan[c];
-		ofs = c * SAB_CHANLEN;
-		mtx_lock_spin(&sc->sc_hwmtx);
-		isr0 = scc_getreg(bas, ofs + SAB_ISR0);
-		isr1 = scc_getreg(bas, ofs + SAB_ISR1);
-		scc_barrier(bas);
-		if (isr0 & SAB_ISR0_TIME) {
-			while (scc_getreg(bas, ofs + SAB_STAR) & SAB_STAR_CEC)
-				;
-			scc_setreg(bas, ofs + SAB_CMDR, SAB_CMDR_RFRD);
-			scc_barrier(bas);
-		}
-		mtx_unlock_spin(&sc->sc_hwmtx);
-
-		ch->ch_ipend = 0;
-		if (isr1 & SAB_ISR1_BRKT)
-			ch->ch_ipend |= SER_INT_BREAK;
-		if (isr0 & SAB_ISR0_RFO)
-			ch->ch_ipend |= SER_INT_OVERRUN;
-		if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
-			ch->ch_ipend |= SER_INT_RXREADY;
-		if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
-			ch->ch_ipend |= SER_INT_SIGCHG;
-		if (isr1 & SAB_ISR1_ALLS)
-			ch->ch_ipend |= SER_INT_TXIDLE;
-		ipend |= ch->ch_ipend;
-	}
-	return (ipend);
-}
-
-static int
-sab82532_bfe_probe(struct scc_softc *sc __unused)
-{
-
-	return (0);
-}
diff --git a/sys/dev/uart/uart.h b/sys/dev/uart/uart.h
index 4ef6af3d901b..ed3b7017d746 100644
--- a/sys/dev/uart/uart.h
+++ b/sys/dev/uart/uart.h
@@ -104,7 +104,6 @@ struct uart_class;
 extern struct uart_class uart_ns8250_class __attribute__((weak));
 extern struct uart_class uart_quicc_class __attribute__((weak));
 extern struct uart_class uart_s3c2410_class __attribute__((weak));
-extern struct uart_class uart_sab82532_class __attribute__((weak));
 extern struct uart_class uart_sbbc_class __attribute__((weak));
 extern struct uart_class uart_z8530_class __attribute__((weak));
 
diff --git a/sys/dev/uart/uart_bus_scc.c b/sys/dev/uart/uart_bus_scc.c
index 6666a35e272e..3b643524825e 100644
--- a/sys/dev/uart/uart_bus_scc.c
+++ b/sys/dev/uart/uart_bus_scc.c
@@ -100,9 +100,6 @@ uart_scc_probe(device_t dev)
 	case SCC_CLASS_QUICC:
 		sc->sc_class = &uart_quicc_class;
 		break;
-	case SCC_CLASS_SAB82532:
-		sc->sc_class = &uart_sab82532_class;
-		break;
 	case SCC_CLASS_Z8530:
 		sc->sc_class = &uart_z8530_class;
 		break;
diff --git a/sys/dev/uart/uart_dev_sab82532.c b/sys/dev/uart/uart_dev_sab82532.c
deleted file mode 100644
index 9cf41be5d7ab..000000000000
--- a/sys/dev/uart/uart_dev_sab82532.c
+++ /dev/null
@@ -1,762 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2003 Marcel Moolenaar
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/conf.h>
-#include <machine/bus.h>
-
-#include <dev/uart/uart.h>
-#include <dev/uart/uart_cpu.h>
-#include <dev/uart/uart_bus.h>
-
-#include <dev/ic/sab82532.h>
-
-#include "uart_if.h"
-
-#define	DEFAULT_RCLK	29491200
-
-/*
- * NOTE: To allow us to read the baudrate divisor from the chip, we
- * copy the value written to the write-only BGR register to an unused
- * read-write register. We use TCR for that.
- */
-
-static int
-sab82532_delay(struct uart_bas *bas)
-{
-	int divisor, m, n;
-	uint8_t bgr, ccr2;
-
-	bgr = uart_getreg(bas, SAB_TCR);
-	ccr2 = uart_getreg(bas, SAB_CCR2);
-	n = (bgr & 0x3f) + 1;
-	m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
-	divisor = n * (1<<m);
-
-	/* 1/10th the time to transmit 1 character (estimate). */
-	return (16000000 * divisor / bas->rclk);
-}
-
-static int
-sab82532_divisor(int rclk, int baudrate)
-{
-	int act_baud, act_div, divisor;
-	int error, m, n;
-
-	if (baudrate == 0)
-		return (0);
-
-	divisor = (rclk / (baudrate << 3) + 1) >> 1;
-	if (divisor < 2 || divisor >= 1048576)
-		return (0);
-
-	/* Find the best (N+1,M) pair. */
-	for (m = 1; m < 15; m++) {
-		n = divisor / (1<<m);
-		if (n < 1 || n > 63)
-			continue;
-		act_div = n * (1<<m);
-		act_baud = rclk / (act_div << 4);
-
-		/* 10 times error in percent: */
-		error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
-
-		/* 3.0% maximum error tolerance: */
-		if (error < -30 || error > 30)
-			continue;
-
-		/* Got it. */
-		return ((n - 1) | (m << 6));
-	}
-
-	return (0);
-}
-
-static void
-sab82532_flush(struct uart_bas *bas, int what)
-{
-
-	if (what & UART_FLUSH_TRANSMITTER) {
-		while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
-			;
-		uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
-		uart_barrier(bas);
-	}
-	if (what & UART_FLUSH_RECEIVER) {
-		while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
-			;
-		uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
-		uart_barrier(bas);
-	}
-}
-
-static int
-sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
-    int parity)
-{
-	int divisor;
-	uint8_t ccr2, dafo;
-
-	if (databits >= 8)
-		dafo = SAB_DAFO_CHL_CS8;
-	else if (databits == 7)
-		dafo = SAB_DAFO_CHL_CS7;
-	else if (databits == 6)
-		dafo = SAB_DAFO_CHL_CS6;
-	else
-		dafo = SAB_DAFO_CHL_CS5;
-	if (stopbits > 1)
-		dafo |= SAB_DAFO_STOP;
-	switch (parity) {
-	case UART_PARITY_EVEN:	dafo |= SAB_DAFO_PAR_EVEN; break;
-	case UART_PARITY_MARK:	dafo |= SAB_DAFO_PAR_MARK; break;
-	case UART_PARITY_NONE:	dafo |= SAB_DAFO_PAR_NONE; break;
-	case UART_PARITY_ODD:	dafo |= SAB_DAFO_PAR_ODD; break;
-	case UART_PARITY_SPACE:	dafo |= SAB_DAFO_PAR_SPACE; break;
-	default:		return (EINVAL);
-	}
-
-	/* Set baudrate. */
-	if (baudrate > 0) {
-		divisor = sab82532_divisor(bas->rclk, baudrate);
-		if (divisor == 0)
-			return (EINVAL);
-		uart_setreg(bas, SAB_BGR, divisor & 0xff);
-		uart_barrier(bas);
-		/* Allow reading the (n-1,m) tuple from the chip. */
-		uart_setreg(bas, SAB_TCR, divisor & 0xff);
-		uart_barrier(bas);
-		ccr2 = uart_getreg(bas, SAB_CCR2);
-		ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
-		ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
-		uart_setreg(bas, SAB_CCR2, ccr2);
-		uart_barrier(bas);
-	}
-
-	uart_setreg(bas, SAB_DAFO, dafo);
-	uart_barrier(bas);
-	return (0);
-}
-
-/*
- * Low-level UART interface.
- */
-static int sab82532_probe(struct uart_bas *bas);
-static void sab82532_init(struct uart_bas *bas, int, int, int, int);
-static void sab82532_term(struct uart_bas *bas);
-static void sab82532_putc(struct uart_bas *bas, int);
-static int sab82532_rxready(struct uart_bas *bas);
-static int sab82532_getc(struct uart_bas *bas, struct mtx *);
-
-static struct uart_ops uart_sab82532_ops = {
-	.probe = sab82532_probe,
-	.init = sab82532_init,
-	.term = sab82532_term,
-	.putc = sab82532_putc,
-	.rxready = sab82532_rxready,
-	.getc = sab82532_getc,
-};
-
-static int
-sab82532_probe(struct uart_bas *bas)
-{
-
-	return (0);
-}
-
-static void
-sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
-    int parity)
-{
-	uint8_t ccr0, pvr;
-
-	if (bas->rclk == 0)
-		bas->rclk = DEFAULT_RCLK;
-
-	/*
-	 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
-	 * Pin 4 is magical, meaning that I don't know what it does, but
-	 * it too has to be set to output.
-	 */
-	uart_setreg(bas, SAB_PCR,
-	    ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
-	uart_barrier(bas);
-	/* Disable port interrupts. */
-	uart_setreg(bas, SAB_PIM, 0xff);
-	uart_barrier(bas);
-	/* Interrupts are active low. */
-	uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
-	uart_barrier(bas);
-	/* Set DTR. */
-	pvr = uart_getreg(bas, SAB_PVR);
-	switch (bas->chan) {
-	case 1:
-		pvr &= ~SAB_PVR_DTR_A;
-		break;
-	case 2:
-		pvr &= ~SAB_PVR_DTR_B;
-		break;
-	}
-	uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
-	uart_barrier(bas);
-
-	/* power down */
-	uart_setreg(bas, SAB_CCR0, 0);
-	uart_barrier(bas);
-
-	/* set basic configuration */
-	ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
-	uart_setreg(bas, SAB_CCR0, ccr0);
-	uart_barrier(bas);
-	uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
-	uart_barrier(bas);
-	uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
-	uart_barrier(bas);
-	uart_setreg(bas, SAB_CCR3, 0);
-	uart_barrier(bas);
-	uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
-	uart_barrier(bas);
-	uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
-	uart_barrier(bas);
-	uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
-	    SAB_RFC_RFTH_32CHAR);
-	uart_barrier(bas);
-
-	sab82532_param(bas, baudrate, databits, stopbits, parity);
-
-	/* Clear interrupts. */
-	uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
-	uart_setreg(bas, SAB_IMR1, 0xff);
-	uart_barrier(bas);
-	uart_getreg(bas, SAB_ISR0);
-	uart_getreg(bas, SAB_ISR1);
-	uart_barrier(bas);
-
-	sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
-
-	/* Power up. */
-	uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
-	uart_barrier(bas);
-}
-
-static void
-sab82532_term(struct uart_bas *bas)
-{
-	uint8_t pvr;
-
-	pvr = uart_getreg(bas, SAB_PVR);
-	switch (bas->chan) {
-	case 1:
-		pvr |= SAB_PVR_DTR_A;
-		break;
-	case 2:
-		pvr |= SAB_PVR_DTR_B;
-		break;
-	}
-	uart_setreg(bas, SAB_PVR, pvr);
-	uart_barrier(bas);
-}
-
-static void
-sab82532_putc(struct uart_bas *bas, int c)
-{
-	int delay, limit;
-
-	/* 1/10th the time to transmit 1 character (estimate). */
-	delay = sab82532_delay(bas);
-
-	limit = 20;
-	while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
-		DELAY(delay);
-	uart_setreg(bas, SAB_TIC, c);
-	limit = 20;
-	while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
-		DELAY(delay);
-}
-
-static int
-sab82532_rxready(struct uart_bas *bas)
-{
-
-	return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0);
-}
-
-static int
-sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx)
-{
-	int c, delay;
-
-	uart_lock(hwmtx);
-
-	/* 1/10th the time to transmit 1 character (estimate). */
-	delay = sab82532_delay(bas);
-
-	while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) {
-		uart_unlock(hwmtx);
-		DELAY(delay);
-		uart_lock(hwmtx);
-	}
-
-	while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
-		;
-	uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
-	uart_barrier(bas);
-
-	while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
-		DELAY(delay);
-
-	c = uart_getreg(bas, SAB_RFIFO);
-	uart_barrier(bas);
-
-	/* Blow away everything left in the FIFO... */
-	while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
-		;
-	uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
-	uart_barrier(bas);
-
-	uart_unlock(hwmtx);
-
-	return (c);
-}
-
-/*
- * High-level UART interface.
- */
-struct sab82532_softc {
-	struct uart_softc base;
-};
-
-static int sab82532_bus_attach(struct uart_softc *);
-static int sab82532_bus_detach(struct uart_softc *);
-static int sab82532_bus_flush(struct uart_softc *, int);
-static int sab82532_bus_getsig(struct uart_softc *);
-static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
-static int sab82532_bus_ipend(struct uart_softc *);
-static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
-static int sab82532_bus_probe(struct uart_softc *);
-static int sab82532_bus_receive(struct uart_softc *);
-static int sab82532_bus_setsig(struct uart_softc *, int);
-static int sab82532_bus_transmit(struct uart_softc *);
-static void sab82532_bus_grab(struct uart_softc *);
-static void sab82532_bus_ungrab(struct uart_softc *);
-
-static kobj_method_t sab82532_methods[] = {
-	KOBJMETHOD(uart_attach,		sab82532_bus_attach),
-	KOBJMETHOD(uart_detach,		sab82532_bus_detach),
-	KOBJMETHOD(uart_flush,		sab82532_bus_flush),
-	KOBJMETHOD(uart_getsig,		sab82532_bus_getsig),
-	KOBJMETHOD(uart_ioctl,		sab82532_bus_ioctl),
-	KOBJMETHOD(uart_ipend,		sab82532_bus_ipend),
-	KOBJMETHOD(uart_param,		sab82532_bus_param),
-	KOBJMETHOD(uart_probe,		sab82532_bus_probe),
-	KOBJMETHOD(uart_receive,	sab82532_bus_receive),
-	KOBJMETHOD(uart_setsig,		sab82532_bus_setsig),
-	KOBJMETHOD(uart_transmit,	sab82532_bus_transmit),
-	KOBJMETHOD(uart_grab,		sab82532_bus_grab),
-	KOBJMETHOD(uart_ungrab,		sab82532_bus_ungrab),
-	{ 0, 0 }
-};
-
-struct uart_class uart_sab82532_class = {
-	"sab82532",
-	sab82532_methods,
-	sizeof(struct sab82532_softc),
-	.uc_ops = &uart_sab82532_ops,
-	.uc_range = 64,
-	.uc_rclk = DEFAULT_RCLK,
-	.uc_rshift = 0
-};
-
-#define	SIGCHG(c, i, s, d)				\
-	if (c) {					\
-		i |= (i & s) ? s : s | d;		\
-	} else {					\
-		i = (i & s) ? (i & ~s) | d : i;		\
-	}
-
-static int
-sab82532_bus_attach(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-	uint8_t imr0, imr1;
-
-	bas = &sc->sc_bas;
-	if (sc->sc_sysdev == NULL)
-		sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
-
-	imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
-	    SAB_IMR0_RPF;
-	uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
-	imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
-	uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
-	uart_barrier(bas);
-
-	if (sc->sc_sysdev == NULL)
-		sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
-	(void)sab82532_bus_getsig(sc);
-	return (0);
-}
-
-static int
-sab82532_bus_detach(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-
-	bas = &sc->sc_bas;
-	uart_setreg(bas, SAB_IMR0, 0xff);
-	uart_setreg(bas, SAB_IMR1, 0xff);
-	uart_barrier(bas);
-	uart_getreg(bas, SAB_ISR0);
-	uart_getreg(bas, SAB_ISR1);
-	uart_barrier(bas);
-	uart_setreg(bas, SAB_CCR0, 0);
-	uart_barrier(bas);
-	return (0);
-}
-
-static int
-sab82532_bus_flush(struct uart_softc *sc, int what)
-{
-
-	uart_lock(sc->sc_hwmtx);
-	sab82532_flush(&sc->sc_bas, what);
-	uart_unlock(sc->sc_hwmtx);
-	return (0);
-}
-
-static int
-sab82532_bus_getsig(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-	uint32_t new, old, sig;
-	uint8_t pvr, star, vstr;
-
-	bas = &sc->sc_bas;
-	do {
-		old = sc->sc_hwsig;
-		sig = old;
-		uart_lock(sc->sc_hwmtx);
-		star = uart_getreg(bas, SAB_STAR);
-		SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
-		vstr = uart_getreg(bas, SAB_VSTR);
-		SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
-		pvr = ~uart_getreg(bas, SAB_PVR);
-		switch (bas->chan) {
-		case 1:
-			pvr &= SAB_PVR_DSR_A;
-			break;
-		case 2:
-			pvr &= SAB_PVR_DSR_B;
-			break;
-		}
-		SIGCHG(pvr, sig, SER_DSR, SER_DDSR);
-		uart_unlock(sc->sc_hwmtx);
-		new = sig & ~SER_MASK_DELTA;
-	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
-	return (sig);
-}
-
-static int
-sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
-{
-	struct uart_bas *bas;
-	uint8_t dafo, mode;
-	int error;
-
-	bas = &sc->sc_bas;
-	error = 0;
-	uart_lock(sc->sc_hwmtx);
-	switch (request) {
-	case UART_IOCTL_BREAK:
-		dafo = uart_getreg(bas, SAB_DAFO);
-		if (data)
-			dafo |= SAB_DAFO_XBRK;
-		else
-			dafo &= ~SAB_DAFO_XBRK;
-		uart_setreg(bas, SAB_DAFO, dafo);
-		uart_barrier(bas);
-		break;
-	case UART_IOCTL_IFLOW:
-		mode = uart_getreg(bas, SAB_MODE);
-		if (data) {
-			mode &= ~SAB_MODE_RTS;
-			mode |= SAB_MODE_FRTS;
-		} else {
-			mode |= SAB_MODE_RTS;
-			mode &= ~SAB_MODE_FRTS;
-		}
-		uart_setreg(bas, SAB_MODE, mode);
-		uart_barrier(bas);
-		break;
-	case UART_IOCTL_OFLOW:
-		mode = uart_getreg(bas, SAB_MODE);
-		if (data)
-			mode &= ~SAB_MODE_FCTS;
-		else
-			mode |= SAB_MODE_FCTS;
-		uart_setreg(bas, SAB_MODE, mode);
-		uart_barrier(bas);
-		break;
-	default:
-		error = EINVAL;
-		break;
-	}
-	uart_unlock(sc->sc_hwmtx);
-	return (error);
-}
-
-static int
-sab82532_bus_ipend(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-	int ipend;
-	uint8_t isr0, isr1;
-
-	bas = &sc->sc_bas;
-	uart_lock(sc->sc_hwmtx);
-	isr0 = uart_getreg(bas, SAB_ISR0);
-	isr1 = uart_getreg(bas, SAB_ISR1);
-	uart_barrier(bas);
-	if (isr0 & SAB_ISR0_TIME) {
-		while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
-			;
-		uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
-		uart_barrier(bas);
-	}
-	uart_unlock(sc->sc_hwmtx);
-
-	ipend = 0;
-	if (isr1 & SAB_ISR1_BRKT)
-		ipend |= SER_INT_BREAK;
-	if (isr0 & SAB_ISR0_RFO)
-		ipend |= SER_INT_OVERRUN;
-	if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
-		ipend |= SER_INT_RXREADY;
-	if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
-		ipend |= SER_INT_SIGCHG;
-	if (isr1 & SAB_ISR1_ALLS)
-		ipend |= SER_INT_TXIDLE;
-
-	return (ipend);
-}
-
-static int
-sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
-    int stopbits, int parity)
-{
-	struct uart_bas *bas;
-	int error;
-
-	bas = &sc->sc_bas;
-	uart_lock(sc->sc_hwmtx);
-	error = sab82532_param(bas, baudrate, databits, stopbits, parity);
-	uart_unlock(sc->sc_hwmtx);
-	return (error);
-}
-
-static int
-sab82532_bus_probe(struct uart_softc *sc)
-{
-	char buf[80];
-	const char *vstr;
-	int error;
-	char ch;
-
-	error = sab82532_probe(&sc->sc_bas);
-	if (error)
-		return (error);
-
-	sc->sc_rxfifosz = 32;
-	sc->sc_txfifosz = 32;
-
-	ch = sc->sc_bas.chan - 1 + 'A';
-
-	switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
-	case SAB_VSTR_V_1:
-		vstr = "v1";
-		break;
-	case SAB_VSTR_V_2:
-		vstr = "v2";
-		break;
-	case SAB_VSTR_V_32:
-		vstr = "v3.2";
-		sc->sc_hwiflow = 0;	/* CTS doesn't work with RFC:RFDF. */
-		sc->sc_hwoflow = 1;
-		break;
-	default:
-		vstr = "v4?";
-		break;
-	}
-
-	snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
-	device_set_desc_copy(sc->sc_dev, buf);
-	return (0);
-}
-
-static int
-sab82532_bus_receive(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-	int i, rbcl, xc;
-	uint8_t s;
-
-	bas = &sc->sc_bas;
-	uart_lock(sc->sc_hwmtx);
-	if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
-		rbcl = uart_getreg(bas, SAB_RBCL) & 31;
-		if (rbcl == 0)
-			rbcl = 32;
-		for (i = 0; i < rbcl; i += 2) {
-			if (uart_rx_full(sc)) {
-				sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
-				break;
-			}
-			xc = uart_getreg(bas, SAB_RFIFO);
-			s = uart_getreg(bas, SAB_RFIFO + 1);
-			if (s & SAB_RSTAT_FE)
-				xc |= UART_STAT_FRAMERR;
-			if (s & SAB_RSTAT_PE)
-				xc |= UART_STAT_PARERR;
-			uart_rx_put(sc, xc);
-		}
-	}
-
-	while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
-		;
-	uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
-	uart_barrier(bas);
-	uart_unlock(sc->sc_hwmtx);
-	return (0);
-}
-
-static int
-sab82532_bus_setsig(struct uart_softc *sc, int sig)
-{
-	struct uart_bas *bas;
-	uint32_t new, old;
-	uint8_t mode, pvr;
-
-	bas = &sc->sc_bas;
-	do {
-		old = sc->sc_hwsig;
-		new = old;
-		if (sig & SER_DDTR) {
-			SIGCHG(sig & SER_DTR, new, SER_DTR,
-			    SER_DDTR);
-		}
-		if (sig & SER_DRTS) {
-			SIGCHG(sig & SER_RTS, new, SER_RTS,
-			    SER_DRTS);
-		}
-	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
-
-	uart_lock(sc->sc_hwmtx);
-	/* Set DTR pin. */
-	pvr = uart_getreg(bas, SAB_PVR);
-	switch (bas->chan) {
-	case 1:
-		if (new & SER_DTR)
-			pvr &= ~SAB_PVR_DTR_A;
-		else
-			pvr |= SAB_PVR_DTR_A;
-		break;
-	case 2:
-		if (new & SER_DTR)
-			pvr &= ~SAB_PVR_DTR_B;
-		else
-			pvr |= SAB_PVR_DTR_B;
-		break;
-	}
-	uart_setreg(bas, SAB_PVR, pvr);
-
-	/* Set RTS pin. */
-	mode = uart_getreg(bas, SAB_MODE);
-	if (new & SER_RTS)
-		mode &= ~SAB_MODE_FRTS;
-	else
-		mode |= SAB_MODE_FRTS;
-	uart_setreg(bas, SAB_MODE, mode);
-	uart_barrier(bas);
-	uart_unlock(sc->sc_hwmtx);
-	return (0);
-}
-
-static int
-sab82532_bus_transmit(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-	int i;
-
-	bas = &sc->sc_bas;
-	uart_lock(sc->sc_hwmtx);
-	while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
-		;
-	for (i = 0; i < sc->sc_txdatasz; i++)
-		uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
-	uart_barrier(bas);
-	while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
-		;
-	uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
-	sc->sc_txbusy = 1;
-	uart_unlock(sc->sc_hwmtx);
-	return (0);
-}
-
-static void
-sab82532_bus_grab(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-	uint8_t imr0;
-
-	bas = &sc->sc_bas;
-	imr0 = SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO; /* No TCD or RPF */
-	uart_lock(sc->sc_hwmtx);
-	uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
-	uart_barrier(bas);
-	uart_unlock(sc->sc_hwmtx);
-}
-
-static void
-sab82532_bus_ungrab(struct uart_softc *sc)
-{
-	struct uart_bas *bas;
-	uint8_t imr0;
-
-	bas = &sc->sc_bas;
-	imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
-	    SAB_IMR0_RPF;
-	uart_lock(sc->sc_hwmtx);
-	uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
-	uart_barrier(bas);
-	uart_unlock(sc->sc_hwmtx);
-}
diff --git a/sys/dev/uart/uart_subr.c b/sys/dev/uart/uart_subr.c
index 2dd10d9f4a2d..96d7735ea0ed 100644
--- a/sys/dev/uart/uart_subr.c
+++ b/sys/dev/uart/uart_subr.c
@@ -53,7 +53,6 @@ __FBSDID("$FreeBSD$");
 
 static struct uart_class *uart_classes[] = {
 	&uart_ns8250_class,
-	&uart_sab82532_class,
 	&uart_z8530_class,
 #if defined(__arm__)
 	&uart_s3c2410_class,
diff --git a/sys/modules/scc/Makefile b/sys/modules/scc/Makefile
index d138bcd3c8f2..7d5efd33d515 100644
--- a/sys/modules/scc/Makefile
+++ b/sys/modules/scc/Makefile
@@ -8,7 +8,7 @@ scc_bfe= scc_bfe_macio.c scc_bfe_quicc.c scc_dev_quicc.c
 
 KMOD=	scc
 SRCS=	${scc_bfe} scc_core.c scc_if.c scc_if.h \
-	scc_dev_sab82532.c scc_dev_z8530.c
+	scc_dev_z8530.c
 SRCS+=	bus_if.h device_if.h ofw_bus_if.h serdev_if.c serdev_if.h
 
 .include <bsd.kmod.mk>
diff --git a/sys/modules/uart/Makefile b/sys/modules/uart/Makefile
index 5832f4c1696d..821fff46763e 100644
--- a/sys/modules/uart/Makefile
+++ b/sys/modules/uart/Makefile
@@ -32,7 +32,7 @@ SRCS=	${uart_bus_acpi} uart_bus_isa.c uart_bus_pccard.c \
 	uart_bus_pci.c uart_bus_puc.c uart_bus_scc.c \
 	uart_core.c ${uart_cpu_acpi} ${uart_cpu_machine} uart_dbg.c \
 	${uart_dev_mvebu} uart_dev_ns8250.c ${uart_dev_mu} \
-	uart_dev_quicc.c uart_dev_sab82532.c uart_dev_z8530.c \
+	uart_dev_quicc.c uart_dev_z8530.c \
 	uart_if.c uart_if.h uart_subr.c uart_tty.c
 
 SRCS+=	acpi_if.h bus_if.h card_if.h device_if.h isa_if.h ${ofw_bus_if} \