dtrace: add register bindings for RISC-V

Reviewed by:	mhorne, markj
MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D39611

(cherry picked from commit 1fef7abdc76bd6f0c93775bd0c1b62b523abd20d)

4 files changed, 137 insertions, 5 deletions

diff --git a/cddl/lib/libdtrace/Makefile b/cddl/lib/libdtrace/Makefile
index 3fb0ec0bafb0..71b6e8c5d57d 100644
--- a/cddl/lib/libdtrace/Makefile
+++ b/cddl/lib/libdtrace/Makefile
@@ -131,6 +131,7 @@ DSRCS+=		regs_x86.d
 
 .if ${MACHINE_CPUARCH} == "riscv"
 SRCS+=		instr_size.c
+DSRCS+=		regs_riscv.d
 .endif
 
 YFLAGS+=-d
diff --git a/cddl/lib/libdtrace/regs_riscv.d b/cddl/lib/libdtrace/regs_riscv.d
new file mode 100644
index 000000000000..e8a9667d2efd
--- /dev/null
+++ b/cddl/lib/libdtrace/regs_riscv.d
@@ -0,0 +1,74 @@
+/*
+ * SPDX-License-Identifier: CDDL 1.0
+ *
+ * Copyright 2023 Christos Margiolis <christos@FreeBSD.org>
+ */
+
+inline int R_ZERO = 0;
+#pragma D binding "1.13" R_ZERO
+inline int R_RA = 1;
+#pragma D binding "1.13" R_RA
+inline int R_SP = 2;
+#pragma D binding "1.13" R_SP
+inline int R_GP = 3;
+#pragma D binding "1.13" R_GP
+inline int R_TP = 4;
+#pragma D binding "1.13" R_TP
+inline int R_T0 = 5;
+#pragma D binding "1.13" R_T0
+inline int R_T1 = 6;
+#pragma D binding "1.13" R_T1
+inline int R_T2 = 7;
+#pragma D binding "1.13" R_T2
+inline int R_S0 = 8;
+#pragma D binding "1.13" R_S0
+inline int R_FP = 8;
+#pragma D binding "1.13" R_FP
+inline int R_S1 = 9;
+#pragma D binding "1.13" R_S1
+inline int R_A0 = 10;
+#pragma D binding "1.13" R_A0
+inline int R_A1 = 11;
+#pragma D binding "1.13" R_A1
+inline int R_A2 = 12;
+#pragma D binding "1.13" R_A2
+inline int R_A3 = 13;
+#pragma D binding "1.13" R_A3
+inline int R_A4 = 14;
+#pragma D binding "1.13" R_A4
+inline int R_A5 = 15;
+#pragma D binding "1.13" R_A5
+inline int R_A6 = 16;
+#pragma D binding "1.13" R_A6
+inline int R_A7 = 17;
+#pragma D binding "1.13" R_A7
+inline int R_S2 = 18;
+#pragma D binding "1.13" R_S2
+inline int R_S3 = 19;
+#pragma D binding "1.13" R_S3
+inline int R_S4 = 20;
+#pragma D binding "1.13" R_S4
+inline int R_S5 = 21;
+#pragma D binding "1.13" R_S5
+inline int R_S6 = 22;
+#pragma D binding "1.13" R_S6
+inline int R_S7 = 23;
+#pragma D binding "1.13" R_S7
+inline int R_S8 = 24;
+#pragma D binding "1.13" R_S8
+inline int R_S9 = 25;
+#pragma D binding "1.13" R_S9
+inline int R_S10 = 26;
+#pragma D binding "1.13" R_S10
+inline int R_S11 = 27;
+#pragma D binding "1.13" R_S11
+inline int R_T3 = 28;
+#pragma D binding "1.13" R_T3
+inline int R_T4 = 29;
+#pragma D binding "1.13" R_T4
+inline int R_T5 = 30;
+#pragma D binding "1.13" R_T5
+inline int R_T6 = 31;
+#pragma D binding "1.13" R_T6
+inline int R_PC = 32;
+#pragma D binding "1.13" R_PC
diff --git a/sys/cddl/dev/dtrace/riscv/dtrace_isa.c b/sys/cddl/dev/dtrace/riscv/dtrace_isa.c
index 6e6459a8ce74..61743c42d9b7 100644
--- a/sys/cddl/dev/dtrace/riscv/dtrace_isa.c
+++ b/sys/cddl/dev/dtrace/riscv/dtrace_isa.c
@@ -311,10 +311,34 @@ dtrace_getstackdepth(int aframes)
 ulong_t
 dtrace_getreg(struct trapframe *rp, uint_t reg)
 {
-
-	printf("IMPLEMENT ME: %s\n", __func__);
-
-	return (0);
+	switch (reg) {
+	case REG_ZERO:
+		return (0);
+	case REG_RA:
+		return (rp->tf_ra);
+	case REG_SP:
+		return (rp->tf_sp);
+	case REG_GP:
+		return (rp->tf_gp);
+	case REG_TP:
+		return (rp->tf_tp);
+	case REG_T0 ... REG_T2:
+		return (rp->tf_t[reg - REG_T0]);
+	case REG_S0 ... REG_S1:
+		return (rp->tf_s[reg - REG_S0]);
+	case REG_A0 ... REG_A7:
+		return (rp->tf_a[reg - REG_A0]);
+	case REG_S2 ... REG_S11:
+		return (rp->tf_s[reg - REG_S2 + 2]);
+	case REG_T3 ... REG_T6:
+		return (rp->tf_t[reg - REG_T3 + 3]);
+	case REG_PC:
+		return (rp->tf_sepc);
+	default:
+		DTRACE_CPUFLAG_SET(CPU_DTRACE_ILLOP);
+		return (0);
+	}
+	/* NOTREACHED */
 }
 
 static int
diff --git a/sys/cddl/dev/dtrace/riscv/regset.h b/sys/cddl/dev/dtrace/riscv/regset.h
index f99b48f8354f..034781f11238 100644
--- a/sys/cddl/dev/dtrace/riscv/regset.h
+++ b/sys/cddl/dev/dtrace/riscv/regset.h
@@ -42,7 +42,40 @@
 extern "C" {
 #endif
 
-/* Place here */
+#define REG_ZERO	0
+#define REG_RA		1
+#define REG_SP		2
+#define REG_GP		3
+#define REG_TP		4
+#define REG_T0		5
+#define REG_T1		6
+#define REG_T2		7
+#define REG_S0		8
+#define REG_FP		8
+#define REG_S1		9
+#define REG_A0		10
+#define REG_A1		11
+#define REG_A2		12
+#define REG_A3		13
+#define REG_A4		14
+#define REG_A5		15
+#define REG_A6		16
+#define REG_A7		17
+#define REG_S2		18
+#define REG_S3		19
+#define REG_S4		20
+#define REG_S5		21
+#define REG_S6		22
+#define REG_S7		23
+#define REG_S8		24
+#define REG_S9		25
+#define REG_S10		26
+#define REG_S11		27
+#define REG_T3		28
+#define REG_T4		29
+#define REG_T5		30
+#define REG_T6		31
+#define REG_PC		32
 
 #ifdef	__cplusplus
 }