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author | Andrew Turner <andrew@FreeBSD.org> | 2024-04-15 14:36:20 +0000 |
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committer | Andrew Turner <andrew@FreeBSD.org> | 2024-04-24 18:17:19 +0000 |
commit | ef80df0a71912500ad84060334a24e903869f00b (patch) | |
tree | 8e3396694609f8523cdcb84e309364607a1e85ad | |
parent | 71b2ba9099115db3c63f15e5085c0a677511f8b8 (diff) | |
download | src-ef80df0a71912500ad84060334a24e903869f00b.tar.gz src-ef80df0a71912500ad84060334a24e903869f00b.zip |
arm64/vmm: Ensure the tlbi has completed
Ensure the TLB is invalidated before enabling the EL2 MMU. Without
this the TLB may be in an inconsistant state leading to a possible
exception when enabling the MMU.
PR: 277559
Reviewed by: markj
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D44799
-rw-r--r-- | sys/arm64/vmm/vmm_hyp_exception.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/arm64/vmm/vmm_hyp_exception.S b/sys/arm64/vmm/vmm_hyp_exception.S index 77cb8cfd6cd7..0e8b31ae8b12 100644 --- a/sys/arm64/vmm/vmm_hyp_exception.S +++ b/sys/arm64/vmm/vmm_hyp_exception.S @@ -215,7 +215,10 @@ LENTRY(handle_hyp_init) /* Load the base address for the translation tables */ msr ttbr0_el2, x0 /* Invalidate the TLB */ + dsb ish tlbi alle2 + dsb ishst + isb /* Use the same memory attributes as EL1 */ mrs x9, mair_el1 msr mair_el2, x9 |