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| author | Ion-Mihai Tetcu <itetcu@FreeBSD.org> | 2006-07-11 19:34:46 +0000 |
|---|---|---|
| committer | Ion-Mihai Tetcu <itetcu@FreeBSD.org> | 2006-07-11 19:34:46 +0000 |
| commit | 3cc6293bbeb57818d7a9228a6ed0e819e8780d16 (patch) | |
| tree | 9cb56dffa5f7618757c034e64442f41a446d934b /cad/Makefile | |
| parent | 645531e3498c1966c1efa6388291d96178088ec9 (diff) | |
| download | ports-3cc6293bbeb57818d7a9228a6ed0e819e8780d16.tar.gz ports-3cc6293bbeb57818d7a9228a6ed0e819e8780d16.zip | |
Jspice3 is a circuit simulator developed to meet the needs of researchers
working with superconducting Josephson junction circuits, yet the program
has the flexibility and power to meet the needs of other technologies.
Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added
features. One added feature is a built-in graphical input front end for
schematic capture. While displayed, simulations can be run and data
plotted through this graphical interface.
While not as powerful or as pretty as the Xic graphical interface, it
holds its own in functionality.
A significantly enhanced output plotting capability is provided, and
Jspice3 has enhanced script interpretation capability.
WWW: http://www.wrcad.com/jspice3.html
PR: ports/93958
Submitted by: Pedro F. Giffuni
Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.
Notes
Notes:
svn path=/head/; revision=167526
Diffstat (limited to 'cad/Makefile')
| -rw-r--r-- | cad/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile index f82711ecf3ac..980c0877bf5a 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -38,6 +38,7 @@ SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog + SUBDIR += jspice3 SUBDIR += kicad SUBDIR += leocad SUBDIR += libgeda |