diff options
| author | Stanislav Sedov <stas@FreeBSD.org> | 2006-10-03 13:34:22 +0000 |
|---|---|---|
| committer | Stanislav Sedov <stas@FreeBSD.org> | 2006-10-03 13:34:22 +0000 |
| commit | dc494c17e32d0921a4f863f395d6345ce42543a7 (patch) | |
| tree | 71a5643491d464d45877595aaa08a58911aa7820 /cad | |
| parent | 3d5ebdecc948eb890644eb242a6bf17acb3cd59a (diff) | |
| download | ports-dc494c17e32d0921a4f863f395d6345ce42543a7.tar.gz ports-dc494c17e32d0921a4f863f395d6345ce42543a7.zip | |
- Update to 0.8.2
- Fix compiling with gcc 4.1
- Change my email
Approved by: sem (mentor)
Notes
Notes:
svn path=/head/; revision=174371
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/iverilog/Makefile | 10 | ||||
| -rw-r--r-- | cad/iverilog/distinfo | 6 | ||||
| -rw-r--r-- | cad/iverilog/files/patch-PExpr.h | 11 | ||||
| -rw-r--r-- | cad/iverilog/pkg-plist | 5 |
4 files changed, 23 insertions, 9 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index 38c7f7c29542..d4e46495664a 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -7,19 +7,19 @@ # PORTNAME= iverilog -PORTVERSION= 0.8.1 +PORTVERSION= 0.8.2 CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/ \ +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \ ftp://ftp.geda.seul.org/pub/geda/dist/ DISTNAME= verilog-${PORTVERSION} -MAINTAINER= ssedov@mbsd.msk.ru +MAINTAINER= stas@FreeBSD.org COMMENT= A Verilog simulation and synthesis tool +GNU_CONFIGURE= yes USE_BISON= yes USE_GMAKE= yes -GNU_CONFIGURE= yes -CONFIGURE_TARGET= --build=${MACHINE_ARCH}-portbld-freebsd${OSREL} +USE_GNOME= gnometarget MAN1= iverilog-vpi.1 iverilog.1 vvp.1 iverilog-fpga.1 diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo index 36360bdec00c..3839ccbfffaf 100644 --- a/cad/iverilog/distinfo +++ b/cad/iverilog/distinfo @@ -1,3 +1,3 @@ -MD5 (verilog-0.8.1.tar.gz) = 61ab44cbf1734acf1b1e6c4c1ed596b6 -SHA256 (verilog-0.8.1.tar.gz) = 9584d54863bb2399b287251ec17ea435b587abdb20784bcf072024bf4965920d -SIZE (verilog-0.8.1.tar.gz) = 1431354 +MD5 (verilog-0.8.2.tar.gz) = 41650504e4460508a0800008a2628e07 +SHA256 (verilog-0.8.2.tar.gz) = c0df02855d547b0b73d3c020f4cc884319fde8f449ab216abcb685639ff69f08 +SIZE (verilog-0.8.2.tar.gz) = 1526676 diff --git a/cad/iverilog/files/patch-PExpr.h b/cad/iverilog/files/patch-PExpr.h new file mode 100644 index 000000000000..90c8212cef47 --- /dev/null +++ b/cad/iverilog/files/patch-PExpr.h @@ -0,0 +1,11 @@ +--- PExpr.h.orig Mon Oct 2 20:26:17 2006 ++++ PExpr.h Mon Oct 2 20:26:23 2006 +@@ -324,7 +324,7 @@ + virtual NetEConst*elaborate_expr(Design*des, NetScope*, + bool sys_task_arg =false) const; + virtual NetEConst*elaborate_pexpr(Design*des, NetScope*sc) const; +- verinum* PEString::eval_const(const Design*, const NetScope*) const; ++ verinum* eval_const(const Design*, const NetScope*) const; + + virtual bool is_constant(Module*) const; + diff --git a/cad/iverilog/pkg-plist b/cad/iverilog/pkg-plist index 0542de33d93d..5925456f341c 100644 --- a/cad/iverilog/pkg-plist +++ b/cad/iverilog/pkg-plist @@ -1,12 +1,15 @@ bin/iverilog bin/iverilog-vpi bin/vvp +include/_pli_types.h include/acc_user.h include/ivl_target.h include/veriuser.h include/vpi_user.h -include/_pli_types.h lib/ivl/cadpli.vpl +lib/ivl/edif-s.conf +lib/ivl/edif.conf +lib/ivl/edif.tgt lib/ivl/fpga-s.conf lib/ivl/fpga.conf lib/ivl/fpga.tgt |