blob: c3db29108304fc816b896f1e44fb4bd2a8f969f8 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
# New ports collection makefile for: Verilog-Perl
# Date created: 11 Apr 2009
# Whom: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
#
# $FreeBSD$
#
PORTNAME= Verilog-Perl
PORTVERSION= 3.251
CATEGORIES= cad perl5
MASTER_SITES= CPAN
PKGNAMEPREFIX= p5-
MAINTAINER= otacilio.neto@ee.ufcg.edu.br
COMMENT= Building point for Verilog support in the Perl language
BUILD_DEPENDS= flex>=2.5.35:${PORTSDIR}/textproc/flex
USE_GMAKE= yes
USE_PERL5= yes
USE_BISON= build
PERL_CONFIGURE= yes
MAN1= vhier.1 vpassert.1 vppreproc.1 vrename.1
MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
.include <bsd.port.pre.mk>
post-patch:
@${REINPLACE_CMD} -e '/EXE_FILES/ s/ vsplitmodule//' \
${WRKSRC}/Makefile.PL
post-configure:
.if ${OSVERSION} < 700042
@${REINPLACE_CMD} -e 's|-O2|-O|g' ${WRKSRC}/Makefile
.endif
post-build:
cd ${WRKSRC} && make test
test:
make post-build
.include <bsd.port.post.mk>
|