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.Dd January 27, 2021
.Dt QAT 4
.Os
.Sh NAME
.Nm qat
.Nd Intel QuickAssist Technology (QAT) driver
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device crypto"
.Cd "device cryptodev"
.Cd "device qat"
.Ed
.Pp
Alternatively, to load the driver as a
module at boot time, place the following lines in
.Xr loader.conf 5 :
.Bd -literal -offset indent
qat_load="YES"
qat_c2xxxfw_load="YES"
qat_c3xxxfw_load="YES"
qat_c62xfw_load="YES"
qat_d15xxfw_load="YES"
qat_dh895xccfw_load="YES"
.Ed
.Sh DESCRIPTION
The
.Nm
driver implements
.Xr crypto 4
support for some of the cryptographic acceleration functions of the Intel
QuickAssist (QAT) device.
The
.Nm
driver supports the QAT devices integrated with Atom C2000 and C3000 and Xeon
C620 and D-1500 platforms, and the Intel QAT Adapter 8950.
Other platforms and adapters not listed here may also be supported.
QAT devices are enumerated through PCIe and are thus visible in
.Xr pciconf 8
output.
.Pp
The
.Nm
driver can accelerate AES in CBC, CTR, XTS (except for the C2000) and GCM modes,
and can perform authenticated encryption combining the CBC, CTR and XTS modes
with SHA1-HMAC and SHA2-HMAC.
The
.Nm
driver can also compute SHA1 and SHA2 digests.
The implementation of AES-GCM has a firmware-imposed constraint that the length
of any additional authenticated data (AAD) must not exceed 240 bytes.
The driver thus rejects
.Xr crypto 9
requests that do not satisfy this constraint.
.Sh SEE ALSO
.Xr crypto 4 ,
.Xr ipsec 4 ,
.Xr pci 4 ,
.Xr random 4 ,
.Xr crypto 7 ,
.Xr crypto 9
.Sh HISTORY
The
.Nm
driver first appeared in
.Fx 13.0 .
.Sh AUTHORS
The
.Nm
driver was written for
.Nx
by
.An Hikaru Abe Aq Mt hikaru@iij.ad.jp
and ported to
.Fx
by
.An Mark Johnston Aq Mt markj@FreeBSD.org .
.Sh BUGS
Some Atom C2000 QAT devices have two acceleration engines instead of one.
The
.Nm
driver currently misbehaves when both are enabled and thus does not enable
the second acceleration engine if one is present.
